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WO2001097290A2 - Transistor a effet de champ a grille inversee enfouie (bigfet) - Google Patents

Transistor a effet de champ a grille inversee enfouie (bigfet) Download PDF

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Publication number
WO2001097290A2
WO2001097290A2 PCT/US2001/040862 US0140862W WO0197290A2 WO 2001097290 A2 WO2001097290 A2 WO 2001097290A2 US 0140862 W US0140862 W US 0140862W WO 0197290 A2 WO0197290 A2 WO 0197290A2
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WO
WIPO (PCT)
Prior art keywords
doped
gate conductor
buried gate
channel
forming
Prior art date
Application number
PCT/US2001/040862
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English (en)
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WO2001097290A3 (fr
Inventor
John A. Iacoponi
Thomas E. Spikes, Jr.
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Advanced Micro Devices, Inc.
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Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to AU2001267034A priority Critical patent/AU2001267034A1/en
Publication of WO2001097290A2 publication Critical patent/WO2001097290A2/fr
Publication of WO2001097290A3 publication Critical patent/WO2001097290A3/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/023—Manufacture or treatment of FETs having insulated gates [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H10D30/615—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel comprising a MOS gate electrode and at least one non-MOS gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/018—Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0217—Manufacture or treatment of FETs having insulated gates [IGFET] forming self-aligned punch-through stoppers or threshold implants under gate regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/721—Insulated-gate field-effect transistors [IGFET] having a gate-to-body connection, i.e. bulk dynamic threshold voltage IGFET 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current

Definitions

  • This invention relates generally to semiconductor fabrication technology, and, more particularly, to techniques for manufacturing a semiconductor devices having a reduced critical dimension.
  • reducing the size, or scale, of the components of a typical transistor also requires being able to form and pattern components such as the gate conductor and gate dielectric on such reduced scales, consistently, robustly and reproducibly, preferably in a self-aligned manner.
  • the ability to form and pattern components such as the gate conductor and gate dielectric on such reduced scales, consistently, robustly and reproducibly is limited by, among other things, physical limits imposed by photolithography. Diffraction effects impose limits on the critical dimensions of components such as gate conductors and gate dielectrics that correspond roughly to the wavelengths of the light used to perform the photolithography.
  • FIG. 1 A conventional approach to achieving reduced critical dimensions, used with or without resorting to expensive deep ultraviolet (DUN) photolithography and/or in high-energy electron beam lithography, is schematically illustrated in Figures 1-4.
  • a conventional "metal oxide semiconductor" field-effect (MOSFET or MOS) transistor 100 may be formed on a semiconducting substrate 105, such as doped-silicon (Si).
  • the MOS transistor 100 may have a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor 115, such as an ⁇ doped-poly (P + -doped-poly) gate conductor 115, formed above a gate dielectric 110 that is formed above the semiconducting substrate 105.
  • the ⁇ -doped-poly (P + -doped-poly) gate conductor 115 and the gate dielectric 110 may be separated from active areas such as ⁇ -doped (P + -doped) source/drain regions 120 of the MOS transistor 100 by dielectric spacers 125.
  • the dielectric spacers 125 may be formed above - ⁇ T-doped (P " -doped) source/drain extension (SDE) regions 130.
  • STI shallow trench isolation regions 140 may be provided to isolate the MOS transistor 100 electrically from neighboring semiconductor devices such as other MOS transistors (not shown).
  • the ⁇ " -doped (P " -doped) SDE regions 130 are typically provided to reduce the magnitude of the maximum channel electric field found close to the .sT-doped (P + -doped) source/drain regions 120 of the MOS transistor 100, and, thereby, to reduce the associated hot-carrier effects.
  • the lower doping of the N " -doped (P " -doped) SDE regions 130, relative to the N + -doped (P + -doped) source/drain regions 120 of the MOS transistor 100 reduces the magnitude of the maximum channel electric field found close to the -ST ⁇ -doped (P + -doped) source/drain regions 120 of the MOS transistor 100, but increases the source-to-drain resistances of the N " -doped (P " -doped) SDE regions 130.
  • the N + -doped-poly (P + -doped-poly) gate conductor 115 and the gate dielectric 110 have a critical dimension D t that effectively determines a channel length L of the MOS transistor 100.
  • the channel length L is approximately the distance between the N " -doped (P " -do ⁇ ed) SDE regions 130 adjacent the N ⁇ -doped-poly (P + -doped-poly) gate conductor 115 and the gate dielectric 110.
  • the critical dimension D t of the N + -doped-poly (P + -doped-poly) gate conductor 115 and the gate dielectric 110 is determined as follows. As shown in Figure 2, a gate dielectric layer 210 is formed above the semiconducting substrate 105, and a gate conductor layer 215 is formed above the gate dielectric layer 210. An antireflective coating (ARC) layer 230 is formed above the gate conductor layer 215, and a photoresist layer 220 is formed and patterned, using conventional, non-deep ultraviolet (non-DUV) photolithography, above the antireflective coating (ARC) layer 230.
  • ARC non-deep ultraviolet
  • the photoresist layer 220 is patterned to have the smallest, diffraction-limited dimension D that may be achieved with existing technology, for example, a smallest, diffraction-limited dimension D in a range of about 1000-2000 A.
  • DUN deep ultraviolet
  • the patterned photoresist layer 220 (indicated in phantom) is trimmed using a controlled photoresist trim to form a trimmed photoresist mask 320.
  • the patterned photoresist layer 220 may be trimmed using any of the processes known to those skilled in the art, having the benefit of the present disclosure.
  • the trimmed photoresist mask 320 will typically have the critical dimension D t that may be in a range of about 500-1000 A that will determine the approximate size of the ⁇ + -doped-poly (P + -doped-poly) gate conductor 115 and the gate dielectric 110, following appropriate patterning processes.
  • the trimmed photoresist mask 320 is used as a mask to remove respective portions 430, 415 and 410 (shown in phantom) from the antireflective coating (ARC) layer 230, gate conductor layer 215 and the gate dielectric layer 210 ( Figures 2-3), respectively, to form a gate structure 400 that includes the -ST ⁇ -doped-poly (P + -do ⁇ ed-poly) gate conductor 115 and the gate dielectric 110.
  • ARC antireflective coating
  • the gate structure 400 and, hence, the N ⁇ -doped-poly (P + -doped-poly) gate conductor 115 and the gate dielectric 110, will also have the critical dimension D t defined by the trimmed photoresist mask 320.
  • the critical dimension D t defined by the trimmed photoresist mask 320 is still too large. Further trimming of the trimmed photoresist mask 320 will not be sufficiently controllable, reliable or feasible to be able to be used to form and pattern components such as gate conductors and gate dielectrics on even more reduced scales, consistently, robustly and reproducibly, preferably in a self-aligned manner. As shown in Figures 2-4, the conventional techniques to form the gate structure 400 typically involve forming and patterning layers of materials and then wastefully subtracting and/or etching away most of those materials to leave a narrow and fragile positive feature having the critical dimension D t , defined by the trimmed photoresist mask 320, that is still too large.
  • a conventional N-channel MOS (NMOS) transistor 100 may operate in the "off state as follows.
  • the gate voltage V gale 0 (or, more precisely, V gale is less than or equal to ⁇ t hreshold , where V threshold is the threshold voltage for the conventional NMOS transistor 100), and the drain-source current is approximately zero, even with a positive voltage (V dml consult > 0) present at the drain 120D.
  • the positive voltage (V draln > 0) present at the drain 120D causes a drain depletion region 160D (shown in phantom) to form in a portion of the p-type semiconducting substrate 105 adjacent the drain 120D, and in a portion of the drain 120D, as well.
  • the drain depletion region 160D is typically larger than a source depletion region 160S (shown in phantom) that forms in a portion of the p-type semiconducting substrate 105 adjacent the source 120S, and in a portion of the source 120S, as well.
  • An effective channel length L f of the MOS transistor 100 is the distance between the drain depletion region 160D and the source depletion region 160S.
  • a conventional N-channel MOS (NMOS) transistor 100 may operate in the "on” state as follows.
  • the drain-source current I dmi foi is positive (to the left) as electrons from the source 120S drift (indicated by the arrow) through an inversion layer 600 (an N-channel) to the drain 120D, with a positive voltage V drai foi > 0 present at the drain 120D.
  • the inversion layer 600 is thought to form as electrons are attracted to the underside of the gate dielectric 110 by the positive gate voltage V g t e > V, hres otd > 0 applied to the lST ⁇ -doped-poly gate conductor 115.
  • the electrons attracted to the underside of the gate dielectric 110 are not able to conduct into the N ⁇ -doped-poly gate conductor 115, since the gate dielectric 110 is an insulator.
  • the effective channel length L f of the MOS transistor 100 for the electrons drifting through the.N-channel inversion layer 600 is the distance between the drain depletion region 160D and the source depletion region 160S.
  • Short-channel effects include, among other things, an increased drain-source leakage current when the MOS transistor is supposed to be switched “off,” believed to be due to an enlarged depletion region relative to the shorter channel length.
  • the present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
  • a method comprising forming a masking layer above a substrate layer, forming an opening in the masking layer, the opening defining a channel region in the substrate layer, and forming a buried gate conductor in the substrate layer below the channel region, using the opening to self-align the buried gate conductor.
  • the method also comprises forming source/drain regions adjacent the channel region.
  • a semiconductor device formed by a method comprising forming a masking layer above a substrate layer, forming an opening in the masking layer, the opening defining a channel region in the substrate layer, and forming a buried gate conductor in the substrate layer below the channel region, using the opening to self-align the buried gate conductor.
  • the method also comprises forming source/drain regions adjacent the channel region.
  • a semiconductor device comprising a substrate layer having a channel region, and source/drain regions adjacent the channel region.
  • the semiconductor device also comprises a buried gate conductor in the substrate layer below the channel region.
  • Figures 1-6 illustrate schematically in cross-section conventional semiconductor devices and/or techniques for fabricating the same.
  • Figures 7-24 illustrate schematically various embodiments of a semiconductor device and/or a method for semiconductor device fabrication, according to the present invention.
  • FIG. 7-24 Illustrative embodiments of a semiconductor device and/or a method for semiconductor device fabrication, according to the present invention, are shown in Figures 7-24. Although the various regions and structures of a semiconductor device are depicted in the drawings as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Nevertheless, the attached drawings are included to provide illustrative examples of the present invention.
  • the present invention is directed towards the manufacture of a semiconductor device.
  • the present method is applicable to a variety of technologies, for example, NMOS, PMOS, CMOS, and the like, and is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, and the like.
  • a buried inverted gate field-effect transistor (BIGFET) 700 may be formed in a semiconducting substrate 105, such as p-doped (n-doped) silicon (Si).
  • the BIGFET 700 may have a doped buried gate conductor such as a P + -doped (IS ⁇ -doped) buried gate conductor 715 formed in the p-doped (n-doped) semiconducting substrate 105, below a self-alignment structure 710 formed above an upper surface 150 of the semiconducting substrate 105.
  • a P + -doped (N + -doped) buried gate conductor 715 formed in a p-doped (n-doped) semiconducting substrate 105, may be used to form an N-channel (P-channel) BIGFET 700, as shown, for example, in Figures 7-9, 19, 23 and 24.
  • an N ⁇ -doped (P + -doped) buried gate conductor 715 formed in a p-doped (n-doped) semiconducting substrate 105, may be used to form an N-channel (P-channel) BIGFET 700, as shown, for example, in Figure 20.
  • the self-alignment structure 710 may be separated from active areas, such as N-doped (P + -doped) source/drain regions 120 of the BIGFET 700, by spacers 125.
  • the spacers 125 may be formed above N ' -doped (P " -doped) source/drain extension (SDE) regions 130.
  • shallow trench isolation (STI) regions 140 may be provided to isolate the BIGFET 700 electrically from neighboring semiconductor devices such as other BIGFETs and/or MOS transistors, and the like (not shown).
  • an N-channel BIGFET 700 having a heavily P + -doped buried gate conductor 715 formed in a p-doped semiconducting substrate 105, may operate in the "off state as follows.
  • the buried gate voltage V buriedga , e 0 (or, more precisely, V bm ⁇ - dgale is greater than or equal to V- h ⁇ hoU , where V t reshold is the threshold voltage for the BIGFET 700), and the drain-source current I drai fie is approximately zero, even with a positive voltage V ram > 0 present at the drain 120D.
  • the positive voltage V m ⁇ personally > 0 present at the drain 120D and the grounding of the source 120S cause depletion regions 160 (shown in phantom) to form in portions of the p-type semiconducting substrate 105 adjacent the drain 120D and source 120S, and in portions of the drain 120D and source 120S, as well.
  • the depletion regions 160 may be about the same size on either side of the heavily P + -doped buried gate conductor 715, and may be prevented from growing larger by the presence of the heavily P + -doped buried gate conductor 715.
  • An effective channel length 1 of the N-channel BIGFET 700 may be the distance between the depletion regions 160, as shown in Figure 8.
  • the effective channel length 1 of the N-channel BIGFET 700 may be about equal to the smallest critical dimension d k of the self-alignment structure 710 of the N-channel BIGFET 700.
  • the N-channel BIGFET 700 having the heavily P + -doped buried gate conductor 715 formed in the p-doped semiconducting substrate 105, may operate in the "on” state as follows. In the "on” state, the buried gate voltage Vbu iedg e ⁇ ⁇ threshold ⁇ 0 > where V objection m shoid is the threshold voltage for the (enhancement-type) N-channel BIGFET 700.
  • the drain-source current I dram is positive (to the left) as electrons from the source 120S drift (indicated by the arrow) through an inversion layer in a channel region 800 (an N-channel) to the drain 120D, with a positive voltage V drai foi > 0 present at the dram 120D.
  • the inversion layer in the channel region 800 is thought to form as holes in the p-doped semiconducting substrate 105 above the heavily P + -doped buried gate conductor 715 are attracted to the heavily P + -doped buried gate conductor 715.
  • the holes are attracted by the negative buried gate voltage Vburi gate * ⁇ V l hr shoi ⁇ ⁇ applied to the heavily P + -doped buried gate conductor 715.
  • Vburi gate * ⁇ V l hr shoi ⁇ ⁇ applied to the heavily P + -doped buried gate conductor 715.
  • electrons above the heavily P + -doped buried gate conductor 715 are driven up to the underside of the self-alignment structure 710 near the upper surface 150 of the semiconducting substrate 105 by the negative buried gate voltage Vb uriedga ⁇ e ⁇ V threS 0 i d ⁇ Q applied to the heavily P + -doped buried gate conductor 715.
  • a depletion region 860 is believed to form adjacent the heavily P + -doped buried gate conductor 715 as mobile holes are attracted by the negative gate voltage buried Vb m i edgate ⁇ V r shotd ⁇ 0 applied to the heavily P + -doped buried gate conductor 715 and as mobile electrons are driven away.
  • the effective channel length 1 of the N-channel BIGFET 700 for the electrons drifting through the N-channel inversion layer in the channel region 800 is the distance between the depletion regions 160.
  • a top view of the N-channel BIGFET 700 is shown schematically in Figure 9.
  • a heavily P + -doped (N ⁇ -doped) well 905 may be formed in the p-doped semiconducting substrate 105. As shown in Figure 10, the heavily P + -doped well 905 may be formed adjacent the self-alignment structure 710. The heavily P + -doped well 905 may extend from the upper surface 150 of the semiconducting substrate 105 down into the semiconducting substrate 105 to provide an electrical contact with the heavily P + -doped buried gate conductor 715.
  • the heavily P + -doped buried gate conductor 715 extends under the self-alignment structure 710 and into the heavily P + -doped well 905 to provide the electrical contact for the application of the buried gate voltage V bu kdga i e ⁇ th esho i d ⁇ 0.
  • the depletion region 860 is also schematically illustrated in Figure 9.
  • the cross-sectional view as shown in Figure 7 is taken along the line VII- VII of Figure 9, and the cross-sectional view as shown in Figure 10, is taken along the line X-X of Figure 9.
  • FIGs 11-17 illustrate a method of forming a BIGFET 700 (Figure 7) according to the present invention.
  • STI shallow trench isolation
  • the shallow trench isolation (STI) regions 140 may, for example, comprise an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (Si0 2 ), a nitrogen-bearing oxide (e.g., nitrogen-bearing Si0 2 ), a nitrogen-doped oxide (e.g., N 2 -implanted Si0 2 ), silicon oxynitride (Si x O y N z ), and the like.
  • an oxide e.g., Ge oxide
  • an oxynitride e.g., GaP oxynitride
  • silicon dioxide Si0 2
  • a nitrogen-bearing oxide e.g., nitrogen-bearing Si0 2
  • a nitrogen-doped oxide e.g., N 2 -implanted Si0 2
  • silicon oxynitride Si x O y N z
  • the shallow trench isolation (STI) regions 140 may also be formed of any suitable "high dielectric constant” or "high K” material, where K is greater than or equal to about 8, such as titanium oxide (Ti x O y , e.g., Ti0 2 ), tantalum oxide (Ta x O y , e.g., Ta 2 0 5 ), barium strontium titanate (BST, BaTi0 3 /SrTi0 3 ), and the like.
  • the shallow trench isolation (STI) regions 140 may also be formed of any suitable "low dielectric constant” or "low K” dielectric material, where K is less than or equal to about 4. Examples include Applied Material's Black Diamond ® , Novellus' Coral ® , Allied Signal's Nanoglass ® , JSR's LKD5104, and the like.
  • a patterned masking layer 1110 may be formed and patterned above the upper surface 150 of the p-doped (n-doped) semiconducting substrate 105, such as doped-silicon (Si).
  • the patterned masking layer 1110 may be formed by a variety of known techniques for forming such layers, e.g, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering and physical vapor deposition (PVD), thermal growing, and the like.
  • the patterned masking layer 1110 may have a thickness q above the upper surface 150 ranging from approximately 1000-5000 A, for example.
  • the patterned masking layer 1110 may be formed from a variety of dielectric materials such as, for example, an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (Si0 2 ), a nitrogen-bearing oxide (e.g., nitrogen-bearing Si0 2 ), a nitrogen-doped oxide (e.g, N 2 -implanted Si0 2 ), silicon oxynitride (Si x O y N 2 ), and the like.
  • the patterned masking layer 1110 may be formed of photoresist, and the like.
  • the patterned masking layer 1110 may be patterned to form an opening 1100 using photolithography, for example.
  • the opening 1100 formed in the patterned masking layer 1110 may have the smallest, diffraction-limited dimension d k that may be achieved with present-day technology.
  • a diffraction-limited dimension d k in a range of about 250-1000 A may be achieved.
  • an even smaller, diffraction-limited dimension d k in a range of about 150-1000 A may be achieved, using phase-shifted masking techniques.
  • the P + -doped (N + -doped) buried gate conductor 715 may be formed in the p-doped (n-doped) semiconducting substrate 105 by being implanted using a dopant 1120 (indicated by arrows) to introduce dopant atoms and/or molecules into the p-doped (n-doped) semiconducting substrate 105.
  • a dose of the dopant 1120 atoms and/or molecules may range from approximately 1.0 x 10 15 - 5.0 x 10 15 ions/cm 2 of the appropriate dopant 1120 atoms and/or molecules, e.g., boron (B) for an illustrative P + -doped buried gate conductor 715 or phosphorus (P) for an illustrative N ⁇ -doped buried gate conductor 715.
  • An implant energy of the dopant 1120 atoms and/or molecules may range from approximately 100-1000 keV.
  • the P + -doped (NT-doped) buried gate conductor 715 may have a peak dopant 1120 concentration in a range of from about 1.0xlO I9 -1.0xl0 21 atoms and/or molecules per cm 3 .
  • the dopant 1120 may be an N 1" implant such as phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and the like, and may form a heavily doped N + -doped buried gate conductor 715.
  • the dopant 1120 may be a P + implant such as boron (B), boron fluoride (BF, BF 2 ), aluminum (Al), gallium (Ga), Indium (In), Thallium (Tl), and the like, and may form a heavily doped P + -doped buried gate conductor 715.
  • the P + -doped (N + -doped) buried gate conductor 715 may be formed to a depth e below the upper surface 150 of the p-doped (n-doped) semiconducting substrate 105 that may be in a range of about 100-1000 A. As shown in Figure 11, the P + -doped (N-doped) buried gate conductor 715 may also have a width that corresponds approximately to the critical dimension d k that may be in a range of about 150-1000 A. The P + -doped (N + -doped) buried gate conductor 715 "inherits" the smallest, diffraction-limited critical dimension d k from the opening 1100 formed in the patterned masking layer 1110.
  • the self-alignment structure 710 formed above the upper surface 150 of the semiconducting substrate 105 may be formed in the opening 1100 in the patterned masking layer 1110.
  • the self-alignment structure 710 may be formed by a variety of known techniques for forming such layers, e.g., chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering and physical vapor deposition (PVD), thermal growing, spin-on-glass, and the like, and may have a thickness q p ranging from approximately 1000-5000 A, for example.
  • CVD chemical vapor deposition
  • LPCVD low-pressure CVD
  • PECVD plasma-enhanced CVD
  • PVD physical vapor deposition
  • the thickness q p of the self-alignment structure 710 may be about the same as the thickness q of the patterned masking layer 1110.
  • the self-alignment structure 710 may be formed in the opening 1100 in the patterned masking layer 1110 by being planarized, for example, by chemical mechanical polishing (CMP).
  • the self-alignment structure 710 may, for example, comprise an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (Si0 2 ), a nitrogen-bearing oxide (e.g., nitrogen-bearing Si0 2 ), a nitrogen-doped oxide (e.g., N 2 -implanted Si0 2 ), silicon oxynitride (Si x O y N z ), and the like.
  • an oxide e.g., Ge oxide
  • an oxynitride e.g., GaP oxynitride
  • silicon dioxide Si0 2
  • a nitrogen-bearing oxide e.g., nitrogen-bearing Si0 2
  • a nitrogen-doped oxide e.g., N 2 -implanted Si0 2
  • silicon oxynitride Si x O y N z
  • the self-alignment structure 710 may also be formed of any suitable "high dielectric constant” or "high K” material, where K is greater than or equal to about 8, such as titanium oxide (Ti x O y , e.g., Ti0 2 ), tantalum oxide (Ta x O y , e.g., Ta 2 0 5 ), barium strontium titanate (BST, BaTi0 3 /SrTi0 3 ), and the like.
  • the self-alignment structure 710 may also be formed of any suitable "low dielectric constant” or "low K” dielectric material, where K is less than or equal to about 4. Examples include Applied Material's Black Diamond ® , Novellus' Coral ® , Allied Signal's Nanoglass ® , JSR's LKD5104, and the like.
  • the self-alignment structure 710 may be formed of a conductive material.
  • the conductive self-alignment structure 710 may be formed by a variety of known techniques, e.g., high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, PVD, CVD, LPCVD, PECVD, and the like, and may have a thickness q p ranging from approximately 1000-5000 A, for example.
  • IMP high-density ionized metal plasma
  • ICP inductively coupled plasma
  • the conductive self-alignment structure 710 may be formed of a variety of metals such as aluminum (Al), titanium (Ti), zirconium (Zr), tungsten (W), tantalum (Ta), nickel (Ni), molybdenum (Mo), cobalt (Co), copper (Cu), and the like.
  • the self-alignment structure 710 may be formed of polycrystalline silicon (poly).
  • the poly self-alignment structure 710 may be formed by a variety of known techniques for forming such layers, e.g., CVD, LPCVD, PECVD, PVD, and the like, and may have a thickness q p ranging from approximately 1000-5000 A, for example.
  • the poly self-alignment structure 710 has a thickness of approximately 3000 A and is formed by an LPCVD process for higher throughput.
  • the self-alignment structure 710 may be comprised of a material that may be selectively removed with respect to the material of the patterned masking layer 1110.
  • the patterned masking layer 1110 may then be selectively removed, leaving the isolated self-alignment structure 710 formed above the upper surface 150 of the p-doped (n-doped) semiconducting substrate 105.
  • the isolated self-alignment structure 710 may have sides 1350.
  • the isolated self-alignment structure 710 may be formed using a variety of known etching techniques, such as an anisotropic etching process.
  • a selective anisotropic etching technique may be used, such as a reactive ion etching (RIE) process using hydrogen bromide (HBr) and argon (Ar) as the etchant gases, for example.
  • RIE reactive ion etching
  • HBr hydrogen bromide
  • Ar argon
  • plasma etching may also be used, in various illustrative embodiments.
  • the photoresist patterned masking layer 1110 may be removed by being stripped away, by ashing, for example.
  • the photoresist patterned masking layer 1110 may be stripped using a 1:1 solution of sulfuric acid (H 2 S0 4 ) to hydrogen peroxide (H 2 0 2 ), for example.
  • a "complementary" masking layer 1300 formed of photoresist, for example, may be formed above the upper surface 150 of the semiconducting substrate 105, and above and adjacent the isolated self-alignment structure 710.
  • the complementary masking layer 1300 may have a thickness ⁇ above the upper surface 150 ranging from approximately 2000-15000 A, for example. In various illustrative embodiments, the thickness ⁇ above the upper surface 150 is about 10000 t .
  • the complementary masking layer 1300 may be patterned to form the complementary mask 1475 above at least a portion of the shallow trench isolation (STI) 140.
  • the complementary masking layer 1300 may be patterned to form the complementary mask 1475 using a variety of known photolithography and/or etching techniques.
  • the complementary mask 1475 may have an edge 1420 spaced apart from the side 1350 of the isolated self-alignment structure 710 by a distance w ranging from approximately 1000-1500 A, for example.
  • the complementary mask 1475 may be formed over the STI region 140, as in conventional CMOS fabrication methods, to protect the P-channel BIGFET (N-channel BIGFET) regions while the complementary N-channel BIGFET (P-channel BIGFET) regions are being implanted to form N ' -doped (P " -doped) regions 1430, for example.
  • a dopant 1400 (indicated by the arrows) may be implanted to introduce dopant atoms and/or molecules into the p-doped (n-doped) semiconducting substrate 105 to form the N ' -doped (P " -doped) regions 1430.
  • N ' -doped (P " -doped) regions 1430 become the N ' -doped (P " -doped) source/drain extension (SDE) regions 130 (as described more fully below with reference to Figure 15).
  • SDE source/drain extension
  • the N " -doped (P " -doped) regions 1430 may be formed by being implanted with a source/drain extension (SDE) dose of As (for N " -doping appropriate for an N-channel BIGFET 700, Figure 7) or BF 2 (for P " -doping appropriate for a P-channel BIGFET 700, Figure 7).
  • SDE source/drain extension
  • the source/drain extension (SDE) dose may range from about l.OxlO 14 - l.OxlO 15 ions/cm 2 at an implant energy ranging from about 3-50 keV.
  • the N ' -doped (P " -doped) regions 1430 may be subjected to a rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 800-1100°C for a time ranging from approximately 5-60 seconds.
  • RTA rapid thermal anneal
  • the rapid thermal anneal (RTA) process may activate the implant and form a more sharply defined and less graded activated implant junction with the substrate 105 than would a rapid thermal anneal (RTA) process following an implant with a source/drain extension (SDE) dose of more mobile phosphorus (P) (for N " -doping appropriate for an N-channel BIGFET 700, Figure 7) or boron (B) (for P ' -doping appropriate for a P-channel BIGFET 700, Figure 7).
  • SDE source/drain extension
  • P mobile phosphorus
  • B boron
  • spacers 125 may be formed adjacent the isolated self-alignment structure 710, either before or after the N ' -doped (P ' -doped) regions 1430 ( Figure 14) are activated to become the N ' -doped (P ' -doped) source/drain extension (SDE) regions 130.
  • the spacers 125 may be formed by a variety of techniques above the N ' -doped (P ' -doped) source/drain extension (SDE) regions 130 and adjacent the isolated self-alignment structure 710.
  • the spacers 125 may be formed by depositing a conformal layer (not shown) of the appropriate material above and adjacent the isolated self-alignment structure 710, and then performing an anisotropic reactive ion etching (RIE) process on the conformally blanket-deposited layer.
  • the spacers 125 may each have a base thickness ranging from approximately 300-1500 A, for example, measured from the sides 1350 of the isolated self-alignment structure 710.
  • the spacers 125 may be formed from a variety of materials.
  • the spacers 125 may be comprised of a fluorine-doped oxide, a fluorine-doped nitride, a fluorine-doped oxynitride, a fluorine-doped low K material, and the like.
  • the spacers 125 are comprised of Si0 2 , having a base thickness of approximately 300 A.
  • the spacers 125 may, for example, comprise an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (Si0 2 ), a nitrogen-bearing oxide (e.g., nitrogen-bearing Si0 2 ), a nitrogen-doped oxide (e.g., N 2 -implanted Si0 2 ), silicon nitride (Si 3 N ), silicon oxynitride (Si x O y N z ), and the like.
  • an oxide e.g., Ge oxide
  • an oxynitride e.g., GaP oxynitride
  • silicon dioxide Si0 2
  • a nitrogen-bearing oxide e.g., nitrogen-bearing Si0 2
  • a nitrogen-doped oxide e.g., N 2 -implanted Si0 2
  • silicon nitride Si 3 N
  • silicon oxynitride Si
  • the spacers 125 may also be formed of any suitable "high dielectric constant” or "high K” material, where K is greater than or equal to about 8, such as titanium oxide (Ti x O y , e.g., Ti0 2 ), tantalum oxide (Ta x O y , e.g., Ta 2 0 5 ), barium strontium titanate (BST, BaTi0 3 /SrTi0 3 ), and the like.
  • the spacers 125 may also be formed of any suitable "low dielectric constant” or "low K” dielectric material, where K is less than or equal to about 4. Examples include Applied Material's Black Diamond ® , Novellus' Coral ® , Allied Signal's Nanoglass ® , JSR's LKD5104, and the like.
  • the spacers 125 may be formed of polycrystalline silicon (poly).
  • the poly spacers 125 may be formed by a variety of known techniques for forming such layers, e.g., CVD, LPCVD, PECVD, PVD, and the like.
  • a dopant 1600 may be implanted to introduce dopant atoms and/or molecules into the p-type (n-type) semiconducting substrate 105 to form N'-doped (P + -doped) regions 1620.
  • the N ⁇ -doped (P + -doped) regions 1620 become N ⁇ -doped (P + -doped) source/drain regions 120 ( Figure 7).
  • a dose of the dopant 1600 atoms and/or molecules may range from approximately 1.0 x 10 15 - 5.0 x 10 15 ions/cm 2 of the appropriate dopant 1600 atoms and/or molecules, e.g., phosphorus (P) for an illustrative N-channel BIGFET or boron (B) for an illustrative P-channel BIGFET.
  • An implant energy of the dopant 1600 atoms and/or molecules may range from approximately 30-100 keV.
  • a dose of the dopant 1600 atoms is approximately 1.0 x 10 15 ions/cm 2 of phosphorus (P) for an N-channel BIGFET or boron (B) for a P-channel BIGFET at an implant energy of approximately 30 keV.
  • the dopant 1600 may be an N + implant such as phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and the like, and may form heavily doped N 1' source/drain regions 120.
  • An N ' implant would be appropriate for the fabrication of an N-channel BIGFET 700, for example.
  • the dopant 1600 may be a P + implant such as boron (B), boron fluoride (BF, BF 2 ), aluminum (Al), gallium (Ga), Indium (In), Thallium (Tl), and the like, and may form heavily doped P + source/drain regions 120.
  • a P + implant would be appropriate for the fabrication of a P-channel BIGFET 700, for example.
  • the N + -doped (P + -doped) regions 1620 may be subjected to a rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 800-1100°C for a time ranging from approximately 5-60 seconds to form the N ⁇ -doped (P + -doped) source/drain regions 120.
  • RTA rapid thermal anneal
  • the rapid thermal anneal (RTA) process may activate the implant of the more mobile phosphorus (P) (for -ST ⁇ -doping appropriate for an N-channel BIGFET 700) or boron (B) (for P + -doping appropriate for a P-channel BIGFET 700) and form a less sharply defined and more graded activated implant junction with the p-type (n-type) semiconducting substrate 105 than would a rapid thermal anneal (RTA) process following an implant with a source/drain dose of less mobile As (for N ⁇ -doping appropriate for an N-channel BIGFET 700) or BF 2 (for P + -doping appropriate for a P-channel BIGFET 700).
  • P more mobile phosphorus
  • B for P + -doping appropriate for a P-channel BIGFET 700
  • a rapid thermal anneal (RTA) process to diffuse and activate the -doped (P + -doped) regions 1620 to form the N ⁇ -doped (P + -doped) source/drain regions 120 may be performed in conjunction with a self-aligned silicidation (salicidation) process (not shown), either prior to, during or following the salicidation.
  • a salicidation-conjoined rapid thermal anneal (RTA) process may be performed at a temperature ranging from approximately 800-1000°C for a time ranging from approximately 10-60 seconds.
  • a self-aligned silicidation (salicidation) process may be used in various of the illustrative embodiments described above in which both the spacers 125 and the self-alignment structure 710 comprise dielectric materials, such as silicon dioxide (Si0 2 ).
  • the suicides of the self-aligned silicidation (salicidation) process are less likely to form on dielectric materials such as silicon dioxide (Si0 2 ).
  • an N-channel (P-channel) BIGFET 1800 having the heavily P + -doped (lsT-doped) buried gate conductor 715 formed in the p-doped (n-doped) semiconducting substrate 105, may also have a buried dielectric structure 1810 formed above the heavily P + -doped (N-doped) buried gate conductor 715.
  • the buried dielectric structure 1810 may be formed, for example, by implanting molecular oxygen (0 2 ) into the p-doped (n-doped) semiconducting substrate 105, through the opening 1100 in the patterned masking layer 1110 ( Figure 11).
  • the molecular oxygen (0 2 ) may be implanted either before or after the dopant 1120 (indicated by arrows) is introduced into the p-doped (n-doped) semiconducting substrate 105.
  • the buried dielectric structure 1810 may then be formed, for example, by reacting the implanted molecular oxygen (0 2 ) with the silicon (Si) present in the p-doped (n-doped) semiconducting substrate 105 to form silicon dioxide (Si0 2 ).
  • Such an in situ silicon dioxide (Si0 2 ) formation process is the basis of the SIMOX process used to form silicon dioxide (Si0 2 ) in silicon-on-insulator (SOI) semiconducting devices.
  • the buried dielectric structure 1810 may be used to isolate the inversion layer in the channel region 800 ( Figure 8) further from the heavily P + -doped (-sT-doped) buried gate conductor 715 formed in the p-doped (n-doped) semiconducting substrate 105.
  • an N-channel (P-channel) BIGFET 1900 having the heavily P + -doped (NT-doped) buried gate conductor 715 formed in the p-doped (n-doped) semiconducting substrate 105, may also have a buried dielectric structure 1910 formed around, and encompassing, the heavily P + -doped (N-doped) buried gate conductor 715.
  • the buried dielectric structure 1910 may be formed, for example, by implanting molecular oxygen (0 2 ) into the p-doped (n-doped) semiconducting substrate 105, through the opening 1100 in the patterned masking layer 1110 ( Figure 11).
  • the molecular oxygen (0 2 ) may be implanted either before or after the dopant 1120 (indicated by arrows) is introduced into the p-doped (n-doped) semiconducting substrate 105.
  • the buried dielectric structure 1910 may then be formed, for example, by reacting the implanted molecular oxygen (0 2 ) with the silicon (Si) present in the p-doped (n-doped) semiconducting substrate 105 to form silicon dioxide (Si0 2 ).
  • Such an in situ silicon dioxide (Si0 2 ) formation process is the basis of the SIMOX process used to form silicon dioxide (Si0 2 ) in silicon-on-insulator (SOI) semiconducting devices.
  • an N-channel BIGFET 1900 may operate in the "on” state as follows.
  • the drain-source current 7 rfra , consider is positive (to the left) as electrons from the source 120S drift (indicated by the arrow) through an inversion layer in the channel region 800 (an N-channel) to the drain 120D, with a positive voltage V d r am > 0 present at the drain 120D.
  • the inversion layer in the channel region 800 is thought to form as holes are attracted to the periphery of the buried dielectric structure 1910 by the negative buried gate voltage V bU riedgate ⁇ V, ⁇ m sho t ⁇ 0 applied to the heavily P + -doped buried gate conductor 715.
  • the holes are attracted by the negative buried gate voltage V b r i e ga i e ⁇ V 'th r es h old ⁇ 0 applied to the heavily P + -doped buried gate conductor 715.
  • the buried dielectric structure 1910 may be used to isolate the inversion layer in the channel region 800 from the heavily P + -doped buried gate conductor 715 formed in the p-doped semiconducting substrate 105.
  • the holes attracted to the heavily P + -doped buried gate conductor 715 are not able to conduct into the heavily P + -doped buried gate conductor 715, since the buried dielectric structure 1910 is an insulator.
  • an N-channel BIGFET 2000 having a heavily -NT-doped buried gate conductor 2015 formed in the p-doped semiconducting substrate 105, may also have the buried dielectric structure 1910 formed around, and encompassing, the heavily N ⁇ -doped buried gate conductor 2015.
  • Such an N-channel BIGFET 2000 may operate in the "on" state as follows. In the "on" state, the buried gate voltage Vbu r i dgat > V t r sho l d > 0, where V thr hold is the threshold voltage for the (enhancement-type) N-channel BIGFET 2000.
  • the drain-source current I dr l is positive (to the left) as electrons from the source 120S drift (indicated by the arrow) through an inversion layer in a channel region 2005 (an N-channel) to the drain 120D, with a positive voltage V dram > 0 present at the drain 120D.
  • the inversion layer in the channel region 2005 is thought to form as electrons are attracted to the periphery of the buried dielectric structure 1910 by the positive buried gate voltage V bur i edg te > ⁇ --*w > 0 applied to the heavily -NT-doped buried gate conductor 2015.
  • V bur i edg te > ⁇ --*w > 0 applied to the heavily -NT-doped buried gate conductor 2015.
  • holes above the heavily N ⁇ -doped buried gate conductor 2015 are driven up to the underside of the self-alignment structure 710 near the upper surface 150 of the semiconducting substrate 105 by the positive buried gate voltage V bur i e gat > V thresho i > 0 applied to the heavily N ⁇ -doped buried gate conductor 2015.
  • the buried dielectric structure 1910 may be used to isolate the inversion layer in the channel region 2005 from the heavily -NT-doped buried gate conductor 2015 formed in the p-doped semiconducting substrate 105.
  • the electrons attracted to the heavily ]ST-doped buried gate conductor 2015 are not able to conduct into the heavily IST-doped buried gate conductor 2015, since the buried dielectric structure 1910 is an insulator.
  • spacers 2110 may be formed in the opening 1100 in the patterned masking layer 1110 ( Figure 11). The spacers 2110 form an opening 2100.
  • the opening 2100 may have a subcritical dimension d sk that may be in a range of about 50-500 A.
  • the subcritical dimension d sk may be smaller than the smallest, diffraction-limited critical dimension d k ( Figure 11) that may be in a range of about 150-1000 A.
  • the spacers 2110 may be formed in a manner similar to the formation of the spacers 125, described above with reference to Figure 15, and may be formed of any of the materials that may be used to form the spacers 125.
  • a P + -doped (N + -doped) buried gate conductor 2115 may be formed in the p-doped (n-doped) semiconducting substrate 105 by being implanted using a dopant 2120 (indicated by arrows) to introduce dopant atoms and/or molecules into the p-doped (n-doped) semiconducting substrate 105.
  • a dose of the dopant 2120 atoms and/or molecules may range from approximately 1.0 x 10 15 ions/cm 2 to approximately 5.0 x 10 15 ions/cm 2 of the appropriate dopant 2120 atoms and/or molecules, e.g., boron (B) for an illustrative P + -doped buried gate conductor 2115 or phosphorus (P) for an illustrative N + -doped buried gate conductor 2115.
  • An implant energy of the dopant 2120 atoms and/or molecules may range from approximately 100-1000 keV.
  • the dopant 2120 may be an N 1" implant such as phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and the like, and may form a heavily doped N ⁇ -doped buried gate conductor 2115.
  • the dopant 2120 may be a P + implant such as boron (B), boron fluoride (BF, BF 2 ), aluminum (Al), gallium (Ga), Indium (In), Thallium (Tl), and the like, and may form a heavily doped P + -doped buried gate conductor 2115.
  • the P + -doped (--T-doped) buried gate conductor 2115 may be formed to a depth e below the upper surface 150 of the p-doped (n-doped) semiconducting substrate 105 that may be in a range of about 100-1000 A. As shown in Figure 21, the P + -doped (-NT-doped) buried gate conductor 2115 may also have the subcritical dimension d sk that may be in a range of about 50-500 A. The P + -doped (N ⁇ -doped) buried gate conductor 2115 "inherits" the subcritical dimension d sk from the opening 2100 formed in the patterned masking layer 1110 using the spacers 2110.
  • an intrinsically-doped (i-doped) region 2215 may be formed in the p-doped (n-doped) semiconducting substrate 105 above the P + -doped (IsT-doped) buried gate conductor 2115 by being implanted using a complementary dopant 2220 (indicated by arrows) to introduce complementary dopant atoms and/or molecules into the p-doped (n-doped) semiconducting substrate 105.
  • An intrinsically-doped (i-doped) region could be formed in the p-doped (n-doped) semiconducting substrate 105, above the P + -doped (IST-doped) buried gate conductor 2115, whether or not the spacers 2110 are used in the opening 2100.
  • the introduction of complementary dopant atoms and/or molecules into the p-doped (n-doped) semiconducting substrate 105 is believed to "cancel out" the doping of the p-doped (n-doped) semiconducting substrate 105 in the intrinsically-doped (i-doped) region 2215.
  • a dose of the complementary dopant 2220 atoms and/or molecules may range from approximately 1.0 x 10 - 1.0 x 10 15 ions/cm 2 of the appropriate complementary dopant 2220 atoms and/or molecules.
  • boron (B) may be used for an illustrative n-doped semiconducting substrate 105 or phosphorus (P) for an illustrative p-doped semiconducting substrate 105.
  • An implant energy of the complementary dopant 2220 atoms and/or molecules may range from approximately 50-150 keV.
  • the complementary dopant 2220 may be an N-type implant such as phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and the like, and may substantially compensate for the doping of the p-doped semiconducting substrate 105, forming the intrinsically-doped (i-doped) region 2215.
  • N-type implant such as phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and the like, and may substantially compensate for the doping of the p-doped semiconducting substrate 105, forming the intrinsically-doped (i-doped) region 2215.
  • the complementary dopant 2220 may be a P-type implant such as boron (B), boron fluoride (BF, BF 2 ), aluminum (Al), gallium (Ga), Indium (In), Thallium (Tl), and the like, and may substantially compensate for the doping of the n-doped semiconducting substrate 105, forming the intrinsically-doped (i-doped) region 2215.
  • boron (B), boron fluoride (BF, BF 2 ), aluminum (Al), gallium (Ga), Indium (In), Thallium (Tl), and the like and may substantially compensate for the doping of the n-doped semiconducting substrate 105, forming the intrinsically-doped (i-doped) region 2215.
  • the intrinsically-doped (i-doped) region 2215 may also have the subcritical dimension d sk that may be in a range of about 50-500 A.
  • the intrinsically-doped (i-doped) region 2215 "inherits" the subcritical dimension d sk from the opening 2100 formed in the patterned masking layer 1110 using the spacers 2110.
  • the P + -doped (NT-doped) buried gate conductor 2115 and/or the intrinsically-doped (i-doped) region 2215 may be formed by diffusing and/or implanting the respective dopant atoms and or molecules through the upper surface 150 of the p-doped (n-doped) semiconducting substrate 105.
  • the respective dopant atoms and/or molecules may be diffused and/or implanted through the opening 2100 formed in the patterned masking layer 1110 using the spacers 2110.
  • the respective dopant atoms and/or molecules may then be subjected to a heat-treating process that may be a rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 800-1100°C for a time ranging from approximately 5-60 seconds.
  • RTA rapid thermal anneal
  • the semiconducting substrate 105 may be intrinsically-doped (i-doped).
  • an intrinsically-doped (i-doped) region such as the intrinsically-doped (i-doped) region 2215, may not have to be separately formed.
  • N ⁇ -doped (P + -doped) source/drain regions may be formed in portions of the patterned masking layer 1110 adjacent the opening 1100 ( Figure 11) or the opening 2100 ( Figure 21), respectively.
  • the - -T-doped (P + -doped) source/drain regions formed in the portions of the patterned masking layer 1110 adjacent the opening 1100 ( Figure 11) or the opening 2100 ( Figure 21) may be formed by diffusing and/or implanting the respective dopant atoms and/or molecules into the respective portions of the patterned masking layer 1110.
  • the respective dopant atoms and/or molecules may then be subjected to a heat-treating process that may be a rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 800-1100°C for a time ranging from approximately 5-60 seconds.
  • RTA rapid thermal anneal
  • the KT-doped (P + -doped) source/drain regions 120 may be formed in the p-doped (n-doped) semiconducting substrate 105 adjacent the self-alignment structure 710 ( Figure 7) or the self-alignment structure 2310 ( Figure 23) without using the spacers 125.
  • source/drain extension (SDE) regions such as the N ' -doped (P ' -doped) source/drain extension (SDE) regions 130, may not have to be formed.
  • an N-channel BIGFET 2300 may be formed in a semiconducting substrate 105, such as p-doped silicon (Si).
  • the N-channel BIGFET 2300 may have a doped gate conductor such as a P + -doped buried gate conductor 2115 formed in the p-doped semiconducting substrate 105, below the intrinsically-doped (i-doped) region 2215, and also below a self-alignment structure 2310 formed above the upper surface 150 of the semiconducting substrate 105.
  • a doped gate conductor such as a P + -doped buried gate conductor 2115 formed in the p-doped semiconducting substrate 105, below the intrinsically-doped (i-doped) region 2215, and also below a self-alignment structure 2310 formed above the upper surface 150 of the semiconducting substrate 105.
  • the self-alignment structure 2310 may be separated from active areas such as N + -doped source/drain regions 120 of the N-channel BIGFET 2300 by spacers 125.
  • the spacers 125 may be formed above N ' -doped source/drain extension (SDE) regions 130.
  • SDE source/drain extension
  • shallow trench isolation (STI) regions 140 may be provided to isolate the N-channel BIGFET 2300 electrically from neighboring semiconductor devices such as other BIGFETs and/or MOS transistors, and the like (not shown).
  • the N-channel BIGFET 2300 having the heavily P + -doped buried gate conductor 2115 formed in a p-doped semiconducting substrate 105 below the intrinsically-doped (i-doped) region 2215, may operate in the "off state as follows.
  • the buried gate voltage V bl ⁇ rledga , e 0 (or, more precisely, V b , lriedga , e is greater than or equal to V, lmsho!d , where V threshold is the threshold voltage for the BIGFET 2300), and the drain-source current I drain is approximately zero, even with a positive voltage V dram > 0 present at the drain 120D.
  • the positive voltage V dram > 0 present at the drain 120D and the grounding of the source 120S cause depletion regions 160 (shown in phantom) to form in portions of the p-type semiconducting substrate 105 adjacent the drain 120D and source 120S, and in portions of the drain 120D and source 120S, as well.
  • the depletion regions 160 may be about the same size on either side of the heavily P + -doped buried gate conductor 2115, and may be prevented from growing larger by the presence of the heavily P + -doped buried gate conductor 2115.
  • the channel length l sk of the N-channel BIGFET 2300 may be the subcritical dimension d sk , about the distance between N ' -doped source/drain extension (SDE) regions 130, as shown in Figure 23.
  • the N-channel BIGFET 2300 having the heavily P + -doped buried gate conductor 2115 formed in a p-doped semiconducting substrate 105 below the intrinsically-doped (i-doped) region 2215, may operate in the "on” state as follows. In the "on” state, the buried gate voltage Vburiedgate ⁇ Vihre hotd ⁇ 0, where Vt resiwid is the threshold voltage for the (enhancement-type) N-channel BIGFET 2300.
  • the drain-source current I dram is positive (to the left) as electrons from the source 120S drift (indicated by the arrow) through an inversion layer in a channel region 2400 (an N-channel) to the drain 120D, with a positive voltage V dra ⁇ consult > 0 present at the drain 120D.
  • the inversion layer in the channel region 2400 is thought to form as holes in the intrinsically-doped (i-doped) region 2215 above the heavily P + -doped buried gate conductor 2115 are attracted to the heavily P + -doped buried gate conductor 2115.
  • the holes are attracted by the negative buried gate voltage Vbu r ied gate ⁇ V t resho i d ⁇ 0 applied to the heavily P + -doped buried gate conductor 2115.
  • a depletion region 2460 is believed to form adjacent the heavily P + -doped buried gate conductor 2115 as mobile holes are attracted by the negative buried gate voltage V bur i edgate ⁇ V, hresh0 ⁇ d ⁇ 0 applied to the heavily P + -doped buried gate conductor 2115 and as mobile electrons are driven away.
  • a polarized/depleted region 2415 is believed to form above the heavily P + -doped buried gate conductor 2115 and below the N-channel inversion layer in the channel region 2400.
  • the polarized/depleted region 2415 is believed to form as mobile holes from the intrinsically-doped (i-doped) region 2215 are attracted by the negative buried gate voltage V u i edg te ⁇ V threshold 0 applied to the heavily P + -doped buried gate conductor 2115 and as mobile electrons from intrinsically-doped (i-doped) region 2215 are driven away.
  • the effective channel length l sk of the N-channel BIGFET 2300 may be the subcritical dimension d sk , about the distance between N ' -doped source/drain extension (SDE) regions 130, as shown in Figure 24.
  • any of the above-disclosed embodiments of a method of manufacturing semiconductor devices with reduced critical dimensions enables the formation and patterning of components such as gate conductors on much reduced scales, consistently, robustly and reproducibly, and in a self-aligned manner.
  • Any of the above-disclosed embodiments of a method of manufacturing semiconductor devices with reduced critical dimensions enables the achievement of reduced critical dimensions using fewer and/or simpler fabrication techniques, decreasing manufacturing costs and increasing throughput, more effectively and more stably than with conventional techniques.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne un procédé qui consiste à: former une couche de masque (1110) au-dessus d'un substrat, former une ouverture (1100, 2100) dans la couche de masque (1110), l'ouverture (1100, 2100) définissant une région de canal (800, 2005, 2400) dans la couche (105) de substrat, puis à former un conducteur (715, 2015, 2115) à grille enfouie dans la couche (105) de substrat sous la région de canal (800, 2005, 2400), l'ouverture (1100, 2100) étant utilisée pour effectuer l'auto-alignement du conducteur (715, 2015, 2115) à grille enfouie. Ce procédé consiste également à former des régions de source/drain (120S, 120D) adjacentes à la région de canal (800, 2005, 2400).
PCT/US2001/040862 2000-06-16 2001-06-06 Transistor a effet de champ a grille inversee enfouie (bigfet) WO2001097290A2 (fr)

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EP0905761A3 (fr) * 1997-08-29 2005-01-26 Texas Instruments Inc. Procédé de fabrication d'un transistor à effet de champ

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