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WO2001097290A3 - Transistor a effet de champ a grille inversee enfouie (bigfet) - Google Patents

Transistor a effet de champ a grille inversee enfouie (bigfet) Download PDF

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Publication number
WO2001097290A3
WO2001097290A3 PCT/US2001/040862 US0140862W WO0197290A3 WO 2001097290 A3 WO2001097290 A3 WO 2001097290A3 US 0140862 W US0140862 W US 0140862W WO 0197290 A3 WO0197290 A3 WO 0197290A3
Authority
WO
WIPO (PCT)
Prior art keywords
bigfet
effect transistor
gate field
inverted gate
forming
Prior art date
Application number
PCT/US2001/040862
Other languages
English (en)
Other versions
WO2001097290A2 (fr
Inventor
John A Iacoponi
Thomas E Spikes Jr
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to AU2001267034A priority Critical patent/AU2001267034A1/en
Publication of WO2001097290A2 publication Critical patent/WO2001097290A2/fr
Publication of WO2001097290A3 publication Critical patent/WO2001097290A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/023—Manufacture or treatment of FETs having insulated gates [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H10D30/615—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel comprising a MOS gate electrode and at least one non-MOS gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/018—Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0217—Manufacture or treatment of FETs having insulated gates [IGFET] forming self-aligned punch-through stoppers or threshold implants under gate regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/721—Insulated-gate field-effect transistors [IGFET] having a gate-to-body connection, i.e. bulk dynamic threshold voltage IGFET 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

La présente invention concerne un procédé qui consiste à: former une couche de masque (1110) au-dessus d'un substrat, former une ouverture (1100, 2100) dans la couche de masque (1110), l'ouverture (1100, 2100) définissant une région de canal (800, 2005, 2400) dans la couche (105) de substrat, puis à former un conducteur (715, 2015, 2115) à grille enfouie dans la couche (105) de substrat sous la région de canal (800, 2005, 2400), l'ouverture (1100, 2100) étant utilisée pour effectuer l'auto-alignement du conducteur (715, 2015, 2115) à grille enfouie. Ce procédé consiste également à former des régions de source/drain (120S, 120D) adjacentes à la région de canal (800, 2005, 2400).
PCT/US2001/040862 2000-06-16 2001-06-06 Transistor a effet de champ a grille inversee enfouie (bigfet) WO2001097290A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001267034A AU2001267034A1 (en) 2000-06-16 2001-06-06 Buried inverted gate field-effect transistor (bigfet)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59597700A 2000-06-16 2000-06-16
US09/595,977 2000-06-16

Publications (2)

Publication Number Publication Date
WO2001097290A2 WO2001097290A2 (fr) 2001-12-20
WO2001097290A3 true WO2001097290A3 (fr) 2002-08-15

Family

ID=24385491

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/040862 WO2001097290A2 (fr) 2000-06-16 2001-06-06 Transistor a effet de champ a grille inversee enfouie (bigfet)

Country Status (2)

Country Link
AU (1) AU2001267034A1 (fr)
WO (1) WO2001097290A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4604444B2 (ja) * 2002-12-24 2011-01-05 トヨタ自動車株式会社 埋設ゲート型半導体装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55132072A (en) * 1979-03-31 1980-10-14 Toshiba Corp Mos semiconductor device
JPS5783059A (en) * 1980-11-11 1982-05-24 Toshiba Corp Manufacture of mos type semiconductor device
JPS63308385A (ja) * 1987-06-10 1988-12-15 Fuji Electric Co Ltd 埋込みゲ−ト型電界効果トランジスタの製造方法
US5371024A (en) * 1988-09-30 1994-12-06 Kabushiki Kaisha Toshiba Semiconductor device and process for manufacturing the same
US5602403A (en) * 1991-03-01 1997-02-11 The United States Of America As Represented By The Secretary Of The Navy Ion Implantation buried gate insulator field effect transistor
US5661051A (en) * 1996-10-09 1997-08-26 National Science Council Method for fabricating a polysilicon transistor having a buried-gate structure
EP0905761A2 (fr) * 1997-08-29 1999-03-31 Texas Instruments Inc. Procédé de fabrication d'un transistor à effet de champ
US5912497A (en) * 1997-08-06 1999-06-15 North Carolina State University Semiconductor switching devices having buried gate electrodes and methods of forming same
US6043535A (en) * 1997-08-29 2000-03-28 Texas Instruments Incorporated Self-aligned implant under transistor gate

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55132072A (en) * 1979-03-31 1980-10-14 Toshiba Corp Mos semiconductor device
JPS5783059A (en) * 1980-11-11 1982-05-24 Toshiba Corp Manufacture of mos type semiconductor device
JPS63308385A (ja) * 1987-06-10 1988-12-15 Fuji Electric Co Ltd 埋込みゲ−ト型電界効果トランジスタの製造方法
US5371024A (en) * 1988-09-30 1994-12-06 Kabushiki Kaisha Toshiba Semiconductor device and process for manufacturing the same
US5602403A (en) * 1991-03-01 1997-02-11 The United States Of America As Represented By The Secretary Of The Navy Ion Implantation buried gate insulator field effect transistor
US5661051A (en) * 1996-10-09 1997-08-26 National Science Council Method for fabricating a polysilicon transistor having a buried-gate structure
US5912497A (en) * 1997-08-06 1999-06-15 North Carolina State University Semiconductor switching devices having buried gate electrodes and methods of forming same
EP0905761A2 (fr) * 1997-08-29 1999-03-31 Texas Instruments Inc. Procédé de fabrication d'un transistor à effet de champ
US6043535A (en) * 1997-08-29 2000-03-28 Texas Instruments Incorporated Self-aligned implant under transistor gate

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 004, no. 189 (E - 039) 25 December 1980 (1980-12-25) *
PATENT ABSTRACTS OF JAPAN vol. 006, no. 164 (E - 127) 27 August 1982 (1982-08-27) *
PATENT ABSTRACTS OF JAPAN vol. 013, no. 147 (E - 741) 11 April 1989 (1989-04-11) *

Also Published As

Publication number Publication date
AU2001267034A1 (en) 2001-12-24
WO2001097290A2 (fr) 2001-12-20

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