WO2001097290A2

WO2001097290A2 - Buried inverted gate field-effect transistor (bigfet)

Info

Publication number: WO2001097290A2
Application number: PCT/US2001/040862
Authority: WO
Inventors: John A. Iacoponi; Thomas E. Spikes, Jr.
Original assignee: Advanced Micro Devices, Inc.
Priority date: 2000-06-16
Filing date: 2001-06-06
Publication date: 2001-12-20
Also published as: AU2001267034A1; WO2001097290A3

Abstract

A method is provided, the method comprising forming a masking layer (1110) above a substrate layer (105), forming an opening (1100, 2100) in the masking layer (1110), the opening (1100, 2100) defining a channel region (800, 2005, 2400) in the substrate layer (105), and forming a buried gate conductor (715, 2015, 2115) in the substrate layer (105) below the channel region (800, 2005, 2400), using the opening (1100, 2100) to self-align the buried gate conductor (715, 2015, 2115). The method also comprises forming source/drain regions (120S, 120D) adjacent the channel region (800, 2005, 2400).

Description

BURIED INVERTED GATE FIELD-EFFECT TRANSISTOR (BIGFET)

TECHNICAL FIELD

This invention relates generally to semiconductor fabrication technology, and, more particularly, to techniques for manufacturing a semiconductor devices having a reduced critical dimension.

BACKGROUND ART

There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.

However, reducing the size, or scale, of the components of a typical transistor also requires being able to form and pattern components such as the gate conductor and gate dielectric on such reduced scales, consistently, robustly and reproducibly, preferably in a self-aligned manner. The ability to form and pattern components such as the gate conductor and gate dielectric on such reduced scales, consistently, robustly and reproducibly, is limited by, among other things, physical limits imposed by photolithography. Diffraction effects impose limits on the critical dimensions of components such as gate conductors and gate dielectrics that correspond roughly to the wavelengths of the light used to perform the photolithography.

A conventional approach to achieving reduced critical dimensions, used with or without resorting to expensive deep ultraviolet (DUN) photolithography and/or in high-energy electron beam lithography, is schematically illustrated in Figures 1-4. As shown in Figure 1, for example, a conventional "metal oxide semiconductor" field-effect (MOSFET or MOS) transistor 100 may be formed on a semiconducting substrate 105, such as doped-silicon (Si). The MOS transistor 100 may have a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor 115, such as an ^doped-poly (P⁺-doped-poly) gate conductor 115, formed above a gate dielectric 110 that is formed above the semiconducting substrate 105. The Ν^-doped-poly (P⁺-doped-poly) gate conductor 115 and the gate dielectric 110 may be separated from active areas such as Ν^-doped (P⁺-doped) source/drain regions 120 of the MOS transistor 100 by dielectric spacers 125. The dielectric spacers 125 may be formed above -ΝT-doped (P^"-doped) source/drain extension (SDE) regions 130. As shown in Figure 1, shallow trench isolation (STI) regions 140 may be provided to isolate the MOS transistor 100 electrically from neighboring semiconductor devices such as other MOS transistors (not shown).

The Ν^"-doped (P^"-doped) SDE regions 130 are typically provided to reduce the magnitude of the maximum channel electric field found close to the .sT-doped (P⁺-doped) source/drain regions 120 of the MOS transistor 100, and, thereby, to reduce the associated hot-carrier effects. The lower doping of the N^"-doped (P^"-doped) SDE regions 130, relative to the N⁺-doped (P⁺-doped) source/drain regions 120 of the MOS transistor 100 (typically lower by at least a factor of two or three), reduces the magnitude of the maximum channel electric field found close to the -ST^-doped (P⁺-doped) source/drain regions 120 of the MOS transistor 100, but increases the source-to-drain resistances of the N^"-doped (P^"-doped) SDE regions 130.

As shown in Figure 1, typically the N⁺-doped-poly (P⁺-doped-poly) gate conductor 115 and the gate dielectric 110 have a critical dimension D_t that effectively determines a channel length L of the MOS transistor 100. The channel length L is approximately the distance between the N^"-doped (P^"-doρed) SDE regions 130 adjacent the N^-doped-poly (P⁺-doped-poly) gate conductor 115 and the gate dielectric 110.

As shown in Figures 2-4, typically the critical dimension D_t of the N⁺-doped-poly (P⁺-doped-poly) gate conductor 115 and the gate dielectric 110 is determined as follows. As shown in Figure 2, a gate dielectric layer 210 is formed above the semiconducting substrate 105, and a gate conductor layer 215 is formed above the gate dielectric layer 210. An antireflective coating (ARC) layer 230 is formed above the gate conductor layer 215, and a photoresist layer 220 is formed and patterned, using conventional, non-deep ultraviolet (non-DUV) photolithography, above the antireflective coating (ARC) layer 230. The photoresist layer 220 is patterned to have the smallest, diffraction-limited dimension D that may be achieved with existing technology, for example, a smallest, diffraction-limited dimension D in a range of about 1000-2000 A. Of course, resorting to expensive deep ultraviolet (DUN) photolithography and/or in high-energy electron beam lithography, the smaller effective wavelengths may result in even smaller dimensions.

As shown in Figure 3, the patterned photoresist layer 220 (indicated in phantom) is trimmed using a controlled photoresist trim to form a trimmed photoresist mask 320. The patterned photoresist layer 220 may be trimmed using any of the processes known to those skilled in the art, having the benefit of the present disclosure. The trimmed photoresist mask 320 will typically have the critical dimension D_t that may be in a range of about 500-1000 A that will determine the approximate size of the Ν⁺-doped-poly (P⁺-doped-poly) gate conductor 115 and the gate dielectric 110, following appropriate patterning processes.

As shown in Figure 4, the trimmed photoresist mask 320, having the critical dimension D_t, is used as a mask to remove respective portions 430, 415 and 410 (shown in phantom) from the antireflective coating (ARC) layer 230, gate conductor layer 215 and the gate dielectric layer 210 (Figures 2-3), respectively, to form a gate structure 400 that includes the -ST^-doped-poly (P⁺-doρed-poly) gate conductor 115 and the gate dielectric 110. The gate structure 400, and, hence, the N^-doped-poly (P⁺-doped-poly) gate conductor 115 and the gate dielectric 110, will also have the critical dimension D_t defined by the trimmed photoresist mask 320.

Nevertheless, the critical dimension D_t defined by the trimmed photoresist mask 320 is still too large. Further trimming of the trimmed photoresist mask 320 will not be sufficiently controllable, reliable or feasible to be able to be used to form and pattern components such as gate conductors and gate dielectrics on even more reduced scales, consistently, robustly and reproducibly, preferably in a self-aligned manner. As shown in Figures 2-4, the conventional techniques to form the gate structure 400 typically involve forming and patterning layers of materials and then wastefully subtracting and/or etching away most of those materials to leave a narrow and fragile positive feature having the critical dimension D_t, defined by the trimmed photoresist mask 320, that is still too large.

As shown in Figure 5, a conventional N-channel MOS (NMOS) transistor 100 may operate in the "off state as follows. In the "off state, the gate voltage V_gale = 0 (or, more precisely, V_gale is less than or equal to ^t_hreshold, where V threshold is the threshold voltage for the conventional NMOS transistor 100), and the drain-source current is approximately zero, even with a positive voltage (V_dml„ > 0) present at the drain 120D. The source 120S is typically grounded (K_SD„_rce = 0), and the p-type semiconducting substrate 105 may either be grounded or have a bias applied thereto (not shown). The positive voltage (V_draln > 0) present at the drain 120D causes a drain depletion region 160D (shown in phantom) to form in a portion of the p-type semiconducting substrate 105 adjacent the drain 120D, and in a portion of the drain 120D, as well. The drain depletion region 160D is typically larger than a source depletion region 160S (shown in phantom) that forms in a portion of the p-type semiconducting substrate 105 adjacent the source 120S, and in a portion of the source 120S, as well. An effective channel length L_f of the MOS transistor 100 is the distance between the drain depletion region 160D and the source depletion region 160S.

As shown in Figure 6, a conventional N-channel MOS (NMOS) transistor 100 may operate in the "on" state as follows. In the "on" state, the gate voltage V_gale > V_thresMd > 0, where V,_hreshotd is the threshold voltage for the (enhancement-type) NMOS transistor 100. In the "on" state, the drain-source current I_dmi„ is positive (to the left) as electrons from the source 120S drift (indicated by the arrow) through an inversion layer 600 (an N-channel) to the drain 120D, with a positive voltage V_drai„ > 0 present at the drain 120D. The inversion layer 600 is thought to form as electrons are attracted to the underside of the gate dielectric 110 by the positive gate voltage V_g t_e > V,_{hres otd} ^> 0 applied to the lST^-doped-poly gate conductor 115. The electrons attracted to the underside of the gate dielectric 110 are not able to conduct into the N^-doped-poly gate conductor 115, since the gate dielectric 110 is an insulator. Again, the effective channel length L_f of the MOS transistor 100 for the electrons drifting through the.N-channel inversion layer 600 is the distance between the drain depletion region 160D and the source depletion region 160S.

This reduction of the effective channel length L_£ of the MOS transistor 100 increases "short-channel" effects, almost by definition, as well as "edge effects" that are relatively unimportant in long channel MOS transistors. Short-channel effects include, among other things, an increased drain-source leakage current when the MOS transistor is supposed to be switched "off," believed to be due to an enlarged depletion region relative to the shorter channel length.

The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.

DISCLOSURE OF INVENTION

In one aspect of the present invention, a method is provided, the method comprising forming a masking layer above a substrate layer, forming an opening in the masking layer, the opening defining a channel region in the substrate layer, and forming a buried gate conductor in the substrate layer below the channel region, using the opening to self-align the buried gate conductor. The method also comprises forming source/drain regions adjacent the channel region.

In another aspect of the present invention, a semiconductor device is provided, formed by a method comprising forming a masking layer above a substrate layer, forming an opening in the masking layer, the opening defining a channel region in the substrate layer, and forming a buried gate conductor in the substrate layer below the channel region, using the opening to self-align the buried gate conductor. The method also comprises forming source/drain regions adjacent the channel region.

In yet another aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising a substrate layer having a channel region, and source/drain regions adjacent the channel region. The semiconductor device also comprises a buried gate conductor in the substrate layer below the channel region. BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which the leftmost significant digit(s) in the reference numerals denote(s) the first figure in which the respective reference numerals appear, and in which:

Figures 1-6 illustrate schematically in cross-section conventional semiconductor devices and/or techniques for fabricating the same; and

Figures 7-24 illustrate schematically various embodiments of a semiconductor device and/or a method for semiconductor device fabrication, according to the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

MODE(S) FOR CARRYING OUT THE INVENTION

Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

Illustrative embodiments of a semiconductor device and/or a method for semiconductor device fabrication, according to the present invention, are shown in Figures 7-24. Although the various regions and structures of a semiconductor device are depicted in the drawings as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Nevertheless, the attached drawings are included to provide illustrative examples of the present invention.

In general, the present invention is directed towards the manufacture of a semiconductor device. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of technologies, for example, NMOS, PMOS, CMOS, and the like, and is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, and the like.

As shown in Figure 7, in various illustrative embodiments, a buried inverted gate field-effect transistor (BIGFET) 700 may be formed in a semiconducting substrate 105, such as p-doped (n-doped) silicon (Si). The BIGFET 700 may have a doped buried gate conductor such as a P⁺-doped (IS^-doped) buried gate conductor 715 formed in the p-doped (n-doped) semiconducting substrate 105, below a self-alignment structure 710 formed above an upper surface 150 of the semiconducting substrate 105. In various illustrative embodiments, a P⁺-doped (N⁺-doped) buried gate conductor 715, formed in a p-doped (n-doped) semiconducting substrate 105, may be used to form an N-channel (P-channel) BIGFET 700, as shown, for example, in Figures 7-9, 19, 23 and 24. In various alternative illustrative embodiments, an N^-doped (P⁺-doped) buried gate conductor 715, formed in a p-doped (n-doped) semiconducting substrate 105, may be used to form an N-channel (P-channel) BIGFET 700, as shown, for example, in Figure 20. The self-alignment structure 710 may be separated from active areas, such as N-doped (P⁺-doped) source/drain regions 120 of the BIGFET 700, by spacers 125. The spacers 125 may be formed above N^'-doped (P^"-doped) source/drain extension (SDE) regions 130. As shown in Figure 7, shallow trench isolation (STI) regions 140 may be provided to isolate the BIGFET 700 electrically from neighboring semiconductor devices such as other BIGFETs and/or MOS transistors, and the like (not shown).

As shown in Figure 7, in various illustrative embodiments, an N-channel BIGFET 700, having a heavily P⁺-doped buried gate conductor 715 formed in a p-doped semiconducting substrate 105, may operate in the "off state as follows. In the "off state, the buried gate voltage V_buriedga,_e = 0 (or, more precisely, V_bmκ- _dgale is greater than or equal to V-_h^_hoU, where V _{t reshold} is the threshold voltage for the BIGFET 700), and the drain-source current I_drai„ is approximately zero, even with a positive voltage V _ram > 0 present at the drain 120D. The source 120S is typically grounded (V_smιrce = 0), and the p-type semiconducting substrate 105 may either be grounded or have a bias applied thereto (not shown). The positive voltage V _m\„ > 0 present at the drain 120D and the grounding of the source 120S cause depletion regions 160 (shown in phantom) to form in portions of the p-type semiconducting substrate 105 adjacent the drain 120D and source 120S, and in portions of the drain 120D and source 120S, as well. The depletion regions 160 may be about the same size on either side of the heavily P⁺-doped buried gate conductor 715, and may be prevented from growing larger by the presence of the heavily P⁺-doped buried gate conductor 715. An effective channel length 1 of the N-channel BIGFET 700 may be the distance between the depletion regions 160, as shown in Figure 8. The effective channel length 1 of the N-channel BIGFET 700 may be about equal to the smallest critical dimension d_k of the self-alignment structure 710 of the N-channel BIGFET 700.

As shown in Figure 8, in various illustrative embodiments, the N-channel BIGFET 700, having the heavily P⁺-doped buried gate conductor 715 formed in the p-doped semiconducting substrate 105, may operate in the "on" state as follows. In the "on" state, the buried gate voltage Vbu iedg e < ^threshold < 0_> where V„_mshoid is the threshold voltage for the (enhancement-type) N-channel BIGFET 700. In the "on" state, the drain-source current I_dram is positive (to the left) as electrons from the source 120S drift (indicated by the arrow) through an inversion layer in a channel region 800 (an N-channel) to the drain 120D, with a positive voltage V_drai„ > 0 present at the dram 120D. The inversion layer in the channel region 800 is thought to form as holes in the p-doped semiconducting substrate 105 above the heavily P⁺-doped buried gate conductor 715 are attracted to the heavily P⁺-doped buried gate conductor 715. The holes are attracted by the negative buried gate voltage Vburi gate *^ V_lhr shoi ^< ^ applied to the heavily P⁺-doped buried gate conductor 715. Similarly, and substantially simultaneously, electrons above the heavily P⁺-doped buried gate conductor 715 are driven up to the underside of the self-alignment structure 710 near the upper surface 150 of the semiconducting substrate 105 by the negative buried gate voltage Vb_uriedgaιe < V_{threS 0}i_d ^< Q applied to the heavily P⁺-doped buried gate conductor 715. A depletion region 860 is believed to form adjacent the heavily P⁺-doped buried gate conductor 715 as mobile holes are attracted by the negative gate voltage buried Vb_mi_edgate < V _{r shotd} < 0 applied to the heavily P⁺-doped buried gate conductor 715 and as mobile electrons are driven away. Again, the effective channel length 1 of the N-channel BIGFET 700 for the electrons drifting through the N-channel inversion layer in the channel region 800 is the distance between the depletion regions 160.

A top view of the N-channel BIGFET 700 is shown schematically in Figure 9. A heavily P⁺-doped (N^-doped) well 905 may be formed in the p-doped semiconducting substrate 105. As shown in Figure 10, the heavily P⁺-doped well 905 may be formed adjacent the self-alignment structure 710. The heavily P⁺-doped well 905 may extend from the upper surface 150 of the semiconducting substrate 105 down into the semiconducting substrate 105 to provide an electrical contact with the heavily P⁺-doped buried gate conductor 715. The heavily P⁺-doped buried gate conductor 715 extends under the self-alignment structure 710 and into the heavily P⁺-doped well 905 to provide the electrical contact for the application of the buried gate voltage V_{bu kdga}i_e < _{th esho}i_d < 0. The depletion region 860 is also schematically illustrated in Figure 9. The cross-sectional view as shown in Figure 7 is taken along the line VII- VII of Figure 9, and the cross-sectional view as shown in Figure 10, is taken along the line X-X of Figure 9.

Figures 11-17 illustrate a method of forming a BIGFET 700 (Figure 7) according to the present invention. As shown in Figure 11, shallow trench isolation (STI) regions 140 formed of suitable dielectric materials may be provided to isolate the BIGFET 700 (Figure 7) electrically from neighboring semiconductor devices such as other BIGFET and/or MOS transistors (not shown). The shallow trench isolation (STI) regions 140 may, for example, comprise an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (Si0₂), a nitrogen-bearing oxide (e.g., nitrogen-bearing Si0₂), a nitrogen-doped oxide (e.g., N₂-implanted Si0₂), silicon oxynitride (Si_xO_yN_z), and the like. The shallow trench isolation (STI) regions 140 may also be formed of any suitable "high dielectric constant" or "high K" material, where K is greater than or equal to about 8, such as titanium oxide (Ti_xO_y, e.g., Ti0₂), tantalum oxide (Ta_xO_y, e.g., Ta₂0₅), barium strontium titanate (BST, BaTi0₃/SrTi0₃), and the like. Alternatively, the shallow trench isolation (STI) regions 140 may also be formed of any suitable "low dielectric constant" or "low K" dielectric material, where K is less than or equal to about 4. Examples include Applied Material's Black Diamond^®, Novellus' Coral^®, Allied Signal's Nanoglass^®, JSR's LKD5104, and the like.

As shown in Figure 11, a patterned masking layer 1110 may be formed and patterned above the upper surface 150 of the p-doped (n-doped) semiconducting substrate 105, such as doped-silicon (Si). The patterned masking layer 1110 may be formed by a variety of known techniques for forming such layers, e.g, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering and physical vapor deposition (PVD), thermal growing, and the like. The patterned masking layer 1110 may have a thickness q above the upper surface 150 ranging from approximately 1000-5000 A, for example. The patterned masking layer 1110 may be formed from a variety of dielectric materials such as, for example, an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (Si0₂), a nitrogen-bearing oxide (e.g., nitrogen-bearing Si0₂), a nitrogen-doped oxide (e.g, N₂-implanted Si0₂), silicon oxynitride (Si_xO_yN₂), and the like. In various alternative illustrative embodiments, the patterned masking layer 1110 may be formed of photoresist, and the like.

As shown in Figure 11, the patterned masking layer 1110 may be patterned to form an opening 1100 using photolithography, for example. As shown in Figure 11, the opening 1100 formed in the patterned masking layer 1110 may have the smallest, diffraction-limited dimension d_k that may be achieved with present-day technology. For example, in various illustrative embodiments, a diffraction-limited dimension d_k in a range of about 250-1000 A may be achieved. In various alternative illustrative embodiments, an even smaller, diffraction-limited dimension d_k in a range of about 150-1000 A may be achieved, using phase-shifted masking techniques.

As shown in Figure 11, the P⁺-doped (N⁺-doped) buried gate conductor 715 may be formed in the p-doped (n-doped) semiconducting substrate 105 by being implanted using a dopant 1120 (indicated by arrows) to introduce dopant atoms and/or molecules into the p-doped (n-doped) semiconducting substrate 105. In one illustrative embodiment, a dose of the dopant 1120 atoms and/or molecules may range from approximately 1.0 x 10¹⁵ - 5.0 x 10¹⁵ ions/cm² of the appropriate dopant 1120 atoms and/or molecules, e.g., boron (B) for an illustrative P⁺-doped buried gate conductor 715 or phosphorus (P) for an illustrative N^-doped buried gate conductor 715. An implant energy of the dopant 1120 atoms and/or molecules may range from approximately 100-1000 keV. The P⁺-doped (NT-doped) buried gate conductor 715 may have a peak dopant 1120 concentration in a range of from about 1.0xlO^I9-1.0xl0²¹ atoms and/or molecules per cm³.

The dopant 1120 may be an N^1" implant such as phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and the like, and may form a heavily doped N⁺-doped buried gate conductor 715. Alternatively, the dopant 1120 may be a P⁺ implant such as boron (B), boron fluoride (BF, BF₂), aluminum (Al), gallium (Ga), Indium (In), Thallium (Tl), and the like, and may form a heavily doped P⁺-doped buried gate conductor 715.

As shown in Figure 11, the P⁺-doped (N⁺-doped) buried gate conductor 715 may be formed to a depth e below the upper surface 150 of the p-doped (n-doped) semiconducting substrate 105 that may be in a range of about 100-1000 A. As shown in Figure 11, the P⁺-doped (N-doped) buried gate conductor 715 may also have a width that corresponds approximately to the critical dimension d_k that may be in a range of about 150-1000 A. The P⁺-doped (N⁺-doped) buried gate conductor 715 "inherits" the smallest, diffraction-limited critical dimension d_k from the opening 1100 formed in the patterned masking layer 1110.

As shown in Figure 12, the self-alignment structure 710 formed above the upper surface 150 of the semiconducting substrate 105 may be formed in the opening 1100 in the patterned masking layer 1110. The self-alignment structure 710 may be formed by a variety of known techniques for forming such layers, e.g., chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering and physical vapor deposition (PVD), thermal growing, spin-on-glass, and the like, and may have a thickness q_p ranging from approximately 1000-5000 A, for example. The thickness q_p of the self-alignment structure 710 may be about the same as the thickness q of the patterned masking layer 1110. The self-alignment structure 710 may be formed in the opening 1100 in the patterned masking layer 1110 by being planarized, for example, by chemical mechanical polishing (CMP).

The self-alignment structure 710 may, for example, comprise an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (Si0₂), a nitrogen-bearing oxide (e.g., nitrogen-bearing Si0₂), a nitrogen-doped oxide (e.g., N₂-implanted Si0₂), silicon oxynitride (Si_xO_yN_z), and the like. The self-alignment structure 710 may also be formed of any suitable "high dielectric constant" or "high K" material, where K is greater than or equal to about 8, such as titanium oxide (Ti_xO_y, e.g., Ti0₂), tantalum oxide (Ta_xO_y, e.g., Ta₂0₅), barium strontium titanate (BST, BaTi0₃/SrTi0₃), and the like. Alternatively, the self-alignment structure 710 may also be formed of any suitable "low dielectric constant" or "low K" dielectric material, where K is less than or equal to about 4. Examples include Applied Material's Black Diamond^®, Novellus' Coral^®, Allied Signal's Nanoglass^®, JSR's LKD5104, and the like.

In various alternative illustrative embodiments, the self-alignment structure 710 may be formed of a conductive material. The conductive self-alignment structure 710 may be formed by a variety of known techniques, e.g., high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, PVD, CVD, LPCVD, PECVD, and the like, and may have a thickness q_p ranging from approximately 1000-5000 A, for example. The conductive self-alignment structure 710 may be formed of a variety of metals such as aluminum (Al), titanium (Ti), zirconium (Zr), tungsten (W), tantalum (Ta), nickel (Ni), molybdenum (Mo), cobalt (Co), copper (Cu), and the like.

In various other alternative illustrative embodiments, the self-alignment structure 710 may be formed of polycrystalline silicon (poly). The poly self-alignment structure 710 may be formed by a variety of known techniques for forming such layers, e.g., CVD, LPCVD, PECVD, PVD, and the like, and may have a thickness q_p ranging from approximately 1000-5000 A, for example. In one illustrative embodiment, the poly self-alignment structure 710 has a thickness of approximately 3000 A and is formed by an LPCVD process for higher throughput.

As shown in Figure 13, in various illustrative embodiments, the self-alignment structure 710 may be comprised of a material that may be selectively removed with respect to the material of the patterned masking layer 1110. The patterned masking layer 1110 may then be selectively removed, leaving the isolated self-alignment structure 710 formed above the upper surface 150 of the p-doped (n-doped) semiconducting substrate 105. The isolated self-alignment structure 710 may have sides 1350. The isolated self-alignment structure 710 may be formed using a variety of known etching techniques, such as an anisotropic etching process. A selective anisotropic etching technique may be used, such as a reactive ion etching (RIE) process using hydrogen bromide (HBr) and argon (Ar) as the etchant gases, for example. Alternatively, an RIE process with CHF₃ and Ar as the etchant gases may be used, for example. Plasma etching may also be used, in various illustrative embodiments.

In various of the illustrative embodiments in which the patterned masking layer 1110 comprises photoresist, the photoresist patterned masking layer 1110 may be removed by being stripped away, by ashing, for example. Alternatively, the photoresist patterned masking layer 1110 may be stripped using a 1:1 solution of sulfuric acid (H₂S0₄) to hydrogen peroxide (H₂0₂), for example.

As shown in Figure 13, a "complementary" masking layer 1300, formed of photoresist, for example, may be formed above the upper surface 150 of the semiconducting substrate 105, and above and adjacent the isolated self-alignment structure 710. The complementary masking layer 1300 may have a thickness τ above the upper surface 150 ranging from approximately 2000-15000 A, for example. In various illustrative embodiments, the thickness τ above the upper surface 150 is about 10000 t .

As shown in Figure 14, the complementary masking layer 1300 may be patterned to form the complementary mask 1475 above at least a portion of the shallow trench isolation (STI) 140. The complementary masking layer 1300 may be patterned to form the complementary mask 1475 using a variety of known photolithography and/or etching techniques. The complementary mask 1475 may have an edge 1420 spaced apart from the side 1350 of the isolated self-alignment structure 710 by a distance w ranging from approximately 1000-1500 A, for example.

The complementary mask 1475 may be formed over the STI region 140, as in conventional CMOS fabrication methods, to protect the P-channel BIGFET (N-channel BIGFET) regions while the complementary N-channel BIGFET (P-channel BIGFET) regions are being implanted to form N^'-doped (P^"-doped) regions 1430, for example. As shown in Figure 14, a dopant 1400 (indicated by the arrows) may be implanted to introduce dopant atoms and/or molecules into the p-doped (n-doped) semiconducting substrate 105 to form the N^'-doped (P^"-doped) regions 1430. After activation, the N^'-doped (P^"-doped) regions 1430 become the N^'-doped (P^"-doped) source/drain extension (SDE) regions 130 (as described more fully below with reference to Figure 15).

In various illustrative embodiments, the N^"-doped (P^"-doped) regions 1430 may be formed by being implanted with a source/drain extension (SDE) dose of As (for N^"-doping appropriate for an N-channel BIGFET 700, Figure 7) or BF₂ (for P^"-doping appropriate for a P-channel BIGFET 700, Figure 7). The source/drain extension (SDE) dose may range from about l.OxlO¹⁴ - l.OxlO¹⁵ ions/cm² at an implant energy ranging from about 3-50 keV. The N^'-doped (P^"-doped) regions 1430 may be subjected to a rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 800-1100°C for a time ranging from approximately 5-60 seconds. The rapid thermal anneal (RTA) process may activate the implant and form a more sharply defined and less graded activated implant junction with the substrate 105 than would a rapid thermal anneal (RTA) process following an implant with a source/drain extension (SDE) dose of more mobile phosphorus (P) (for N^"-doping appropriate for an N-channel BIGFET 700, Figure 7) or boron (B) (for P^'-doping appropriate for a P-channel BIGFET 700, Figure 7).

As shown in Figure 15, spacers 125 may be formed adjacent the isolated self-alignment structure 710, either before or after the N^'-doped (P^'-doped) regions 1430 (Figure 14) are activated to become the N^'-doped (P^'-doped) source/drain extension (SDE) regions 130. As shown in Figure 15, the spacers 125 may be formed by a variety of techniques above the N^'-doped (P^'-doped) source/drain extension (SDE) regions 130 and adjacent the isolated self-alignment structure 710. For example, the spacers 125 may be formed by depositing a conformal layer (not shown) of the appropriate material above and adjacent the isolated self-alignment structure 710, and then performing an anisotropic reactive ion etching (RIE) process on the conformally blanket-deposited layer. The spacers 125 may each have a base thickness ranging from approximately 300-1500 A, for example, measured from the sides 1350 of the isolated self-alignment structure 710.

The spacers 125, like the patterned masking layer 1110 and the self-alignment structure 710, may be formed from a variety of materials. For example, the spacers 125 may be comprised of a fluorine-doped oxide, a fluorine-doped nitride, a fluorine-doped oxynitride, a fluorine-doped low K material, and the like. In one illustrative embodiment, the spacers 125 are comprised of Si0₂, having a base thickness of approximately 300 A.

The spacers 125 may, for example, comprise an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (Si0₂), a nitrogen-bearing oxide (e.g., nitrogen-bearing Si0₂), a nitrogen-doped oxide (e.g., N₂-implanted Si0₂), silicon nitride (Si₃N ), silicon oxynitride (Si_xO_yN_z), and the like. The spacers 125 may also be formed of any suitable "high dielectric constant" or "high K" material, where K is greater than or equal to about 8, such as titanium oxide (Ti_xO_y, e.g., Ti0₂), tantalum oxide (Ta_xO_y, e.g., Ta₂0₅), barium strontium titanate (BST, BaTi0₃/SrTi0₃), and the like. Alternatively, the spacers 125 may also be formed of any suitable "low dielectric constant" or "low K" dielectric material, where K is less than or equal to about 4. Examples include Applied Material's Black Diamond^®, Novellus' Coral^®, Allied Signal's Nanoglass^®, JSR's LKD5104, and the like.

In various other alternative illustrative embodiments, the spacers 125 may be formed of polycrystalline silicon (poly). The poly spacers 125 may be formed by a variety of known techniques for forming such layers, e.g., CVD, LPCVD, PECVD, PVD, and the like.

As shown in Figures 16-17, a dopant 1600 (indicated by arrows) may be implanted to introduce dopant atoms and/or molecules into the p-type (n-type) semiconducting substrate 105 to form N'-doped (P⁺-doped) regions 1620. After activation, the N^-doped (P⁺-doped) regions 1620 become N^-doped (P⁺-doped) source/drain regions 120 (Figure 7). In one illustrative embodiment, a dose of the dopant 1600 atoms and/or molecules may range from approximately 1.0 x 10¹⁵ - 5.0 x 10¹⁵ ions/cm² of the appropriate dopant 1600 atoms and/or molecules, e.g., phosphorus (P) for an illustrative N-channel BIGFET or boron (B) for an illustrative P-channel BIGFET. An implant energy of the dopant 1600 atoms and/or molecules may range from approximately 30-100 keV. In another illustrative embodiment, a dose of the dopant 1600 atoms is approximately 1.0 x 10¹⁵ ions/cm² of phosphorus (P) for an N-channel BIGFET or boron (B) for a P-channel BIGFET at an implant energy of approximately 30 keV.

The dopant 1600 may be an N⁺ implant such as phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and the like, and may form heavily doped N^1' source/drain regions 120. An N ^' implant would be appropriate for the fabrication of an N-channel BIGFET 700, for example. Alternatively, the dopant 1600 may be a P⁺ implant such as boron (B), boron fluoride (BF, BF₂), aluminum (Al), gallium (Ga), Indium (In), Thallium (Tl), and the like, and may form heavily doped P⁺ source/drain regions 120. A P⁺ implant would be appropriate for the fabrication of a P-channel BIGFET 700, for example.

As shown in Figures 16-17, the N⁺-doped (P⁺-doped) regions 1620 may be subjected to a rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 800-1100°C for a time ranging from approximately 5-60 seconds to form the N^-doped (P⁺-doped) source/drain regions 120. The rapid thermal anneal (RTA) process may activate the implant of the more mobile phosphorus (P) (for -ST^-doping appropriate for an N-channel BIGFET 700) or boron (B) (for P⁺-doping appropriate for a P-channel BIGFET 700) and form a less sharply defined and more graded activated implant junction with the p-type (n-type) semiconducting substrate 105 than would a rapid thermal anneal (RTA) process following an implant with a source/drain dose of less mobile As (for N^-doping appropriate for an N-channel BIGFET 700) or BF₂ (for P⁺-doping appropriate for a P-channel BIGFET 700).

Alternatively, a rapid thermal anneal (RTA) process to diffuse and activate the -doped (P⁺-doped) regions 1620 to form the N^-doped (P⁺-doped) source/drain regions 120 may be performed in conjunction with a self-aligned silicidation (salicidation) process (not shown), either prior to, during or following the salicidation. Such a salicidation-conjoined rapid thermal anneal (RTA) process may be performed at a temperature ranging from approximately 800-1000°C for a time ranging from approximately 10-60 seconds. A self-aligned silicidation (salicidation) process may be used in various of the illustrative embodiments described above in which both the spacers 125 and the self-alignment structure 710 comprise dielectric materials, such as silicon dioxide (Si0₂). The suicides of the self-aligned silicidation (salicidation) process are less likely to form on dielectric materials such as silicon dioxide (Si0₂).

As shown in Figure 18, in various alternative illustrative embodiments, an N-channel (P-channel) BIGFET 1800, having the heavily P⁺-doped (lsT-doped) buried gate conductor 715 formed in the p-doped (n-doped) semiconducting substrate 105, may also have a buried dielectric structure 1810 formed above the heavily P⁺-doped (N-doped) buried gate conductor 715. The buried dielectric structure 1810 may be formed, for example, by implanting molecular oxygen (0₂) into the p-doped (n-doped) semiconducting substrate 105, through the opening 1100 in the patterned masking layer 1110 (Figure 11). The molecular oxygen (0₂) may be implanted either before or after the dopant 1120 (indicated by arrows) is introduced into the p-doped (n-doped) semiconducting substrate 105. The buried dielectric structure 1810 may then be formed, for example, by reacting the implanted molecular oxygen (0₂) with the silicon (Si) present in the p-doped (n-doped) semiconducting substrate 105 to form silicon dioxide (Si0₂). Such an in situ silicon dioxide (Si0₂) formation process is the basis of the SIMOX process used to form silicon dioxide (Si0₂) in silicon-on-insulator (SOI) semiconducting devices. The buried dielectric structure 1810 may be used to isolate the inversion layer in the channel region 800 (Figure 8) further from the heavily P⁺-doped (-sT-doped) buried gate conductor 715 formed in the p-doped (n-doped) semiconducting substrate 105.

As shown in Figure 19, in various other alternative illustrative embodiments, an N-channel (P-channel) BIGFET 1900, having the heavily P⁺-doped (NT-doped) buried gate conductor 715 formed in the p-doped (n-doped) semiconducting substrate 105, may also have a buried dielectric structure 1910 formed around, and encompassing, the heavily P⁺-doped (N-doped) buried gate conductor 715. The buried dielectric structure 1910 may be formed, for example, by implanting molecular oxygen (0₂) into the p-doped (n-doped) semiconducting substrate 105, through the opening 1100 in the patterned masking layer 1110 (Figure 11). The molecular oxygen (0₂) may be implanted either before or after the dopant 1120 (indicated by arrows) is introduced into the p-doped (n-doped) semiconducting substrate 105. The buried dielectric structure 1910 may then be formed, for example, by reacting the implanted molecular oxygen (0₂) with the silicon (Si) present in the p-doped (n-doped) semiconducting substrate 105 to form silicon dioxide (Si0₂). Such an in situ silicon dioxide (Si0₂) formation process is the basis of the SIMOX process used to form silicon dioxide (Si0₂) in silicon-on-insulator (SOI) semiconducting devices.

As shown in Figure 19, an N-channel BIGFET 1900 may operate in the "on" state as follows. In the "on" state, the buried gate voltage V_buriedgaιe < ,ι_mshoid < 0, where V„_mshoid is the threshold voltage for the (enhancement-type) N-channel BIGFET 1900. In the "on" state, the drain-source current 7_rfra,„ is positive (to the left) as electrons from the source 120S drift (indicated by the arrow) through an inversion layer in the channel region 800 (an N-channel) to the drain 120D, with a positive voltage V_dr_am > 0 present at the drain 120D.

The inversion layer in the channel region 800 is thought to form as holes are attracted to the periphery of the buried dielectric structure 1910 by the negative buried gate voltage V_bUriedgate ^< V,ι_msho_t ^< 0 applied to the heavily P⁺-doped buried gate conductor 715. The holes are attracted by the negative buried gate voltage V_{b r}i_{e ga}i_e ^< V 'th_res_hold < 0 applied to the heavily P⁺-doped buried gate conductor 715. Similarly, and substantially simultaneously, electrons above the heavily P⁺-doped buried gate conductor 715 are driven up to the underside of the self-alignment structure 710 near the upper surface 150 of the p-doped semiconducting substrate 105 by the negative buried gate voltage V_buri _{dg t} < _thre _hold < 0 applied to the heavily P⁺-doped buried gate conductor 715. The buried dielectric structure 1910 may be used to isolate the inversion layer in the channel region 800 from the heavily P⁺-doped buried gate conductor 715 formed in the p-doped semiconducting substrate 105. In particular, the holes attracted to the heavily P⁺-doped buried gate conductor 715 are not able to conduct into the heavily P⁺-doped buried gate conductor 715, since the buried dielectric structure 1910 is an insulator.

As shown in Figure 20, in still other various alternative illustrative embodiments, an N-channel BIGFET 2000, having a heavily -NT-doped buried gate conductor 2015 formed in the p-doped semiconducting substrate 105, may also have the buried dielectric structure 1910 formed around, and encompassing, the heavily N^-doped buried gate conductor 2015. Such an N-channel BIGFET 2000 may operate in the "on" state as follows. In the "on" state, the buried gate voltage Vbu_ri dgat > V _{t r sho}l_d > 0, where V thr hold is the threshold voltage for the (enhancement-type) N-channel BIGFET 2000. In the "on" state, the drain-source current I_{dr l} is positive (to the left) as electrons from the source 120S drift (indicated by the arrow) through an inversion layer in a channel region 2005 (an N-channel) to the drain 120D, with a positive voltage V_dram > 0 present at the drain 120D.

The inversion layer in the channel region 2005 is thought to form as electrons are attracted to the periphery of the buried dielectric structure 1910 by the positive buried gate voltage V_buri_{edg te} > ^--*w^> 0 applied to the heavily -NT-doped buried gate conductor 2015. Similarly, and substantially simultaneously, holes above the heavily N^-doped buried gate conductor 2015 are driven up to the underside of the self-alignment structure 710 near the upper surface 150 of the semiconducting substrate 105 by the positive buried gate voltage V_buri_{e gat} > V_threshoi ^> 0 applied to the heavily N^-doped buried gate conductor 2015. The buried dielectric structure 1910 may be used to isolate the inversion layer in the channel region 2005 from the heavily -NT-doped buried gate conductor 2015 formed in the p-doped semiconducting substrate 105. In particular, the electrons attracted to the heavily ]ST-doped buried gate conductor 2015 are not able to conduct into the heavily IST-doped buried gate conductor 2015, since the buried dielectric structure 1910 is an insulator. As shown in Figure 21, in various alternative illustrative embodiments, spacers 2110 may be formed in the opening 1100 in the patterned masking layer 1110 (Figure 11). The spacers 2110 form an opening 2100. The opening 2100 may have a subcritical dimension d_sk that may be in a range of about 50-500 A. The subcritical dimension d_sk may be smaller than the smallest, diffraction-limited critical dimension d_k (Figure 11) that may be in a range of about 150-1000 A. The spacers 2110 may be formed in a manner similar to the formation of the spacers 125, described above with reference to Figure 15, and may be formed of any of the materials that may be used to form the spacers 125.

As shown in Figure 21, a P⁺-doped (N⁺-doped) buried gate conductor 2115 may be formed in the p-doped (n-doped) semiconducting substrate 105 by being implanted using a dopant 2120 (indicated by arrows) to introduce dopant atoms and/or molecules into the p-doped (n-doped) semiconducting substrate 105. In one illustrative embodiment, a dose of the dopant 2120 atoms and/or molecules may range from approximately 1.0 x 10¹⁵ ions/cm² to approximately 5.0 x 10¹⁵ ions/cm² of the appropriate dopant 2120 atoms and/or molecules, e.g., boron (B) for an illustrative P⁺-doped buried gate conductor 2115 or phosphorus (P) for an illustrative N⁺-doped buried gate conductor 2115. An implant energy of the dopant 2120 atoms and/or molecules may range from approximately 100-1000 keV.

The dopant 2120 may be an N^1" implant such as phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and the like, and may form a heavily doped N^-doped buried gate conductor 2115. Alternatively, the dopant 2120 may be a P⁺ implant such as boron (B), boron fluoride (BF, BF₂), aluminum (Al), gallium (Ga), Indium (In), Thallium (Tl), and the like, and may form a heavily doped P⁺-doped buried gate conductor 2115.

As shown in Figure 21 , the P⁺-doped (--T-doped) buried gate conductor 2115 may be formed to a depth e below the upper surface 150 of the p-doped (n-doped) semiconducting substrate 105 that may be in a range of about 100-1000 A. As shown in Figure 21, the P⁺-doped (-NT-doped) buried gate conductor 2115 may also have the subcritical dimension d_sk that may be in a range of about 50-500 A. The P⁺-doped (N^-doped) buried gate conductor 2115 "inherits" the subcritical dimension d_sk from the opening 2100 formed in the patterned masking layer 1110 using the spacers 2110.

As shown in Figure 22, an intrinsically-doped (i-doped) region 2215 may be formed in the p-doped (n-doped) semiconducting substrate 105 above the P⁺-doped (IsT-doped) buried gate conductor 2115 by being implanted using a complementary dopant 2220 (indicated by arrows) to introduce complementary dopant atoms and/or molecules into the p-doped (n-doped) semiconducting substrate 105. An intrinsically-doped (i-doped) region could be formed in the p-doped (n-doped) semiconducting substrate 105, above the P⁺-doped (IST-doped) buried gate conductor 2115, whether or not the spacers 2110 are used in the opening 2100. The introduction of complementary dopant atoms and/or molecules into the p-doped (n-doped) semiconducting substrate 105 is believed to "cancel out" the doping of the p-doped (n-doped) semiconducting substrate 105 in the intrinsically-doped (i-doped) region 2215. In one illustrative embodiment, for example, a dose of the complementary dopant 2220 atoms and/or molecules may range from approximately 1.0 x 10 - 1.0 x 10¹⁵ ions/cm² of the appropriate complementary dopant 2220 atoms and/or molecules. For example, boron (B) may be used for an illustrative n-doped semiconducting substrate 105 or phosphorus (P) for an illustrative p-doped semiconducting substrate 105. An implant energy of the complementary dopant 2220 atoms and/or molecules may range from approximately 50-150 keV. The complementary dopant 2220 may be an N-type implant such as phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and the like, and may substantially compensate for the doping of the p-doped semiconducting substrate 105, forming the intrinsically-doped (i-doped) region 2215. Alternatively, the complementary dopant 2220 may be a P-type implant such as boron (B), boron fluoride (BF, BF₂), aluminum (Al), gallium (Ga), Indium (In), Thallium (Tl), and the like, and may substantially compensate for the doping of the n-doped semiconducting substrate 105, forming the intrinsically-doped (i-doped) region 2215.

As shown in Figure 22, the intrinsically-doped (i-doped) region 2215 may also have the subcritical dimension d_sk that may be in a range of about 50-500 A. The intrinsically-doped (i-doped) region 2215 "inherits" the subcritical dimension d_sk from the opening 2100 formed in the patterned masking layer 1110 using the spacers 2110.

In various alternative illustrative embodiments, the P⁺-doped (NT-doped) buried gate conductor 2115 and/or the intrinsically-doped (i-doped) region 2215 may be formed by diffusing and/or implanting the respective dopant atoms and or molecules through the upper surface 150 of the p-doped (n-doped) semiconducting substrate 105. The respective dopant atoms and/or molecules may be diffused and/or implanted through the opening 2100 formed in the patterned masking layer 1110 using the spacers 2110. Once suitably introduced, the respective dopant atoms and/or molecules may then be subjected to a heat-treating process that may be a rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 800-1100°C for a time ranging from approximately 5-60 seconds. In various other alternative illustrative embodiments, the semiconducting substrate 105 may be intrinsically-doped (i-doped). In these embodiments, an intrinsically-doped (i-doped) region, such as the intrinsically-doped (i-doped) region 2215, may not have to be separately formed.

In various alternative illustrative embodiments, as shown in Figure 11 or Figure 21, for example, N^-doped (P⁺-doped) source/drain regions may be formed in portions of the patterned masking layer 1110 adjacent the opening 1100 (Figure 11) or the opening 2100 (Figure 21), respectively. The - -T-doped (P⁺-doped) source/drain regions formed in the portions of the patterned masking layer 1110 adjacent the opening 1100 (Figure 11) or the opening 2100 (Figure 21) may be formed by diffusing and/or implanting the respective dopant atoms and/or molecules into the respective portions of the patterned masking layer 1110. Once suitably introduced, the respective dopant atoms and/or molecules may then be subjected to a heat-treating process that may be a rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 800-1100°C for a time ranging from approximately 5-60 seconds. In various other alternative illustrative embodiments, the KT-doped (P⁺-doped) source/drain regions 120 may be formed in the p-doped (n-doped) semiconducting substrate 105 adjacent the self-alignment structure 710 (Figure 7) or the self-alignment structure 2310 (Figure 23) without using the spacers 125. In these embodiments, source/drain extension (SDE) regions, such as the N^'-doped (P^'-doped) source/drain extension (SDE) regions 130, may not have to be formed.

As shown in Figure 23, in various illustrative embodiments, an N-channel BIGFET 2300 may be formed in a semiconducting substrate 105, such as p-doped silicon (Si). A method (not shown) of forming the N-channel

BIGFET 2300 according to the present invention may start from the fabrication state shown in Figure 22, and then resemble the method of forming the BIGFET 700 (Figure 7) illustrated schematically in Figures 12-17, as described above. The N-channel BIGFET 2300 may have a doped gate conductor such as a P⁺-doped buried gate conductor 2115 formed in the p-doped semiconducting substrate 105, below the intrinsically-doped (i-doped) region 2215, and also below a self-alignment structure 2310 formed above the upper surface 150 of the semiconducting substrate 105. The self-alignment structure 2310 may be separated from active areas such as N⁺-doped source/drain regions 120 of the N-channel BIGFET 2300 by spacers 125. The spacers 125 may be formed above N^'-doped source/drain extension (SDE) regions 130. As shown in Figure 23, shallow trench isolation (STI) regions 140 may be provided to isolate the N-channel BIGFET 2300 electrically from neighboring semiconductor devices such as other BIGFETs and/or MOS transistors, and the like (not shown).

As shown in Figure 23, in various illustrative embodiments, the N-channel BIGFET 2300, having the heavily P⁺-doped buried gate conductor 2115 formed in a p-doped semiconducting substrate 105 below the intrinsically-doped (i-doped) region 2215, may operate in the "off state as follows. In the "off state, the buried gate voltage V_blιrledga,_e = 0 (or, more precisely, V_b,_lriedga,_e is greater than or equal to V,_lmsho!d, where V _threshold is the threshold voltage for the BIGFET 2300), and the drain-source current I_drain is approximately zero, even with a positive voltage V_dram > 0 present at the drain 120D. The source 120S is typically grounded (V_source = 0), and the p-type semiconducting substrate 105 may either be grounded or have a bias applied thereto (not shown). The positive voltage V_dram > 0 present at the drain 120D and the grounding of the source 120S cause depletion regions 160 (shown in phantom) to form in portions of the p-type semiconducting substrate 105 adjacent the drain 120D and source 120S, and in portions of the drain 120D and source 120S, as well. The depletion regions 160 may be about the same size on either side of the heavily P⁺-doped buried gate conductor 2115, and may be prevented from growing larger by the presence of the heavily P⁺-doped buried gate conductor 2115. The channel length l_sk of the N-channel BIGFET 2300 may be the subcritical dimension d_sk, about the distance between N^'-doped source/drain extension (SDE) regions 130, as shown in Figure 23.

As shown in Figure 24, in various illustrative embodiments, the N-channel BIGFET 2300, having the heavily P⁺-doped buried gate conductor 2115 formed in a p-doped semiconducting substrate 105 below the intrinsically-doped (i-doped) region 2215, may operate in the "on" state as follows. In the "on" state, the buried gate voltage Vburiedgate < Vihre hotd < 0, where Vt resiwid is the threshold voltage for the (enhancement-type) N-channel BIGFET 2300. In the "on" state, the drain-source current I_dram is positive (to the left) as electrons from the source 120S drift (indicated by the arrow) through an inversion layer in a channel region 2400 (an N-channel) to the drain 120D, with a positive voltage V_draι„ > 0 present at the drain 120D.

The inversion layer in the channel region 2400 is thought to form as holes in the intrinsically-doped (i-doped) region 2215 above the heavily P⁺-doped buried gate conductor 2115 are attracted to the heavily P⁺-doped buried gate conductor 2115. The holes are attracted by the negative buried gate voltage Vbu_ried_gate < V_{t resho}i_d ^< 0 applied to the heavily P⁺-doped buried gate conductor 2115. Similarly, and substantially simultaneously, electrons in the intrinsically-doped (i-doped) region 2215 above the heavily P⁺-doped buried gate conductor 2115 are driven up to the underside of the self-alignment structure 2310 near the upper surface 150 of the semiconducting substrate 105 by the negative buried gate voltage V_burie gat < V_{thr shotd} ^< Q applied to the heavily P⁺-doped buried gate conductor 2115.

A depletion region 2460 is believed to form adjacent the heavily P⁺-doped buried gate conductor 2115 as mobile holes are attracted by the negative buried gate voltage V_buri_edgate < V,_hresh0ι_d < 0 applied to the heavily P⁺-doped buried gate conductor 2115 and as mobile electrons are driven away. Similarly, a polarized/depleted region 2415 is believed to form above the heavily P⁺-doped buried gate conductor 2115 and below the N-channel inversion layer in the channel region 2400. The polarized/depleted region 2415 is believed to form as mobile holes from the intrinsically-doped (i-doped) region 2215 are attracted by the negative buried gate voltage V _u i_edg te < V threshold 0 applied to the heavily P⁺-doped buried gate conductor 2115 and as mobile electrons from intrinsically-doped (i-doped) region 2215 are driven away. Again, the effective channel length l_sk of the N-channel BIGFET 2300 may be the subcritical dimension d_sk, about the distance between N^'-doped source/drain extension (SDE) regions 130, as shown in Figure 24.

Any of the above-disclosed embodiments of a method of manufacturing semiconductor devices with reduced critical dimensions enables the formation and patterning of components such as gate conductors on much reduced scales, consistently, robustly and reproducibly, and in a self-aligned manner. Any of the above-disclosed embodiments of a method of manufacturing semiconductor devices with reduced critical dimensions enables the achievement of reduced critical dimensions using fewer and/or simpler fabrication techniques, decreasing manufacturing costs and increasing throughput, more effectively and more stably than with conventional techniques.

The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. In particular, every range of values (of the form, "from about a to about b," or, equivalently, "from approximately to b," or, equivalently, "from approximately -b") disclosed herein is to be understood as referring to the power set (the set of all subsets) of the respective range of values, in the sense of Georg Cantor. Accordingly, the protection sought herein is as set forth in the claims below.

Claims

1. A method comprising: forming a masking layer (1110) above a substrate layer (105); forming an opening (1100,2100) in the masking layer (1110), the opening (1100,2100) defining a channel region (800,2005,2400) in the substrate layer (105); forming a buried gate conductor (715,2015,2115) in the substrate layer (105) below the channel region (800,2005,2400), using the opening (1100,2100) to self-align the buried gate conductor (715,2015,2115); and forming source/drain regions (120S,120D) adjacent the channel region (800,2005,2400).

2. The method of claim 1, wherein forming the buried gate conductor (715,2015,2115) in the substrate layer (105) below the channel region (800,2005,2400) comprises introducing a dopant into the substrate layer (105) below the channel region (800,2005,2400).

3. The method of claim 2, wherein introducing the dopant into the substrate layer (105) below the channel region (800,2005,2400) comprises at least one of implanting and diffusing the dopant into the substrate layer (105) below the channel region (800,2005,2400).

4. The method of claim 1, further comprising: forming a buried dielectric structure in the substrate layer (105) below the channel region (800,2005,2400).

5. The method of claim 4, wherein forming the buried dielectric structure in the substrate layer (105) below the channel region (800,2005,2400) comprises forming the buried dielectric structure above the buried gate conductor (715,2015,2115).

6. The method of claim 4, wherein forming the buried dielectric structure in the substrate layer (105) below the channel region (800,2005,2400) comprises forming the buried dielectric structure around and encompassing the buried gate conductor (715,2015,2115).

7. The method of claim 1, wherein forming the opening (1100,2100) in the masking layer (1110) comprises forming spacers in the opening (1100,2100).

8. The method of claim 1, wherein forming the source/drain regions (120S,120D) adjacent the channel region (800,2005,2400) comprises forming the source/drain regions (120S,120D) in at least one of portions of the substrate layer (105) and portions of the masking layer (1110) adjacent the channel region (800,2005,2400).

9. A method comprising: forming a sacrificial layer above a substrate layer (105) having an upper surface; forming an opening (1100,2100) in the sacrificial layer; forming a buried gate conductor (715,2015,2115) in the substrate layer (105) below the upper surface, using the opening (1100,2100) to self-align the buried gate conductor (715,2015,2115); forming a self-alignment structure (710,2310) in the opening (1100,2100); removing the sacrificial layer; and forming source/drain regions (120S,120D) in the substrate layer (105) adjacent the self-alignment structure (710,2310).

10. A semiconductor device (700,1800,1900,2000,2300) comprising: a substrate layer (105) having a channel region (800,2005,2400); source/drain regions (120S,120D) adjacent the channel region (800,2005,2400); and a buried gate conductor (715,2015,2115) in the substrate layer (105) below the channel region (800,2005,2400).