+

WO2008133087A1 - Dispositif de mémorisation à semi-conducteurs et son procédé de fonctionnement - Google Patents

Dispositif de mémorisation à semi-conducteurs et son procédé de fonctionnement Download PDF

Info

Publication number
WO2008133087A1
WO2008133087A1 PCT/JP2008/057285 JP2008057285W WO2008133087A1 WO 2008133087 A1 WO2008133087 A1 WO 2008133087A1 JP 2008057285 W JP2008057285 W JP 2008057285W WO 2008133087 A1 WO2008133087 A1 WO 2008133087A1
Authority
WO
WIPO (PCT)
Prior art keywords
error
data
operation method
symbol
bit
Prior art date
Application number
PCT/JP2008/057285
Other languages
English (en)
Japanese (ja)
Inventor
Noboru Sakimura
Tadahiko Sugibayashi
Ryusuke Nebashi
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2009511795A priority Critical patent/JP4905866B2/ja
Priority to US12/596,243 priority patent/US8510633B2/en
Publication of WO2008133087A1 publication Critical patent/WO2008133087A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé de fonctionnement qui peut être appliqué à une mémoire PRAM, une mémoire ReRAM, ou une mémoire à électrolyte solide qui contient des codes de correction d'erreurs, formés chacun par une pluralité de symboles, formés chacun par une pluralité de bits, et qui peut effectuer une correction d'erreurs dans une unité de symbole. Dans ce procédé de fonctionnement, les symboles utilisent des cellules de référence (12) différentes les unes des autres. Lorsqu'une erreur corrigeable est détectée lors de l'extraction des données d'une cellule de données (11) constituant le code avec correction d'erreur correspondant à une adresse entrée : pour un premier symbole d'erreur qui est un motif d'erreur de 1 bit, les données dans la cellule de données (11) correspondant au bit d'erreur sont corrigées ; et pour un deuxième symbole d'erreur qui est un motif d'erreur de multiples bits, les données dans la cellule de référence (12) utilisées pour extraire le deuxième symbole d'erreur sont corrigées.
PCT/JP2008/057285 2007-04-17 2008-04-14 Dispositif de mémorisation à semi-conducteurs et son procédé de fonctionnement WO2008133087A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009511795A JP4905866B2 (ja) 2007-04-17 2008-04-14 半導体記憶装置及びその動作方法
US12/596,243 US8510633B2 (en) 2007-04-17 2008-04-14 Semiconductor storage device and method of operating the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-108569 2007-04-17
JP2007108569 2007-04-17

Publications (1)

Publication Number Publication Date
WO2008133087A1 true WO2008133087A1 (fr) 2008-11-06

Family

ID=39925545

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/057285 WO2008133087A1 (fr) 2007-04-17 2008-04-14 Dispositif de mémorisation à semi-conducteurs et son procédé de fonctionnement

Country Status (3)

Country Link
US (1) US8510633B2 (fr)
JP (1) JP4905866B2 (fr)
WO (1) WO2008133087A1 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110043210A (ko) * 2009-10-21 2011-04-27 삼성전자주식회사 불휘발성 메모리 장치, 그것의 읽기 방법, 그리고 그것을 포함하는 메모리 시스템
CN102298972A (zh) * 2010-06-22 2011-12-28 慧荣科技股份有限公司 快闪记忆体的资料读取方法
JP2012221536A (ja) * 2011-04-12 2012-11-12 Sharp Corp 半導体記憶装置
JP2013020683A (ja) * 2011-07-14 2013-01-31 Toshiba Corp 不揮発性半導体メモリ
JP2013516725A (ja) * 2010-01-08 2013-05-13 インターナショナル・ビジネス・マシーンズ・コーポレーション スピン・トルク・ベースの記憶装置のためのリファレンス・セル
JP5363644B2 (ja) * 2010-02-16 2013-12-11 株式会社日立製作所 半導体装置
TWI455142B (zh) * 2010-04-08 2014-10-01 Silicon Motion Inc 快閃記憶體之資料讀取的方法以及資料儲存裝置

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007046350A1 (fr) * 2005-10-18 2007-04-26 Nec Corporation Procede de fonctionnement d'une mram
JP4905866B2 (ja) 2007-04-17 2012-03-28 日本電気株式会社 半導体記憶装置及びその動作方法
KR101466695B1 (ko) * 2008-04-30 2014-12-01 삼성전자주식회사 멀티 비트 레벨 데이터의 부호화 및 복호화 방법
US8589760B1 (en) * 2010-03-31 2013-11-19 Sk Hynix Memory Solutions Inc. Defect scan and manufacture test
US9570162B2 (en) * 2010-04-08 2017-02-14 Silicon Motion, Inc. Data read method for flash memory
US8572445B2 (en) * 2010-09-21 2013-10-29 Freescale Semiconductor, Inc. Non-volatile memory (NVM) with imminent error prediction
US8837211B2 (en) * 2012-04-24 2014-09-16 Being Advanced Memory Corporation Robust initialization with phase change memory cells in both configuration and array
US20140146601A1 (en) * 2012-08-28 2014-05-29 Being Advanced Memory Corporation Processors and systems with multiple reference columns in multibit phase-change memory
JP2015053096A (ja) 2013-09-09 2015-03-19 マイクロン テクノロジー， インク． 半導体装置、及び誤り訂正方法
US9417957B2 (en) * 2013-10-04 2016-08-16 Infineon Technologies Ag Method of detecting bit errors, an electronic circuit for detecting bit errors, and a data storage device
KR102133209B1 (ko) * 2013-12-13 2020-07-14 에스케이하이닉스 주식회사 데이터 복호화 장치 및 데이터 복호화 방법
US10381102B2 (en) 2014-04-30 2019-08-13 Micron Technology, Inc. Memory devices having a read function of data stored in a plurality of reference cells
US9904595B1 (en) 2016-08-23 2018-02-27 Texas Instruments Incorporated Error correction hardware with fault detection
KR102445560B1 (ko) * 2018-03-09 2022-09-22 에스케이하이닉스 주식회사 저항성 메모리 장치 및 그의 동작 방법
US11127459B1 (en) 2020-03-16 2021-09-21 Globalfoundries Singapore Pte. Ltd. Memory devices and methods of forming the same
US11381260B2 (en) * 2020-05-27 2022-07-05 The Royal Institution For The Advancement Of Learning / Mcgill University Architecture for guessing random additive noise decoding (GRAND)
KR20220168519A (ko) * 2021-06-16 2022-12-23 에스케이하이닉스 주식회사 에러정정방법을 이용하여 에러정정동작을 수행하는 반도체시스템
CN114138544A (zh) * 2021-12-03 2022-03-04 海光信息技术股份有限公司 数据读取、写入方法及装置、软错误处理系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005056556A (ja) * 2003-08-05 2005-03-03 Hewlett-Packard Development Co Lp 論理データブロック、磁気ランダムアクセスメモリ、メモリモジュール、コンピュータシステムおよび方法
WO2007046350A1 (fr) * 2005-10-18 2007-04-26 Nec Corporation Procede de fonctionnement d'une mram

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2583547B2 (ja) * 1988-01-13 1997-02-19 株式会社日立製作所 半導体メモリ
US5758050A (en) * 1996-03-12 1998-05-26 International Business Machines Corporation Reconfigurable data storage system
US6055178A (en) 1998-12-18 2000-04-25 Motorola, Inc. Magnetic random access memory with a reference memory array
US6584589B1 (en) * 2000-02-04 2003-06-24 Hewlett-Packard Development Company, L.P. Self-testing of magneto-resistive memory arrays
US7036068B2 (en) 2001-07-25 2006-04-25 Hewlett-Packard Development Company, L.P. Error correction coding and decoding in a solid-state storage device
US20030023922A1 (en) 2001-07-25 2003-01-30 Davis James A. Fault tolerant magnetoresistive solid-state storage device
US6981196B2 (en) 2001-07-25 2005-12-27 Hewlett-Packard Development Company, L.P. Data storage method for use in a magnetoresistive solid-state storage device
US6545906B1 (en) 2001-10-16 2003-04-08 Motorola, Inc. Method of writing to scalable magnetoresistance random access memory element
US20030172339A1 (en) 2002-03-08 2003-09-11 Davis James Andrew Method for error correction decoding in a magnetoresistive solid-state storage device
JP3821066B2 (ja) 2002-07-04 2006-09-13 日本電気株式会社 磁気ランダムアクセスメモリ
JP4242117B2 (ja) 2002-07-11 2009-03-18 株式会社ルネサステクノロジ 記憶装置
JP4170108B2 (ja) 2003-02-20 2008-10-22 株式会社ルネサステクノロジ 磁気記憶装置
US7191379B2 (en) 2003-09-10 2007-03-13 Hewlett-Packard Development Company, L.P. Magnetic memory with error correction coding
US7733729B2 (en) * 2004-04-01 2010-06-08 Nxp B.V. Thermally stable reference voltage generator for MRAM
JP4660249B2 (ja) 2005-03-31 2011-03-30 株式会社東芝 磁気ランダムアクセスメモリ
JP4853735B2 (ja) 2005-10-18 2012-01-11 日本電気株式会社 Ｍｒａｍ、及びその動作方法
US7321507B2 (en) * 2005-11-21 2008-01-22 Magic Technologies, Inc. Reference cell scheme for MRAM
US7286429B1 (en) 2006-04-24 2007-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. High speed sensing amplifier for an MRAM cell
US7747926B2 (en) 2006-05-02 2010-06-29 Everspin Technologies, Inc. Methods and apparatus for a memory device with self-healing reference bits
US7865797B2 (en) * 2006-11-16 2011-01-04 Freescale Semiconductor, Inc. Memory device with adjustable read reference based on ECC and method thereof
JP4905866B2 (ja) 2007-04-17 2012-03-28 日本電気株式会社 半導体記憶装置及びその動作方法
US7770079B2 (en) * 2007-08-22 2010-08-03 Micron Technology Inc. Error scanning in flash memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005056556A (ja) * 2003-08-05 2005-03-03 Hewlett-Packard Development Co Lp 論理データブロック、磁気ランダムアクセスメモリ、メモリモジュール、コンピュータシステムおよび方法
WO2007046350A1 (fr) * 2005-10-18 2007-04-26 Nec Corporation Procede de fonctionnement d'une mram

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110043210A (ko) * 2009-10-21 2011-04-27 삼성전자주식회사 불휘발성 메모리 장치, 그것의 읽기 방법, 그리고 그것을 포함하는 메모리 시스템
KR101601849B1 (ko) 2009-10-21 2016-03-09 삼성전자주식회사 불휘발성 메모리 장치, 그것의 읽기 방법, 그리고 그것을 포함하는 메모리 시스템
JP2013516725A (ja) * 2010-01-08 2013-05-13 インターナショナル・ビジネス・マシーンズ・コーポレーション スピン・トルク・ベースの記憶装置のためのリファレンス・セル
JP5363644B2 (ja) * 2010-02-16 2013-12-11 株式会社日立製作所 半導体装置
TWI455142B (zh) * 2010-04-08 2014-10-01 Silicon Motion Inc 快閃記憶體之資料讀取的方法以及資料儲存裝置
CN102298972A (zh) * 2010-06-22 2011-12-28 慧荣科技股份有限公司 快闪记忆体的资料读取方法
JP2012221536A (ja) * 2011-04-12 2012-11-12 Sharp Corp 半導体記憶装置
JP2013020683A (ja) * 2011-07-14 2013-01-31 Toshiba Corp 不揮発性半導体メモリ

Also Published As

Publication number Publication date
US20110016371A1 (en) 2011-01-20
JPWO2008133087A1 (ja) 2010-07-22
US8510633B2 (en) 2013-08-13
JP4905866B2 (ja) 2012-03-28

Similar Documents

Publication Publication Date Title
WO2008133087A1 (fr) Dispositif de mémorisation à semi-conducteurs et son procédé de fonctionnement
US8046660B2 (en) System and method for correcting errors in non-volatile memory using product codes
US8788905B2 (en) Flash memory device error correction code controllers and related methods and memory systems
WO2008086237A3 (fr) Codes destinés à des erreurs asymétriques à intensité limitée dans des mémoires flash
WO2007046084A3 (fr) Correction d'erreur probabiliste dans une memoire flash a bits multiples par cellule
JP2003115197A5 (fr)
KR102387195B1 (ko) 메모리 시스템 및 이의 에러 정정 방법
WO2009070406A3 (fr) Procédé et appareil pour lire des données à partir d'une mémoire flash
WO2007036834A3 (fr) Circuit de detection/correction d'erreurs et procede associe
WO2010078167A3 (fr) Correction d'erreur améliorée dans un disque ssd
WO2008004226A3 (fr) Procédé de correction d'erreur dans une mémoire flash multi-bits-par-cellule
WO2009009302A3 (fr) Stockage de récupération d'erreur le long d'une chaîne flash non et
WO2007133963A3 (fr) Mémoire non volatile à codage de convolution
WO2010080257A3 (fr) Reprise sur erreur de données dans une mémoire non volatile
WO2004003750A3 (fr) Code de detection/correction d'erreurs permettant de detecter et de corriger une panne de composant, et de fournir une correction d'erreur de bits unique, suite a une panne de composant
WO2004112048A3 (fr) Procede et appareil de detection et de correction d'erreur dans une memoire magnetoresistive a acces aleatoire
WO2007043042A3 (fr) Procede de correction d'erreur dans une memoire flash mbc
CN106469099B (zh) 在应用wom码的情况下的错误纠正
WO2007010189A3 (fr) Correction d'erreurs flash
WO2010093441A8 (fr) Rafraîchissement automatique permettant d'ameliorer la retention des donnees et les caracteristiques d'endurance d'une memoire non volatile integree dans un processus de logique cmos standard
WO2008005781A3 (fr) Amélioration de la fiabilité, de la disponibilité et de la facilité de maintenance dans un dispositif à mémoire
TW200737215A (en) A method for arranging data in a multi-level cell memory device
EP1282040A3 (fr) Procédé de stockage de données dans un mémoire à semi-conducteurs magnétorésistif
EP1619582A3 (fr) Dispositif de mémoire à semi-conducteurs contenant un circuit de CCE et son procédé d'essai
DE602008006455D1 (de) Korrektur von fehlern in einem speicherarray

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08740373

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009511795

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 12596243

Country of ref document: US

122 Ep: pct application non-entry in european phase

Ref document number: 08740373

Country of ref document: EP

Kind code of ref document: A1

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载