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WO2008133087A1 - 半導体記憶装置及びその動作方法 - Google Patents

半導体記憶装置及びその動作方法 Download PDF

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Publication number
WO2008133087A1
WO2008133087A1 PCT/JP2008/057285 JP2008057285W WO2008133087A1 WO 2008133087 A1 WO2008133087 A1 WO 2008133087A1 JP 2008057285 W JP2008057285 W JP 2008057285W WO 2008133087 A1 WO2008133087 A1 WO 2008133087A1
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WO
WIPO (PCT)
Prior art keywords
error
data
operation method
symbol
bit
Prior art date
Application number
PCT/JP2008/057285
Other languages
English (en)
French (fr)
Inventor
Noboru Sakimura
Tadahiko Sugibayashi
Ryusuke Nebashi
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to US12/596,243 priority Critical patent/US8510633B2/en
Priority to JP2009511795A priority patent/JP4905866B2/ja
Publication of WO2008133087A1 publication Critical patent/WO2008133087A1/ja

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

　本発明の動作方法は、それぞれが複数のシンボルから構成され、各々のシンボルが複数のビットから構成され、更にシンボル単位での誤り訂正が可能な誤り訂正符号を記憶するＰＲＡＭ、ＲｅＲＡＭ、又は固体電解質メモリに適用される。当該動作方法では、各々のシンボルは互いに異なる参照セル１２を用いて読み出しが行われる。入力されたアドレスに対応する誤り訂正符号を構成するデータセル１１の読み出しデータに訂正可能な誤りが検出された場合、１ビットの誤りパターンである第１の誤りシンボルに対しては、その誤りビットに対応するデータセル１１のデータを訂正し、複数ビットの誤りパターンである第２の誤りシンボルに対しては、第２の誤りシンボルの読み出しに使用された参照セル１２のデータを訂正する。
PCT/JP2008/057285 2007-04-17 2008-04-14 半導体記憶装置及びその動作方法 WO2008133087A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/596,243 US8510633B2 (en) 2007-04-17 2008-04-14 Semiconductor storage device and method of operating the same
JP2009511795A JP4905866B2 (ja) 2007-04-17 2008-04-14 半導体記憶装置及びその動作方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-108569 2007-04-17
JP2007108569 2007-04-17

Publications (1)

Publication Number Publication Date
WO2008133087A1 true WO2008133087A1 (ja) 2008-11-06

Family

ID=39925545

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/057285 WO2008133087A1 (ja) 2007-04-17 2008-04-14 半導体記憶装置及びその動作方法

Country Status (3)

Country Link
US (1) US8510633B2 (ja)
JP (1) JP4905866B2 (ja)
WO (1) WO2008133087A1 (ja)

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KR20110043210A (ko) * 2009-10-21 2011-04-27 삼성전자주식회사 불휘발성 메모리 장치, 그것의 읽기 방법, 그리고 그것을 포함하는 메모리 시스템
CN102298972A (zh) * 2010-06-22 2011-12-28 慧荣科技股份有限公司 快闪记忆体的资料读取方法
JP2012221536A (ja) * 2011-04-12 2012-11-12 Sharp Corp 半導体記憶装置
JP2013020683A (ja) * 2011-07-14 2013-01-31 Toshiba Corp 不揮発性半導体メモリ
JP2013516725A (ja) * 2010-01-08 2013-05-13 インターナショナル・ビジネス・マシーンズ・コーポレーション スピン・トルク・ベースの記憶装置のためのリファレンス・セル
JP5363644B2 (ja) * 2010-02-16 2013-12-11 株式会社日立製作所 半導体装置
TWI455142B (zh) * 2010-04-08 2014-10-01 Silicon Motion Inc 快閃記憶體之資料讀取的方法以及資料儲存裝置

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US8281221B2 (en) * 2005-10-18 2012-10-02 Nec Corporation Operation method of MRAM including correcting data for single-bit error and multi-bit error
WO2008133087A1 (ja) 2007-04-17 2008-11-06 Nec Corporation 半導体記憶装置及びその動作方法
KR101466695B1 (ko) * 2008-04-30 2014-12-01 삼성전자주식회사 멀티 비트 레벨 데이터의 부호화 및 복호화 방법
US8589760B1 (en) * 2010-03-31 2013-11-19 Sk Hynix Memory Solutions Inc. Defect scan and manufacture test
US9570162B2 (en) * 2010-04-08 2017-02-14 Silicon Motion, Inc. Data read method for flash memory
US8572445B2 (en) * 2010-09-21 2013-10-29 Freescale Semiconductor, Inc. Non-volatile memory (NVM) with imminent error prediction
WO2013163243A2 (en) * 2012-04-24 2013-10-31 Being Advanced Memory Corporation Robust initialization with phase change memory cells in both configuration and array
US20140063927A1 (en) * 2012-08-28 2014-03-06 Being Advanced Memory Corporation Cell-Generated Reference in Phase Change Memory
JP2015053096A (ja) 2013-09-09 2015-03-19 マイクロン テクノロジー， インク． 半導体装置、及び誤り訂正方法
US9417957B2 (en) * 2013-10-04 2016-08-16 Infineon Technologies Ag Method of detecting bit errors, an electronic circuit for detecting bit errors, and a data storage device
KR102133209B1 (ko) * 2013-12-13 2020-07-14 에스케이하이닉스 주식회사 데이터 복호화 장치 및 데이터 복호화 방법
US10381102B2 (en) 2014-04-30 2019-08-13 Micron Technology, Inc. Memory devices having a read function of data stored in a plurality of reference cells
US9904595B1 (en) * 2016-08-23 2018-02-27 Texas Instruments Incorporated Error correction hardware with fault detection
KR102445560B1 (ko) * 2018-03-09 2022-09-22 에스케이하이닉스 주식회사 저항성 메모리 장치 및 그의 동작 방법
US11127459B1 (en) 2020-03-16 2021-09-21 Globalfoundries Singapore Pte. Ltd. Memory devices and methods of forming the same
US11381260B2 (en) * 2020-05-27 2022-07-05 The Royal Institution For The Advancement Of Learning / Mcgill University Architecture for guessing random additive noise decoding (GRAND)
KR20220168519A (ko) * 2021-06-16 2022-12-23 에스케이하이닉스 주식회사 에러정정방법을 이용하여 에러정정동작을 수행하는 반도체시스템
CN114138544A (zh) * 2021-12-03 2022-03-04 海光信息技术股份有限公司 数据读取、写入方法及装置、软错误处理系统

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WO2007046350A1 (ja) * 2005-10-18 2007-04-26 Nec Corporation Ｍｒａｍの動作方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110043210A (ko) * 2009-10-21 2011-04-27 삼성전자주식회사 불휘발성 메모리 장치, 그것의 읽기 방법, 그리고 그것을 포함하는 메모리 시스템
KR101601849B1 (ko) 2009-10-21 2016-03-09 삼성전자주식회사 불휘발성 메모리 장치, 그것의 읽기 방법, 그리고 그것을 포함하는 메모리 시스템
JP2013516725A (ja) * 2010-01-08 2013-05-13 インターナショナル・ビジネス・マシーンズ・コーポレーション スピン・トルク・ベースの記憶装置のためのリファレンス・セル
JP5363644B2 (ja) * 2010-02-16 2013-12-11 株式会社日立製作所 半導体装置
TWI455142B (zh) * 2010-04-08 2014-10-01 Silicon Motion Inc 快閃記憶體之資料讀取的方法以及資料儲存裝置
CN102298972A (zh) * 2010-06-22 2011-12-28 慧荣科技股份有限公司 快闪记忆体的资料读取方法
JP2012221536A (ja) * 2011-04-12 2012-11-12 Sharp Corp 半導体記憶装置
JP2013020683A (ja) * 2011-07-14 2013-01-31 Toshiba Corp 不揮発性半導体メモリ

Also Published As

Publication number Publication date
US20110016371A1 (en) 2011-01-20
JPWO2008133087A1 (ja) 2010-07-22
US8510633B2 (en) 2013-08-13
JP4905866B2 (ja) 2012-03-28

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