WO2000060660A1 - Procede de conception d'un dispositif a semi-conducteur et support d'enregistrement exploitable sur ordinateur - Google Patents
Procede de conception d'un dispositif a semi-conducteur et support d'enregistrement exploitable sur ordinateur Download PDFInfo
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- WO2000060660A1 WO2000060660A1 PCT/JP1999/001729 JP9901729W WO0060660A1 WO 2000060660 A1 WO2000060660 A1 WO 2000060660A1 JP 9901729 W JP9901729 W JP 9901729W WO 0060660 A1 WO0060660 A1 WO 0060660A1
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- design data
- design
- designing
- computer
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000013461 design Methods 0.000 claims abstract description 268
- 238000004422 calculation algorithm Methods 0.000 claims abstract description 86
- 230000006870 function Effects 0.000 claims abstract description 60
- 230000035772 mutation Effects 0.000 claims abstract description 13
- 230000002068 genetic effect Effects 0.000 claims description 80
- 238000005457 optimization Methods 0.000 claims description 47
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Definitions
- FIG. 16 is an explanatory diagram showing an example of a membership function and fuzzy variables
- Fig. 17 is a configuration diagram showing an example of an experimental software system
- Fig. 18 is a configuration diagram showing a hardware system example
- Figure 19 is an explanatory diagram showing an example of inference in the early generations
- Fig. 20 is an explanatory diagram showing an example of initial placement by fuzzy inference
- Fig. 21 is an explanatory diagram showing an example of an individual by genetic algorithm
- Figs. 22 to 24 are examples of experimental results of fuzzy inference and genetic algorithm.
- FIG. 25 is a graph showing an example of progress of costs
- FIGS. 26 to 28 are explanatory diagrams showing examples of logical cluster division.
- Fig. 5 shows a model of the arrangement of objects.
- Fig. 5 (a) shows the shape and netlist of block 1
- Fig. 5 (b) shows the chip area.
- rectangular blocks 1 are shown connected by wiring paths.
- the aspect ratio and dimensions of each rectangular block 1 are also shown.
- This figure also shows semiconductor chips whose dimensions and aspect ratios correspond to each other.
- the basic operation is as follows.
- FIG. 16 shows the membership functions and fuzzy variables used in the experimental software.
- the parameters for the fuzzy variables are determined based on the knowledge of the skilled technician.
- Block 1 (A) is created by connecting Block 1 (B) and Block 1 (C).
- Block 1 (B, C) is a lower-level block. It is created by connecting 1.
- An example of such a hierarchical relationship is shown in Fig. 26, for example.
- a to Z represent logic elements (block 1).
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Architecture (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
L'invention concerne un procédé de conception d'un dispositif à semi-conducteur selon lequel de meilleures valeurs initiales peuvent être obtenues lors du démarrage de la conception d'implantation et de la division de groupage logique, que le concepteur soit expérimenté ou non, et en particulier, de meilleures valeurs initiales peuvent être obtenues au début d'une conception complexe même si le concepteur est un débutant dans la conception de puces à semi-conducteur. Selon un logiciel destiné à une telle conception de semi-conducteur, un contrôleur principal (11) permet d'exploiter des fonctions telles que l'inférence floue (12) et un algorithme générique (13) et de produire en sortie un rapport contenant des dessins par la production en sortie (14) de résultats. La fonction d'inférence floue (12) lie des paramètres et des données d'entrée, elle juge si oui ou non un réglage des paramètres est nécessaire, elle règle les paramètres si un réglage des paramètres est nécessaire, et elle infère les blocs à agencer au centre et dans les coins d'une puce (S1701 à S1707). A partir du résultat d'inférence, l'algorithme générique (13) permet d'obtenir une première production et répète la sélection, les croisements, la mutation, une conservation de l'élite ainsi qu'une sélection naturelle (S1705, S1706), il permet d'obtenir un groupe de données de conception et des solutions optimales et il arrange les blocs sur une puce à semi-conducteur.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP1999/001729 WO2000060660A1 (fr) | 1999-04-01 | 1999-04-01 | Procede de conception d'un dispositif a semi-conducteur et support d'enregistrement exploitable sur ordinateur |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP1999/001729 WO2000060660A1 (fr) | 1999-04-01 | 1999-04-01 | Procede de conception d'un dispositif a semi-conducteur et support d'enregistrement exploitable sur ordinateur |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2000060660A1 true WO2000060660A1 (fr) | 2000-10-12 |
Family
ID=14235370
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP1999/001729 WO2000060660A1 (fr) | 1999-04-01 | 1999-04-01 | Procede de conception d'un dispositif a semi-conducteur et support d'enregistrement exploitable sur ordinateur |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO2000060660A1 (fr) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04199329A (ja) * | 1990-11-29 | 1992-07-20 | Toshiba Corp | 論理合成システム |
| JPH04338876A (ja) * | 1991-05-16 | 1992-11-26 | Mitsubishi Heavy Ind Ltd | 自動設計装置 |
| JPH04344572A (ja) * | 1991-05-21 | 1992-12-01 | Matsushita Electric Ind Co Ltd | 配線遅延最適化方法 |
| JPH0652250A (ja) * | 1992-07-31 | 1994-02-25 | Omron Corp | 機能自動生成装置 |
| JPH06290225A (ja) * | 1993-03-31 | 1994-10-18 | Mazda Motor Corp | 設計支援装置 |
-
1999
- 1999-04-01 WO PCT/JP1999/001729 patent/WO2000060660A1/fr active Search and Examination
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04199329A (ja) * | 1990-11-29 | 1992-07-20 | Toshiba Corp | 論理合成システム |
| JPH04338876A (ja) * | 1991-05-16 | 1992-11-26 | Mitsubishi Heavy Ind Ltd | 自動設計装置 |
| JPH04344572A (ja) * | 1991-05-21 | 1992-12-01 | Matsushita Electric Ind Co Ltd | 配線遅延最適化方法 |
| JPH0652250A (ja) * | 1992-07-31 | 1994-02-25 | Omron Corp | 機能自動生成装置 |
| JPH06290225A (ja) * | 1993-03-31 | 1994-10-18 | Mazda Motor Corp | 設計支援装置 |
Non-Patent Citations (7)
| Title |
|---|
| GU Z. C., et al., "Special Selection on VLSI Design and CAD Algorithms A Fuzzy-Theoretic Timing Driven Placement Method", IEICE Trans Fundam Electron Commun Comput Sci, 1992, Vol. E75-A, No. 10, pages 1280-1285. * |
| GU Z. C., YAMADA S., YONEDA S., "Timing Driven Placement Based on Fuzzy Theory", IEICE Trans Fundam Electron Commun Comput Sci, 1992, Vol. E75-A, No. 7, pages 917-919. * |
| JAYABHARATHI R., MANZOUL M. A., "Fuzzy logic for standard cell placement", Cybern Syst, 1993, Vol. 24, No. 3, pages 197-215. * |
| LIN R-B., SHRAGOWITZ E., "Fuzzy Logic Approach to Placement Problem", Proc Des Autom Conf, 1992, Vol. 29, pages 153-158. * |
| SHRAGOWITZ E., KANG E. Q., LEE J-Y., "Application of Fuzzy Logic in Computer-Aided VLSI Design", IEEE Trans Fuzzy Syst, 1998, Vol. 6, No. 1, pages 163-172. * |
| YAN J-T., "Area-Ratio-Constrained Min-Cut Partitioning for Row-Based Placement", Proc IEEE Midwest Symp Circuits Syst, 1994, 37th, Vol. 1, pages 403-406. * |
| YAN J-T., HSIAO P-Y., "Orientation Assignment of Standard Cells Using A Fuzzy Mathematical Transformation", Tencon, 1994, Vol. 2, pages 1014-1019. * |
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