WO2000060660A1

WO2000060660A1 - Method for designing semiconductor device and computer-readable recording medium

Info

Publication number: WO2000060660A1
Application number: PCT/JP1999/001729
Authority: WO
Inventors: Kazuhiko Eguchi; Toshiyuki Majima; Teruya Tanaka; Kenji Oshima
Original assignee: Hitachi, Ltd.
Priority date: 1999-04-01
Filing date: 1999-04-01
Publication date: 2000-10-12

Abstract

A method for designing a semiconductor device, by which better initial values at starting floor plan design and logical cluster division can be obtained whether the designer is skilled or not, and especially, better initial values at starting complex designing can be obtained even if the designer is a beginner of semiconductor chip designing. According to a software for such semiconductor designing, a main controller (11) causes the functions, such as fuzzy inference (12) and generic algorithm (13), to operate and outputs a report containing drawings through result output (14). The function of the fuzzy inference (12) reads parameters and input data, judges whether or not parameter adjustment is necessary, adjusts parameters if parameter adjustment is necessary, and infers blocks to be arranged in the center and corners of a chip (S1701 to S1704). From the result of inference, the generic algorithm (13) produces an early generation and repeats selection, cross over, mutation, elite conservation, and natural selection (S1705, S1706), obtains a group of design data on optimal solutions, and arranges blocks on a semiconductor chip.

Description

TECHNICAL FIELD Design method of semiconductor device and computer-readable recording medium

The present invention relates to a semiconductor device design technique, and in particular, to provide a novice of a semiconductor chip design for mounting an integrated circuit such as a VLSI (Very Large Scale Integration) to provide good initial conditions at the start of a complex design. The present invention relates to a design method of a semiconductor device that can be used, and a technique that is effective when applied to a computer-readable recording medium that records a program for realizing the design method. Background art

As a technology studied by the present inventors, the design of a semiconductor device on which an integrated circuit such as a VLSI is mounted is based on a function design process of designing the function of the integrated circuit based on system specifications and a design data obtained by the process. Logic design process for designing an integrated circuit at the logic gate level, and circuit design process for designing the logic gates at the transistor level based on the design data obtained by the logic design process. Each design process includes a layout design process for arranging and routing logic gates based on the design data and the design data obtained in the circuit design process.The design engineers proceed with each of the above design processes to satisfy the system specifications. As a result, the semiconductor device is completed through the subsequent manufacturing and testing processes.

For example, in the layout design process, the VLSI floor plan is to determine the approximate relative arrangement of the functional blocks on the VLSI chip. The layout problem of random logic circuits composed of cells (NAND gates, NOR gates, flip-flops, etc.), which are primitive logic components called so-called standard cells, has been a long-standing effort of many researchers. It is extremely highly automated by this technology, and the effective EDA (Electronic Design Automation) tool that implements it is used as a tool.

However, advanced VLSIs in recent years have not only It is equipped with various memory blocks, CPU modules, blocks for many peripheral devices, and sometimes analog modules. Therefore, the floorplan for determining the relative placement of these blocks is an important design step that determines the final chip size and performance. Already, several floorplanning tools have been commercialized, which provide useful information to support chip design and provide a user-friendly floorplanning environment, but are basically editing tools. is there.

On the actual design floor, this floor plan placement decision still relies on the designer's insight. And, as a result, it depends heavily on who did it. And this is a tedious task, with skilled technicians generally giving better results in less time than novice or less experienced technicians. However, the time required to complete a design, even for a skilled technician, depends on what information was initially provided. In the case of unskilled engineers, the design quality of the final chip, which is the result of the design, and the time required to complete the design also strongly depend on what initial values are given.

Thus, the results of the present inventors' examination of the above-described VLSI floor plan are shown below. That is, in the present invention, it is better to give a better initial value at the start of floor blanking design for skilled engineers and unskilled engineers than to give the final design result at once by automatic design. Is the main focus. As this approach,

(1) We tried to solve it as a global optimization problem by an optimization processing method (for example, a genetic algorithm).

(2) The actual design site has a lot of knowledge and know-how of skilled engineers, but many of them are transmitted in a pre-language form. We arranged these to some extent in the form of natural language and tried to create a fuzzy rule.

(3) Based on the fuzzy rules obtained in the previous section, we tried to infer the initial placement of macro blocks. Finding all blocks by fuzzy inference requires complicated rules and parameters.

—It will make it difficult to adjust the data and move away from reality. However, some high-priority blocks were determined to be significant enough to be determined by fuzzy inference.

(4) Apply the placement information obtained by the fuzzy inference in the previous section to the initial data generation of the genetic algorithm, and leave the block that can be practically determined by the fuzzy inference as it is. We considered a method in which a block that has little or no significance in deciding the placement by fuzzy inference is left to the optimization problem solving of the genetic algorithm.

(5) An experimental program that implements the above (1) or (4) was developed, and computer experiments were performed. In some cases, results approaching the design results of a skilled engineer could be obtained.

As will be described in detail later, in this example, a comparison of the design results by a skilled engineer, the results obtained using only genetic algorithms, and the results obtained by using fuzzy inference for the generation of the initial generation is shown for three types of examples. In the case of the genetic algorithm alone, there is still a large difference from the results obtained by skilled engineers, but in combination with the fuzzy inference, it is possible to obtain results close to those designed by humans. For example, as a technique using only an optimization processing technique such as a genetic algorithm, there is a technique described in Japanese Patent Laid-Open No. 10-275175.

Therefore, an object of the present invention is to provide a better initial value at the start of floor plan design and further at the start of logical cluster division, and particularly to provide a good initial condition at the start of a complex design such as a semiconductor chip design. It is an object of the present invention to provide a method of designing a semiconductor device that can be used, and a computer-readable recording medium storing the design method as a program.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The following is a brief description of an outline of typical inventions among the inventions disclosed in the present application.

According to the present invention, based on the above-mentioned approaches (1) to (5), a design method employing an optimization processing method such as a genetic algorithm and a fuzzy inference based on knowledge of a skilled engineer and fuzzy rule conversion of know-how. Is provided.

Next, it will be described more specifically.

The present invention provides a function design step of designing a function of an integrated circuit based on system specifications, and logically setting an integrated circuit at a logic gate level based on design data obtained thereby. A logic design process for performing logic planning, a circuit design process for designing a logic gate at a transistor level based on the design data obtained thereby, a design data obtained from the logic design process, and a circuit design process. For example, the present invention is applied to a semiconductor device design method including a late design process of arranging and wiring logic gates based on the obtained design data.

That is, in the method of designing a semiconductor device according to an example of the present invention, in the creation of design data in each of the design steps, a step of creating a plurality of design data groups using fuzzy inference; And a step of selecting a design data group having a high degree of conformity using an optimization processing method based on the plurality of design data groups created in each of the above steps; and a step of selecting the selected design data group. Based on the above, the following multiple design data groups are created by using an optimization processing method and sequentially repeated while selecting a design data group with a high degree of conformity, to create a design data group that provides an optimal solution. Process is provided.

Also, in another method of designing a semiconductor device according to the present invention, in the creation of the design data in each of the design steps, a step of creating a partial design data group that becomes an optimal solution using fuzzy inference; A step of creating a plurality of design data groups, a step of selecting a design data group having a high degree of conformity using an optimization processing method based on the created plurality of design data groups, and a step of selecting the selected design data groups. Based on the data group, the next multiple design data groups are created using the optimization processing technique and are sequentially repeated while selecting the design data group with a high degree of conformity. The step of creating the is provided.

Further, the present invention also provides a computer-readable recording medium in which a program for causing a computer to execute the method for designing a semiconductor device is recorded.

In particular, the present invention is applied to floor planning in the layout design process, uses a genetic algorithm as an optimization processing method, generates an initial design data group of the genetic algorithm using fuzzy inference, and generates an optimal solution. A plurality of blocks are arranged on a semiconductor chip using different design data groups. In addition, coding, evaluation functions, mutation, and fuzzy inference in this floor planning Each of them has characteristics described in detail below. Further, the present invention is applied to the logical cluster division in the logical design process, using a genetic algorithm as an optimization processing method, generating an initial design data group of the genetic algorithm using fuzzy inference, and Multiple blocks are divided into clusters using different design data groups. Further, the fuzzy inference and the evaluation function in this logical cluster division have characteristics which will be described in detail later.

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

(1) According to the semiconductor device design method and the computer-readable recording medium of the present invention, an optimization processing method such as a genetic algorithm and a fuzzy inference based on the fuzzy rules of the knowledge and know-how of engineers are adopted. By being applied to floor planning in the layout design process, it is possible to provide better initial values at the start of floor plan design. In particular, it becomes possible to give good initial conditions to a beginner of a semiconductor chip design at the start of a complicated design.

(2) According to the semiconductor device design method and the computer-readable recording medium of the present invention, an optimization processing method such as a genetic algorithm and fuzzy inference based on the fuzzy rules of engineers' knowledge and know-how are adopted. By being applied to the logical cluster division in the logical design process, it is possible to provide a better initial value for dividing the logical cluster. In particular, it is possible to give good initial conditions to a beginner of a complex design for a beginner of semiconductor chip design and the like.

(3) As a result, according to the present invention, floorplanning and logical cluster division in a better initial state can be provided in floor planning in a layout design step and logical cluster division in a logical design step. It is possible to realize an automatic design that can obtain better effects in both the design efficiency and the design quality of the final semiconductor chip in the design of a semiconductor device, regardless of whether it is a skilled person or an unskilled engineer. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a flowchart showing a method of designing a semiconductor device according to an embodiment of the present invention. FIG. 2 is an explanatory diagram showing an example of floor planning in the semiconductor device of this embodiment. FIG. 3 shows a genetic algorithm. Fig. 4 is an explanatory diagram showing a coding example, Fig. 5 is an explanatory diagram showing an example of an arrangement model, Fig. 6 is an explanatory diagram showing an example of evaluation items of an evaluation function, and Fig. 7 is an explanatory diagram showing a mutation example. Figures 8 to 10 are explanatory diagrams showing examples of test data, Figures 11 to 13 are explanatory diagrams showing examples of experimental results of the genetic algorithm, and Figures 14 and 15 show examples of rules for fuzzy inference. Fig. 16 is an explanatory diagram showing an example of a membership function and fuzzy variables, Fig. 17 is a configuration diagram showing an example of an experimental software system, Fig. 18 is a configuration diagram showing a hardware system example, Figure 19 is an explanatory diagram showing an example of inference in the early generations Fig. 20 is an explanatory diagram showing an example of initial placement by fuzzy inference, Fig. 21 is an explanatory diagram showing an example of an individual by genetic algorithm, and Figs. 22 to 24 are examples of experimental results of fuzzy inference and genetic algorithm. FIG. 25 is a graph showing an example of progress of costs, and FIGS. 26 to 28 are explanatory diagrams showing examples of logical cluster division. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings of FIGS. In all of the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.

First, an example of a method for designing a semiconductor device according to the present embodiment will be described with reference to FIG. The method of designing a semiconductor device according to the present embodiment is, for example, a method of designing a VLSI chip, and includes a function design step (S 101) of designing a function of an integrated circuit based on system specifications, A logic design process (S102) for performing a logic design of an integrated circuit at the logic gate level based on data, and a circuit design for designing a logic gate at a transistor level based on the design data obtained thereby. A step (S104), a layout design step (S104) for arranging and routing logic gates based on the design data obtained in the logic design step and the design data obtained in the circuit design step. The design data obtained by these design processes The chip manufacturing process (SI 05) is performed based on this, and the semiconductor device is completed through the packaging and testing process (S 106).

In the present embodiment, when creating design data for each design process, optimization processing methods such as genetic algorithms and fuzzy inference based on knowledge of skilled engineers and know-how fuzzy rules are used. Applying the location information obtained by fuzzy inference to the initial data generation of the genetic algorithm, leaving blocks that can be practically determined by fuzzy inference as it is, and making little or no significance in determining the location by fuzzy inference Plock adopts a method that leaves it to the optimization problem solving of the genetic algorithm.

Next, an example of application to floor planning in the layout design process of step S104 is shown in FIG. 2, for example, as shown in FIG. 2, each block 1 (# 0 to # 9) is arranged in the internal area, and IZO The layout and wiring of the VL SI chip where the buffer 2 is placed will be described in order for each item. Here, we show examples of three types of examples using genetic algorithms and fuzzy inference.

1. Floor planning by genetic algorithm

Some examples of EDA of this genetic algorithm can mainly obtain the ability to optimize this algorithm and the ability to avoid local optimization. Here, by applying the genetic algorithm to the VLSI design floorplanning stage, even a beginner in semiconductor chip design can give better initial conditions at the start of a complex design process. It is a technique to make.

As a general procedure of this genetic algorithm, for example, as shown in an example in FIG. 3, first, an initial generation is set (S301), and the fitness by the evaluation function is evaluated (S302). Then, elite preservation (S303), selection Z crossover (S304), mutation (S305), and selection (S306) for the next generation are repeated until the termination condition (S307). The process ends when the end condition is reached.

1. 1. Coding

Coding is the association between a chromosome and a target optimization problem. The coding scheme for this example is shown in Figure 4, for example. Figure 4 (a) shows the tip Block 1, located in the internal region of Fig. 4, shows the structure of the chromosome. Here, the width indicating the size of each block 1 is W, the height is H, the XY coordinates of the center are (Xi, Yi), and the rotation is Ri. For example, when R i = 0, the shape is portrait, and when R i = 1, the shape is landscape.

First, define the XY coordinates as shown in the figure. In this case, the rotation of block 1 is also considered. Prepare three chromosomes, and call them X chromosome, Y chromosome, and rotating chromosome. Block 1 (# 0) located at (X0, YO) shown in Fig. 4 and having zero rotation (R) is represented as shown below.

• The 0th gene on the X chromosome is X0.

· The 0th gene on the Y chromosome is Y0.

• The 0th gene of the rotating chromosome is 0.

Next, block 1 (# 1) located at (X1, Y1) and rotated 90 degrees is shown below.

♦ The first gene on the X chromosome is X1.

· The first gene on the Y chromosome is Y1.

• The first gene on the rotating chromosome is 1.

It is permissible in this coding scheme for blocks 1 to overlap or to extend beyond the frame. A method is employed in which the evaluation function is evaluated to eliminate overlaps and protrusions between the blocks 1.

1. 2. Application of Genetic Algorithm to Floorplanning

Fig. 5 shows a model of the arrangement of objects. Fig. 5 (a) shows the shape and netlist of block 1, and Fig. 5 (b) shows the chip area. In this figure, rectangular blocks 1 are shown connected by wiring paths. The aspect ratio and dimensions of each rectangular block 1 are also shown. This figure also shows semiconductor chips whose dimensions and aspect ratios correspond to each other. The basic operation is as follows.

(1) Generate the initial generation randomly.

(2) The fitness is evaluated by calculating the evaluation function.

(3) Generate offspring. Save the elite individual. Perform selection, crossover, and mutation. (4) Repeat steps 2 and 3.

(5) After repeating the generation operation to some extent, select the best offspring.

1. 3. Evaluation function

The minimum number of items for the components of the evaluation function is selected based on the skills of the skilled designer. When evaluating the evaluation function, the actual wiring length L i between the blocks 1, the overlapping portion S i between the blocks 1, and the portion OV i of the block 1 protruding from the designated area are taken into consideration. FIG. 6 shows an example of the calculation of the evaluation function parameters. Fig. 6 (a) shows the actual wiring length, Fig. 6 (b) shows the overlapping part, and Fig. 6 (c) shows the protruding part. L i is the effective center-to-center wiring length of each block 1 weighted by the number of connections, and includes the wiring length of each block 1 and the wiring length between the block 1 and the IZO buffer 2. The wiring path between block 1 and I / 〇buffer 2 weights the wiring length of block 1 by 10 times. The total number of IZO buffer 2 interconnects is limited by the number of pins. The number of VLSI external pins varies from tens to hundreds. Current technology is capable of handling up to 104 pins. On the other hand, the number of wiring paths between block 1 1 0 ³ 1 0 ⁴ of the order - a. However, the experience of the connection of the buffer 2 per wiring route to the placement quality is 10 to 20 times that per block 1 wiring route.

The evaluation function Ε is given by Equation 1 below.

E = a∑ L i + j3 ∑ S i + 7 ∑OV i

Here, α, β, and γ are adjustment coefficients as weights. Each evaluation item is shown in Figure 6. From the preliminary experimental results, hi = 1, / 3 = 10 and γ = 100 are selected.

1. 4. Mutation

Mutation is, for example, as shown in FIG. 7 in which the selected block 1 is randomly moved by a certain distance with respect to the chromosome shown in FIG. 4 (FIG. 7 (a)) (FIG. 7 (b) )), And randomly change the orientation of the selected block 1 (Fig. 7 (c)). This moving distance is also determined at random, but is set to a value smaller than a predetermined value. How many mutations in a block The ratio of doing is programmable and is determined based on experience.

1.5. Test data

For the purpose of the experiment, three examples as shown in Figs. 8, 9, and 10 were prepared as test data. The test data is based on what was originally designed by a skilled design engineer. Test data (1) and (2) corresponding to FIG. 8 and FIG. 9 are constructed from an actual design example, and test data corresponding to FIG.

(3) was created intentionally to test the performance of this algorithm. In FIGS. 8, 9, and 10, the wiring between the block 1 and the IZO buffer 2 and the wiring between the blocks 1 have a width corresponding to the number of wires.

What applies to the program is the netlist (internal blocks 1 and I Z

(4) Connection information between buffers 2) Only data on target chip dimensions and block 1 dimensions.

1.6 Results of Genetic Algorithm Experiment

Figures 11, 12, and 13 show the results when floorplanning was performed using a genetic algorithm. The left side (a) of each figure corresponds to the examples of FIGS. 8 to 10 and shows a floor plan created by a skilled person using test data. Figure (b) on the right shows the design results of the genetic algorithm created by the experimental program. In each case, the value of the evaluation function, that is, the cost, converges to a constant value after generation of 60 to 65 generations (iteration generation). The number of individuals in the initial generation is set to 2000. The number of offspring emanating from the parent is 150% and the total number of offspring is 30000. However, the number of individuals that can be parents for the next generation is 20000. The remaining 100 individuals are discarded. The rate of mutation is 8%. In the above case, the number of surviving elites is 40.

In the case of the test data (1) shown in Fig. 11, the cost (that is, the value of the evaluation function) of the design example created by the skilled designer is 715. This figure consists of the effective wiring length between block 1 and I / O buffer 2. Therefore, the smaller the value, the better the result. The number of initial generations was set to 20000 using a genetic algorithm, and the cost of generating up to 70 generations was 9766. The cost reached this value when it was generated up to 46 generations, after which no improvement was seen. Therefore, it can be considered that the local convergence has been achieved.

Observing the results based on the genetic algorithm, if you are a skilled designer, based on your individual experience as a technician, Block 1 (# 9), Block 1 (# 2) and Block 1 (# 8) Can be pointed out as inappropriate.

In the case of test data (2), better results were obtained using the genetic algorithm than in the case of test data (1). The cost was 501 in the manual design, but it was 5266 in the design generated by the genetic algorithm. However, again, skilled technicians can point out that block 1 (# 2) and block 1 (# 0) should be exchanged.

Regarding the test data (3), the results based on the genetic algorithm have not yet reached the desired level even after the evaluation function was saturated in the 50th generation. There is still much room for improvement in this area.

2. Problems in the analysis of genetic algorithms

Genetic algorithms are probable simulations of evolutionary processes in the field of biology. In this algorithm, the initial generation is often determined at random by a randomization method (the number generation method), so the final result often depends on this initial condition.

Genetic algorithms are generally aimed at global optimization, but the end result depends heavily on the initial generation combination. In other words, it is extremely unlikely that a final result will be produced that uses information that was not included in the genes of the early generation as a component, except when it occurs as a mutation effect. It is necessary to produce a large number of individuals that make up the initial generation to produce better results. However, if a large number of individuals are prepared for the initial generation, the calculation time is required alone. It is difficult to predict how many generations will be required to obtain more satisfactory results.

3. Proposal of fuzzy inference applied to early generations in genetic algorithms Genetic algorithms are an excellent method for solving optimization problems, but as mentioned above, there is still much room for improvement. . Practical experience and much There are a large number of skilled workers with an accumulation of knowledge. Here, we propose a method of applying fuzzy inference based on the knowledge of a skilled designer to the setting of optimal initial conditions in the operation of a genetic algorithm.

The fuzzy theory has been widely applied when constructing automatic control systems based on the knowledge of experts. Fuzzy theory is a good fit when the object cannot be described by strict mathematical equations or algorithmic methodologies or is difficult to describe. Demonstrate the nature. Inference based on fuzzy theory (fuzzy inference) is well known in the field of automatic control.

Here, the proposed method applies fuzzy inference extracted from the expertise of experienced VLSI designers to obtain limited initial conditions in genetic algorithms. In order to apply fuzzy inference, it is necessary to obtain expert knowledge. However, the knowledge applied to floorplanning placement issues described in natural language is often complex and ambiguous.

3.1 Design knowledge

The following example describes what a VLSI design engineer thinks (knowledge and know-how) during floor planning. The following modules correspond to Block 1.

(1) The position of the IZO buffer 2 (located around the chip) is given. (2) Check that the outer shape of the chip is as square as possible.

(3) Make sure that the chip dimensions are set as small as possible.

(4) Make sure that relatively large blocks 1, such as CPU cores and RAMs, are placed along the edge of the chip, preferably at the corners.

(5) Modules with high connectivity to the I / O buffer 2 (block 1) should be located along the periphery of the die, ie along the edge of the chip area, regardless of shape and size.

(6) If the module's connectivity with the IZO buffer 2 is low, compare the die if the module (block 1) dimensions are not so large or if the module's connectivity with other modules is high. It may be arranged at the target center. (7) The connectivity between the I / O buffer 2 and the module (block 1) placed inside can be considered similar to the centrifugal system, and the connection 14 between the modules placed inside is connected to the centripetal system. You can think alike.

(8) Modules (Block 1) should be placed adjacent to each other if they show high connectivity.

The above guidelines are, of course, not conclusive, and actual design situations will require many more detailed guidelines, weighing their characteristics, performance, cost and other factors. However, when fuzzy inference is performed on the initial generation of genetic algorithms based on the above information, the generality of application is not impaired.

3. 2.

The following inference rules are derived based on the design guidelines described above.

(1) For the module (block 1) located near the center of the chip, select a module with low connection to the IZO buffer 2, and select a module with high connection to this module in an adjacent position. To place. However, the module to be placed near this center should be a relatively small module unless it is a module selected according to the rules described above.

(2) For modules to be placed in corners (block 1) (similarly for all four corners), they have moderate connectivity to larger modules and adjacent modules Choose one.

(3) Modules with relatively high connectivity to IZO buffer 2 (block 1) should be located along the periphery of the effective chip area. However, this shall not apply if this peripheral area has already been allocated to another module as a result of the application of the aforementioned rules.

The above rules in fuzzy inference can be shown, for example, in Figure 14 for modules located near the center of the chip and in Figure 15 for modules to be located in the corners of the chip. . For example, in Fig. 14, when the connectivity with IZO buffer 2 is low and the connectivity with other modules is high, W indicates that if the size of block 1 is small, the conformity is high; if it is medium, it is moderate; if it is large, the conformity is low. The same applies to other cases.

Membership functions and fuzzy variables have been developed for the fuzzy rules described above. For example, Figure 16 shows the membership functions and fuzzy variables used in the experimental software. The dimensions of block 1, the connectivity between modules (block 1) and the connection to IZO buffer 2 This is to evaluate the gender. The parameters for the fuzzy variables are determined based on the knowledge of the skilled technician.

For example, as for the connectivity with I / O buffer 2 shown in Fig. 16 (a), when the amount of wiring is normalized and the average value is set to 1.0, the connectivity is low at 1.0 or less and 2 It is said that connectivity is high at 0 or more. Regarding the connectivity with other modules (block 1) shown in Fig. 16 (b), the connectivity is low at 0.5 or less, the connectivity is moderate near 0.8, and the connectivity is 1.3 or more. It is said that the nature is high. As for the dimensions of block 1 shown in Fig. 16 (c), the average value is assumed to be 1.0, small at 0.6 or less, moderate near 1.0, and large at 3.0 or more. Figure 16 (d) shows the positions of high, medium, and low conformity.

4. Implementation

Experimental software has been developed to verify the effectiveness of this proposal, and Figure 17 shows an overview of this software. In this software, the main controller 11 operates the functions of the fuzzy inference 12 and the genetic algorithm 13 described above, and outputs the drawing as a report via the result output 14. In the function of fuzzy inference 12, the parameters and input data are read (S1701), the presence or absence of parameter adjustment is determined (S1702), and if parameter adjustment is necessary, the parameters are adjusted. (S1703), the block 1 to be arranged at the center and corner of the chip is inferred (S1704). The result of this inference is generated in the function of the genetic algorithm 13 by generating an initial generation (S1705), and selection, crossover, mutation, elite conservation, and selection are repeatedly executed (S1706). This software, for example, as shown in Figure 18, the main controller 1 In addition to 1, storage devices such as ROM and RAM 21; input devices 22 such as a keyboard and mouse; output devices 23 such as displays and printers; and auxiliary storage devices 24 such as disk devices It is configured to operate on a computer system consisting of hardware. The algorithms such as the fuzzy inference 12 and the genetic algorithm 13 are recorded as a program on a recording medium 25 such as a CD-ROM that can be inserted into and removed from the auxiliary storage device 24. 5 is read out to the storage device 21 and each process is executed under the control of the main controller 11.

In this software, prior to applying the genetic algorithm 13, the position of the block 1 is inferred by fuzzy inference 12 based on the fuzzy rule described in 3.2 above. The software also adjusts parameters for fuzzy variables if needed. The procedure for this parameter adjustment follows the Back propagation Method;

The software first attempts to find the best block 1 to place near the center of the chip. This software employs the fuzzy rule shown in FIG. 14 and the membership function described in FIG. The block 1 selected by this procedure is placed at the center of the chip. Selected block 1 is excluded from the subsequent steps.

Next, this software evaluates the conformity value between each block 1 and each corner based on the fuzzy rule described in FIG. The membership functions are the same as those described above. The four corners are the upper left, lower left, lower right, and upper right corners. Here, a trial value is calculated for the combination of block 1 and the corner. The best combination of Block 1 and the corner where it is placed will give the best fit. Therefore, it is confirmed that the block 1 of the best combination selected is placed at the corner, and that the placed block 1 does not protrude from the chip boundary.

Next, this software examines the remaining combinations of block 1 and selects a candidate for how to place block 1 in the remaining corners. The software tries to find the best candidate for each corner, according to the fit values listed first, starting with the highest number. However, when the value of the conformance value is smaller than a certain value, The software finishes the inference process and only recommends two or three candidates.

Once the inference result is obtained, the initial generation is generated randomly according to the same method used in the conventional method (random number generation). The inferred block 1 gene is rewritten based on the result of the inference. The rate at which genes are rewritten can be freely programmed. However, if the conformance value is larger than a certain value, the gene is rewritten 100%. Also, if this fit falls below that value, the fit will rewrite some percentage of the gene, not 100%. At this time, the software starts the normal genetic algorithm. For example, FIG. 19 illustrates the above process for test data (1). At this time, the software reads the information on the geometric arrangement and the connectivity of block 1 from the data file as a set of input parameters. These data files also read the fuzzy parameters. The connectivity information is represented by a connectivity matrix expressed in a tabular format. The right half of the table shows the connection information between block 1 and I〇buffer 2, and the left half shows the connection information between block 1 and block 1.

The numbers shown in the table are the normalized values of the wiring amount between blocks 1. For the connection with the 1 / O buffer 2, the wiring amount is weighted 10 times. This means that the absolute value of the wiring between I / O buffer 2 and block 1 is small (limited by the total number of pins), despite having a greater influence on the floor plan layout than the wiring between blocks 1 Because it is expressed). First, in this software, block 1 (# 3) is selected as block 1 located in the center by fuzzy inference 12. The matching value is 0.8823 (S1901).

Next, infer the combination of block 1 to be placed at the corner. The best fit in this case is to place block 1 (# 1) in the upper right corner (fit value is 0.547516) (S1902). The next possible match is to place block 1 (# 0) in the upper left corner (fit value is 0.459838) (S1903). The next conformance is to place block 1 (# 4) in the lower left corner. The conforming value of this block 1 (# 4) is 0.3955 7 (S1904 ). The above example is a meaningful reasoning.

Block 1 (# 7) and block 1 (# 9) are considered as candidates to be placed in the lower right corner (S1905). However, since the relevance values are extremely small, 0.15 0 2 0 4 and 0.1 0 5 0 7 1, respectively, it is necessary to determine whether these numbers are relevant to meaningful inference results. It is difficult. Here, the initial generation randomly generated based on the editing and merging functions is rewritten (S1906). When the inference result is meaningful, 100% of the genes are replaced. If the fit value is low (below 0.2), such as Block 1 (# 7) and Block 1 (# 9) in the lower right corner, then apply Block 1 (# 7) and Block 1 (# 9) And apply the best result. This experimental program consists of about 450 lines of code and is written in C language.

4. 1. Individual examples of implementation

Figures 20 and 21 show how the position information (coordinates, etc.) of block 1 obtained by fuzzy inference 12 is reflected in the processing of genetic algorithm 13. In FIG. 20, solid block 1 (# 3, # 0, # 4, # 7, # 1) is obtained by fuzzy inference 12 and the remaining block 1 (# 2, # 5, # 6, # 9, # 8) are left undetermined by the fuzzy inference 12 and left to the genetic algorithm 13.

For each block 1, there are a plurality of individuals 1 to n as shown in FIG. 21, and uppercase letters indicate the center coordinate values of block 1 obtained by fuzzy inference 12. However, since the rotation (] "= 0 or 1) follows the generation of random numbers, adjust each case so that it does not protrude from the chip area. Thus, for example, for block 1 (# 0), r The values of (AO, BO) when 0 = 0 and (A 0, BO) when r 0 = 1 are different, but are the same throughout all individuals if r 0 is the same. , Italic numbers indicate values generated by random numbers.

Therefore, as shown in Fig. 21, for block 1 (# 0, # 1, # 3, # 4, # 7), the value (gene) determined by fuzzy inference 1 2 is carried over to the final solution. . On the other hand, in block 1 (# 2, # 5, # 6, # 8, # 9), random numbers are generated. The optimal value is optimized by the genetic algorithm 13 and the best individual at the time when the termination condition is satisfied is selected as the solution. This best individual becomes the design data group of the block arrangement in floor planning.

5. Experimental results

Fig. 22, Fig. 23 and Fig. 24 show the results of experiments on floor planning by a genetic algorithm 13 based on the early generation to which fuzzy inference 12 based on fuzzy theory is applied.

5. 1. Test data (1)

Figure 22 shows the results of applying the fuzzy inference 12 and the genetic algorithm 13 to the test data (1). Results).

Block 1 (# 3) is placed in the center, Block 1 (# 0) is placed in the upper left corner, Block 1 (# 4) is placed in the lower left corner, and Block 1 (# 1) is placed in the upper right corner. (This is the result of inference) is the same as the design result by the skilled design engineer. These conditions are set as initial conditions, and are maintained as conditions that are not changed even when the operation is performed by the genetic algorithm 13. As shown in FIG. 22, the number of candidates for block 1 located in the lower right corner is 10%. How the remaining blocks 1 are arranged is left to the genetic algorithm 13. This result was obtained by performing 50 generation operations on 1 000 initial generations. The required calculation time was much less than when the design was performed using only the genetic algorithm 13. The time required to obtain the results shown in FIG. 11 was, for example, 4 hours on Sparc 10, but was 40 minutes in the example shown in FIG. The resulting cost of this experimental software was 7476. This value is a cost close to 7 155 when designed by a skilled design engineer. Compared to 9766, the cost of using only genetic algorithm 13, it can be said that substantial progress has been achieved.

The visual impression of this result is good. The results of a review and evaluation by skilled personnel indicated that the practical application has great potential.

5. 2. Test data (2) Figure 23 shows the results of test data (2). The relative position of each block 1 is the same as the design result by the skilled design engineer.

The conforming values are 0.741 509 for block 1 (# 3) located at the center of the chip, 0.51 6279 for block 1 (# 0) located at the upper left corner, and the block at the lower left corner. 1 (# 5) is 0.42 1 739, block 1 in the lower right corner (# 7) is 0.30484, and block 1 (# 1) in the upper right corner is 0.2242806. The resulting cost after 50 generations was 4820. This is the first generation 1

This is the case where the number is set to 000 (half of the case with only the genetic algorithm 13), and an 8% improvement is obtained as compared with the result of the genetic algorithm 13 alone. This value has been improved when compared to the results by experienced designers.

5. 3. Test data (3)

Figure 24 shows the results of test data (3). The fit value for block 1 (# 9) located in the center of the chip is 0.740964, and the fit value for block 1 (# 8) located in the upper left corner is 0.5586265. The conforming value of block 1 (# 7) located in the upper right corner is 0.231 984. The block 1 with the highest suitability for the lower left corner is block 1 (# 0), which has a fit value of 0.157509, and the block 1 with the next highest suitability is block 1 (# 1). ) And 0.121 322. If block 1 (# 4) is placed in the lower right corner, it will be 0.12 1 322.If block 1 (# 1) is placed in the lower right corner, the corresponding value will be 0.1 1 0256, and block 1 (# 0 in case of 6).

It becomes 1 10256.

What we have learned from our experience and preliminary experiments is that if the fitted value falls below 0.2, it is difficult to judge whether it makes sense or not.

From this, it can be seen that in the upper left corner and upper right corner, no block 1 clearly exceeds the suitability of the block 1 arranged based on the result obtained by the fuzzy inference 12. However, in the arrangement with respect to the lower left corner, Block 1 (# 0) and Block 1 (# 1) are slightly more compatible than the other Block 1. Block 1 (# 4) and block It can be said that 1 (# 1) is a candidate with relatively high suitability. When block 1 (# 1) is placed in the lower right corner, the conforming value is 0.11 0256, and when block 1 (# 1) is placed in the lower left corner, the conforming value is 0.12 1322. Therefore, an attempt was made for the latter case. Placing Block 1 (# 9) in the center, placing Block 1 (# 8) in the upper left corner, and placing Block 1 (# 7) in the upper right corner are fixed. Under these conditions, the following three combinations are examined for their quality. Block 1 (# 1) in the lower left corner, block 1 (# 4) in the lower right corner, block 1 (# 0) in the lower left corner, block 1 (# 4) in the lower right corner, block 1 (# 0) is placed at the lower left corner and block 1 (# 1) is placed at the lower right corner.

Block 1 (# 1) in the lower left corner and Block 1 (# 4) in the lower right corner provided the best cost performance. The cost in this case is 6627, which is close to 6601 when performed manually, which is a large improvement compared to 9324 when performed only with the genetic algorithm 13. Considering the results, it was as satisfactory as in the case of test data (1) and test data (2). Therefore, this objective of "giving good initial conditions at the beginning of complex designs such as semiconductor chip design" has been achieved.

5. 4. Changes in cost (value of evaluation function)

The cost is calculated based on the evaluation function defined by Equation 1 above. Figure 25 is a graph showing the change in cost with the number of generations of test data (1).

Genetic algorithm for randomly generated early generations (1 000 individuals) 1

In case 3, the cost converges after 50 generations, and there is almost no improvement from the cost of about 10,000. This genetic algorithm 13 fell to the local optimum.

Genetic algorithm with fuzzy inference 1 with the initial generation number set to 1 000 Converges around 45 generations in case of 13 and in this case is about the same level as when an expert designs Is approaching.

6 ^ mouth 0BH Therefore, when applied to floor planning in the layout design process of step S104 in FIG. Although we have proposed to apply 1 2, experimental results have shown that this may be quite practical. The purpose of this was to “provide good initial conditions at the beginning of complex designs such as semiconductor chip design”, but this goal was largely achieved. Furthermore, by adjusting the parameters of fuzzy inference 1 and 2 more appropriately based on practical experience, and by considering the handling of genes when the fitness value of each block 1 is low, the design efficiency and design quality can be improved. A better effect can be obtained on both sides.

Next, an example of application to the logical cluster division in the logical design process of step S102 in FIG. 1 will be described for a case in which the same fuzzy inference 12a and genetic algorithm 13a as in the above floorplanning are used. I do.

1 1. Logical Cluster Partitioning in Genetic Algorithm

In the VLSI design as described above, processing the whole chip at once is not efficient in terms of data scale, and it is necessary to divide it into several blocks, and this is noticeable mainly at the layout stage. become. Automatically arranging and wiring large circuits at once reduces the mounting rate (number of transistors per area) in block 1, and using a large number of small blocks 1 This leads to an increase in the wiring area. To solve this problem, it is effective to divide the logical data into suitable size ranges.

Logical data is usually created hierarchically, for example, as shown in FIG. In Figure 26, Block 1 (A) is created by connecting Block 1 (B) and Block 1 (C). Similarly, Block 1 (B, C) is a lower-level block. It is created by connecting 1. An example of such a hierarchical relationship is shown in Fig. 26, for example. In the figure, A to Z represent logic elements (block 1).

Dividing logical data into groups by focusing on the hierarchical structure of such logical data and dividing appropriate data into groups is called logical cluster division. Figure 28 shows an example of this division. A method for automating this cluster division in the same manner as the floor planning An example is shown below.

1 2.

First, a block 1 in which the number of logic elements and the number of internal nets within an appropriate range and the number of nets connected to the outside are small is determined by fuzzy inference. At this time, in the case of a logical hierarchy that includes those already obtained as a cluster, as in block 1 (C) in Fig. 28, the range excluding that cluster is considered as a cluster. In the example of Figure 27, cluster 2 is created except cluster 3. This fuzzy inference 1 2a is performed on blocks 1 of all layers, and only those that correspond are used as clusters, and the parts that do not apply remain undecided.

Next, the initial value of the cluster is randomly determined for the remaining part, and the optimal solution is obtained by the genetic algorithm 13a. The evaluation function at this time is (estimated area calculated from the number of logic elements and nets in the cluster + estimated wiring area calculated from the number of nets between blocks), and the function with the smallest value is selected. The method of estimating the area here is defined in advance as an empirical function.

Note that the purpose of minimizing the area and the evaluation function for this purpose are only examples.By preparing inference rules and evaluation functions according to the purpose of dividing a logic circuit, the division of all logic circuits is automated. It becomes possible.

13 · ? fe p books

Therefore, even when applied to the logical cluster division in the logical design process, the logical data can be divided into appropriate size ranges. It is possible to suppress a decrease in the mounting rate within the block 1 and to suppress an increase in the wiring area between the blocks 1 when a large number of small blocks 1 are used.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in addition to the genetic algorithm, other optimization methods such as simulated annealing can be used. Alternatively, it is also possible to use the results obtained by fuzzy inference as constraints (initial conditions) and use the other heuristic (heuristic) methods for the rest. It is possible. Industrial applicability

As described above, the semiconductor device design technique according to the present invention can provide a semiconductor device design novice, particularly a VLSI or the like, which can provide good initial conditions at the beginning of a complicated design to a beginner of a semiconductor chip design. It is useful for a device designing method, and can be applied to a computer-readable recording medium or the like in which a program for causing a computer to execute the semiconductor device designing method is recorded.

Claims

The scope of the claims

1. A function design process for designing the function of the integrated circuit based on the system specifications;

A logic design step of performing a logic design on the integrated circuit at a logic gate level based on the design data obtained in the function design step;

A circuit design step of designing the logic gate at a transistor level based on the design data obtained in the logic design step;

A layout design step of arranging and wiring the logic gates based on the design data obtained in the logic design step and the design data obtained in the circuit design step; In creating the data,

A first step of creating multiple design data groups using fuzzy inference,

A second step of randomly generating a plurality of design data groups;

Based on the plurality of design data groups created in the first step and the plurality of design data groups created in the second step, a high-fitness V and design data group A third step of selecting

Based on the design data group selected in the third step, using the optimization processing method, further generation of a plurality of next design data groups is sequentially repeated while selecting a design data group having a high degree of conformity. A fourth step of creating a design data group that provides an optimum solution. A method for designing a semiconductor device, comprising:

2. A function design process for designing the function of the integrated circuit based on the system specifications;

A logic design step of performing a logic design of the integrated circuit at a logic gate level based on the design data obtained in the function design step;

A first step of creating a partial design data group that becomes an optimal solution using fuzzy inference; A second step of randomly generating a plurality of design data groups;

A third step of selecting a design data group having a high degree of fitness using an optimization processing method based on the plurality of design data groups created in the second step;

Based on the design data group selected in the third step, using the optimization processing method, further generation of a plurality of next design data groups is sequentially repeated while selecting a design data group having a high degree of conformity. A fourth step of creating a design data group of another part that becomes an optimal solution, and a method of designing a semiconductor device.

3. The method for designing a semiconductor device according to claim 1, wherein the layout designing step is floor planning for arranging and wiring a plurality of blocks on a semiconductor chip.

A genetic algorithm is used as the optimization processing method, an initial design data group of the genetic algorithm is generated by using the fuzzy inference, and the plurality of blocks are generated by using the design data group that becomes the optimal solution. A method of designing a semiconductor device, wherein the method is arranged on a semiconductor chip.

4. The method for designing a semiconductor device according to claim 3, wherein the coding in the floor planning includes:

A method of designing a semiconductor device, wherein a center X-Y coordinate and rotation of each block are associated with a chromosome of the genetic algorithm.

5. The method for designing a semiconductor device according to claim 3, wherein the evaluation in the floor planning is:

The actual wire length between the blocks is L i, the overlapping portion is S i, the portion protruding from the designated area is O V i, and the weighting factors are β, γ,

E = a∑L i + j3∑S i + y∑O V i

A semiconductor device design method characterized by evaluating the arrangement and wiring of each block based on the value obtained from the evaluation function E of (1).

6. The method for designing a semiconductor device according to claim 3, wherein the mutation in the floor planning is:

A half of the plurality of blocks is moved in a predetermined direction by a predetermined distance, and the direction of the block is changed to a predetermined direction. Design method of conductor device.

7. The method for designing a semiconductor device according to claim 3, wherein the fuzzy inference in the floor planning is:

A block arranged near the center of the semiconductor chip has a low connectivity to the I / O buffer and a small size.

The block arranged in the corner of the semiconductor chip has a large size and a medium block having a medium connectivity with an adjacent block is selected.

A block having high connectivity to the IΖο buffer is arranged along the periphery of the semiconductor chip,

A semiconductor device design method based on the following rule.

8. The method for designing a semiconductor device according to claim 1, wherein the logical design step is a logical cluster division for dividing a plurality of blocks into clusters.

A genetic algorithm is used as the optimization processing method, an initial design data group of the genetic algorithm is generated using the fuzzy inference, and the plurality of blocks are generated using the design data group that becomes the optimal solution. A method for designing a semiconductor device, comprising dividing the device into clusters.

9. The method for designing a semiconductor device according to claim 8, wherein the fuzzy inference in the logical cluster division includes:

A method for designing a semiconductor device, wherein the number of logic elements and the number of internal nets included in each block are within a predetermined range, and a block having a small number of external connection nets is determined. .

10. The method for designing a semiconductor device according to claim 8, wherein the evaluation in the logical cluster division is:

The cluster is divided based on a value obtained from an evaluation function obtained by adding an estimated area obtained from the number of logic elements and the number of nets in the cluster and an estimated wiring area obtained from the number of nets between the blocks. A method for designing a semiconductor device characterized by evaluating.

11. A function design process for designing a function of an integrated circuit based on system specifications, and a logic design process for performing a logic design at a logic gate level on the integrated circuit based on design data obtained in the function design process. , A circuit design step of designing the logic gate at a transistor level based on the design data obtained in the logic design step;

A first step of creating a plurality of design data groups using fuzzy inference,

A second step of randomly generating a plurality of design data groups;

Based on the plurality of design data groups created in the first step and the plurality of design data groups created in the second step, a design data group having a high degree of conformity is determined using an optimization processing method. A third step to choose,

Based on the design data group selected in the third step, the next plurality of design data groups are sequentially repeated using the optimization processing method while sequentially selecting design data groups having a high degree of conformity, A computer-readable recording medium, which records a program for causing a computer to execute a method of designing a semiconductor device having a fourth step of creating a design data group that becomes an optimal solution.

1 2. A function design step of designing a function of an integrated circuit based on system specifications, and a logic design step of performing a logic design of the integrated circuit at a logic gate level based on design data obtained in the function design step. ,

A first step of creating a partial design data group that becomes an optimal solution using fuzzy inference;

A second step of randomly generating a plurality of design data groups;

Based on the design data group selected in the third step, the optimization processing method A fourth step of successively repeating the creation of the next plurality of design data groups while selecting a design data group having a high degree of conformity by using the above to create another part of the design data group that becomes an optimal solution; and

A computer-readable recording medium on which a program for causing a computer to execute a method of designing a semiconductor device having the above is recorded.

13. The computer-readable recording medium according to claim 11 or 12, wherein the layout designing step is floor planning for arranging and wiring a plurality of blocks on a semiconductor chip.

A genetic algorithm is used as the optimization processing method, an initial design data group of the genetic algorithm is generated by using the fuzzy inference, and the plurality of blocks are generated by using the design data group that becomes the optimal solution. A computer-readable recording medium, which is arranged on a semiconductor chip.

14. The computer-readable recording medium according to claim 13, wherein the coding in the floor planning is:

A computer-readable recording medium, wherein a rotation of a center X-Y coordinate of each block is associated with a chromosome of the genetic algorithm.

15. The computer-readable recording medium according to claim 13, wherein the evaluation in the floor planning is:

The actual wiring length between the blocks is L i, the overlapping part is S i, the part protruding from the specified area is ΔV i, and the weighting coefficients are β, γ,

Ε = α∑ L i + | 3∑ S i + y∑O V i

A computer-readable recording medium characterized in that the arrangement and wiring of each block are evaluated based on a value obtained from the evaluation function E.

16. The computer-readable recording medium according to claim 13, wherein the mutation in the floor plan is:

A computer-readable recording medium characterized in that an arbitrary block among the plurality of blocks is moved in a predetermined direction by a predetermined distance, and the direction of the block is changed in a predetermined direction.

17. The computer-readable recording medium according to claim 13, wherein the file The fuzzy inference in lower planning is:

Blocks that are placed near the center of the semiconductor chip should have low connectivity to the Iζο buffer and small dimensions.

A block having high connectivity to the IZO buffer is arranged along the periphery of the semiconductor chip,

A computer-readable recording medium based on the following rule.

18. The computer-readable storage medium according to claim 11, wherein the logical design step is a logical cluster division that divides a plurality of blocks into clusters.

A genetic algorithm is used as the optimization processing method, an initial design data group of the genetic algorithm is generated using the fuzzy inference, and the plurality of blocks are generated by using the design data group that becomes the optimal solution. A computer-readable recording medium characterized by being divided into clusters.

19. The computer-readable recording medium according to claim 8, wherein the fuzzy inference in the logical cluster division is:

Computer-readable recording based on the rule that the number of logic elements and the number of internal nets included in each block are within a predetermined range and a block having a small number of external connection nets is determined. Medium.

20. The computer-readable recording medium according to claim 18, wherein the evaluation in the logical cluster division is:

The cluster is divided based on a value obtained from an evaluation function obtained by adding an estimated area obtained from the number of logic elements and the number of nets in the cluster and an estimated wiring area obtained from the number of nets between the blocks. A computer-readable recording medium characterized by being evaluated.

2 1. The first step of creating design data using fuzzy inference,

A second step of randomly generating a plurality of design data groups; Based on the design data created in the first step and the plurality of design data groups created in the second step, a design data group including design data with high adaptability is selected by an optimization processing method. The third step,

A semiconductor device comprising: a fourth step of selecting a design data group including design data having a high degree of conformity by an optimization processing method based on the design data group selected in the third step. Design method.

2 2. The first step of creating partial design data using fuzzy inference,

A second step of randomly generating a plurality of design data groups;

A third step of selecting a design data group including design data having a high degree of conformity by an optimization processing method based on the plurality of design data groups created in the second step; and A fourth step of selecting a design data group having a high degree of conformity by an optimization processing method based on the design data group, and a fourth step of designing the semiconductor device.

23. The method for designing a semiconductor device according to claim 22, wherein a genetic algorithm is used as the optimization processing method, and initial design data of the genetic algorithm is generated using the fuzzy inference. A method for designing a semiconductor device.

2 4. The first step of creating design data using fuzzy inference,

A second step of randomly generating a plurality of design data groups;

Based on the design data created in the first step and the plurality of design data groups created in the second step, a design data group including design data with high adaptability is selected by an optimization processing method. The third step,

A fourth step of selecting a design data group including design data having a high degree of conformity by an optimization processing method based on the design data group selected in the third step;

And a computer-readable recording medium having recorded thereon a program for causing a computer to execute the program.

25. The first step of creating partial design data using fuzzy inference,

A second step of randomly generating a plurality of design data groups;

A third step of selecting a design data group including design data having a high degree of conformity by an optimization processing method based on the plurality of design data groups created in the second step; A fourth step of selecting a design data group having a high degree of conformity by an optimization processing method based on the design data group selected in the third step;

26. The computer-readable recording medium according to claim 25, wherein a genetic algorithm is used as the optimization processing method, and initial design data of the genetic algorithm is generated using the fuzzy inference. A computer-readable recording medium characterized by the above-mentioned.

27. The method for designing a semiconductor device according to claim 21, wherein a membership function is used in the fuzzy inference.

28. The method for designing a semiconductor device according to claim 23, wherein a membership function is used in said fuzzy inference.

29. The computer-readable recording medium according to claim 24, wherein a membership function is used in said fuzzy inference.

30. The computer-readable recording medium according to claim 26, wherein a membership function is used in said fuzzy inference.

3 1. The first step of creating design data using the membership function,

A second step of creating a plurality of design data groups;

Based on the design data created in the first step and the plurality of design data groups created in the second step, a design data group including the design data having a high degree of conformity is obtained by an optimization processing method. A third step to choose,

A fourth step of selecting a design data group having a high degree of suitability by an optimization processing method based on the design data group selected in the third step, and a fourth step of designing the semiconductor device. .

32. The method for designing a semiconductor device according to claim 31, wherein the second step is a random number. A method of designing a semiconductor device, wherein the plurality of design data groups are created.

33. The semiconductor device design method according to claim 32, wherein a part of data provided to the optimization processing method is design data created in the first step, and a part of the data is provided. Is a design data created in the second step.

3 4. The first step of creating design data using membership functions,

A second step of creating a plurality of design data groups;

Based on the design data created in the first step and the plurality of design data groups created in the second step, a design data group including design data with a high degree of conformity is selected by an optimization processing method. A third step,

A fourth step of selecting a design data group having a high degree of conformity by an optimization processing method based on the design data group selected in the third step;

35. The computer-readable recording medium according to claim 34, wherein in the second step, the plurality of design data groups are randomly generated.

36. The computer-readable recording medium according to claim 35, wherein a part of data provided to the optimization processing method is design data created in the first step. A computer-readable recording medium, wherein the unit is the design data created in the second step.