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WO1999030327A1 - Dispositif a memoire a semiconducteur, dispositif a semiconducteur et appareil electronique dans lequel il est utilise - Google Patents

Dispositif a memoire a semiconducteur, dispositif a semiconducteur et appareil electronique dans lequel il est utilise Download PDF

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Publication number
WO1999030327A1
WO1999030327A1 PCT/JP1998/005585 JP9805585W WO9930327A1 WO 1999030327 A1 WO1999030327 A1 WO 1999030327A1 JP 9805585 W JP9805585 W JP 9805585W WO 9930327 A1 WO9930327 A1 WO 9930327A1
Authority
WO
WIPO (PCT)
Prior art keywords
redundant
circuit
address
program
signal
Prior art date
Application number
PCT/JP1998/005585
Other languages
English (en)
Japanese (ja)
Inventor
Yasuhiko Tomohiro
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corporation filed Critical Seiko Epson Corporation
Publication of WO1999030327A1 publication Critical patent/WO1999030327A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/835—Masking faults in memories by using spares or by reconfiguring using programmable devices with roll call arrangements for redundant substitutions

Definitions

  • the present invention relates to a semiconductor memory device, a semiconductor device, and an electronic apparatus using the same, and more particularly to an improvement in a redundant circuit of the semiconductor memory device.
  • Redundant circuits used in many semiconductor memory devices are technologies that can relieve memory cell failures that occur during the manufacturing process, and have a significant effect on yield improvement. Such a technique is described, for example, on pages after Nikkei Electronics, December 30, 1985, p. 124.
  • FIG. 7 shows a redundant circuit in a conventional semiconductor memory device reduced to four internal addresses (two external addresses) for convenience of explanation.
  • the redundant decoder 300 has four redundant address decoders 301, 302, 303, and 304 each having one input as the internal address signal Ai, Aib, Ai + 1, Ai + lb. , Ai + lb are complementary signals of the internal address signals Ai and Ai + 1, respectively.
  • the other inputs to the redundant address decoders 301-304 are the outputs from the address program circuits RAP (i), RAP (ib), RAP (i + l), RAP (i + lb) respectively.
  • the redundant address decoders 301 to 304 program the selection of the internal address signals Ai, Aib, Ai + 1, Ai + 1b based on these inputs.
  • the redundant use signal R—E / D signal is active at the low level and inactive at the high level.
  • the output of the NAND gate 305 to which the outputs of the redundant address decoders 301 and 302 are input, is an inverted signal of the output of the redundant address decoder 301, that is, the internal address signal Aib.
  • a low level is output from the inverter circuit 402 as an output of the above-described program circuit.
  • the LOW level output from the inverter 403 is applied to the gate of the N-channel transistor 402, causing the N-channel transistor 402 to enter the 0 FF state.
  • the latch state is established, and the output of the receiver 403 is fixed at the low level.
  • the circuit configuration of the redundant circuit is simplified by converting an external address signal into a complementary internal address signal.
  • the external address signal lb it selects two addresses, while the internal address signal 1 bit specifies whether one address is selected or not.
  • the lowest bit bit of the external address signal can select address 0 or 1 depending on "0" or "1". If the internal address signals generated from these external address signals are A0 and AOb, AO specifies address 0 and AOb specifies whether address 1 is selected or not. Here, it is assumed that the internal address signal is selected when it is “1" and is not selected when it is “0". In this case, if the internal address signal AO is "1", address 0 is selected, and the internal address signal AOb is a complementary signal of AO, "0", and address 1 is not specified. If the internal address signal AO is "0", address 0 is not selected, and its complementary signal AOb becomes "1" and address 1 is selected. As a result, it is only necessary to prepare one type of circuit for detecting the selection / non-selection state of the internal address signal in the redundant circuit, and the circuit configuration can be simplified.
  • the semiconductor memory device of the present invention is a semiconductor memory device of the present invention.
  • a normal memory cell array in which a plurality of normal memory cells are arranged in a matrix a redundant memory cell array in which a plurality of redundant memory cells used when one of the plurality of normal memory cells is defective is arranged in a matrix,
  • Row and column selecting means for selecting any one of the plurality of normal memory cell arrays and the plurality of redundant memory cell arrays
  • the row / column selecting means prohibits the selection of the normal memory cells based on an output from the redundant circuit.
  • - includes a one redundant address program circuit, and one of the redundant use program circuit, The redundant circuit,
  • a redundant address decode circuit for outputting a plurality of redundant address signals based on the 2 n internal address signals and information from the two redundant address program circuits;
  • a redundancy decoding circuit that outputs the redundancy use signal based on the plurality of redundancy address signals from the redundancy address decode circuit and information from the redundancy use program circuit;
  • a redundant use signal for relieving a normal memory cell is output only by preparing 2 n — 1 redundant address program circuits. Can be done. Therefore, the number of program elements can be halved compared to the conventional case, high integration can be achieved, and the redundant address programming time can be shortened.
  • two internal address signals can be selected according to the program state and the non-program state in one redundant address program circuit.
  • the redundant address decode circuit of the present invention comprises:
  • One of a complementary signal, said and one 2 eta number of internal address signal is input, a first selection circuit for outputting one of internal Adoresu signal synchronized with the signal by one of the state of the complementary signals,
  • Conversion circuit 2 It is possible to have 2 n — 1 inverters that invert the logic of the outputs from the redundant address program circuits.
  • the redundant decoder can be constituted by an AND gate. This AND gate activates the redundant use signal only when both the redundant address signals from the redundant address decode circuit and the output from the redundant use program circuit are at the H GH level.
  • the 2n internal address signals can be complementary signals formed based on 2 "external address signals input from the outside.
  • the present invention can be applied to a semiconductor device in which the above-described semiconductor storage device is formed on a semiconductor substrate and an electronic device using the same.
  • FIG. 2 is a circuit diagram showing different types of redundant circuits of the semiconductor memory device according to the second embodiment of the present invention.
  • FIG. 4 is a schematic explanatory diagram showing, on an enlarged scale, two of the 16 memory cell array blocks shown in FIG.
  • FIG. 5 is a wiring diagram showing wiring in the memory cell array block shown in FIG.
  • FIG. 6 is a block diagram showing a memory cell selection circuit of the semiconductor memory device shown in FIG.
  • FIG. 7 is a circuit diagram showing a redundant circuit of a conventional semiconductor memory device.
  • FIG. 8 is a circuit diagram in which the redundant address decoder of FIG. 7 is configured by NAND gates.
  • FIG. 9 is a circuit diagram showing a conventional program circuit.
  • FIG. 1 is a circuit diagram showing a redundant circuit of a semiconductor memory device according to a first embodiment of the present invention.
  • FIG. 1 shows two redundant address program circuits RAP (i) and RAP (i + l), two redundant address decode circuits 100 and 110, a redundant use program circuit RP, and a redundant decode circuit 120. ing.
  • the internal address signals Ai, Aib, Ai + 1, Ai + lb are input to this redundant circuit. These internal address signals are formed based on the external address signals Ai, Ai + 1.
  • the internal address signal Aib is formed by inverting the external address signal Ai by the receiver 121.
  • the internal address signal Ai + lb is formed by inverting the external address signal Ai + 1 by the receiver 121. Accordingly, the complementary signal of the internal address signal Ai becomes the internal address signal Aib, and the complementary signal of the internal address signal Ai + 1 becomes the internal address signal Ai + lb.
  • the external memory (Ai, Ai + 1) can specify four memory cell addresses (1, 1), (1, 0), (0, 1), and (0, 0). Has become.
  • the redundant address program circuits RAP (i) and RAP (i + l) both have the circuit configuration shown in FIG. That is, when the fuse 401 shown in FIG. 9 is blown to enter the redundant program state, the outputs of the redundant address program circuits RAP (i) and RAP (i + 1) are both fixed at the high level. . When the fuse 401 shown in FIG. 9 is not blown and enters the non-redundant program state, the outputs of the redundant address program circuits RAP (i) and RAP (i + 1) are both fixed at the low level. .
  • the redundant address decode circuit 100 is a circuit that decodes the internal address signals Ai and Aib
  • the redundant address decode circuit 110 is a circuit that decodes the address signals Ai + 1 and Ai + lb.
  • the redundant address decode circuit 100 includes an inverter 101 and NAND gates 102 to 104.
  • the internal address signal Ai is input to one of the input terminals of the NAND gate 102, and the output of the redundant address program circuit RAP (i) is input to the other input terminal via the inverter 101.
  • One input terminal of the NAND gate 103 receives the internal address signal Aib, and the other input terminal receives the output of the redundant address program circuit RAP (i).
  • the outputs of the NAND gates 102 and 103 are input to the NAND gate 104 and are logically synthesized.
  • Each output of the NAND gates 104 and 114 and the output of the redundant use program circuit RP are input to an AND gate 120 which is a redundant decode circuit. Therefore, the outputs of the NAND gates 104 and 114 are logically combined with the output of the redundant use program circuit RP in the AND gate 120 and controlled.
  • the redundant use program circuit RP when the redundant use program circuit RP is set to the program state, when the programmed address is selected, all three inputs to the AND gate 120 are set to the high level, and the output is output. The output goes high and the redundant use signal R—E / D is activated. If the redundant use program circuit RP is not programmed, the output of the redundant use program circuit RP is fixed at LOW level, so that the output of the AND gate 120 is fixed at LOW level.
  • the redundant address program circuit RAP (i) is set to the program state and RAP (i + l) is set to the non-program state will be described.
  • the redundant use program circuit RP is also set to the program state, and its output is fixed at the HIGH level.
  • the high-level output from the redundant address program circuit RAP (i) is The signal is input to NAND gate 102 via overnight 101. Based on the operation logic of the NAND gate 102, the output of the NAND gate 102 is fixed at the HIGH level regardless of the logic of the other input of the NAND gate 102 (that is, Ai is not selected).
  • the logic of the other input of the NAND gate 103 is based on the operation logic of the NAND gates.
  • the output of the NAND gate 103 changes (that is, Aib is selected).
  • the NAND gate 113 since the LOW level from RAP (i + l) is directly input to the NAND gate 113, the NAND gate 113 does not matter from the operation logic of the NAND gate, regardless of the logic of the other input. Output is fixed at high level. This means that the internal address signal Ai + 1b is not selected.
  • the NAND gate 114 receives an inverted level signal of the internal address signal Ai + 1 and a signal fixed at a high level. Therefore, from the operation logic of the NAND gate, the logic of the internal address signal Ai + 1 is eventually output as the output of the NAND gate 114. This means that the internal address signal Ai + 1 becomes the redundant address signal Rdi + 1. From the above operation, the redundant address signal Rdi from the NAND gate 104 becomes the internal address signal Aib, and the redundant address signal Rdi + 1 from the NAND gate 114 becomes the internal address signal Ai + 1.
  • the internal address signals Ai and Ai + lb are selected as the program addresses, and the memory cell 2 in (2) described above is defective.
  • the fuse 401 in FIG. 9 which is one element of the redundant address program circuit RAP (i) is not blown, and the output of the redundant address program circuit RAP (i) is L. Fixed to OW level.
  • the fuse 401 in FIG. 9, which is one element of the redundant address program circuit RAP (i + 1) is blown, and the output of the redundant address program circuit RAP (i + l) is fixed at a high level. .
  • the fuse 401 shown in FIG. 9, which is one element of the redundant use program circuit RP is blown, and the output of the redundant address program circuit RP is fixed at the HIGH level.
  • the redundant address signal Rdi from the NAND gate 104 becomes the internal address signal Ai
  • the redundant address signal Rdi + 1 from the NAND gate 114 becomes the internal address signal Ai + lb.
  • the internal address signals Ai and Ai + lb are selected as the program addresses, and the memory cell 1 in (1) described above is defective.
  • the fuse 401 in FIG. 9, which is one of the elements constituting the redundant address program circuit RAP (i), RAP (i + l), is blown, and the redundant address program circuit RAP Both outputs of (i) and RAP (i + l) are fixed at HIGH level.
  • the fuse 401 in FIG. 9, which is one element of the redundant use program circuit RP is blown, and the output of the redundant address program circuit RP is fixed at the HIGH level.
  • a redundant address program can be performed for two internal address signals Ai and Ai + 1 by one redundant address program circuit RAP (i). Also, for two internal address signals Aib and Ai + lb, One redundant address program circuit RAP (i + 1) enables a redundant address program in the program circuit. Therefore, it becomes possible to reduce the number of program elements for redundant address programming by half. As a result, the area occupied by the program element is halved, and the element can be highly integrated. Further, as a result of halving the number of program elements, the number of times the redundant address program is performed can be halved, so that the time required for programming can be reduced.
  • an electronic device can be formed using a semiconductor device including the semiconductor storage device of the present invention. Therefore, the present invention can be applied to various electronic devices using the semiconductor storage device as a memory, and can be applied to a stationary type such as a personal convenience device, and particularly to a portable electronic device such as a mobile convenience device and a mobile phone. When applied to, it can contribute to downsizing of equipment.

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Abstract

Circuit redondant produisant en sortie un signal d'utilisation redondante, dans lequel une cellule mémoire redondante est utilisée à la place d'une cellule mémoire normale défectueuse, en fonction de 2n (n étant valant 2 ou plus) signaux d'adresse interne Ai, Aib, Ai+1, Ai+1b pour la sélection d'une cellule arbitraire parmi plusieurs cellules mémoires normales, et des informations provenant de plusieurs circuits de programme. Lesdits circuits de programme comprennent chacun 2n-1 circuits de programme d'adresse redondante RAP (i), RAP (i+1) et un circuit de programme d'utilisation redondante RP. Le circuit redondant comporte des circuits de décodage d'adresse redondante (100, 110), produisant en sortie plusieurs signaux d'adresse redondante Rdi, Rdi+1. Un circuit de décodage redondant (120) produit en sortie un signal d'utilisation redondante R_E/D en fonction des signaux d'adresse redondante Rdi, Rdi+1 et des informations provenant du circuit de programme d'utilisation redondante RP.
PCT/JP1998/005585 1997-12-11 1998-12-10 Dispositif a memoire a semiconducteur, dispositif a semiconducteur et appareil electronique dans lequel il est utilise WO1999030327A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP34108997 1997-12-11
JP9/341089 1997-12-11

Publications (1)

Publication Number Publication Date
WO1999030327A1 true WO1999030327A1 (fr) 1999-06-17

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02177087A (ja) * 1988-12-27 1990-07-10 Nec Corp リダンダンシーデコーダ
JPH05120895A (ja) * 1991-10-29 1993-05-18 Hitachi Ltd 半導体集積回路装置
JPH0877791A (ja) * 1994-08-25 1996-03-22 Samsung Electron Co Ltd 半導体メモリ装置のカラム冗長方法及びその回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02177087A (ja) * 1988-12-27 1990-07-10 Nec Corp リダンダンシーデコーダ
JPH05120895A (ja) * 1991-10-29 1993-05-18 Hitachi Ltd 半導体集積回路装置
JPH0877791A (ja) * 1994-08-25 1996-03-22 Samsung Electron Co Ltd 半導体メモリ装置のカラム冗長方法及びその回路

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