WO1999030327A1

WO1999030327A1 - Semiconductor memory device, semiconductor device and electronic apparatus employing it

Info

Publication number: WO1999030327A1
Application number: PCT/JP1998/005585
Authority: WO
Inventors: Yasuhiko Tomohiro
Original assignee: Seiko Epson Corporation
Priority date: 1997-12-11
Filing date: 1998-12-10
Publication date: 1999-06-17

Abstract

A redundant circuit outputting a redundant use signal using a redundant memory cell in place of a defective normal memory cell based on 2n (n is an integer of 2 or more) internal address signals Ai, Aib, Ai+1, Ai+1b for selecting an arbitrary one of a plurality of normal memory cells, and the information from a plurality of program circuits. The program circuits each comprise 2n-1 redundant address program circuits RAP(i), RAP(i+1), and one redundant use program circuit RP. The redundant circuit comprises redundant address decoding circuits (100, 110) outputting a plurality of redundant address signals Rdi, Rdi+1. A redundant decoding circuit (120) outputs a redundant use signal R_E/D based on the redundant address signals Rdi, Rdi+1 and the information from the redundant use program circuit RP.

Description

Description Semiconductor storage device, semiconductor device, and electronic apparatus using the same

[Technical field]

The present invention relates to a semiconductor memory device, a semiconductor device, and an electronic apparatus using the same, and more particularly to an improvement in a redundant circuit of the semiconductor memory device.

[Background technology]

Redundant circuits used in many semiconductor memory devices are technologies that can relieve memory cell failures that occur during the manufacturing process, and have a significant effect on yield improvement. Such a technique is described, for example, on pages after Nikkei Electronics, December 30, 1985, p. 124.

The overall configuration of this type of semiconductor memory device is described in, for example, Electronic Materials January 1984 p1

It is disclosed in a number of documents, such as pages 05 onwards.

FIG. 7 shows a redundant circuit in a conventional semiconductor memory device reduced to four internal addresses (two external addresses) for convenience of explanation. In FIG. 7, the redundant decoder 300 has four redundant address decoders 301, 302, 303, and 304 each having one input as the internal address signal Ai, Aib, Ai + 1, Ai + lb. , Ai + lb are complementary signals of the internal address signals Ai and Ai + 1, respectively. The other inputs to the redundant address decoders 301-304 are the outputs from the address program circuits RAP (i), RAP (ib), RAP (i + l), RAP (i + lb) respectively. The redundant address decoders 301 to 304 program the selection of the internal address signals Ai, Aib, Ai + 1, Ai + 1b based on these inputs.

Each redundant dead address coder shown in FIG. 7 can be composed of, for example, a two-input NAND gate as shown in FIG.

Each output from the redundant address decoders 301 and 302 shown in FIG. 7 is input to a NAND gate 305, and each output from the redundant decoders 303 and 304 is a NAND gate. Input to D gate 306. Each output from the NAND gates 305 and 306 and a signal obtained by inverting the output of the redundant use program circuit RP by the inverter 312 are input to the three-input NOR gate 310. The NOR gate 310 makes the output of the redundant use signal R-E / D signal active or non-active. The output of the redundant use program circuit RP is fixed to HIGH during programming and fixed to LOW during non-programming.

In FIG. 7, the redundant use signal R—E / D signal is active at the low level and inactive at the high level.

When the redundant address program circuit RAP (i) is programmed, the output of RAP (i) is fixed at the HIGH level. This high level is input to the redundancy decoder 301, and an inverted signal of the internal address signal Ai is obtained as an output of the redundancy decoder 301.

Since the other redundant address program circuits RAP (ib), RAP (i + l), and RAP (i + lb) are in the non-program state, their outputs are fixed at the low level. The outputs of the redundant address decoders 302, 303, and 304 to which the LOW level is input are fixed to the H HI level regardless of the state of the other input.

Therefore, the output of the NAND gate 305, to which the outputs of the redundant address decoders 301 and 302 are input, is an inverted signal of the output of the redundant address decoder 301, that is, the internal address signal Aib. The output of the NAND gate 306, to which the outputs of the redundant address decoders 303 and 304 are input, is fixed at the LOW level because the input is fixed at the HIGH level.

Figure 9 shows an example of a circuit configuration using fuse elements in the redundant address program circuits RAP (i), RAP (ib), RAP (i + l), RAP (i + lb) and the redundant use program circuit RP. Show. In FIG. 9, a fuse element 401 and an N-channel transistor 403 are connected in series between a power supply potential VCC and a ground potential GND.

In a non-program state in which the fuse element 401 is not blown, a high level is output from the inverter 402 as an output of the above-described program circuit. I The HIGH level, which is the output of the member 403, is applied to the gate of the N-channel transistor 402, turning on the N-channel transistor 402. As a result, the latch state is established, and the output of the receiver 403 is fixed at the HIGH level.

In the program state in which the fuse element 401 is blown, a low level is output from the inverter circuit 402 as an output of the above-described program circuit. The LOW level output from the inverter 403 is applied to the gate of the N-channel transistor 402, causing the N-channel transistor 402 to enter the 0 FF state. As a result, the latch state is established, and the output of the receiver 403 is fixed at the low level. In this semiconductor memory device, the circuit configuration of the redundant circuit is simplified by converting an external address signal into a complementary internal address signal. The external address signal lb it selects two addresses, while the internal address signal 1 bit specifies whether one address is selected or not.

For example, the lowest bit bit of the external address signal can select address 0 or 1 depending on "0" or "1". If the internal address signals generated from these external address signals are A0 and AOb, AO specifies address 0 and AOb specifies whether address 1 is selected or not. Here, it is assumed that the internal address signal is selected when it is "1" and is not selected when it is "0". In this case, if the internal address signal AO is "1", address 0 is selected, and the internal address signal AOb is a complementary signal of AO, "0", and address 1 is not specified. If the internal address signal AO is "0", address 0 is not selected, and its complementary signal AOb becomes "1" and address 1 is selected. As a result, it is only necessary to prepare one type of circuit for detecting the selection / non-selection state of the internal address signal in the redundant circuit, and the circuit configuration can be simplified.

However, the conventional redundant circuit required one address program circuit for one internal address signal as shown in FIG. For example, if 10 internal address signals are required, 10 address program circuits and 1 redundant use program circuit are required, and at least 11 program elements are required.

Currently, there is no way to program a fuse element by laser fusing. Often used. This is because the fuse element has advantages such as simple structure, reliable programming, and the programmed state does not change with temperature and time. On the other hand, it is necessary to provide a special area to prevent the alignment accuracy of the laser device from affecting the surrounding elements and the like due to the laser fusing, which is disadvantageous in that it occupies a large area. Other alternative program elements may be used, for example, non-volatile storage elements such as EEPROM elements and flash memory elements. However, in this case, the program element itself does not take up an area, but requires a large area for a circuit for the program.

Therefore, an object of the present invention is to provide a semiconductor memory device, a semiconductor device, and an electronic device using the same, which can reduce the number of program elements to achieve high integration and a short redundant address programming time.

[Disclosure of the Invention]

The semiconductor memory device of the present invention

A normal memory cell array in which a plurality of normal memory cells are arranged in a matrix, a redundant memory cell array in which a plurality of redundant memory cells used when one of the plurality of normal memory cells is defective is arranged in a matrix,

Row and column selecting means for selecting any one of the plurality of normal memory cell arrays and the plurality of redundant memory cell arrays;

The normal memory cell which is defective based on 2 ⁿ (n is an integer of 2 or more) internal address signals for selecting any one of the plurality of normal memory cells and information from a plurality of program circuits. A redundancy circuit that outputs a redundant use signal using the redundant memory cell instead of

Has,

The row / column selecting means prohibits the selection of the normal memory cells based on an output from the redundant circuit. - includes a ^one redundant address program circuit, and one of the redundant use program circuit, The redundant circuit,

A redundant address decode circuit for outputting a plurality of redundant address signals based on the 2 ⁿ internal address signals and information from the two redundant address program circuits;

A redundancy decoding circuit that outputs the redundancy use signal based on the plurality of redundancy address signals from the redundancy address decode circuit and information from the redundancy use program circuit;

It is characterized by having.

According to the present invention, when 2 ⁿ internal address signals are input, a redundant use signal for relieving a normal memory cell is output only by preparing 2 ⁿ — ¹ redundant address program circuits. Can be done. Therefore, the number of program elements can be halved compared to the conventional case, high integration can be achieved, and the redundant address programming time can be shortened.

According to the present invention, the redundant address decode circuit selects one of the 2 ⁿ internal address signals as one of a plurality of redundant address signals when one of the 2 "redundant address program circuits is in a non-program state, When one redundant address program circuit is in the program state, another one of the ²ⁿ internal address signals can be selected as one of a plurality of redundant address signals.

As described above, two internal address signals can be selected according to the program state and the non-program state in one redundant address program circuit.

The redundant address decode circuit of the present invention comprises:

2 A conversion circuit for converting the outputs from the ^η redundant address program circuits into complementary signals,

One of a complementary signal, said and one 2 ^eta number of internal address signal is input, a first selection circuit for outputting one of internal Adoresu signal synchronized with the signal by one of the state of the complementary signals,

And other complementary signal, 2 ^eta number of the other one of the internal address signal is input, outputs one of the internal Adoresu signal synchronized with the signal by the other state of the other complementary signal A second selection circuit to

Can be included.

In this case, if each of the first and second selection circuits is constituted by a transmission gate, the increase in the number of elements can be reduced.

Conversion circuit 2. It is possible to have 2 ⁿ — ¹ inverters that invert the logic of the outputs from the redundant address program circuits.

The redundant decoder can be constituted by an AND gate. This AND gate activates the redundant use signal only when both the redundant address signals from the redundant address decode circuit and the output from the redundant use program circuit are at the H GH level.

The ²ⁿ internal address signals can be complementary signals formed based on 2 "external address signals input from the outside.

The present invention can be applied to a semiconductor device in which the above-described semiconductor storage device is formed on a semiconductor substrate and an electronic device using the same.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a redundant circuit of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing different types of redundant circuits of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 3 is a schematic diagram for explaining block division of a semiconductor memory device applied to the first and second embodiments of the present invention.

FIG. 4 is a schematic explanatory diagram showing, on an enlarged scale, two of the 16 memory cell array blocks shown in FIG.

FIG. 5 is a wiring diagram showing wiring in the memory cell array block shown in FIG. FIG. 6 is a block diagram showing a memory cell selection circuit of the semiconductor memory device shown in FIG.

FIG. 7 is a circuit diagram showing a redundant circuit of a conventional semiconductor memory device.

FIG. 8 is a circuit diagram in which the redundant address decoder of FIG. 7 is configured by NAND gates. O

FIG. 9 is a circuit diagram showing a conventional program circuit.

[Best Mode for Carrying Out the Invention]

(Configuration of the redundant circuit of the first embodiment)

FIG. 1 is a circuit diagram showing a redundant circuit of a semiconductor memory device according to a first embodiment of the present invention. FIG. 1 shows two redundant address program circuits RAP (i) and RAP (i + l), two redundant address decode circuits 100 and 110, a redundant use program circuit RP, and a redundant decode circuit 120. ing.

The internal address signals Ai, Aib, Ai + 1, Ai + lb are input to this redundant circuit. These internal address signals are formed based on the external address signals Ai, Ai + 1. The internal address signal Aib is formed by inverting the external address signal Ai by the receiver 121. Similarly, the internal address signal Ai + lb is formed by inverting the external address signal Ai + 1 by the receiver 121. Accordingly, the complementary signal of the internal address signal Ai becomes the internal address signal Aib, and the complementary signal of the internal address signal Ai + 1 becomes the internal address signal Ai + lb.

Although the case where four internal address signals are input is described here for simplification of the description, it goes without saying that the present invention can be applied even when the number of internal address signals is large.

In this embodiment, the external memory (Ai, Ai + 1) can specify four memory cell addresses (1, 1), (1, 0), (0, 1), and (0, 0). Has become.

Here, the relationship between the external address (Ai, Ai + 1) and the four memory cell addresses is defined as follows.

(Ai, Ai + 1) = (1, 1)… memory cell 1 ... (1)

(Ai, Ai + 1) = (1, 0)… memory cell 2 (2)

(Ai, Ai + 1) = (0, 1)… memory cell 3 '' (3)

(Ai, Ai + 1) = (0, 0)… memory cell 4 (4) In the present embodiment, if any one of the memory cells 1 to 4 is defective, and the address of the defective memory cell is specified, the redundant decode circuit 120 A high-level signal is output; otherwise, a low-level signal is output. Then, when a high-level signal is output by the redundant decoding circuit 120, the designation of the normal memory cell is prohibited, and an alternative redundant memory cell is selected.

In the present embodiment, by having four internal address signals Ai, Aib, Ai + 1, Ai + lb, when any one of the addresses of the four memory cells 1 to 4 is specified, One of Ai, Ai + 1), (Ai, Ai + lb), (Aib, Ai + 1), and (Aib, Ai + lb) is always (1, 1).

That is, when the signal shown in (1) is input, (Ai, Ai + 1) = (1, 1), and when the signal shown in (2) is input, (Ai, Ai + (lb) = (1, 1), and when the signal shown in (3) is input, (Aib, Ai + 1) = (1, 1), and when the signal shown in (4) is input Has (Aib, Ai + lb) = (1, 1).

In this embodiment, when four internal address signals are input, two redundant address program circuits RAP (i) and RAP (i + l) may be prepared. This number is half that of the conventional technology shown in Fig. 7. In this embodiment, when 2 ⁿ (n is an integer of 2 or more) internal address signals are generally input, it is sufficient to provide 2η- ¹ redundant address program circuits.

The redundant address program circuits RAP (i) and RAP (i + l) both have the circuit configuration shown in FIG. That is, when the fuse 401 shown in FIG. 9 is blown to enter the redundant program state, the outputs of the redundant address program circuits RAP (i) and RAP (i + 1) are both fixed at the high level. . When the fuse 401 shown in FIG. 9 is not blown and enters the non-redundant program state, the outputs of the redundant address program circuits RAP (i) and RAP (i + 1) are both fixed at the low level. .

Similarly, the redundant use program circuit RP has the circuit configuration shown in FIG. If any one of the memory cells 1 to 4 is defective, the redundant use program is executed. The circuit RP is set to the program state. In this program state, the fuse 401 shown in FIG. 9 is blown, and the output of the redundant use program circuit RP is fixed at the HIGH level. In the non-program state, the fuse 401 shown in FIG. 9 is not blown, and the output of the redundant use program circuit RP is fixed at the low level.

The redundant address decode circuit 100 is a circuit that decodes the internal address signals Ai and Aib, and the redundant address decode circuit 110 is a circuit that decodes the address signals Ai + 1 and Ai + lb.

The redundant address decode circuit 100 includes an inverter 101 and NAND gates 102 to 104. The internal address signal Ai is input to one of the input terminals of the NAND gate 102, and the output of the redundant address program circuit RAP (i) is input to the other input terminal via the inverter 101. One input terminal of the NAND gate 103 receives the internal address signal Aib, and the other input terminal receives the output of the redundant address program circuit RAP (i). The outputs of the NAND gates 102 and 103 are input to the NAND gate 104 and are logically synthesized.

The redundant address decode circuit 110 has the same circuit configuration as the redundant address decode circuit 100, and includes an inverter 111 and NAND gates 112 to 114. The internal address signal Ai + 1 is input to one of the input terminals of the NAND gate 112, and the other input terminal is connected to the redundant address program circuit RAP (i + l) via the inverter 111. Output is input. The internal address signal Ai + lb is input to one of the input terminals of the NAND gate 113, and the output of the redundant address program circuit RAP (i + l) is input to the other input terminal. Outputs of the NAND gates 112 and 113 are input to a NAND gate 114 and are logically synthesized.

Each output of the NAND gates 104 and 114 and the output of the redundant use program circuit RP are input to an AND gate 120 which is a redundant decode circuit. Therefore, the outputs of the NAND gates 104 and 114 are logically combined with the output of the redundant use program circuit RP in the AND gate 120 and controlled. In other words, when the redundant use program circuit RP is set to the program state, when the programmed address is selected, all three inputs to the AND gate 120 are set to the high level, and the output is output. The output goes high and the redundant use signal R—E / D is activated. If the redundant use program circuit RP is not programmed, the output of the redundant use program circuit RP is fixed at LOW level, so that the output of the AND gate 120 is fixed at LOW level.

(Operation of the first embodiment)

Next, the operation of the redundant circuit shown in FIG. 1 will be described separately for the above cases (1) to (4).

(1) When RAP (i) is in program state and RAP (i + l) is in non-program state

First, the operation when the redundant address program circuit RAP (i) is set to the program state and RAP (i + l) is set to the non-program state will be described. In this case, the redundant use program circuit RP is also set to the program state, and its output is fixed at the HIGH level.

In the above case, the internal address signals Aib and Ai + 1 are selected as the program addresses, and the memory cell 3 of (3) described above is defective. Therefore, only when the internal address signal of (Ai, Aib, Ai + 1, Ai + lb) = (0, 1, 1, 0) is input, a high-level signal is output from the AND gate 120. Is forced. When an internal address signal other than the above is input, a low level signal is output from the AND gate 120.

In order to perform such programming, the fuse 401 in FIG. 9, which is one element of the redundant address program circuit RAP (i), is blown, and the output of the redundant address program circuit RAP (i) becomes high level. Fixed to On the other hand, the fuse 401 in FIG. 9, which is one element constituting the redundant address program circuit RAP (i + l), is not blown, and the output of the redundant address program circuit RAP (i + 1) is fixed at the LOW level. . Further, the fuse 401 shown in FIG. 9, which is one element of the redundant use program circuit RP, is blown, and the output of the redundant address program circuit RP is fixed at the HIGH level.

The high-level output from the redundant address program circuit RAP (i) is The signal is input to NAND gate 102 via overnight 101. Based on the operation logic of the NAND gate 102, the output of the NAND gate 102 is fixed at the HIGH level regardless of the logic of the other input of the NAND gate 102 (that is, Ai is not selected).

Since one of the NAND gates 103 is directly supplied with the HIGH level which is the output of the redundant address program circuit RAP (i), the logic of the other input of the NAND gate 103 is based on the operation logic of the NAND gates. The output of the NAND gate 103 changes (that is, Aib is selected).

Each output of the NAND gates 102 and 103 is input to the NAND gate 104. Since the output of the NAND gate 102 is fixed at the HIGH level, the inverted level of the output of the NAND gate 103 is output as the output of the NAND gate 104 based on the operation logic of the NAND gate. This means that the internal address signal Aib becomes the redundant address signal Rdi.

On the other hand,: Since AP (i + l) is in the non-program state, its output is fixed at LOW level. This low-level signal is inverted by the inverter 11 1 so that one input of the NAND gate 112 is fixed at the high level. The operating logic of a NAND gate is that when one of the inputs is at the HIGH level, its output changes with a change in the other input level. In this case, since the other input of the NAND gate 112 is Ai + 1, the output of the NAND gate 112 outputs an inverted level signal of the internal address signal Ai + 1.

Also, since the LOW level from RAP (i + l) is directly input to the NAND gate 113, the NAND gate 113 does not matter from the operation logic of the NAND gate, regardless of the logic of the other input. Output is fixed at high level. This means that the internal address signal Ai + 1b is not selected.

The NAND gate 114 receives an inverted level signal of the internal address signal Ai + 1 and a signal fixed at a high level. Therefore, from the operation logic of the NAND gate, the logic of the internal address signal Ai + 1 is eventually output as the output of the NAND gate 114. This means that the internal address signal Ai + 1 becomes the redundant address signal Rdi + 1. From the above operation, the redundant address signal Rdi from the NAND gate 104 becomes the internal address signal Aib, and the redundant address signal Rdi + 1 from the NAND gate 114 becomes the internal address signal Ai + 1.

Therefore, when (Ai, Aib, Ai + 1, Ai + lb) = (0, 1, 1, 0), all three inputs to the ND gate 120 are at the HIGH level. A high level output is obtained from gate 120. When an internal address signal of another logic state is input, a low level output is obtained from the AND gate 120.

(2) When RAP (i) is in the program state,: AP (i + l) is in the non-program state

Next, in a case where the redundant address program circuit RAP (i) is set to the non-program state and the redundant address program circuit RAP (i + 1) is set to the program state, contrary to the above-described program state of the redundant address program circuit. explain.

In the above case, the internal address signals Ai and Ai + lb are selected as the program addresses, and the memory cell 2 in (2) described above is defective. In order to perform such programming, the fuse 401 in FIG. 9 which is one element of the redundant address program circuit RAP (i) is not blown, and the output of the redundant address program circuit RAP (i) is L. Fixed to OW level. On the other hand, the fuse 401 in FIG. 9, which is one element of the redundant address program circuit RAP (i + 1), is blown, and the output of the redundant address program circuit RAP (i + l) is fixed at a high level. . Further, the fuse 401 shown in FIG. 9, which is one element of the redundant use program circuit RP, is blown, and the output of the redundant address program circuit RP is fixed at the HIGH level.

By performing such programming, the redundant address signal Rdi from the NAND gate 104 becomes the internal address signal Ai, and the redundant address signal Rdi + 1 from the NAND gate 114 becomes the internal address signal Ai + lb.

Therefore, when (Ai, Aib, Ai + 1, Ai + lb) = (1, 0, 0, 1), all three inputs to the AND gate 120 are at the HIGH level, and only in this case From the AND gate 120, a high level output is obtained. When an internal address signal having another logic state is input, a low level output is obtained from the AND gate 120.

(3) When both RAP (i) and RAP (i + l) are in the programmed state Next, when the redundant address program circuits RAP (i) and RAP (i + l) are both in the programmed state explain.

In the above case, the internal address signals Ai and Ai + lb are selected as the program addresses, and the memory cell 1 in (1) described above is defective. In order to perform such programming, the fuse 401 in FIG. 9, which is one of the elements constituting the redundant address program circuit RAP (i), RAP (i + l), is blown, and the redundant address program circuit RAP Both outputs of (i) and RAP (i + l) are fixed at HIGH level. Further, the fuse 401 in FIG. 9, which is one element of the redundant use program circuit RP, is blown, and the output of the redundant address program circuit RP is fixed at the HIGH level.

With such programming, the redundant address signal Rdi from the NAND gate 104 becomes the internal address signal Ai, and the redundant address signal Rdi + 1 from the NAND gate 114 becomes the internal address signal Ai + 1. .

Therefore, when (Ai, Aib, Ai + 1, Ai + lb) = (1, 0, 1, 0), all three inputs to the ND gate 120 are at the HIGH level. A high level output is obtained from gate 120. When an internal address signal of another logic state is input, a low level output is obtained from the AND gate 120.

(4) When both RAP (i) and RAP (i + 1) are in the non-program state Next, when both the redundant address program circuits RAP (i) and RAP (i + l) are in the non-program state Will be described.

In the above case, the internal address signals Aib and Ai + lb are selected as program addresses, and the memory cell 4 in (4) is defective. To perform such programming, the redundant address program circuit RA The fuse 401 in FIG. 9, which is one of the elements constituting P (i) and RAP (i + 1), is not blown, and the outputs of the redundant address program circuits RAP (i) and RAP (i + l) Both are fixed to LOW level. Further, the fuse 401 in FIG. 9, which is one element of the redundant use program circuit RP, is blown, and the output of the redundant address program circuit is fixed at the HIGH level.

By performing the programming in this manner, the redundant address signal Rdi from the NAND gate 104 becomes the internal address signal Aib, and the redundant address signal Rdi + 1 from the NAND gate 114 becomes the internal address signal Ai + lb.

Therefore, when (Ai, Aib, Ai + 1, Ai + lb) = (0, 1, 0, 1), all three inputs to the ND gate 120 are at the HIGH level. A high level output is obtained from gate 120. When an internal address signal having another logic state is input, a low level output is obtained from the AND gate 120.

As described above, in the first embodiment shown in FIG. 1, a redundant address program can be performed for two internal address signals Ai and Aib by one redundant address program circuit RAP (i). Also, redundant address programming can be performed for two internal address signals Ai + 1 and Ai + lb by one redundant address program circuit RAP (i + 1). Therefore, it becomes possible to reduce the number of program elements for redundant address programming to half of the conventional one. As a result, the area occupied by the program element is halved, and the element can be highly integrated. Further, as a result of halving the number of program elements, the number of times of performing the redundant address program can be halved, thereby reducing the time required for programming.

(Configuration of the second embodiment device)

FIG. 2 is a circuit diagram of a redundant circuit of the semiconductor memory device according to the second embodiment of the present invention. In FIG. 2, the number of elements is further reduced than in the first embodiment by configuring the redundant address decoder with a transmission gate circuit. Also, in this second embodiment, one redundant address program circuit is set to the program / non-program state, so that two other internal addresses that are not complementary, such as internal address signals, The signals Ai and Ai + 1 can be selected.

Hereinafter, only the configuration of FIG. 2 that is different from that of FIG. 1 will be described.

In FIG. 2, since the redundant decode circuits 130 and 140 have the same configuration, the redundant decode circuit 130 will be described, and the description of the redundant decode circuit 140 will be omitted.

The redundant decoding circuit 130 includes an inverter 131 and two transmission gates 132 and 135. Transmission gate 132 includes a P-channel transistor 133 and an N-channel transistor 134. The transmission gate 135 includes a P-channel transistor 136 and an N-channel transistor 137.

The output of the redundant address program circuit RAP (i) is directly input to the gates of the P-channel transistor 133 and the N-channel transistor 137. The output of the redundant address program circuit RAP (i) is inverted and input to the gates of the N-channel transistor 134 and the P-channel transistor 135 by the inverter 131.

An internal address signal Ai is input to a transmission gate 132 composed of a P-channel transistor 133 and an N-channel transistor 134.

An internal address signal Ai + 1 is input to a transmission gate 135 composed of a P-channel transistor 136 and an N-channel transistor 137. The outputs of these two transmission gates 132 and 135 are the same and become a common redundant address signal Rdi.

Further, in the device of the second embodiment, a NAND gate 150 is used as a redundant decoding circuit. The AND gate 150 receives the outputs of the redundant address decode circuits 130 and 140 and the inverted signal obtained by inverting the output of the redundant use program circuit RP at the inverter 151. The inverter 152 can be included in the redundant use program circuit RP.

(Explanation of the operation of the second embodiment)

Next, the operation of the second embodiment is the same as (1) and (2) described in the first embodiment. The description will be made separately for one program state.

(1) When RAP (i) is in program state and RAP (i + l) is in non-program state

First, the operation when the redundant address program circuit RAP (i) is set to the program state and: RAP (i + l) is set to the non-program state will be described. In this case, the redundant use program circuit RP is also set to the program state, and its output is fixed at the HIGH level.

In the above case, the internal address signals Aib and Ai + 1 are set as the program address, and the memory cell 3 of (3) described above is defective. To perform such programming, the settings may be made in the same manner as in (1) of the first embodiment.

When the redundant address program circuit RAP (i) is in the programmed state and its output is fixed at the high level, the high level is applied to the P-channel transistor 133 of the transmission gate 132 and the N-channel transistor 134 is applied. Is high level. Accordingly, the two transistors 132 and 133 are both turned off, and the transmission gate 132 is turned off.

On the other hand, since the low level is applied to the P-channel transistor 136 of the transmission gate 135 and the high level is applied to the N-channel transistor 137, the two transistors 136 and 137 are turned on, and The mission gate 135 is turned on.

Therefore, the internal address signal Ai + 1 is output as the redundant address signal Rdi, and the internal address signal Ai is not selected.

The redundancy decoding circuit 140 is the same as the redundancy decoding circuit 130. If the redundancy address program circuit RAP (i + 1) is not programmed, the internal address signal Aib is output as the redundancy address signal Rdi + 1 and the internal address signal is output. Ai is not selected.

Therefore, when (Ai, Aib, Ai + 1, Ai + lb) = (0, 1, 1, 0), A All three inputs to the ND gate 150 are at a high level, and only in this case, a high level output can be obtained from the AND gate 150. When an internal address signal of another logic state is input, a low level output is obtained from the AND gate 150.

(2) When RAP (i) is in the non-program state and RAPU + 1) is in the program state

In the above case, the internal address signals Ai and Ai + lb are set as the program address, and the memory cell 2 in (2) described above is defective. To perform such programming, the settings may be made in the same manner as in the case of (2) of the first embodiment.

When the redundant address program circuit RAP (i) is not programmed and its output is fixed at a low level, the transmission gate 132 is turned on and the transmission gate 135 is turned on. Therefore, the internal address signal Ai becomes the redundant address signal Rdi, and the internal address signal Ai + 1 is not selected.

When the redundant address program circuit RAP (i + 1) is in the programmed state and its output is fixed at the HIGH level, the internal address signal Ai + lb is output as the redundant address signal Rdi + 1 and the internal address signal Aib is not selected.

Therefore, when (Ai, Aib, Ai + 1, Ai + lb) = (1, 0, 0, 1), all three inputs to the AND gate 150 are at the HIGH level, and only in this case A high level output is obtained from the gate 150. When an internal address signal of another logic state is input, a low level output is obtained from the AND gate 150.

As described above, in the second embodiment shown in FIG. 2, a redundant address program can be performed for two internal address signals Ai and Ai + 1 by one redundant address program circuit RAP (i). Also, for two internal address signals Aib and Ai + lb, One redundant address program circuit RAP (i + 1) enables a redundant address program in the program circuit. Therefore, it becomes possible to reduce the number of program elements for redundant address programming by half. As a result, the area occupied by the program element is halved, and the element can be highly integrated. Further, as a result of halving the number of program elements, the number of times the redundant address program is performed can be halved, so that the time required for programming can be reduced.

In the first and second embodiments, the program element is the fuse element shown in FIG. 9, but another program element such as a nonvolatile memory element such as an EEPROM may be used instead.

(Description of the semiconductor memory device to which the first and second embodiments are applied)

Next, a semiconductor memory device to which the redundant circuits of the first and second embodiments are applied will be described with reference to FIGS.

FIG. 3 is a schematic explanatory view showing a block division of a memory cell array of a semiconductor memory device. FIG. 4 is a schematic explanatory diagram showing two of the memory cell array blocks shown in FIG. 3 in an enlarged manner. FIG. 5 is a wiring diagram showing details in the memory cell array block shown in FIG.

In FIG. 3, 16 memory cell array blocks 200 having block numbers 0 to 15 are provided. As shown in FIGS. 4 and 5, a normal memory cell array 201 in which 1024 × 64 normal memory cells 10 are arranged is arranged in each memory cell array block 200. For this purpose, 256 main word lines MWL are provided, and four 1024 sub word lines SWL are provided for one main word line MWL. Note that the 256 main word lines MWL are shared by the 16 memory cell array blocks 200. There are 64 bit line pairs BL and / BL each. The memory cell 10 is connected to one sub-word line SWL and a pair of bit lines BL and / BL.

Further, in the memory cell array block 200, in addition to the normal memory cell array 201, a row redundancy memory cell array 202 in which a plurality of row redundancy memory cells are arranged is arranged. This row redundant memory cell array 202 has a structure as shown in FIG. In addition, two redundant main word lines RMWL, eight redundant sub-word lines RSWL, and 16 sets of redundant bit lines BL, / BL (not shown) are also arranged.

In the memory cell array block 200, a column redundant memory cell array 203 in which a plurality of column redundant memory cells are arranged is provided outside the normal memory cell region as shown in FIG.

The 256 main word lines MWL are connected to the main row selection decoder 210, and one main word line MWL is connected to the upper main row address signals A8 to A11 and A13 to A16 input to the main row selection decoder 210. The main lead line MWL is activated.

The 1024 sub-line lines SWL are connected to sub-port selection decoders 220 provided for each block 200. By this sub-row selection decoder 220, one sub-word line SWL is activated. The details of the sub-selection decoder 220 will be described later.

A block selection decoder 230 is provided to select any one of the 16 memory cell array blocks 200. The block selection decoder 230 receives any two of the block selection address signals A3 to A6 and the lower-order sub-row address signals A7 and A12 for selecting the sub-word line SWL. Further, a boosted line VLINE1 is connected to the block selection decoder 230.

The column predecoder 240 receives a program selection signal BSS and a column address signal A0 to A2, and outputs a signal for simultaneously selecting a pair of eight bit lines BL and / BL in one memory cell array block 200. C to be output to the decoder 242. That is, as shown in FIG. 3, one memory cell array block 200 is divided into eight bit line pairs に selected at the same time and divided into eight column numbers 0 to 7. The block selection signal BSS is generated by the block selection decoder 230 and input to the column predecoder 240 via the block control circuit 250.

The data buses DB and / DB are connected to a read bus 270 and a write bus 280 via eight sense amplifiers 260. These sense amplifiers 26 The value of 0 is controlled by the block control circuit 250.

Here, the block control circuit 250 has a function of outputting a redundancy use signal JSS for selecting a redundant memory cell to the work selection decoder 230 and the column predecoder 240. Based on the redundant use signal JSS from the block control circuit 250, the block selection decoder 230 replaces the defective normal memory cell with the row redundant memory cell array 202 or the column redundant memory cell array 204. It has a function to select the redundant memory cell of the.

The logic of the main word line and a prohibition signal for prohibiting the selection of the normal memory cell when the redundant memory cell is used are input to the sub-row selection decoder 220. This prohibition signal is generated by the block selection decoder 230 based on the redundant use signal JSS from the block control circuit 250.

Therefore, the redundant circuits shown in the first and second embodiments are provided in the block control circuit 250 shown in FIG. Then, the redundant use signal R-E / D output from the decode circuits 120 and 150 of the first and second embodiments can be used as the redundant use signal JSS shown in FIG.

FIG. 6 shows normal memory cells in the normal memory cell array 201, row redundant memory cell array 202 and column redundant memory cell array 203 provided in one memory cell block 200 shown in FIG. Alternatively, the configuration for selecting a redundant memory cell is schematically shown. In FIG. 6, circuits having the same functions as the circuits shown in FIG. 4 are denoted by the same reference numerals. The row decoder 290 shown in FIG. 6 is a general term for the main row selection decoder 210 and the sub row selection decoder 220 shown in FIG.

Further, FIG. 6 shows a column redundant circuit 255 and a row redundant circuit 254 arranged in the block control circuit 250 in FIG. FIG. 6 shows a row predecoder 232 arranged in the block selection decoder 230 in FIG.

The internal address signal A i converted by the address input circuit (not shown) is output from the column predecoder 240, the column redundancy circuit 252, the row predecoder 2332, and the row redundancy circuit. Road 2 5 4 is forced. When the redundant circuits 252 and 254 are not used, the redundant use signal JSS becomes non-active. As a result, the redundant memory cells in the row redundant memory cell array 202 and the column redundant memory cell array 203 are not selected, and the normal memory cells in the normal memory cell array 201 are selected.

The use of the redundant circuits 25 2 and 25 4 is only when the internal address signal to be relieved is input. At this time, the redundant use signal JSS becomes active and the redundant memory cell is selected. The redundant use signal JSS is also input to the column and row predecoders 240 and 232, and functions as a prohibition signal for prohibiting the selection of a normal memory cell. Therefore, redundant memory cells and normal memory cells are not selected twice. Therefore, a defective memory cell can be replaced with a redundant memory cell. At this time, whether to select a row redundant memory cell or a column redundant memory cell is determined by an address programmed in the redundant circuits 252 and 254.

Note that these semiconductor storage devices are configured as semiconductor devices formed on one semiconductor substrate together with other functional blocks. In this semiconductor device, since the number of program elements is halved, high integration is possible.

Further, an electronic device can be formed using a semiconductor device including the semiconductor storage device of the present invention. Therefore, the present invention can be applied to various electronic devices using the semiconductor storage device as a memory, and can be applied to a stationary type such as a personal convenience device, and particularly to a portable electronic device such as a mobile convenience device and a mobile phone. When applied to, it can contribute to downsizing of equipment.

Claims

The scope of the claims

1. A normal memory cell array in which a plurality of normal memory cells are arranged in a matrix,

A redundant memory cell array in which a plurality of redundant memory cells used when any of the plurality of normal memory cells is defective are arranged in a matrix;

Has,

The row / column selecting means prohibits the selection of the normal memory cells based on an output from the redundant circuit,

Wherein the plurality of program circuits 2 ¹¹ - includes a ^one redundant address program circuit, and one of the redundant use program circuit,

The redundant circuit,

Wherein the 2 ⁿ pieces of internal Adoresu signal, the 2 ⁿ - and de circuit, - ^one based on the information from the redundant § address program circuit, a redundant Adoresudeko for outputting a plurality of redundant Adoresu signal

A redundant decode circuit that outputs the redundant use signal based on the plurality of redundant address signals from the redundant address decode circuit and information from the redundant use program circuit;

A semiconductor memory device comprising:

2. In Claim 1,

Said redundancy Adoresudeko one hard circuit, the 2 ¹¹ - when one of the ^one redundant § address program circuit is in the non-programmed state, the double one of the 2 ⁿ pieces of internal Adoresu signal And one of the ²ⁿ internal address signals is selected as one of the plurality of redundant address signals when the one redundant address program circuit is in a programmed state. A semiconductor memory device, which is selected.

3. In Claim 2,

The redundant address decode circuit,

Said 2. The output from one ^one redundant § address program circuit, a conversion circuit for converting it its complementary signal,

One of the complementary signals and one of the ²ⁿ internal address signals are inputted, and a first selection is made to output a signal synchronized with the one internal address signal according to one state of the complementary signals. Circuit and

The other of the complementary signals and another one of the ²ⁿ internal address signals are inputted, and a signal synchronized with the other internal address signal according to the other state of the complementary signal. A second selection circuit that outputs

A semiconductor memory device comprising:

4. In Claim 3,

A semiconductor memory device, wherein each of the first and second selection circuits is a transmission gate.

5. In Claim 4,

The conversion circuit according to the second aspect. The semiconductor memory device characterized by having ^one Inba Isseki - 2 "for inverting the logic of the output from one ^one redundant § address program circuit.

6. In any one of claims 1 to 5,

The redundant decoder is constituted by an AND gate. The AND gate operates only when the plurality of redundant address signals from the redundant address decode circuit and the output from the redundant use program circuit are both at a high level. A semiconductor memory device, wherein the redundant use signal is activated.

7. In any one of claims 1 to 6,

2. The semiconductor memory device according to claim 1, wherein the 2 ⁿ internal address signals are complementary signals formed based on two external address signals input from outside.

8. A semiconductor device comprising the semi-conductor memory device according to any one of claims 1 to 7.

9. An electronic apparatus comprising the semiconductor device according to claim 8.