R

RISC-V

A RISC-V simulator with an integrated debugger. Support full RV32IM instruction set, along with pseudo instruction and several environmental calls.

Retro-V is a SoftCPU in Verilog that implements RISC-V 32-bit architecture RV32I, but with 8-bit external bus

x86 and RISC-V assembler

Education-friendly RISC-V based system emulator

Bootdisks and Linux images for SBCs and TV boxes.

The Dumb Bootloader for RISC-V systems

RISC-V assembler in Common Lisp

This is a project to enable other developers to modify an open source spec for a CPU, build a simulator and run tests.

Minimalist modular assembler for RISC-V. ISA extensions can be added/modified easily through csv files.

Virtual machine for Yeti Project / RISC-V Virtual machine as library

A 32-bit pipelined RISC-V CPU

Simple RISC-V Disassembler based on RISC-V Sliderules Web Script

E203 with GSNN AI acclerate module

RISC-V C Baremetal Example

A basic RV32I core for practice.

Development environment useful for debugging RVV (RISC-V Vector) software without hardware with GDB.

A simple educational operating system from scratch.

Bare-Metal 'Guil-OS' (Electronics & Electricals Projects)

(x86 / Risc-V / Aarch64)