R

RISC-V

This is the central "hub" project for the Mutually Assured Accountability (MAA) Framework. This repository contains the master README, which provides the unified vision, architecture, and links to all component projects.

Bare-Metal 'Guil-OS' (Electronics & Electricals Projects)

(x86 / Risc-V / Aarch64)

A simple educational operating system from scratch.

Development environment useful for debugging RVV (RISC-V Vector) software without hardware with GDB.

Virtual machine for Yeti Project / RISC-V Virtual machine as library

A basic RV32I core for practice.

RISC-V C Baremetal Example

E203 with GSNN AI acclerate module

Simple RISC-V Disassembler based on RISC-V Sliderules Web Script

A RISC-V simulator with an integrated debugger. Support full RV32IM instruction set, along with pseudo instruction and several environmental calls.

native-blink_asm example for board SparkFun RED-V thing plus (CPU FE310). Based on https://github.com/platformio/platform-sifive/tree/develop/examples/native-blink_asm

An operating system for RISC-V ISA

A Clojure library designed for writing RISC-V assembly in clojure

Bootdisks and Linux images for SBCs and TV boxes.

RISC-V IDE

Experiments and examples for the WEMOS LOLIN C3 MINI board.

Minimalist modular assembler for RISC-V. ISA extensions can be added/modified easily through csv files.

RISC-V assembler in Common Lisp