R

RISC-V

This project develops RISC-V processor implementations.

A RISC-V simulator with an integrated debugger. Support full RV32IM instruction set, along with pseudo instruction and several environmental calls.

x86 and RISC-V assembler

Bootdisks and Linux images for SBCs and TV boxes.

This is a project to enable other developers to modify an open source spec for a CPU, build a simulator and run tests.

A simple educational operating system from scratch.

Bare-Metal 'Guil-OS' (Electronics & Electricals Projects)

(x86 / Risc-V / Aarch64)

A Clojure library designed for writing RISC-V assembly in clojure

Experiments and examples for the WEMOS LOLIN C3 MINI board.

Blink example using no external crate, the Peripherals Access Crate gd32vf103-pac, then using the Hardware Abstraction Layer gd32vf103xx-hal.

Requires rust nightly.

Check https://gitlab.com/jeancf/longan-nano-blink for the assembly version.

RISC-V assembler in Common Lisp

Education-friendly RISC-V based system emulator

A 32-bit pipelined RISC-V CPU

native-blink_asm example for board SparkFun RED-V thing plus (CPU FE310). Based on https://github.com/platformio/platform-sifive/tree/develop/examples/native-blink_asm

RISC-V IDE

https://ovsienko.info/D1/

An operating system for RISC-V ISA

This is the central "hub" project for the Mutually Assured Accountability (MAA) Framework. This repository contains the master README, which provides the unified vision, architecture, and links to all component projects.