APS: Open-Source Hardware-Software Co-Design Framework for Agile Processor Specialization Research

NEX - Hardware Accelerator Full-Stack Simulation Framework

Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

🚀 Efficient implementations of state-of-the-art linear attention models

Open ABI and FFI for Machine Learning Systems

Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving

A fork of Xiangshan for AI

Top-level repository of ACT Ecosystem

Mirage Persistent Kernel: Compiling LLMs into a MegaKernel

Public repository for Skills

A machine learning accelerator core designed for energy-efficient AI at the edge.

Asterinas is a secure, fast, and general-purpose OS kernel, written in Rust and providing Linux-compatible ABI.

High level synthesis language for hardware design

Partial evaluator for Arm's Architecture Specification Language (ASL)

Domain-specific language designed to streamline the development of high-performance GPU/CPU/Accelerators kernels

ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference

DeepSeek-V3/R1 inference performance simulator

MLIR Compiler for Arm Specification Lanuage

The Herd toolsuite to deal with .cat memory models (version 7.xx)

VAST is an experimental compiler pipeline designed for program analysis of C and C++. It provides a tower of IRs as MLIR dialects to choose the best fit representations for a program analysis or fu…

Safe interop between Rust and C++

MLIR+EqSat

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Home for "How To Scale Your Model", a short blog-style textbook about scaling LLMs on TPUs

magic-trace collects and displays high-resolution traces of what a process is doing

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores