Open-source high-performance RISC-V processor

Chisel: A Modern Hardware Design Language

Rocket Chip Generator

Generic programming for Scala

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SonicBOOM: The Berkeley Out-of-Order Machine

Scala based HDL

Berkeley's Spatial Array Generator

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

Flexible Intermediate Representation for RTL

Simple RISC-V 3-stage Pipeline in Chisel

A python-ish pure and total functional programming language

Vector Acceleration IP core for RISC-V*

Operations for primitive and String singleton types

A dynamic verification library for Chisel.

UCLID5: formal modeling, verification, and synthesis of computational systems

Get the name of an variable, function, class member, or type as a string--at compile-time!

Time-sensitive affine types for predictable hardware generation

Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)

Example code to accompany shapeless-guide.

Provides dot visualizations of chisel/firrtl circuits

A eDSL framework based on Scala and MLIR, focusing on the Hardware design.

Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC

A fork of Xiangshan for AI

Domain-Specific Architecture Generator 2

Hands-On Scala Programming [Video], published by Packt

Polyite: Iterative Schedule Optimization for Parallelization in the Polyhedron Model