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WO2018127950A1 - Appareil de transmission optique - Google Patents

Appareil de transmission optique Download PDF

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Publication number
WO2018127950A1
WO2018127950A1 PCT/JP2017/000074 JP2017000074W WO2018127950A1 WO 2018127950 A1 WO2018127950 A1 WO 2018127950A1 JP 2017000074 W JP2017000074 W JP 2017000074W WO 2018127950 A1 WO2018127950 A1 WO 2018127950A1
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WO
WIPO (PCT)
Prior art keywords
error correction
unit
monitor
code error
inner code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2017/000074
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English (en)
Japanese (ja)
Inventor
聖史 斧原
泰久 島倉
理 飯島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to PCT/JP2017/000074 priority Critical patent/WO2018127950A1/fr
Publication of WO2018127950A1 publication Critical patent/WO2018127950A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes

Definitions

  • the present invention relates to an optical transmission apparatus, and in particular, to receive an optical signal converted from a transmission signal including a plurality of transmission frames in which error correction coding of an outer code and error correction coding of an inner code are performed for each unit frame.
  • the present invention relates to a transmission apparatus.
  • the error correction function in the conventional optical transmission apparatus improves error correction performance by concatenating a plurality of codes. This is called a concatenated code, a code positioned in the preceding stage in the encoding process of the connected code is called an outer code, and a code positioned in the subsequent stage is called an inner code.
  • the error correction function in the conventional optical transmission apparatus handles a signal with a bit rate of 10 Gbps or 40 Gbps for an information signal to be transmitted and received, so that an outer code error correction encoding unit and an outer code error correction are performed with a single LSI (Large Scale Integration). It was possible to implement a decoding unit, an inner code error correction coding unit, and an inner code error correction decoding unit.
  • outer code error correction decoding unit In carrying out error correction of the received signal based on information theory in these outer code error correction coding unit, outer code error correction decoding unit, inner code error correction coding unit and inner code error correction decoding unit, In order to observe the influence of the signal distortion generated in the transmission path, it is necessary to obtain the sum of the number of correction bits of the frame decoded at the same timing in the decoding unit of each of the inner code and the outer code. It is necessary to synchronize the frame phase of the conversion unit.
  • the outer code error correction coding unit and outer code error correction decoding unit, and the inner code error correction coding unit and inner code error correction decoding unit must be implemented with a single LSI. It is difficult to implement the decoding unit for each of the outer code and the inner code with separate LSIs. Furthermore, when transmitting and receiving a bit rate exceeding 400 Gbps, the inner code decoding unit and the outer code decoding unit may be mounted on a plurality of LSIs.
  • the error correction information of the inner code and the outer code is temporally determined from the positions of FP (Frame Pulse) and MFP (Multi-Frame Pulse) generated from the LSI on which the outer code and the inner code are mounted.
  • FP Full Pulse
  • MFP Multi-Frame Pulse
  • an object of the present invention is to easily synchronize the measurement time of the number of error correction bits of the inner code and the outer code, and to accurately obtain the sum.
  • the optical transmission apparatus provides light converted from a transmission signal including a plurality of transmission frames in which error correction coding of an outer code and error correction coding of an inner code are performed for each unit frame.
  • An optical transmission device that receives a signal, wherein the optical signal is received and a conversion unit that converts the optical signal into an electrical signal is synchronized with the plurality of transmission frames included in the electrical signal.
  • a frame synchronization unit for generating a received signal, and performing error decoding of the inner code on the received signal for each unit frame, thereby generating a first decoded signal, and for each unit frame, An inner code error correction decoding unit that counts the number of first error correction bits, which is the number of bits corrected in error, and error decoding of the outer code for the first decoded signal for each unit frame And the second An outer code error correction decoding unit that generates a decoded signal and counts a second error correction bit number that is the number of bits in which an error has been corrected for each unit frame; and the first error correction bit number for each period An inner code error correction monitor unit that calculates a first addition value by adding, and an outer code error correction monitor unit that calculates a second addition value by adding the second error correction bit number for each period And reporting the cycle to the inner code error correction monitor unit and the outer code error correction monitor unit, and correcting the error for each cycle by summing the first addition value and the second addition value. And an overall error correction monitor unit for calculating the total
  • the optical transmission apparatus performs error correction coding of an outer code and error correction coding of an inner code for each unit frame, and includes a plurality of transmission frames including a monitor cycle bit indicating a cycle.
  • An optical transmission apparatus that receives a converted optical signal, the optical transmission device receiving the optical signal and converting the optical signal into an electrical signal, and the plurality of transmission frames included in the electrical signal. By synchronizing, a received signal is generated, and a frame synchronization unit that detects the monitor cycle bit, and error decoding of the inner code is performed on the received signal for each unit frame.
  • An inner code error correction decoding unit that generates a decoded signal and counts a first error correction bit number that is the number of bits in which an error is corrected for each unit frame, and for each unit frame, By performing error decoding of the outer code on one decoded signal, a second decoded signal is generated, and the number of second error correction bits, which is the number of bits corrected for errors, for each unit frame is counted.
  • An outer code error correction decoding unit, and an inner code for calculating a first addition value by adding the first error correction bit number for each period indicated by the monitor period bit detected by the frame synchronization unit An outer code error correction monitor that calculates a second addition value by adding the error correction monitor unit and the second error correction bit number for each period indicated by the monitor period bits detected by the frame synchronization unit And the first addition value and the second addition value are summed to calculate the total number of bits in which errors are corrected for each period indicated by the monitor period bits detected by the frame synchronization unit.
  • the overall error correction monitoring unit that, characterized in that it comprises a.
  • the optical transmission apparatus is an optical transmission device that converts light transmitted from a transmission signal including a plurality of transmission frames that have been subjected to error correction coding of an outer code and error correction coding of an inner code for each unit frame.
  • An optical transmission device that receives a signal, wherein the optical signal is received and a conversion unit that converts the optical signal into an electrical signal is synchronized with the plurality of transmission frames included in the electrical signal.
  • a frame synchronization unit that generates a received signal, a first dividing unit that divides the received signal into n divided received signals that are integers of 2 or more, and the n divided received signals for each unit frame
  • error decoding of the inner code is performed to generate n first divided decoded signals, and n first error correction bits that are the number of bits in which the error is corrected for each unit frame
  • An error correction decoding unit a second dividing unit that synthesizes the n first divided decoded signals and divides them into m second divided decoded signals that are integers of 2 or more, and for each unit frame
  • By performing error decoding of the outer code on the m second divided decoded signals to generate m third divided decoded signals and the number of bits in which the error is corrected for each unit frame By adding the m number of outer code error correction decoding units that count the number m of the second error correction bits and the number n of the first error correction bits for each period, By adding the n number of inner code
  • a code error correction monitor unit, the n inner code error correction monitor units, and the m outer codes The correction correction monitor unit is notified of the period, and the sum of the n first addition values and the m second addition values is calculated to calculate the total number of bits in which errors are corrected for each period. And an overall error correction monitor unit.
  • the number of error correction bits is added in the inner code error correction decoding unit and the outer code error correction coding unit based on the period notified from the overall error correction monitoring unit. Therefore, it is possible to easily synchronize the measurement time of the number of error correction bits of the inner code and the outer code, and to accurately obtain the sum.
  • the error correction bit is determined in the inner code error correction decoding unit and the outer code error correction encoding unit based on the cycle indicated by the monitor cycle bit included in the transmission frame. Since the numbers are added, it is possible to easily synchronize the measurement times of the error correction bit numbers of the inner code and the outer code, and to accurately obtain the sum.
  • FIG. 1 is a block diagram schematically showing a configuration of an optical communication system according to Embodiments 1 to 4.
  • FIG. 1 is a block diagram schematically showing a configuration of an optical transmission device in a first embodiment.
  • 6 is a schematic diagram showing a configuration of an OTUk frame according to Embodiments 1, 2, and 4.
  • FIG. 6 is a schematic diagram showing a configuration of an FEC frame in the first to fourth embodiments.
  • 3 is a block diagram schematically showing a configuration of an inner code error correction monitor unit in the first embodiment.
  • FIG. 6 is a schematic diagram illustrating an example of a PM_SYNC signal in Embodiment 1.
  • FIG. 3 is a block diagram schematically showing a configuration of an outer code error correction monitoring unit in the first embodiment.
  • FIG. 6 is a block diagram schematically showing a configuration of an optical transmission apparatus in a second embodiment.
  • FIG. 10 is a block diagram schematically showing a configuration of an inner code error correction monitor unit in the second embodiment.
  • FIG. 10 is a block diagram schematically showing a configuration of an outer code error correction monitor unit in the second embodiment.
  • FIG. 6 is a block diagram schematically showing a configuration of an optical transmission device in the third and fourth embodiments.
  • FIG. 10 is a block diagram schematically showing a configuration of a transmission unit in a third embodiment.
  • FIG. 10 is a schematic diagram illustrating a configuration of an OTUk frame in a third embodiment.
  • FIG. 10 is a block diagram schematically showing a configuration of a receiving unit in a third embodiment.
  • FIG. 10 is a block diagram schematically showing a configuration of an inner code error correction monitor unit in the third embodiment.
  • FIG. 10 is a block diagram schematically showing a configuration of an outer code error correction monitoring unit in a third embodiment.
  • FIG. 10 is a block diagram schematically showing a configuration of a transmission unit in a fourth embodiment.
  • FIG. 10 is a block diagram schematically showing a configuration of a receiving unit in a fourth embodiment.
  • FIG. 1 is a block diagram schematically showing a configuration of an optical communication system 100 according to the first embodiment.
  • the optical communication system 100 includes an optical transmission device 110A and an optical transmission device 110B.
  • the two optical transmission apparatuses 110A and 110B are connected by a communication path 101.
  • the optical transmission apparatus 110 when it is not necessary to distinguish each of the optical transmission apparatuses 110A and 110B, they are referred to as the optical transmission apparatus 110.
  • FIG. 2 is a block diagram schematically showing the configuration of the optical transmission apparatus 110 according to the first embodiment.
  • the optical transmission device 110 includes a transmission unit 120 and a reception unit 130.
  • the optical transmission apparatus 110 transmits / receives an optical signal converted from a transmission signal including a plurality of transmission frames subjected to error correction coding of an outer code and error correction coding of an inner code for each unit frame.
  • the transmission unit 120 includes an OTU (Optical channel Transport Unit) framer 121, an outer code error correction encoding unit 122, an inner code error correction encoding unit 123, and an E / O (Electrical / Optical) conversion unit 124. .
  • OTU Optical channel Transport Unit
  • E / O Electronic / Optical
  • the OTU framer 121 converts the client signal CS indicating the data to be transmitted to the communication path 101 into an OTUk frame that is a transmission frame, and transmits the transmission signal including a plurality of converted OTUk frames to the outer code error correction encoding unit 122.
  • the OTU framer 121 satisfies “ITU-T Recommendation G.709 / Y.1331”.
  • K in the OTUk frame is an identification number representing a bit rate, and is an integer of 0 or more.
  • FIG. 3 is a schematic diagram showing the configuration of the OTUk frame.
  • the OTUk frame 102 includes an overhead part 102a, a payload part 102b, and an error correction parity part 102c.
  • the overhead unit 102a stores overhead information such as FAS (Frame Alignment Signal) and MFAS (Multi-FAS).
  • the payload part 102b stores the client signal CS.
  • the error correction parity unit 102c stores redundant bits added by the outer code error correction coding unit 122 and the inner code error correction coding unit 123.
  • the outer code error correction encoding unit 122 encodes the transmission signal by adding the redundant bits corresponding to the transmission signal as an information sequence.
  • the outer code error correction encoding unit 122 then provides the encoded transmission signal (first encoded signal) to the inner code error correction encoding unit 123.
  • the outer code error correction coding unit 122 divides the signal in the OTUk frame into several parts so as to be easily coded, and performs coding.
  • the frame encoded in this way is called an FEC frame (unit frame).
  • FIG. 4 is a schematic diagram showing the configuration of the FEC frame.
  • the outer code FEC frame 103 # includes an information bit portion 103a and an outer code redundant bit portion 103b in order from the head of the frame.
  • the inner code redundant bit unit 103c is added by the inner code error correction coding unit 123 as described later.
  • the inner code error correction encoding unit 123 encodes the first encoded signal, which is the encoded transmission signal, as an information sequence and adds redundant bits corresponding to the information sequence.
  • the inner code error correction encoding unit 123 supplies the transmission signal (second encoded signal) thus encoded to the E / O conversion unit 124.
  • the inner code FEC frame 103 includes an information bit part 103a, an outer code redundant bit part 103b, and an inner code redundant bit part 103c.
  • the E / O conversion unit 124 converts an electrical signal, which is a transmission signal (second encoded signal) subjected to error correction coding, into an optical signal OS, and transmits the optical signal OS to the communication path 101. .
  • the receiving unit 130 of the optical transmission apparatus 110 includes an O / E (Optical / Electrical) conversion unit 131, a frame synchronization unit 132, an inner code error correction decoding unit 133, an outer code error correction decoding unit 134, and an OTU.
  • a deframer 135, an inner code error correction monitor unit 140, an outer code error correction monitor unit 150, and an overall error correction monitor unit 160 are provided.
  • the inner code error correction decoding unit 133 and the inner code error correction monitor unit 140 are connected by the first serial bus 170.
  • Outer code error correction decoding section 134 and outer code error correction monitor section 150 are connected by a second serial bus 171.
  • the inner code error correction monitor unit 140 and the overall error correction monitor unit 160 are connected by a third serial bus 172 and a first control line 174.
  • the outer code error correction monitor unit 150 and the overall error correction monitor unit 160 are connected by a fourth serial bus 173 and a second control line 175.
  • the serial bus includes I2C that satisfies "THE I2C-BUS SPECIFICATION” and MDIO (Management Data Input / Output) that satisfies "IEEE802.3ba”, etc., LSI, FPGA (Field Programmable Gate Array, ROM, and ROM). ), Etc., to exchange alarms such as reception errors and performance information.
  • the O / E converter 131 receives an optical signal from the communication path 101 and converts the optical signal into an electrical signal.
  • the frame synchronization unit 132 generates a reception signal by synchronizing a plurality of OTUk frames 102 included in the electrical signal converted by the O / E conversion unit 131. For example, the frame synchronization unit 132 synchronizes the OTUk frame 102 from the overhead unit 102 a of the OTUk frame 102 of the electrical signal, and transmits a reception signal including the synchronized frame to the inner code error correction decoding unit 133.
  • the inner code error correction decoding unit 133 performs error correction decoding processing of the inner code of the received signal, and provides the decoded received signal (first decoded signal) to the outer code error correction decoding unit 134. For example, the inner code error correction decoding unit 133 generates a first decoded signal by performing error decoding of the inner code on the received signal for each FEC frame. Further, the inner code error correction decoding unit 133 counts the number of error correction bits (first error correction bit number), which is the number of bits corrected for errors, for each FEC frame.
  • Outer code error correction decoding section 134 further performs error correction decoding processing of the outer code on the first decoded signal that is the received signal that has been subjected to error correction decoding of the inner code by inner code error correction decoding section 133.
  • the received received signal (second decoded signal) is transmitted to the OTU deframer 135.
  • the outer code error correction decoding unit 134 generates the second decoded signal by performing error decoding of the outer code on the received signal for each FEC frame. Further, the outer code error correction decoding unit 134 counts the number of error correction bits (second error correction bit number), which is the number of bits corrected for errors, for each FEC frame.
  • the OTU deframer 135 deletes the overhead part 102a and the error correction parity part 102c of the OTUk frame 102 shown in FIG. 3, and outputs the signal stored in the payload part 102b as the client signal CS.
  • the inner code error correction monitor unit 140 reads error correction information indicating the number of error correction bits of the FEC frame generated by the inner code error correction decoding unit 133 via the first serial bus 170.
  • the error correction information may include the number of uncorrectable frames of the FEC frame and other information.
  • the inner code error correction monitoring unit 140 calculates the added value (first added value) by periodically adding the number of error correction bits indicated by the read error correction information. The cycle for adding the number of error correction bits is notified from the overall error correction monitor unit 160.
  • FIG. 5 is a block diagram schematically showing the configuration of the inner code error correction monitoring unit 140.
  • the inner code error correction monitor unit 140 includes a monitor I / F unit 141, an error correction bit addition unit 142, a PM_SYNC detection unit 143, a register unit 144 as a first register unit, and a serial bus I / F unit 145. Is provided.
  • the monitor I / F unit 141 functions as a first interface unit that communicates with the inner code error correction decoding unit 133.
  • the monitor I / F unit 141 uses the first serial bus 170 to transmit bits for which error correction has been performed by the inner code error correction decoding unit 133 from the inner code error correction decoding unit 133 for each FEC frame. Error correction information indicating the number is received.
  • the error correction bit addition unit 142 sequentially acquires error correction information indicating the number of error correction bits from the inner code error correction decoding unit 133, and sequentially adds the number of error correction bits indicated by the acquired error correction information. It functions as an error correction bit adder.
  • PM_SYNC detector 143 functions as a second interface unit that communicates with overall error correction monitor unit 160.
  • the PM_SYNC detection unit 143 receives a PM_SYNC signal that is a periodic signal output from the overall error correction monitor unit 160 via the first control line 174 and transmits the PM_SYNC signal to the error correction bit addition unit 142.
  • FIG. 6 is a schematic diagram illustrating an example of the PM_SYNC signal.
  • the error correction bit addition unit 142 stops adding the number of error correction bits indicated by the error correction information at the timing of receiving the PM_SYNC signal. For example, the error correction bit adding unit 142 stops the addition at the timing when the PM_SYNC signal shown in FIG. 6 indicates “1”. Then, the error correction bit addition unit 142 stores the addition result in the register unit 144. Next, the error correction bit addition unit 142 clears (resets) the addition result to “0” and restarts the addition.
  • the addition result here is an addition value of the number of bits corrected by the inner code error correction decoding unit 133 for each period indicated by the PM_SYNC signal.
  • the serial bus I / F unit 145 functions as a fifth interface unit that communicates with the overall error correction monitor unit 160.
  • the serial bus I / F unit 145 communicates with the overall error correction monitor unit 160 via the third serial bus 172.
  • the overall error correction monitor unit 160 makes an access request (first access request) to the serial bus I / F unit 145 via the third serial bus 172, so that the addition result is received from the register unit 144. Is read.
  • control lines for FP and MFP are used between the inner code error correction decoding unit and the inner code error correction monitor unit.
  • control lines for FP and MFP are not used, and the first serial bus 170 mounted between the inner code error correction decoding unit 133 and the inner code error correction monitor unit 140 is used.
  • the serial bus is normally connected between a DSP (Digital Signal Processor) and an external control circuit, and is prepared for monitoring an alarm in each block.
  • DSP Digital Signal Processor
  • the inner code error correction decoding unit 133 and the inner code error correction monitor unit 140 may be mounted on the same LSI.
  • the interface in this case does not necessarily need to use a serial bus, and may use control lines for FP and MFP.
  • the outer code error correction monitor unit 150 reads the error correction information indicating the number of correction bits of the FEC frame generated by the outer code error correction decoding unit 134 via the second serial bus 171.
  • the outer code error correction monitor unit 150 adds the number of correction bits indicated by the error correction information for each period indicated by the PM_SYNC signal sent from the overall error correction monitor unit 160 via the second control line 175.
  • the added result (second added value) is calculated.
  • overall error correction monitor unit 160 reads the addition result from outer code error correction monitor unit 150 by sending an access request (second access request) via fourth serial bus 173.
  • FIG. 7 is a block diagram schematically showing the configuration of the outer code error correction monitoring unit 150.
  • the outer code error correction monitoring unit 150 includes a monitor I / F unit 151 as a third interface unit, an error correction bit addition unit 152 as a second error correction bit addition unit, and a PM_SYNC detection unit 153 as a fourth interface unit.
  • a register unit 154 as a second register unit, and a serial bus I / F unit 155 as a sixth interface unit.
  • Each unit of the outer code error correction monitor unit 150 performs the same processing as the corresponding unit of the inner code error correction monitor unit 140 shown in FIG.
  • the outer code error correction decoding unit 134 and the outer code error correction monitor unit 150 may be mounted on the same LSI.
  • the overall error correction monitor unit 160 transmits a monitor synchronization signal to the inner code error correction monitor unit 140 and the outer code error correction monitor unit 150 via the first control line 174 and the second control line 175.
  • the PM_SYNC signal is a synchronization signal of performance monitor information defined in “CFP MSA Management Interface Specification”.
  • the PM_SYNC signal normally communicates between the host and the module on a one-to-one basis.
  • the PM_SYNC signal is communicated between the host and the module on a one-to-one basis. From the overall error correction monitor unit 160 to the inner code error correction monitor unit 140 and the outer code error correction monitor unit 150, By transmitting the PM_SYNC signal at the same timing, it becomes possible to match the timing with the measurement cycle of the number of error bits of the inner code and the outer code. At this time, the signal wiring lengths of the overall error correction monitoring unit 160 and the inner code error correction monitoring unit 140 and the signal wiring lengths of the overall error correction monitoring unit 160 and the outer code error correction monitoring unit 150 need to be the same. .
  • the overall error correction monitor unit 160 reads the addition results stored in the register units 144 and 154 in the inner code error correction monitor unit 140 and the outer code error correction monitor unit 150, respectively, and adds the respective results to obtain a period. Each time, the total number of error correction bits indicated by the error correction information is calculated.
  • the processing circuit 10 may be a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuits), or an FPGA.
  • a part or all of the inner code error correction monitor unit 140, the outer code error correction monitor unit 150, and the entire error correction monitor unit 160 are, for example, a memory 11 and a memory as shown in FIG. 11 may be configured with a processor 12 such as a CPU (Central Processing Unit) that executes a program stored in the computer 11.
  • a program may be provided through a network, or may be provided by being recorded on a recording medium.
  • Embodiment 2 assumes a case where the PM_SYNC signal described in the first embodiment cannot be used.
  • the optical communication system 200 includes an optical transmission device 210A and an optical transmission device 210B.
  • the two optical transmission apparatuses 210A and 210B are connected by the communication path 101.
  • an optical transmission apparatus 210 When it is not necessary to distinguish each of the optical transmission apparatuses 210A and 210B, they are referred to as an optical transmission apparatus 210.
  • FIG. 9 is a block diagram schematically showing the configuration of the optical transmission apparatus 210 in the second embodiment.
  • the optical transmission apparatus 210 includes a transmission unit 120 and a reception unit 230.
  • the optical transmission apparatus 210 in the second embodiment is configured in the same manner as the optical transmission apparatus 110 in the first embodiment except for the receiving unit 230.
  • the receiving unit 230 includes an O / E conversion unit 131, a frame synchronization unit 132, an inner code error correction decoding unit 133, an outer code error correction decoding unit 134, an OTU deframer 135, and an inner code error correction monitoring unit. 240, an outer code error correction monitor unit 250, and an overall error correction monitor unit 260.
  • the receiving unit 230 in the second embodiment is configured in the same manner as the receiving unit 130 in the first embodiment except for the inner code error correction monitor unit 240, the outer code error correction monitor unit 250, and the overall error correction monitor unit 260. Yes.
  • the inner code error correction monitoring unit 240 and the overall error correction monitoring unit 260 are connected by the third serial bus 172, and unlike the first embodiment, the first control line 174 is used. Not.
  • the outer code error correction monitor unit 250 and the overall error correction monitor unit 260 are connected by the fourth serial bus 173, and unlike the first embodiment, the second control line 175 is not used.
  • the overall error correction monitor unit 260 notifies the inner code error correction monitor unit 240 via the third serial bus 172 and also the outer code error correction monitor via the fourth serial bus 173. The period is notified to the unit 250.
  • FIG. 10 is a block diagram schematically showing the configuration of the inner code error correction monitoring unit 240.
  • the inner code error correction monitoring unit 240 includes a monitor I / F unit 141, an error correction bit addition unit 242, a register unit 144, a serial bus I / F unit 145, and an access detection unit 246.
  • the inner code error correction monitoring unit 240 in the second embodiment is configured in the same manner as the inner code error correction monitoring unit 140 in the first embodiment except for the access detection unit 246 and the error correction bit addition unit 242.
  • the serial bus I / F unit 145 functions as a second interface unit that communicates with the overall error correction monitor unit 260.
  • the access detection unit 246 detects an access request from the overall error correction monitor unit 260 to the serial bus I / F unit 145. When the access detection unit 246 detects an access request, the access detection unit 246 notifies the error correction bit addition unit 242.
  • the error correction bit addition unit 242 stops adding the number of error correction bits indicated by the error correction information at the timing when the notification from the access detection unit 246 is received. Then, the error correction bit addition unit 242 stores the addition result in the register unit 144. Next, the error correction bit addition unit 242 clears the addition result to “0” and restarts the addition.
  • the addition result here is the number of bits corrected by the inner code error correction decoding unit 133 for each period in which an access request is made from the overall error correction monitor unit 260.
  • FIG. 11 is a block diagram schematically showing the configuration of the outer code error correction monitoring unit 250.
  • the outer code error correction monitor unit 250 includes a monitor I / F unit 151, an error correction bit addition unit 252, a register unit 154, a serial bus I / F unit 155, and an access detection unit 256.
  • Each unit of the outer code error correction monitor unit 250 performs the same processing as the corresponding unit of the inner code error correction monitor unit 240 shown in FIG.
  • the serial bus I / F unit 155 functions as a fourth interface unit that communicates with the overall error correction monitor unit 260.
  • the overall error correction monitoring unit 260 does not transmit the PM_SYNC signal in the second embodiment, unlike the first embodiment.
  • the overall error correction monitor unit 260 then issues an access request (first access request) to the inner code error correction monitor unit 240 via the third serial bus 172.
  • the serial bus I / F unit 145 transmits the calculation result stored in the register unit 144 to the overall error correction monitor unit 260.
  • the overall error correction monitor unit 260 makes an access request (second access request) to the outer code error correction monitor unit 250 through the fourth serial bus 173.
  • the serial bus I / F unit 155 transmits the calculation result stored in the register unit 154 to the overall error correction monitor unit 260.
  • the total error correction monitor unit 260 calculates the total number of error correction bits indicated by the error correction information by summing the read addition results.
  • register access from the overall error correction monitoring unit 260 to the inner code error correction monitoring unit 240 and the outer code error correction monitoring unit 250 must be performed simultaneously.
  • the inner code error correction monitor unit 240 is mounted inside the CFP-DCO optical transceiver, and the outer code error correction monitor unit 250 is installed on the side of the mother board on which the CFP-DCO optical transceiver is mounted. Therefore, the overall error correction monitor unit 260 can be accessed simultaneously by dividing the bus.
  • the optical communication system 300 includes an optical transmission device 310A and an optical transmission device 310B.
  • the two optical transmission apparatuses 310A and 310B are connected by the communication path 101.
  • an optical transmission apparatus 310 When it is not necessary to distinguish each of the optical transmission apparatuses 310A and 310B, they are referred to as an optical transmission apparatus 310.
  • FIG. 12 is a block diagram schematically showing a configuration of optical transmission apparatus 310 in the third embodiment.
  • the optical transmission device 310 includes a transmission unit 320 and a reception unit 330.
  • FIG. 13 is a block diagram schematically showing a configuration of transmission section 320 in the third embodiment.
  • the transmission unit 320 includes an OTU framer 321, an outer code error correction encoding unit 122, an inner code error correction encoding unit 123, an E / O conversion unit 124, and an integration start instruction adding unit 325.
  • Transmitting section 320 in the third embodiment is configured in the same manner as transmitting section 120 in the first embodiment except for OTU framer 321 and integration start instruction adding section 325.
  • the accumulation start instruction adding unit 325 periodically issues an instruction to the OTU framer 321 as an instruction to start accumulation of correction bits.
  • the OTU framer 321 performs the same processing as in the first embodiment, and receives an instruction from the integration start instruction adding unit 325 and adds an integration start instruction to the OTUk frame. For example, the OTU framer 321 assigns a monitor cycle bit 302d to the overhead unit 302a as in the OTUk frame 302 shown in FIG. “1 (High)” is inserted into 302d. The period can be indicated by the monitor period bit 302d.
  • FIG. 15 is a block diagram schematically showing a configuration of receiving section 330 in the third embodiment.
  • the reception unit 330 includes an O / E conversion unit 131, a frame synchronization unit 332, an inner code error correction decoding unit 133, an outer code error correction decoding unit 134, an OTU deframer 135, and an inner code error correction monitoring unit. 340, an outer code error correction monitor unit 350, an overall error correction monitor unit 360, and an integration start instruction unit 361.
  • the receiving unit 330 in the third embodiment is the same as that in the third embodiment except for the frame synchronization unit 332, the inner code error correction monitor unit 340, the outer code error correction monitor unit 350, the overall error correction monitor unit 360, and the integration start instruction unit 361. 1 is configured in the same manner as the first receiving unit 130.
  • the inner code error correction monitor unit 340 and the overall error correction monitor unit 360 are connected by the third serial bus 172, and unlike the first embodiment, the first control line 174 is used. Not.
  • the inner code error correction monitor unit 340 and the integration start instruction unit 361 are connected by a third control line 376.
  • the outer code error correction monitor unit 350 and the overall error correction monitor unit 360 are connected by the fourth serial bus 173, and unlike the first embodiment, the second control line 175 is not used.
  • the outer code error correction monitor unit 350 and the integration start instruction unit 361 are connected by a fourth control line 377. Furthermore, the integration start instruction unit 361 and the overall error correction monitor unit 360 are connected by a fifth control line 378.
  • the frame synchronization unit 332 performs the same processing as in the first embodiment, and detects whether or not an integration start instruction is included in the OTUk frame 302 included in the received signal. For example, the frame synchronization unit 332 detects the monitor cycle bit 302d assigned to the overhead unit 302a of the OTUk frame 302, confirms the value thereof, and starts integration when the value is “0 (Low)”. It is determined that no instruction is included, and if this value is “1”, it is determined that an integration start instruction is included. Then, when the OTUk frame 302 includes an integration start instruction, the frame synchronization unit 332 notifies the integration start instruction unit 361. In the third embodiment, the inner code error correction monitor unit 340 and the outer code error correction monitor unit 350 add the number of error correction bits in the cycle indicated by the monitor cycle bit 302d detected by the frame synchronization unit 332.
  • the integration start instruction unit 361 receives an inner code error correction monitor unit 340, an outer code error via the third control line 376, the fourth control line 377, and the fifth control line 378.
  • An integration start instruction signal which is a signal indicating an instruction, is sent to the correction monitor unit 350 and the overall error correction monitor unit 360.
  • the integration start instruction signal is, for example, a signal that outputs “1 (High)” at the timing of receiving an instruction from the frame synchronization unit 332 and then returns to “0 (Low)”. Since the OTUk frame 302 includes an integration start instruction periodically, the integration start instruction signal is also a signal that periodically outputs “1”, and can indicate the period.
  • FIG. 16 is a block diagram schematically showing the configuration of the inner code error correction monitoring unit 340.
  • the inner code error correction monitor unit 340 includes a monitor I / F unit 141, an error correction bit addition unit 342, a register unit 144, a serial bus I / F unit 145, and an integration start instruction signal detection unit 347.
  • the inner code error correction monitoring unit 340 in the third embodiment is configured in the same manner as the inner code error correction monitoring unit 140 in the first embodiment, except for the error correction bit adding unit 342 and the integration start instruction signal detecting unit 347. Yes.
  • the serial bus I / F unit 145 functions as a third interface unit.
  • the integration start instruction signal detection unit 347 functions as a first detection unit that detects an instruction from the integration start instruction unit 361.
  • the integration start instruction signal detection unit 347 receives the integration start instruction signal that is a periodic signal output from the integration start instruction unit 361 via the third control line 376 and transmits the integration start instruction signal to the error correction bit addition unit 342. .
  • the error correction bit addition unit 342 stops adding the number of error correction bits indicated by the error correction information at the timing of receiving the integration start instruction signal. For example, the error correction bit adding unit 342 stops the addition at a timing when the integration start instruction signal indicates “1”. Then, the error correction bit addition unit 342 stores the addition result in the register unit 144. Next, the error correction bit addition unit 342 clears the addition result to “0” and restarts the addition.
  • the addition result here is the number of bits corrected by the inner code error correction decoding unit 133 for each period indicated by the integration start instruction signal.
  • FIG. 17 is a block diagram schematically showing the configuration of the outer code error correction monitor unit 350.
  • the outer code error correction monitor unit 350 includes a monitor I / F unit 151, an error correction bit addition unit 352, a register unit 154, a serial bus I / F unit 155, and an integration start instruction signal detection unit 357.
  • Each unit of the outer code error correction monitor unit 350 performs the same processing as the corresponding unit of the inner code error correction monitor unit 340 shown in FIG.
  • error correction bit adder 352 functions as a second error correction bit adder
  • integration start instruction signal detector 357 functions as a second detector
  • serial bus I / F unit 155 It functions as a fourth interface unit.
  • the integration start instructing unit 361 transmits the integration start instruction signal to the inner code error correction monitoring unit 340 and the outer code error correction monitoring unit 350 at the same timing, so that the measurement cycle of the number of error bits of the inner code and the outer code is set. It becomes possible to adjust the timing. At this time, the signal wiring lengths of the integration start instruction unit 361 and the inner code error correction monitor unit 340 need to be the same as the signal wiring lengths of the integration start instruction unit 361 and the outer code error correction monitor unit 350.
  • the overall error correction monitor unit 360 reads the addition results stored in the register units 144 and 154 in the inner code error correction monitor unit 340 and the outer code error correction monitor unit 350 after the timing at which the integration start instruction signal is received. Then, the sum of the number of error correction bits indicated by the error correction information is calculated by adding the respective results.
  • Embodiment 3 since the addition results in the inner code error correction monitor unit 340 and the outer code error correction monitor unit 350 are held unless the monitoring period inserted by the OTU framer 321 of the transmission unit 320 is exceeded, The register access from the error correction monitor unit 360 to the inner code error correction monitor unit 340 and the outer code error correction monitor unit 350 need not be performed simultaneously with the timing at which the integration start instruction signal is received.
  • Embodiment 4 FIG.
  • systems for transmitting and receiving signals having a bit rate exceeding 400 Gbps are being developed.
  • the fourth embodiment assumes such a case.
  • the optical communication system 400 includes an optical transmission device 410A and an optical transmission device 410B.
  • the two optical transmission devices 410A and 410B are connected by the communication path 101.
  • an optical transmission apparatus 410 When it is not necessary to distinguish each of the optical transmission apparatuses 410A and 410B, they are referred to as an optical transmission apparatus 410.
  • FIG. 12 is a block diagram schematically showing the configuration of the optical transmission apparatus 410 according to the fourth embodiment.
  • the optical transmission device 410 includes a transmission unit 420 and a reception unit 430.
  • FIG. 18 is a block diagram schematically showing a configuration of transmission section 420 in the fourth embodiment.
  • the transmission unit 420 includes an OTU framer 121, a plurality of outer code error correction encoding units 422-1 to 422-m (m is an integer of 2 or more), and a plurality of inner code error correction encoding units 423-1 to 423-1 423-n (n is an integer of 2 or more), an E / O conversion unit 424, a first OTU frame switching unit 426, and a second OTU frame switching unit 427.
  • the OTU framer 121 of the transmission unit 420 in the fourth embodiment is configured similarly to the OTU framer 121 of the transmission unit 120 in the first embodiment.
  • the OTU framer 121 of the transmission unit 420 in the fourth embodiment provides the transmission signal to the first OTU frame switching unit 426. Further, when it is not necessary to particularly distinguish each of the plurality of outer code error correction encoding units 422-1 to 422-m, they are referred to as outer code error correction encoding units 422. When there is no need to particularly distinguish each of the plurality of inner code error correction encoding units 423-1 to 423-n, they are referred to as inner code error correction encoding units 423.
  • the first OTU frame switching unit 426 divides the transmission signal given from the OTU framer 121 into m pieces, and gives them to the outer code error correction coding unit 422 as the first divided transmission signals.
  • the outer code error correction encoding unit 422 encodes the divided transmission signal by adding the redundant bits corresponding to the first divided transmission signal as an information series. Then, the outer code error correction encoding unit 422 gives the encoded divided transmission signal (first divided encoded signal) to the second OTU frame switching unit 427.
  • the second OTU frame switching unit 427 synthesizes the encoded first divided coded signal given from the outer code error correction coding unit 422, divides it into n pieces, and uses the second divided transmission signal as an inner code error correction.
  • the data is supplied to the encoding unit 423.
  • the inner code error correction encoding unit 423 performs encoding by using the second divided transmission signal as an information series and adding redundant bits corresponding thereto.
  • the inner code error correction encoding unit 423 supplies the E / O conversion unit 424 with the divided transmission signal (second divided encoded signal) thus encoded.
  • the E / O converter 424 combines the error correction encoded transmission signal (second divided encoded signal), converts the combined electric signal into the optical signal OS, and transmits the optical signal OS to the communication path 101. To do.
  • FIG. 19 is a block diagram schematically showing a configuration of receiving section 430 in the fourth embodiment.
  • the reception unit 430 includes an O / E conversion unit 131, a frame synchronization unit 132, a plurality of inner code error correction decoding units 433-1 to 433-n, and a plurality of outer code error correction decoding units 434-1 to 434-1 434-m, an OTU deframer 435, a plurality of inner code error correction monitoring units 440-1 to 440-n, a plurality of outer code error correction monitoring units 450-1 to 450-m, and an overall error correction monitoring unit 460 And a third OTU frame switching unit 436 and a fourth OTU frame switching unit 437.
  • the O / E conversion unit 131 and the frame synchronization unit 132 of the reception unit 430 in the fourth embodiment are configured in the same manner as the O / E conversion unit 131 and the frame synchronization unit 132 of the reception unit 130 in the first embodiment.
  • frame synchronization section 132 in the fourth embodiment provides the received signal to third OTU frame switching section 436.
  • the outer code error correction decoding unit 434 is referred to.
  • inner code error correction monitoring units 440 When there is no need to particularly distinguish each of the plurality of inner code error correction monitoring units 440-1 to 440-n, they are referred to as inner code error correction monitoring units 440.
  • outer code error correction monitoring unit 450 When there is no need to particularly distinguish each of the plurality of outer code error correction monitoring units 450-1 to 450-m, it is referred to as an outer code error correction monitoring unit 450.
  • the third OTU frame switching unit 436 functions as a first dividing unit that divides the reception signal given from the frame synchronization unit 132 into n pieces and gives each to the inner code error correction decoding unit 433 as a divided reception signal.
  • the inner code error correction decoding unit 433 performs error correction decoding processing of the inner code of the divided reception signal, and gives the decoded divided reception signal (first division decoded signal) to the fourth OTU frame switching unit 437.
  • the fourth OTU frame switching unit 437 synthesizes the first divided decoded signal given from the inner code error correction decoding unit 433, divides it into m pieces, and outputs the second divided decoded signal as an outer code error correction decoding unit 434. It functions as a second division unit to be given to each.
  • Outer code error correction decoding section 434 further performs error correction decoding processing of the outer code on the second divided decoded signal given from fourth OTU frame switching section 437, and receives the decoded received signal (third divided signal). (Decoded signal) is applied to the OTU deframer 435.
  • the OTU deframer 435 combines the third divided decoded signal given from the outer code error correction decoding unit 434, deletes the overhead unit 102a and the error correction parity unit 102c of the OTUk frame 102 shown in FIG.
  • the signal stored in the payload part 102b is output as the client signal CS.
  • each of the plurality of inner code error correction decoding units 433-1 to 433-n and each of the plurality of inner code error correction monitoring units 440-1 to 440-n includes a plurality of first codes.
  • Each of the serial buses 470-1 to 470-n is connected. Note that the first serial buses 470 are referred to when the first serial buses 470-1 to 470-n do not need to be distinguished from each other.
  • the inner code error correction monitor unit 440 reads the error correction information indicating the number of correction bits of the FEC frame generated by the inner code error correction decoding unit 433 via the first serial bus 470. Then, the inner code error correction monitor unit 440 adds the number of correction bits indicated by the error correction information for each period. The overall error correction monitor unit 460 reads the addition result from the inner code error correction monitor unit 440 for each period.
  • the inner code error correction monitor unit 440 may be configured in the same manner as the inner code error correction monitor unit 140 in the first embodiment, and is configured in the same manner as the inner code error correction monitor unit 240 in the second embodiment. Also good.
  • the inner code error correction monitor unit 440 is configured in the same manner as the inner code error correction monitor unit 140 of the first embodiment, the inner code error correction monitor unit 440 and the overall error correction monitor unit 460 are the same as those in the first embodiment. 1 is connected in the same way as the inner code error correction monitor unit 140 and the entire error correction monitor unit 160 in FIG. 1, and the entire error correction monitor unit 460 is a process similar to that of the entire error correction monitor unit 160 in the first embodiment.
  • the addition result is read from the code error correction monitor unit 440.
  • the inner code error correction monitor unit 440 When the inner code error correction monitor unit 440 is configured in the same manner as the inner code error correction monitor unit 240 of the second embodiment, the inner code error correction monitor unit 440 and the entire error correction monitor unit 460 are the same as those in the embodiment. 2 is connected in the same way as the inner code error correction monitor unit 240 and the entire error correction monitor unit 260 in FIG. 2, and the entire error correction monitor unit 460 is the same process as the entire error correction monitor unit 260 in the second embodiment. The addition result is read from the code error correction monitor unit 440.
  • each of the plurality of outer code error correction decoding units 434-1 to 434-m and each of the plurality of outer code error correction monitoring units 450-1 to 450-m includes a plurality of second codes.
  • Each of the serial buses 471-1 to 471-m is connected. Note that the second serial buses 471-1 to 471-m are referred to as second serial buses 471 when it is not necessary to distinguish them.
  • the outer code error correction monitor unit 450 reads error correction information indicating the number of correction bits of the FEC frame generated by the outer code error correction decoding unit 434 via the second serial bus 471.
  • the outer code error correction monitor unit 450 adds the number of correction bits indicated by the error correction information for each period.
  • Overall error correction monitor section 460 reads the addition result from outer code error correction monitor section 450 for each period.
  • Outer code error correction monitor section 450 may be configured in the same manner as outer code error correction monitor section 150 in the first embodiment, and is configured in the same manner as outer code error correction monitor section 250 in the second embodiment. Also good.
  • the outer code error correction monitor unit 450 is configured similarly to the outer code error correction monitor unit 150 of the first embodiment, the outer code error correction monitor unit 450 and the overall error correction monitor unit 460 are the same as those of the first embodiment. 1 are connected in the same manner as the outer code error correction monitoring unit 150 and the entire error correction monitoring unit 160 in FIG. 1, and the entire error correction monitoring unit 460 is a process similar to that of the entire error correction monitoring unit 160 in the first embodiment.
  • the addition result is read from the code error correction monitor unit 450.
  • the outer code error correction monitor unit 450 When the outer code error correction monitor unit 450 is configured in the same manner as the outer code error correction monitor unit 250 of the second embodiment, the outer code error correction monitor unit 450 and the overall error correction monitor unit 460 are the same as those of the second embodiment. 2 is connected in the same manner as the outer code error correction monitoring unit 250 and the entire error correction monitoring unit 260 in FIG. 2, and the entire error correction monitoring unit 460 is a process similar to that of the entire error correction monitoring unit 260 in the second embodiment. The addition result is read from the code error correction monitor unit 450.
  • the total error correction monitor unit 460 adds the addition results read from the inner code error correction monitor unit 440 and the outer code error correction monitor unit 450, thereby calculating the total number of error correction bits indicated by the error correction information. .
  • Each of 1 to 440-n and each of the plurality of outer code error correction monitoring units 450-1 to 450-m do not need to be mounted on one LSI, and the plurality of parts are integrated into one LSI. May be implemented.

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Optical Communication System (AREA)

Abstract

La présente invention comprend : une unité de décodage de correction d'erreurs de code interne (133) qui génère un premier signal décodé, pour chaque trame unitaire, par exécution d'un décodage d'erreurs d'un code interne par rapport à un signal reçu, et qui compte le nombre de premiers bits à erreurs corrigées qui est le nombre de bits pour lesquels une erreur a été corrigée, pour chaque trame unitaire; une unité de décodage de correction d'erreurs de code externe (134) qui génère un second signal décodé, pour chaque trame unitaire, par exécution d'un décodage d'erreurs d'un code externe par rapport au premier signal décodé, et qui compte le nombre de seconds bits à erreurs corrigées, qui est le nombre de bits pour lesquels une erreur a été corrigée, pour chaque trame unitaire; une unité de surveillance de correction d'erreurs de code interne (140) qui calcule une première valeur d'addition en ajoutant le nombre de premiers bits à erreurs corrigées pour chaque cycle; une unité de surveillance de correction d'erreurs de code externe (150) qui calcule une seconde valeur d'addition en ajoutant le nombre de seconds bits à erreurs corrigées pour chacun des cycles; une unité de surveillance de correction d'erreurs globale (160) qui calcule le nombre total de bits à erreurs corrigées, pour chacun des cycles, en totalisant la première valeur d'addition et la seconde valeur d'addition.
PCT/JP2017/000074 2017-01-05 2017-01-05 Appareil de transmission optique Ceased WO2018127950A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001358597A (ja) * 2000-06-09 2001-12-26 Hitachi Ltd エラー訂正符号の構成方法、復号方法、伝送装置、ネットワーク
JP5586448B2 (ja) * 2010-12-20 2014-09-10 三菱電機株式会社 光伝送装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001358597A (ja) * 2000-06-09 2001-12-26 Hitachi Ltd エラー訂正符号の構成方法、復号方法、伝送装置、ネットワーク
JP5586448B2 (ja) * 2010-12-20 2014-09-10 三菱電機株式会社 光伝送装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CFP MSA MANAGEMENT INTERFACE SPECIFICATION 100/40 GIGABIT TRANSCEIVER PACKAGE MULTI-SOURCE AGREEMENT, 1 July 2013 (2013-07-01), pages 112 - 113, XP055613020 *

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