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WO2018126542A1 - Structure pop ( boîtier sur boîtier) et borne - Google Patents

Structure pop ( boîtier sur boîtier) et borne Download PDF

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Publication number
WO2018126542A1
WO2018126542A1 PCT/CN2017/078636 CN2017078636W WO2018126542A1 WO 2018126542 A1 WO2018126542 A1 WO 2018126542A1 CN 2017078636 W CN2017078636 W CN 2017078636W WO 2018126542 A1 WO2018126542 A1 WO 2018126542A1
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WO
WIPO (PCT)
Prior art keywords
layer
potting
encapsulation layer
silicon wafer
package
Prior art date
Application number
PCT/CN2017/078636
Other languages
English (en)
Chinese (zh)
Inventor
史洪宾
叶润清
龙浩晖
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201780018241.0A priority Critical patent/CN108780790B/zh
Publication of WO2018126542A1 publication Critical patent/WO2018126542A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present application relates to the field of electronic devices, and in particular, to a stacked package structure and a terminal.
  • PoP stack on package
  • underfill materials are widely used to protect board-level solder joints.
  • a liquid underfill material is applied to the periphery of the component to be dispensed by injection or spraying, and then penetrates between the component to be dispensed and the main board by capillary flow, and finally heated or ultraviolet (ultraviolet, UV ) curing under conditions.
  • Underfill material can distribute the mechanical stress and thermal stress originally concentrated on the corner solder joints of the component to all solder joints relatively evenly, thereby improving the overall reliability of the PoP.
  • the present application provides a stacked package structure and a terminal for solving the problem of complete filling or easy partial filling between two adjacent packaging layers in the prior art, and improving the reliability of the stacked package structure.
  • the present application provides a stacked package structure including a main board and at least two encapsulation layers stacked in a direction away from the main board, wherein
  • An encapsulation layer of the at least two encapsulation layers closest to a side of the main board is soldered to the main board;
  • the encapsulation layer adjacent to the side of the main board of any two adjacent encapsulation layers is a lower encapsulation layer, and the encapsulation layer away from the side of the main board is an upper encapsulation layer, and the lower encapsulation layer is soldered to the upper encapsulation layer ;
  • a first potting layer is further disposed between the lower encapsulating layer and the upper encapsulating layer, and a first potting area corresponding to the first potting layer is disposed in the lower encapsulating layer, and the The first potting zone does not overlap the upper encapsulating layer.
  • the lower encapsulation layer is provided with a first potting zone, and the first potting zone does not overlap with the upper encapsulation layer, and when the stacking package structure is dispensed, Taking any two adjacent encapsulation layers as one structural unit, respectively, the lower encapsulation layer in each structural unit is separately dispensed, that is, the dispensing material is dropped into the first potting area by using a dispensing tool, and the dispensing material is The first potting zone penetrates into the gap between the lower encapsulating layer and the upper encapsulating layer, and after the filling is sufficiently filled, the dispensing is stopped, and the dispensing material is solidified to form a first potting layer; thus, any adjacent two encapsulating layers The complete filling can be achieved between the two, which solves the problem that the top and bottom encapsulation layers are completely filled or easily partially filled in the prior art.
  • the stacked package structure protects the solder joint between the lower package layer and the upper package layer under load such as drop impact, bending and temperature cycling, so that the mechanical stress concentrated on the edge solder joint It is distributed relatively evenly on all solder joints with thermal stress, preventing the failure of high stress solder joints at the edges and improving the reliability of the structure.
  • the reliability of the stacked package structure is further improved.
  • the encapsulation layer of the at least two encapsulation layers closest to the side of the main board a second potting layer is further disposed between the main boards, the second potting area corresponding to the second potting layer is disposed on the main board, and the second potting area and the at least two The encapsulation layers do not overlap.
  • an orthographic projection of the upper encapsulation layer on a plane of the lower encapsulation layer is located in the lower encapsulation layer.
  • the lower encapsulation layer is a polygon, and at least one of the lower encapsulation layers is provided with the first potting zone.
  • the setting of the first potting zone comprises a plurality of forms, and in the specific setting, when at least two sides of the lower encapsulating layer are provided with the first potting zone, the at least two A glue filling area is not connected to each other.
  • the at least two first potting zones are connected to form a whole.
  • At least two first potting zones are connected to form a plurality of shapes. Specifically, when the first potting zone is disposed on each side of the lower encapsulating layer, the first irrigation provided on each side The glue zones are connected to each other to form a frame shape.
  • the three first potting zones are connected to form a whole.
  • the above various embodiments are also applicable to the arrangement between the silicon wafer and the silicon wafer in the encapsulation layer and the arrangement between the silicon wafer and the substrate.
  • the encapsulation layer includes the substrate and is away from the At least two silicon wafers stacked in a direction of the substrate, wherein
  • One of the at least two silicon wafers closest to the side of the substrate is soldered to the substrate;
  • the silicon wafer adjacent to one side of the substrate of any two adjacent silicon wafers is a lower silicon wafer, and the silicon wafer away from one side of the substrate is an upper silicon wafer, and the lower silicon wafer is soldered to the upper silicon wafer.
  • a third potting layer is further disposed between the lower silicon wafer and the upper silicon wafer;
  • a third potting layer is further disposed between the lower layer silicon wafer and the upper layer silicon wafer, and the lower layer silicon wafer is provided with the third potting layer Corresponding third potting zone, and the third potting zone does not overlap with the upper silicon wafer.
  • any two adjacent silicon wafers can be completely filled with the dispensing material during dispensing, preventing solder joint breakage between the silicon wafers, and improving the reliability of the stacked package structure.
  • the reliability of the stacked package structure is further improved, and in a specific arrangement, the silicon wafer closest to the side of the substrate among the at least two silicon wafers a fourth potting layer is further disposed between the substrate, and the fourth potting zone corresponding to the fourth potting layer is disposed on the substrate, and the fourth The potting zone does not overlap with the at least two silicon wafers.
  • the third silicon filling region is disposed on the lower silicon wafer.
  • the orthographic projection of the upper silicon wafer on the plane of the lower silicon wafer is located in the lower silicon wafer.
  • the lower silicon wafer is polygonal, and at least one of the lower silicon wafers is provided with a third potting zone.
  • the at least two third potting zones are not connected to each other, or the at least two third potting zones are Connected to form a whole.
  • the embodiment of the present application further provides a terminal, including the foregoing stacked package structure.
  • any two adjacent encapsulating layers can be completely filled with the dispensing material when dispensing, and any adjacent two silicon wafers in each encapsulating layer can also be dispensed. It is completely filled with the dispensing material to prevent the solder joint between the package layers and the solder joint breakage between the silicon wafers, thereby improving the quality and reliability of the terminal.
  • 1a is a schematic diagram of a stacked package structure according to an embodiment of the present application.
  • FIG. 1b is a schematic diagram of another stacked package structure according to an embodiment of the present application.
  • FIG. 2a is a top view of a single-sided dispensing package layer according to Embodiment 1 of the present application;
  • Figure 2b is a front view of the encapsulation layer of the single-sided dispensing of Figure 2a;
  • Figure 2c is a left side view of the encapsulation layer of the single-sided dispensing of Figure 2a;
  • 3a is a top view of a portion of a single-sided dispensing package provided in Embodiment 1 of the present application;
  • Figure 3b is a front view of the encapsulation layer of a portion of the single-sided dispensing of Figure 3a;
  • Figure 3c is a left side view of the encapsulation layer of a portion of the single-sided dispensing of Figure 3a;
  • FIG. 4a is a top view of an encapsulation layer of a double-sided dispensing provided in Embodiment 2 of the present application;
  • Figure 4b is a front view of the encapsulation layer of the double-sided dispensing of Figure 4a;
  • Figure 4c is a left side view of the encapsulation layer of the double-sided dispensing in Figure 4a;
  • 5a is a top view of a portion of a double-sided dispensing package provided in Embodiment 2 of the present application;
  • Figure 5b is a front view of the encapsulation layer of a portion of the double-sided dispensing of Figure 5a;
  • Figure 5c is a left side view of the encapsulation layer of a portion of the double-sided dispensing of Figure 5a;
  • 6a is a top view of a package layer of a frame-shaped four-sided dispensing provided in Embodiment 3 of the present application;
  • Figure 6b is a front view of the encapsulation layer of the frame-shaped four-sided dispensing of Figure 6a;
  • Figure 6c is a left side view of the encapsulation layer of the frame-shaped four-sided dispensing of Figure 6a;
  • FIG. 7a is a top view of an L-shaped double-sided dispensing encapsulation layer according to Embodiment 4 of the present application.
  • Figure 7b is a front view of the encapsulation layer of the L-shaped double-sided dispensing of Figure 7a;
  • Figure 7c is a left side view of the encapsulation layer of the L-shaped double-sided dispensing in Figure 7a;
  • FIG. 8a is a top view of a portion of an L-shaped double-sided dispensing package provided in Embodiment 4 of the present application;
  • Figure 8b is a front view of the encapsulation layer of the partial L-shaped double-sided dispensing of Figure 8a;
  • Figure 8c is a left side view of the encapsulation layer of a portion of the L-shaped double-sided dispensing of Figure 8a;
  • FIG. 9a is a top view of another partial L-shaped double-sided dispensing encapsulation layer according to Embodiment 4 of the present application.
  • Figure 9b is a front view of the encapsulation layer of the partial L-shaped double-sided dispensing of Figure 9a;
  • Figure 9c is a left side view of the encapsulation layer of the partial L-shaped double-sided dispensing of Figure 9a;
  • 10a is a top view of a package layer of a U-shaped three-sided dispensing provided in Embodiment 5 of the present application;
  • Figure 10b is a front view of the encapsulation layer of the U-shaped three-sided dispensing of Figure 10a;
  • Figure 10c is a left side view of the encapsulation layer of the U-shaped three-sided dispensing of Figure 10a;
  • FIG. 11 is a schematic structural diagram of an encapsulation layer according to Embodiment 6 of the present application.
  • FIG. 11b is a schematic structural diagram of another encapsulation layer according to Embodiment 6 of the present application.
  • FIG. 12 is a schematic structural diagram of an encapsulation layer according to Embodiment 7 of the present application.
  • FIG. 12b is a schematic structural diagram of another encapsulation layer according to Embodiment 7 of the present application.
  • the embodiment of the present application provides a stacked package structure for solving the problem that it is difficult to completely fill or easily partially fill between the lower package layer and the upper package layer in the prior art.
  • the stacked package structure includes a motherboard and is far away. At least two encapsulation layers are stacked in the direction of the main board, wherein
  • the encapsulation layer of the at least two encapsulation layers closest to the side of the main board is soldered to the main board;
  • the encapsulation layer adjacent to the motherboard side of any two adjacent encapsulation layers is a lower encapsulation layer, and the encapsulation layer away from the main board side is an upper encapsulation layer, and the lower encapsulation layer is soldered to the upper encapsulation layer;
  • a first potting layer is further disposed between the lower encapsulating layer and the upper encapsulating layer, and a first potting area corresponding to the first potting layer is disposed in the lower encapsulating layer, and the first potting area and the upper encapsulating layer are not overlapping.
  • the first potting layer is formed by solidifying and coagulating the liquid dispensing material, and the first potting area is a liquid dispensing material that is dropped on the lower encapsulating layer, and the stacked encapsulating structure shown in FIG.
  • the first potting zone is a region in which the lower encapsulating layer is exposed outside the upper encapsulating layer, that is, a portion of the lower encapsulating layer that extends to the outside of the upper encapsulating layer is the first potting zone, or
  • the upper encapsulation layer is recessed inwardly at a position on the side to form a notch, and the portion corresponding to the notch in the lower encapsulation layer is the first potting area; when dispensing, the dispensing material is dropped on the dispensing material In the first potting zone, according to the principle of capillary flow, the dispensing material penetrates from the first potting zone into the gap between the lower encapsulating layer and the upper encapsulating layer, thereby filling the adjacent two encapsulating layers.
  • the dispensing tool In order to speed up the filling speed of the dispensing material, the dispensing tool is moved in the first filling zone to widen the flow channel of the dispensing material, and the dispensing gap is stopped after the gap between the upper and lower packaging layers is completely filled, and the dispensing material is In heating or ultraviolet (ultraviolet, The first potting layer is formed after curing under UV conditions.
  • any two adjacent package layers are used as one structural unit, and the lower package layer in each structural unit is separately dispensed, and the first potting layer is formed after the dispensing material is solidified, and the solution is solved.
  • the adjacent two structural units share one encapsulation layer, that is, in the stacked package structure, the encapsulation layer located in the middle serves as both the upper encapsulation layer of one structural unit and the lower encapsulation layer of another structural unit.
  • the package layer on the middle portion has a first potting area except for the package layers located at the uppermost end and the lowermost end.
  • the first potting zone is located on the same side, forming a step-like structure, so that when dispensing, Dispense sequentially from bottom to top (or top to bottom) to facilitate the entire dispensing operation.
  • the encapsulation layer of the at least two encapsulation layers adjacent to the main board side is soldered to the main board, and at least two encapsulation layers a second potting layer is disposed between the encapsulating layer on the side of the main board and the main board, and the second potting area corresponding to the second potting layer is disposed on the main board, and the second potting area and the at least two packages are
  • the layers do not overlap; the second potting layer is also formed by solidifying the liquid dispensing material, and the second potting area is a liquid dispensing material that is dropped on the main board.
  • the area of the main board is much larger than that of the encapsulating layer. Area, and there are multiple components on the main board.
  • a second potting area is set on the area of the main board near the edge of the encapsulation layer; when dispensing, the dispensing material is dropped on the main board.
  • the dispensing material is infiltrated into the gap between the main board and the encapsulating layer near the side of the main board by the second potting area, and the dispensing material stops the dispensing after the gap is completely filled.
  • a second potting layer is formed.
  • the adjacent two first potting layers and the first potting layer and the second potting layer are integrated, and
  • the tension of the surface of the rubber material, the entire potting layer has a trapezoid Along.
  • the second potting layer distributes the mechanical stress and thermal stress concentrated on the edge solder joints relatively uniformly over all the solder joints, preventing the encapsulation layer and the main board.
  • the high stress solder joint breaks between failures.
  • the stacked package structure includes a main board 10 and two encapsulation layers stacked in a direction away from the main board 10.
  • the encapsulation layer on the side close to the main board 10 is referred to as a lower encapsulation layer 20, away from the side of the main board 10.
  • the encapsulation layer is referred to as the upper encapsulation layer 30, and the lower encapsulation layer 20 is soldered to the upper encapsulation layer 30.
  • the lower encapsulation layer 20 and the upper encapsulation layer 30 are soldered by a reflow soldering process, and the lower encapsulation layer 20 and the upper encapsulation layer are A plurality of solder joints 60 are formed between 30, and a plurality of solder joints 60 are formed in a frame shape.
  • the lower package layer 20 is soldered to the main board 10 and can also be soldered by a reflow soldering process.
  • a first potting layer 40 is disposed between the lower encapsulating layer 20 and the upper encapsulating layer 30, and a first potting area 21 corresponding to the first potting layer 40 is disposed in the lower encapsulating layer 20,
  • the first potting zone 21 and the upper encapsulating layer 30 do not overlap.
  • the first potting zone 21 is located in a region surrounded by a circle on the lower encapsulation layer 20.
  • the orthographic projection of the upper encapsulation layer 30 on the plane of the lower encapsulation layer 20 is located in the lower encapsulation layer 20, and it can be understood that the projection of the frame of the upper encapsulation layer 30 is completely within the frame of the lower encapsulation layer 20, or the upper encapsulation layer 30.
  • the projection of the frame overlaps with the frame portion of the lower encapsulation layer 20, wherein the first potting area 21 is an area between the frame projection of the upper encapsulation layer 30 and the bezel of the lower encapsulation layer 20; or, as shown in FIG. 1b,
  • the orthographic projection portion of the encapsulation layer 30 on the plane of the lower encapsulation layer 20 is located in the lower encapsulation layer 20.
  • the upper encapsulation layer 30 is shifted to the right in the horizontal direction, and the lower encapsulation layer 20 is exposed on the upper encapsulation layer.
  • the outer portion of the 30 is set as the first potting zone 21.
  • the lower encapsulation layer 20 is a polygon, and at least one side of the lower encapsulation layer 20 is provided with a first potting area 21, wherein the setting of the first potting area 21 includes various forms, Several specific embodiments are described in detail.
  • the lower encapsulation layer 20 is polygonal, and only one side of the lower encapsulation layer 20 is provided with a first potting area.
  • FIG. 2a to FIG. 2c wherein FIG. 2a is a top view when the upper encapsulation layer 30 and the lower encapsulation layer 20 are stacked, FIG. 2b is a front view thereof, and FIG. 2c is a left side view thereof.
  • the upper package layer 30 and the lower package layer 20 are both rectangular, one side of the upper package layer 30 and one side of the lower package layer 20 are equal in length, and the area of the upper package layer 30 is smaller than the lower package.
  • the area of layer 20 is polygonal, and only one side of the lower encapsulation layer 20 is provided with a first potting area.
  • the upper package layer 30 is aligned with the equal length sides of the lower package layer 20, such that one side of the lower package layer 20 will extend to the outside of the upper package layer 30, and the lower package layer 20 is extended to the lower package layer 20
  • the portion outside the upper encapsulation layer 30 is set as the first potting zone 21a, and as shown in FIG. 2a, the first potting zone 21a is disposed on the entire area of the side of the lower encapsulation layer 20.
  • FIG. 3a to FIG. 3c wherein FIG. 3a is a top view when the upper encapsulation layer 30 and the lower encapsulation layer 20 are stacked, FIG. 3b is a front view thereof, and FIG. 3c is a left side thereof.
  • the upper package layer 30 and the lower package layer 20 are rectangular of the same size, but one side of the upper package layer 30 is provided with a notch, and when the package is packaged, the upper package layer 30 and the lower package layer are provided.
  • the four end angles of 20 are aligned, and a portion of the lower encapsulation layer 20 corresponding to the notch of the upper encapsulation layer 30 is set as the first potting area 21b, and the first potting area 21b is disposed on a partial area of the side of the lower encapsulation layer 20.
  • the notch on the upper encapsulation layer 30 is rectangular, and correspondingly, the first potting area 21b on the lower encapsulation layer 20 is also rectangular.
  • the lower encapsulation layer 20 is polygonal, and at least two sides of the lower encapsulation layer 20 are provided with a first potting zone, and at least two first potting zones are disposed that are not in communication with each other.
  • FIG. 4a to FIG. 4c wherein FIG. 4a is a top view when the upper encapsulation layer 30 and the lower encapsulation layer 20 are stacked, FIG. 4b is a front view thereof, and FIG. 4c is a left side view thereof.
  • the upper package layer 30 and the lower package layer 20 are both rectangular, one side of the upper package layer 30 and one side of the lower package layer 20 are equal in length, and the area of the upper package layer 30 is smaller than the lower package.
  • the area of the layer 20 is such that the upper package layer 30 and the lower package layer 20 are vertically aligned while the package is stacked, and the sides of the upper package layer 30 are kept parallel to the sides of the lower package layer 20, so that the lower package layer There are two opposite sides of the opposite arrangement, and the two sides will extend to the outside of the upper package layer 30, and then the portions of the lower package layer 20 that are extended to the outside of the upper package layer 30 are respectively set as the first glue filling area 21c, as shown in the figure. As shown in 4a, each of the first potting zones 21c is disposed over the entire area of the side of the lower encapsulation layer 20.
  • FIG. 5a to FIG. 5c wherein FIG. 5a is a top view when the upper encapsulation layer 30 and the lower encapsulation layer 20 are stacked, FIG. 5b is a front view thereof, and FIG. 5c is a left side thereof.
  • the upper encapsulation layer 30 and the lower encapsulation layer 20 are rectangular of the same size, but the upper encapsulation layer 30 is respectively provided with a notch on the opposite sides, and when the package is packaged, the upper encapsulation layer 30 is provided.
  • the portions of the lower encapsulation layer 20 corresponding to the two notches of the upper encapsulation layer 30 are respectively set as the first potting area 21d, and each of the first potting areas 21d is disposed under
  • the two notches on the upper encapsulation layer 30 are rectangular, and correspondingly, the two first encapsulation areas 21d on the lower encapsulation layer 20 are also rectangular.
  • the lower encapsulation layer 20 is a polygonal shape.
  • the first potting zones provided on each side are connected to each other to form a frame shape.
  • FIG. 6a to FIG. 6c wherein FIG. 6a is a top view when the upper encapsulation layer 30 and the lower encapsulation layer 20 are stacked, FIG. 6b is a front view thereof, and FIG. 6c is a left side view thereof.
  • the upper package layer 30 and the lower package layer 20 are both rectangular, and the length and width of the upper package layer 30 are smaller than the length and width of the lower package layer 20, and when the package is packaged, the upper package layer 30 is
  • the center of the lower encapsulation layer 20 is vertically aligned, while the sides of the upper encapsulation layer 30 are kept parallel to the sides of the lower encapsulation layer 20, such that each side of the lower encapsulation layer 20 will extend to the outside of the upper encapsulation layer 30.
  • the portions of each of the lower encapsulation layers 20 that are extended to the outside of the upper encapsulation layer 30 are respectively set as the first potting regions 21e. As shown in FIG. 6a, the four first potting regions 21e are connected to each other to form a frame shape.
  • the lower encapsulation layer 20 is a polygon. When two adjacent sides of the lower encapsulation layer 20 are respectively provided with the first potting area, the two first potting areas are connected to form a whole.
  • FIG. 7a to FIG. 7c wherein FIG. 7a is a top view when the upper encapsulation layer 30 and the lower encapsulation layer 20 are stacked, FIG. 7b is a front view thereof, and FIG. 7c is a left side view thereof.
  • the upper package layer 30 and the lower package layer 20 are both rectangular, and the length and width of the upper package layer 30 are smaller than the length and width of the lower package layer 20, and when the package is packaged, the upper package layer 30 is One end angle is aligned with one end corner of the lower encapsulation layer 20 such that adjacent sides of the lower encapsulation layer 20 will extend to the upper encapsulation layer 30.
  • the portions of the lower encapsulation layer 20 that are extended to the outside of the upper encapsulation layer 30 are respectively set as the first potting area 21f. As shown in FIG. 7a, each of the first potting areas 21f is set. On the entire area of the side of the lower encapsulation layer 20, the two first potting zones 21f are connected to form an L shape.
  • FIG. 8a to FIG. 8c wherein FIG. 5a is a top view when the upper encapsulation layer 30 and the lower encapsulation layer 20 are stacked, FIG. 8b is a front view thereof, and FIG. 8c is a left side thereof.
  • the upper encapsulation layer 30 and the lower encapsulation layer 20 are rectangular of the same size, but the upper encapsulation layer 30 is provided with an L-shaped notch at one end corner, and the other encapsulation layer 30 is laminated when the package is packaged.
  • the three end angles are respectively aligned with the three end angles of the lower encapsulation layer 20, and the portion of the lower encapsulation layer 20 corresponding to the L-shaped notch of the upper encapsulation layer 30 is set as the first potting area 21g, as shown in FIG. 8a, under A first potting zone 21g is respectively disposed on a portion of the adjacent sides of the encapsulating layer 20, and the two first potting zones 21g are connected to form an L shape.
  • FIG. 9a is a top view when the upper encapsulation layer 30 and the lower encapsulation layer 20 are stacked
  • FIG. 9b is a front view thereof
  • FIG. 9c is a left side view thereof.
  • the upper encapsulation layer 30 and the lower encapsulation layer 20 are rectangular of the same size, but the lower encapsulation layer 20 is outwardly expanded at one end corner, and the other three end angles of the lower encapsulation layer 20 and the upper encapsulation layer 30 are laminated when the package is packaged.
  • the three end corners are respectively aligned, and the portion of the lower encapsulation layer 20 that extends outward at the corners is set as the first potting zone 21h.
  • the first potting zone 21h is L-shaped.
  • the lower encapsulation layer 20 is a polygon. When one side of the lower encapsulation layer 20 and two sides adjacent thereto are respectively provided with the first potting area, the three first potting areas are connected to form a whole.
  • FIG. 10a to FIG. 10c wherein FIG. 10a is a top view when the upper encapsulation layer 30 and the lower encapsulation layer 20 are stacked, FIG. 10b is a front view thereof, and FIG. 10c is a left side view thereof.
  • the upper package layer 30 and the lower package layer 20 are both rectangular, and the length and width of the upper package layer 30 are smaller than the length and width of the lower package layer 20, and when the package is packaged, the upper package layer 30 is One side is aligned with one side of the lower encapsulation layer 20, but the end points do not coincide.
  • the lower encapsulation layer 20 will have three sides extending to the outside of the upper encapsulation layer 30, and then the three sides of the lower encapsulation layer 20 are extended to The portions outside the upper encapsulation layer 30 are respectively set as the first potting zone 21i, as shown in FIG. 10a, each of the first potting zones 21i is disposed on the entire area of the side, and three first potting zones 21i communicates to form a U shape.
  • Embodiments 1 to 5 describe the arrangement of the upper encapsulation layer 30, the lower encapsulation layer 20, and the first potting area 21 in detail, and the upper encapsulation layer 30 and the lower encapsulation layer can be adjusted according to the development of the dispensing technology level.
  • the difference in size of 20 makes the width of the first potting zone set to meet the dispensing requirements.
  • the width of the first potting zone can be set to 0.5 mm. It should be noted that any solution that adjusts the size and shape of the upper encapsulation layer 30 and the lower encapsulation layer 20 to form a first encapsulation region on the lower encapsulation layer 20 that does not overlap with the upper encapsulation layer 30 belongs to the protection scope of the present application.
  • a second potting layer 50 is disposed between the lower encapsulating layer 20 and the main board 10, and a second potting area corresponding to the second potting layer 50 is disposed on the main board 10, and the second potting area is compared.
  • the area of the main board is much larger than the area of the encapsulation layer, and the second filling area can be set in any area on the main board near the edge of the lower encapsulation layer 20, which will not be described in detail herein.
  • the dispensing material is dropped into the first potting area 21 on the lower encapsulation layer 20.
  • the dispensing material will be filled by the first potting material.
  • the region penetrates into the gap between the lower encapsulation layer 20 and the upper encapsulation layer 30.
  • the dispensing tool is moved in the first potting zone 21 to widen the flow channel of the dispensing material.
  • the dispensing is stopped, the dispensing material is cured to form the first potting layer 40; secondly, the dispensing material is dropped on the second potting area on the main board 10, and the dispensing material is The second potting zone penetrates into the gap between the encapsulating layer 20 and the main board 10. After the dispensing material is sufficiently filled in the gap, the dispensing is stopped, and the dispensing material is cured to form the second potting layer 50.
  • the first potting layer 40 and the second filling The glue layers 50 are integrally connected, and the entire potting layer has a trapezoidal edge due to the tension of the surface of the dispensing material, and the entire potting layer is opposite to the solder joint 60 between the lower encapsulation layer 20 and the upper encapsulation layer 30 and the lower package.
  • the solder joint 60 between the layer 20 and the main plate 10 serves to protect the mechanical stress and thermal stress concentrated on the edge solder joint 60 from being uniformly distributed under all loads such as drop impact, bending and temperature cycling. At point 60, the high stress solder joint 60 of the edge is prevented from failing.
  • dispensing between the lower encapsulation layer 20 and the upper encapsulation layer 30 and between the lower encapsulation layer 20 and the main board 10 respectively ensures that the dispensing material can be completely filled in both spaces, improving the stacking.
  • the area of the forbidden area of the adhesive sensitive component improves the layout flexibility of the motherboard 10, and eliminates the plate vibration, fine pitch component dendrites, and WLCSP (Wafer Level Chip Scale Package) environment associated with the overflow.
  • the heat dissipation channel from the application processor to the memory is mainly located at the solder joint 60 and the dispensing material portion.
  • a filled area and in the present application, the dispensing material is completely filled between the upper encapsulation layer 30 and the lower encapsulation layer 20, the solder joint 60 between the upper encapsulation layer 30 and the lower encapsulation layer 20, and the first potting layer 40 whole Area can be used for cooling, the cooling channel widening from the application processor to the memory, to improve the heat dissipation effect of the stack package, in particular the use of dispensing a material of high thermal conductivity.
  • each encapsulation layer includes a substrate 70 and at least two silicon wafers stacked in a direction away from the substrate 70, wherein any adjacent two silicon wafers are adjacent to the substrate.
  • the silicon wafer on one side is the lower silicon wafer
  • the silicon wafer on the side away from the substrate 70 is the upper silicon wafer
  • the lower silicon wafer is soldered to the upper silicon wafer
  • the third silicon filler is also provided between the lower silicon wafer and the upper silicon wafer.
  • the layer 101; at least one pair of two adjacent silicon wafers, the lower layer of silicon wafer is provided with a third potting zone 103 corresponding to the third potting layer 101, and the third potting zone 103 does not overlap with the upper layer of silicon wafers.
  • the third potting zone 103 is located in a region surrounded by a circle on the lower silicon wafer.
  • the third potting layer 101 is formed by solidifying and coagulating the liquid dispensing material, and the third potting area 103 is a region in which the liquid dispensing material drops on the lower silicon wafer.
  • a third potting zone 103 is disposed on a portion of the lower silicon wafer that is extended to the outside of the upper silicon wafer, or the upper silicon wafer is recessed inward at a position on the side to form a gap, and in the lower silicon wafer The portion corresponding to the notch is provided with a third potting zone 103.
  • an encapsulation layer having four silicon wafers will be described in detail below as an example.
  • the encapsulation layer comprises a substrate 70 and four silicon wafers, and four silicon wafers are stacked in a direction away from the substrate 70, and a plastic encapsulation layer 90 is disposed on the outer side of the silicon wafer.
  • the reference is made in a direction away from the substrate 70.
  • the silicon wafers are sequentially referred to as the first silicon wafer 81, the second silicon wafer 82, the third silicon wafer 83, and the fourth silicon wafer 84; the adjacent two silicon wafers are soldered and connected, and between the adjacent two silicon wafers
  • the third potting layer 101 is provided, and at least one pair of two silicon wafers are disposed in the four silicon wafers, wherein the lower silicon wafer is provided with a third potting area 103 corresponding to the third potting layer 101. And the third potting zone 103 does not overlap with the upper silicon wafer.
  • the first silicon wafer 81, the second silicon wafer 82, and the first The three silicon wafers 83 are the same size and aligned, and the orthographic projection of the fourth silicon wafer 84 on the plane of the third silicon wafer 83 is located on the third silicon wafer 83. It can be understood that the projection of the fourth silicon wafer 84 frame is completely located.
  • the projection of the frame of the third silicon wafer 83 or the frame of the fourth silicon wafer 84 coincides with the frame portion of the third silicon wafer 83, wherein the third potting region 103 is the frame projection of the fourth silicon wafer 84 and the third silicon wafer.
  • the orthographic projection portion of the fourth silicon wafer 84 on the plane of the third silicon wafer 83 is located in the third silicon wafer 83, as shown in FIG. 11b, the fourth silicon wafer 84 is shifted to the right in the horizontal direction, and A portion of the third silicon wafer 83 exposed on the outside of the fourth silicon wafer 84 is set as the third potting region 103.
  • the dispensing material is dropped into the third potting zone 103 by using a dispensing tool. According to the capillary flow principle, the dispensing material penetrates into the gap between the third silicon wafer 83 and the fourth silicon wafer 84.
  • the dispensing continues, and the dispensing material will penetrate along the sidewall of the third silicon wafer 83 to the gap between the third silicon wafer 83 and the second silicon wafer 82, and so on, and the silicon material to be dispensed
  • the dispensing is stopped, and after the dispensing material is cured, a third potting layer 101 is formed between the adjacent two silicon wafers.
  • the lower silicon wafer is provided with a third potting region 103 which does not overlap with the upper silicon wafer.
  • the upper silicon wafer is The orthographic projection on the plane of the lower silicon wafer is located in the lower silicon wafer, and when the lower silicon wafer is polygonal, at least one side of the lower silicon wafer is provided with a third potting region 103, specifically, at least one of the lower silicon wafers
  • the third potting zone 103 is disposed on both sides, the at least two third potting zones 103 are not connected to each other, or the at least two third potting zones 103 are arranged to form a whole; or, as shown in the figure In 12b, in the adjacent two silicon wafers, the orthographic projection portion of the upper silicon wafer on the plane of the lower silicon wafer is located in the lower silicon wafer.
  • the four silicon wafers are respectively shifted and displaced in a direction parallel to the substrate. Therefore, in any two adjacent silicon wafers, a portion where the lower silicon wafer is exposed outside the upper silicon wafer is set as the third potting region 103.
  • the specific arrangement of the package layer described above is also applicable to the silicon wafer, and the detailed description thereof will not be repeated here.
  • a silicon wafer on a side of the at least two silicon wafers adjacent to the substrate 70 is soldered to the substrate 70, and a fourth potting layer is further disposed between the silicon wafer on the side of the substrate 70 adjacent to the substrate 70 and the substrate 70.
  • the substrate 70 is provided with a fourth potting zone corresponding to the fourth potting layer 102, the fourth potting zone does not overlap with at least two silicon wafers; the fourth potting layer 102 is also composed of a liquid dispensing material. Forming and solidifying, the fourth potting zone is a region where the liquid dispensing material is dropped on the substrate 70.
  • a fourth potting zone is disposed on the substrate 70 near the edge of the silicon wafer layer; when dispensing, The dispensing material is dropped on the fourth potting zone on the substrate 70. According to the principle of capillary flow, the dispensing material is infiltrated into the gap between the substrate 70 and the silicon wafer near the side of the substrate 70 by the fourth potting zone. After the adhesive material completely fills the void, the dispensing is stopped, and the dispensing material is solidified to form a fourth potting layer 102.
  • the adjacent two third potting layers 101 and the third potting glue are integrally connected, and due to the tension of the surface of the dispensing material, the entire irrigation Layer has a trapezoidal edges.
  • the entire potting layer protects the solder joint 60 between the lower silicon wafer and the upper silicon wafer and the solder joint 60 between the lower silicon wafer and the substrate 70, so that under load such as drop impact, bending and temperature cycling, The mechanical and thermal stresses concentrated on the edge solder joints can be distributed relatively evenly over all solder joints to prevent high stress solder joints from failing at the edges.
  • the embodiment of the present application further provides a terminal, including the above-mentioned stacked package structure, wherein the arrangement of the package layer in the stacked package structure may refer to the structural features described in Embodiments 1 to 5, and the silicon wafer in each package layer
  • the structural features described in Embodiment 6 and Embodiment 7 can be referred to.
  • the lower encapsulation layer 20 is provided. a first potting zone 21 that does not overlap with the upper encapsulating layer 30, so that when dispensing, any two adjacent encapsulating layers are used as one structural unit, and the first filling on the lower encapsulating layer 20 in each structural unit
  • the glue zone 21 is dispensed, so that the plurality of package layers disposed in the stack can be completely filled with the glue material, thereby improving the reliability of the package structure; the TSV 3D package technology is adopted between the plurality of silicon wafers in the package layer.
  • At least one pair of adjacent silicon wafers is present, wherein the lower silicon wafer is provided with a third potting zone which does not overlap with the upper silicon wafer, so as to ensure that the silicon wafer can be dispensed between materials during dispensing. Fully filled, improving the reliability of the stacked package structure.
  • a third potting zone can be disposed on any of the two adjacent silicon wafers on the lower silicon wafer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Buffer Packaging (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

L'invention concerne une structure PoP (boîtier sur boîtier) et une borne. La structure PoP comprend : une carte principale (10) et au moins deux couches d'emballage agencées de manière empilée le long de la direction à l'opposé de la carte principale, la couche d'emballage, la plus proche d'un côté de la carte principale, dans lesdites au moins deux couches d'emballage étant en liaison soudée avec la carte principale; la couche d'emballage, proche d'un côté de la carte principale, dans toutes les deux couches d'emballage adjacentes est une couche d'emballage inférieure (20), et la couche d'emballage à l'opposé d'un côté de la carte principale est une couche d'emballage supérieure (30); la couche d'emballage inférieure est en liaison soudée avec la couche d'emballage supérieure; une première couche de versage adhésive (40) est également disposée entre la couche d'emballage inférieure et la couche d'emballage supérieure; une première zone de versage adhesive (21) correspondant à la première couche de versage adhésive est disposée dans la couche d'emballage inférieure; et la première zone de versage adhésive ne chevauche pas la couche d'emballage supérieure. Pendant la distribution, un matériau de distribution est égoutté dans la première zone de versage adhésive de la couche d'emballage inférieure, après que le matériau de distribution remplit complètement la première zone de versage adhésive, la distribution est arrêtée, et la première couche de versage adhésive est formée après que le matériau de distribution a été durci, ce qui permet de résoudre le problème dans l'état de la technique selon lequel un espace entre la couche d'emballage inférieure et la couche d'emballage supérieure est difficile à remplir complètement ou est facilement rempli partiellement.
PCT/CN2017/078636 2017-01-04 2017-03-29 Structure pop ( boîtier sur boîtier) et borne WO2018126542A1 (fr)

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