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WO2018109064A1 - Module comprenant des puces de diode électroluminescente - Google Patents

Module comprenant des puces de diode électroluminescente Download PDF

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Publication number
WO2018109064A1
WO2018109064A1 PCT/EP2017/082762 EP2017082762W WO2018109064A1 WO 2018109064 A1 WO2018109064 A1 WO 2018109064A1 EP 2017082762 W EP2017082762 W EP 2017082762W WO 2018109064 A1 WO2018109064 A1 WO 2018109064A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
cover layer
metallization
openings
vias
Prior art date
Application number
PCT/EP2017/082762
Other languages
German (de)
English (en)
Inventor
Jürgen Moosburger
Thomas Schwarz
Jan Kostelnik
Original Assignee
Osram Opto Semiconductors Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of WO2018109064A1 publication Critical patent/WO2018109064A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10H20/00
    • H01L25/0753—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10H20/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls

Definitions

  • the invention relates to a module with light-emitting diode chips according to patent claim 1 and a method for producing a module according to patent claim 8.
  • the object of the invention is to provide an improved Mo ⁇ dul and an improved method for manufacturing the module.
  • An advantage of the proposed module and the pre-strike ⁇ NEN method is that established technologies are used for circuit board manufacture. Furthermore, the proposed module detects enables an integration of wide ⁇ ren electronic components such as a micro-controller, sensors and an advanced electronic control system to the module.
  • a module with light-emitting diode chips is proposed, wherein the light-emitting diode chips each have a first and a second contact electrode on opposite sides.
  • the light-emitting diode chips are arranged on a printed circuit board where ⁇ has a carrier layer in the printed circuit board. On a top side of the carrier layer, a first metallization ⁇ plane is arranged with row lines and redistribution lines.
  • the light-emitting diode chips are arranged with the first contact electrodes on the row lines and are electrically conductively connected to the row lines.
  • the carrier layer has first and fourth vias, which are guided by ei ⁇ ner top of the support layer to an underside of the Trä ⁇ carrier layer.
  • the row lines are connected via the first fürorialie ⁇ stanchions with the first contact surfaces of the second metallisation plane.
  • the rewiring lines are connected via the fourth vias to the second contact surfaces of the second metallization level.
  • the first cover layer covers the LED chips.
  • the first cover layer ⁇ has second through-contacts which are guided from a top of the first covering layer to the second contacts ⁇ lektroden of the LED chips.
  • a third metallization is arranged with column lines, wherein the second vias are electrically connected to the column lines. Third vias are connected to the column lines and led from the top of the first cover layer to the redistribution lines of the second metallization level.
  • a second cap layer is disposed on the underside of the carrier layer, a fourth metal ⁇ lleitersebene is arranged with further contact areas on the Untersei ⁇ te the second cover layer, wherein the first contact areas of the second metallization level on fifth vias with the other contact surfaces of the fourth Metallization level are connected.
  • comprise the second vias and / or the third via holes in an edge region adjacent to the first cover layer has a growth ⁇ layer, wherein the growth layer of the first via and / or the second via surrounding a central material cone.
  • the growth layer and the material cone are produced in different processes and can have different materials.
  • the growth layer comprises titanium and copper .
  • the top of the module with a cover, in particular covered with a top coat where ⁇ provided at about the LED chip openings for electromagnetic radiation of the LED chips Oberläs- sig.
  • the first cover layer and / or the second cover layer are formed from at least one film.
  • the third metallization level comprises a galvanically deposited material.
  • a method for producing a module with light-emitting diode chips wherein the light-emitting diode chips each have a first and a second contact electrode on opposite sides.
  • a printed circuit board wherein the printed circuit board has a carrier layer, wherein on an upper side of the carrier layer a first metallization is arranged with row lines and Umverdrah- management lines.
  • the light-emitting diode chips are arranged with the first contact electrodes on the row lines.
  • the carrier layer has first and fourth vias, which are guided from a top of the support layer to an underside of the carrier ⁇ layer.
  • a second metallization is arranged with first and second contact surfaces.
  • the row lines are connected via the first plated-through holes to the first contact area of the second metallization level.
  • the rewiring lines are connected via the fourth plated-through holes to the second contact surfaces of the second metallization level.
  • a first layer is applied in such a way that the first cover layer, the first metallization ⁇ covered and
  • the second contact electrodes of the light-emitting diode chips can be covered with the first cover layer or second openings are formed above the second contact electrodes in the first cover layer. If the second Publ ⁇ voltages not yet been formed in the first covering layer during the application of the top layer, then into the top of the top layer are above the second contact electrodes second
  • the second openings are led from the top of the first covering layer to the second contacts ⁇ lektroden. In the second openings second vias are introduced. On the upper side of the first cover layer, a third metallization level is provided
  • the first cover layer may already have third openings during application. If the first cover layer has no third openings during application, third openings are introduced into the first cover layer after application. The third openings are led to the redistribution lines of the first metallization level. Third vias are introduced into the third Publ ⁇ voltages are formed to the wiring lines said third vias from the top of the top layer.
  • a second cover layer is applied on the underside of the carrier layer, wherein the second cover layer has fifth openings or fifth openings are made after application in the second cover layer.
  • the fifth openings are led to the first and second contact surfaces of the second metallization.
  • the fifth openings are filled with fifth vias.
  • the fifth vias are connected to the other contact surfaces.
  • the first covering layer and / or the second covering layer in the form of at least one film is then ⁇ introduced, in particular laminated on.
  • the first covering layer and / or the second covering layer in the form of two different alsei ⁇ Nander arranged films are formed, wherein the first film surrounds the LED chip, and wherein the second film, the light emitting diode chip at least partially or completely from ⁇ covers, where in particular used as the first film has an epoxy resin film and the second film has a film acrylate ⁇ the.
  • the first film may have openings for receiving the LED chips.
  • the second film may comprise second ⁇ ffnun ⁇ gene for the formation of the second vias.
  • the third metallization level is laminated to the cover layer in the form of a film.
  • the foil of the first cover layer has recesses for the light-emitting diode chips.
  • the foil of the first cover layer has recesses for receiving the light-emitting diode chips and / or second openings for forming the second via contacts and / or third openings for forming the third plated-through holes.
  • the film of the second cover layer has fourth and fifth openings.
  • the second covering layer is introduced after forming the first and / or the second covering layer, wherein insbeson ⁇ particular, the openings using a laser, a drill, or with a plasma etching are introduced.
  • in the second openings of the first cover layer and / or in the third openings of the first cover layer is a growth layer on side walls of the second and / or third openings and on the top of the first
  • the mixture is then electrodeposited on the growth ⁇ metal layer, wherein the openings are filled with via holes and a metal layer on top of the first covering layer is formed.
  • a growth layer is applied to 3955n ⁇ de of the openings of the second cladding layer and on the bottom of the second covering layer.
  • the mixture is then electrodeposited on the growth layer of metal, where ⁇ be filled in the openings of the second outer layer with fürjorie ⁇ stanchions and a metal layer is formed on the lower side of the cover layer ⁇ .
  • the growth layer is deposited using a sputtering process.
  • a photoresist technique wherein insbeson ⁇ particular, the photoresist layer is applied in liquid form or as a film is used for the electrodeposition of the metal layer.
  • 1 is an electrical equivalent circuit diagram for a module with LED chips
  • FIG. 2 is a plan view of a printed circuit board with a first metallization
  • 3 is a plan view of the circuit board after Mon ⁇ animals of the LED chips without representation of the first metallization
  • FIG. 4 is a schematic representation of a detail of a printed circuit board with a first metallization and with mounted LED chips of FIG. 3, FIG.
  • FIG. 5 shows a cross section through the section of Fig. 4,
  • FIG. 6 shows a cross section through the arrangement of FIG. 5 after the embedding of the light-emitting diode chips in a cover layer and the application of a third metallization plane
  • FIG. 7 shows a plan view of an embodiment of a first
  • Cover layer in the form of a film with recesses, 8 shows a cross section through the arrangement of FIG. 6 after the introduction of openings for through-contacts
  • FIG. 9 shows a cross-section through the arrangement of FIG. 8 after the application of a growth layer
  • FIG. 10 shows a cross section through the arrangement of FIG. 9 after the application of a mask
  • FIG. 11 shows a cross section through the arrangement of FIG. 10 after the deposition of metal using a gal ⁇ vanischen method
  • FIG. 12 is a cross section through the arrangement of Fig. 11, after removing the mask
  • FIG. 13 shows a cross section through the arrangement of FIG. 12 after the removal of the growth layer and the structuring of a third and fourth metallization plane, FIG.
  • FIG. 14 shows a cross section through the module of FIG. 13 after the application of a covering layer
  • FIG. 15 shows a schematic cross section of the module of FIG.
  • 17 is a schematic representation of a cross-section of the module of FIG. 14 in the plane of the printed circuit board showing the first and fourth
  • a schematic representation of a further From ⁇ guide a third metallization with electrical column lines, which connect each upper electrical contact electrodes of light emitting diodes of a column with each other, is a schematic representation of a cross section through the first covering layer showing the third vias, which are guided by the third metallization level to the first metallization ⁇ plane through the first cover layer, a schematic representation of the column lines in the third metallization level according to the off ⁇ guide of FIGS. 14 and 15, Fig. 22 is a a more detailed view of the column lines according to the embodiment of FIG.
  • Fig. 1 shows in a schematic representation of an electrical equivalent circuit diagram of a module 1 having a plurality of LED chips 2.
  • LED chips 2 are in Zei ⁇ len 3 and arranged in columns 4.
  • Each LED chip 2 has two electrical connections, wherein in each case one electrical connection to a row line 9 and a second electrical connection to a column line 6 is electrically conductively connected.
  • the LED chips 2 are thus using a cross matrix interconnection using the Row lines 9 and the column lines 6 supplied with power. By appropriate energization of a particular row line 9 and a specific column line 6, each LED chip 2 can be controlled individually.
  • the module 1 with the row lines 9 and the column lines 6 can be constructed on the basis of a printed circuit board.
  • Fig. 2 shows in a schematic representation of a plan view of a top side 16 of the circuit board having a Trä- carrier layer 7, on which a first metallization plane is brought to ⁇ 8.
  • Rei ⁇ hen einen 9 are arranged parallel to each other.
  • Each row line 9 has a connection contact 10 to a first feedthrough 11.
  • the first plated-through hole 11 is guided down to an underside of the carrier layer 7.
  • the first metallization 8 has between Whitneynleitun ⁇ gene on first wiring lines 9 12th
  • the rewiring lines 12 may have different lengths.
  • imaginary grid lines 13, 14 for a pixel grid are shown on the printed circuit board 7.
  • the grid lines 13, 14 are arranged parallel to each other and delimit in the illustrated embodiment, a square FLAE ⁇ surface, which occupies a pixel 15th 16
  • Fig. 3 shows the top side of the circuit board 7 with montier ⁇ th LED chip 2.
  • the light-emitting diode chips 2 are arranged on the corresponding row lines of the first metallization level.
  • the LED chips 2 are arranged in rows and columns 3, 4.
  • the imaginary first and second grid lines 13, 14 again define square pixels 15.
  • one pixel 15 has three LED chips 2 arranged in a row 3.
  • a pixel 15 may also have more or fewer LED chips 2.
  • a pixel 15 is formed by three LED chips.
  • a light emitting diode chip is formed, for example, in the form of a laser diode or a lichtemit ⁇ animal ends diode.
  • the LED diode chips 2 of a pixel 15 may emit light of the same color or different colors.
  • one pixel has one
  • LED chip with a red color a LED chip with a blue color and a LED chip with a green color.
  • the pixels 15 represent pixels which are arranged in a PERIODIC ⁇ gene, two-dimensional rectangular grid.
  • 16 x 16 pixels are provided.
  • a module may also have more or fewer pixels.
  • the individual pixels may have an edge length which is, for example, Zvi ⁇ rule 0.3 mm and 2 mm, in particular, for example, Zvi ⁇ rule 0.5 mm and 1 mm.
  • the light-emitting diode chips of the module or the light-emitting diode chips of a pixel can also emit blue, green, yellow, red or orange light.
  • the light-emitting diode chips 2 are arranged linearly next to one another in rows.
  • the light-emitting diode chips 2 of a row 3 can also be arranged laterally offset in height.
  • the light-emitting diode chips can also be arranged in a different arrangement, in particular distributed statistically.
  • the individual LED chips 2 of a pixel 15 can at ⁇ game as a distance from a side edge of a light-emitting diode chips ⁇ to the side edge of the adjacent light-emitting diode have chips which is between 30 ym and 60 ym.
  • the individual light-emitting diode chips may, for example, have an edge length which is between 0.1 mm and 0.5 mm.
  • Fig. 4 shows a plan view of a partial section of
  • Printed circuit board 7 of FIG. 3 with two row lines 9, arranged on the LED chips 2 and a arranged between the two row lines 9 first Umverdrahtungslei- direction 12.
  • a cross-sectional guide AA is shown as a dashed line, which is ver ⁇ used for further cross-sections ,
  • Fig. 5 shows the circuit board 7 of Figure 4 in cross section AA.
  • the printed circuit board for example, has a thickness of 0.2 to 0.5 mm and may be formed as a flexible printed circuit board.
  • the circuit board 7 illustrates a backing layer.
  • the circuit board 7 has, on the top side 16 of the first Metalli ⁇ s réellesebene 8, as shown in Fig. 2.
  • Darge ⁇ presented cross section two sections of a series line 9 are shown. Due to the cross-section of the Erasmusnlei ⁇ tung 9 is not illustrated throughout. Between the two sub-pieces of the row line ⁇ 9 is part of the first rewiring circuit 12 is shown.
  • the first rewiring line 12 is guided via a fourth through-connection 17 to an underside 18 of the printed circuit board 7.
  • the second rewiring lines 20 are each connected to the arranged above the row line 9 via a first through-connection, not shown.
  • the third rewiring lines 21 are electrically insulated from the second rewiring lines 20.
  • the third redistribution lines 21 are connected via the fourth plated-through holes. 17 in each case with a first rewiring 12 in connection.
  • the row lines 9 have trenches 22, which are formed transversely to the longitudinal extent of the row lines 9 between the light-emitting diode chips 2.
  • the LED chips 2 are each connected to a lower ⁇ side via a connecting layer 23 with the row lines 9.
  • the light-emitting diode chips 2 have first contact electrodes 24 on the lower side.
  • the first contact electrodes 24 are electrically conductively connected to the row line 9 via the electrically conductive connection layer 23.
  • the light-emitting diode chips 2 have second contact electrodes 25 on the upper side.
  • the electrically conductive connection layer 23 can consist, for example, of a solder material or of an electrically conductive adhesive.
  • the row lines 9 and the second and third redistribution lines 20, 21 and the first redistribution lines 12 may be made of copper, for example.
  • the row lines 9 and the first rewiring line 12 may be provided on the upper side with a NiAu layer in order to improve the assembly of the LED chips 2 or an electrical contact with a via.
  • each LED chip 2 of the group can produce a light of a different color.
  • a different color For example, a
  • the light-emitting diode chips ⁇ example, may be composed of gallium nitride.
  • the LED chip 2 may have a substrate ⁇ on which the LED chip 2 is disposed.
  • the substrate may be formed of sapphire.
  • the substrate is, for example, electrically conductive or it is a via from a bottom of the LED chip on the underside of the substrate out.
  • the first contact electrode 24 is arranged on the underside of the substrate and not directly on the underside of the LED chip 2.
  • connection layer 23 may also consist of a silver conductive adhesive, a conductive paste or a solder.
  • the row lines 9 may have a surface made of gold or nickel, or a gereinig ⁇ te copper surface.
  • a normal copper surface for the assembly of the LED chips 2 may be provided on the top of the row lines 9.
  • FIG. 6 shows a cross section through the printed circuit board 7 after a further method step.
  • a first coating layer was 26 be applied to the upper ⁇ ⁇ page 16 of the printed circuit board. 7
  • the first cover layer 26 surrounds the LED chip 2 and also covers the second contact elements 25 on the upper surface of the LED chip 2. Moreover, it is on the first clad layer 26, a third metallization layer 27 be ⁇ introduced.
  • a first 26 and a second part covering ⁇ layer 28, 29 has the first covering layer.
  • the first partial covering layer 28 is guided starting from the upper side 16 of the printed circuit board 7 up to a first height of the LED chips 2. If the light-emitting diode chip 2 has a substrate, then the first partial covering layer 28 can be led to the upper edge of the substrate.
  • the first partial covering layer 28 may, for example, comprise or be formed from an epoxy resin.
  • Part of capping layer 29 is disposed on top of the first part cover ⁇ layer 28 and covers the second Kunststoffele ⁇ elements 25 of the LED chip 2. Assigns the LED chip 2, a substrate, then surrounds and covers the second portion of cover layer the LED chip 2 itself.
  • the first cover layer 26 may also be made of only one material, such as, for example Epoxy resin or acrylate may be formed. In addition, other materials such as silicone can be used.
  • the third metallization 27 may be formed, for example, of copper. In addition, the third metallization 27 may also be formed of a material other than copper.
  • a second cover layer 30 is arranged on the underside 18 of the printed circuit board 7 and on the second metallization 19, a second cover layer 30 is arranged.
  • the second cover layer 30 likewise has a first partial cover layer 28 and, arranged thereon, a second partial cover layer 29.
  • the first partial cover layer 28 is arranged on the underside 18 of the Lei ⁇ terplatte 7.
  • the second partial covering layer 29 is arranged on the first partial covering layer 28.
  • the second cover layer 30 may also be formed of a uniform material.
  • a fourth metallization 31 is applied on the two ⁇ th covering layer 30, a fourth metallization 31 is applied.
  • the fourth metallization plane 31 may consist of copper or of another suitable metal.
  • the first and the second cover layer 26, 30 may ⁇ example as liquid or applied in the form of a film.
  • the film via a lamination process with the printed ⁇ te is mechanically connected.
  • the second cover layer 30 can be dispensed with.
  • the second cover layer 30 offers the advantage that a mechanical stabilization of the printed circuit board 7 is achieved.
  • FIG. 7 shows, in a schematic illustration, a plan view of a first cover layer 32, which is designed in the form of a film, recesses 33 for receiving the light-emitting diode chips 2 being arranged in the cover layer.
  • the recesses 33 may extend through the entire thickness of the film or be formed only as partial recesses in the film.
  • the recesses 33 may be provided for receiving the LED chips 2.
  • the recesses can be provided for the formation of plated-through holes.
  • the first and fourth metallization 8, 19 are applied in the form of a Fo ⁇ lie, especially in the form of a copper foil and laminated can.
  • the third and the fourth metallization 27,31 can be in the form of a film out ⁇ forms.
  • the films may or may not be filled with fiberglass material. The films may be patterned before application or patterned after application.
  • Fig. 8 shows the circuit board of FIG. 6 after the introduction of openings 34,35,36 in the first and the second cover ⁇ layer 26, 30.
  • the third metallization 27 and the first cover layer 26 were above the second Druck ⁇ tide 25 of the LED chips 2, the second openings 34 introduced.
  • the second openings 34 are led to the second contact electrodes 25.
  • third openings 35 have been introduced into the third metallization level 27 and the first cover layer 26, wherein the third openings 35 are led to the first rewiring line 12.
  • fifth openings 36 have been introduced into the fourth metallization plane 31 and the second cover layer 30.
  • the fifth openings 36 are led to the second metallization level 19 and to the second and third redistribution lines 20, 21.
  • the second, third and fifth openings 34, 35, 36 various methods can be used.
  • the second, third and / or fifth openings 34 35 may, 36 using mechanical be also introduced by using plasma-assisted process drilling, laser drilling or the like.
  • the second openings 34 which may have a smaller depth and a smaller diameter than the third and fifth openings 35, 36, can be introduced by means of a laser drilling method.
  • Fig. 9 shows the arrangement of Fig. 8 in which applied to the third Metallticiansebe ⁇ ne 27, a growth layer 37 and in the second and third ports 34 for a subsequent method step, 35, a growth layer 37 is turned ⁇ introduced.
  • the growth layer 37 can be deposited, for example with ⁇ a sputtering method.
  • the wax ⁇ tumstik 37 may, for example, titanium and copper are ⁇ be.
  • the growth layer 37 may, for example, a di ⁇ blocks of 0.2 to 3 have ym ym.
  • the growth layer 37 serves as a growth layer for a later electrodeposition process.
  • On the fourth metallization 31 and in the fifth openings 36 is also a growth ⁇ layer 37 or introduced.
  • Growth layer may have a thickness between 0.2 ym and 3 ym.
  • the first and second cover mask 38, 39 may be formed, for example, from photoresist.
  • the first mask 38 the upper surface is covered in a ge ⁇ desired structure, said regions via the second openings 34, the portions through the third openings 35 and gap portions 40 are not covered with the first mask.
  • the second mask 39 covers the lower ⁇ side of the arrangement of Fig. 10 desired first and second and third contact regions 41, 42, 43 not with the fifth ⁇ ffnun ⁇ gene 36 from.
  • FIG. 11 shows the arrangement of FIG. 10 after the deposition of a metal layer 44, 45 on surfaces of the top side and the bottom side of the arrangement of FIG. 10 not covered by the cover masks 38, 39.
  • the metal layers 44, 45 are produced by means of a galvanic deposition method generated.
  • Both the second holes 34 and the third openings 35 with the metal, particularly copper ⁇ be filled.
  • the filled-in second openings 34 represent second plated-through holes 46.
  • the filled-in third openings 35 represent third plated-through holes 47.
  • the second and third plated-through holes 46, 47 have material cones 58 which are surrounded by the growth layer 37.
  • the material cone 58 may for example consist of copper.
  • the growth layer 37 can be, for example, from a stand ⁇ TiCu layer.
  • 46 column lines 6 are formed on the second plated-through holes.
  • the padded Spaltenbe- rich 40 also provide column lines 6 illustrates the fill on ⁇ takes place up to a desired height above the top of
  • the second metal layer 45 is applied to the underside of the arrangement of FIG. 10.
  • the fifth openings 36 are filled.
  • the filled-in fifth openings represent fifth plated-through holes 48.
  • a fourth metallization level 31 with contact areas 49 is produced in the first, second and third contact areas 41, 42, 43.
  • FIG. 12 shows a further method step in which the first and the second cover mask 38, 39 have been removed. For ⁇ the first and the second metal layer 44, 45 can be planarized to a desired thickness. Thus, a module 1 is obtained.
  • the growth layers will drive 37 from the top and from the bottom for example by means of etching methods.
  • LED chips 2 are covered, covered with a covering layer 50, for example in the form of a topcoat.
  • the light emitting diodes ⁇ chips 2 emit light 56 on the top of the module 1 via the uncovered surfaces of the cover layer.
  • the cover ⁇ layer 50 may for example have a black color and be impermeable to electromagnetic radiation.
  • the cover layer 50 is structured in such a way that the FLAE ⁇ surfaces 56 are above upper Abstrahlence of the LED chips 2 free of the covering layer 50th
  • the cover layer 50 may be introduced, for example large area listed are especially imprinted and are subsequently ⁇ lord structured by photolithographic methods.
  • the covering layer 50 can also be applied in the form of a film, in particular as a lacquer film, which is structured after application. For structuring, for example, a laser can be used.
  • the cover layer 50 may be applied as the structured film who ⁇ , said film having openings for the Abstrahlence of the LED chips. 2 The openings may correspond to the free surfaces 56.
  • further electrical components 55 can be integrated in the printed circuit board 7 itself or in the first or in the second cover layer 26, 30.
  • electrical components 55 may be provided for example microcontroller, sensors or an extended control electronics.
  • the further electrical components 55 are connected to the light-emitting diode chips 2 via electrical lines (not shown). This allows a compact design to be achieved using established PCB manufacturing technologies.
  • Fig. 15 shows the module 1 of Fig. 14, wherein on the contact surfaces 49 each have a solder ball 51 is provided as a contact part for further electrical contacting.
  • an insulating layer 52 e.g. arranged in the form of a Lötstopplackes to cover.
  • FIG. 16 shows a schematic representation of the underside of the module 1 of FIG. 15.
  • the imaginary first and second grid lines 13, 14 are shown, which schematically show the arrangement of the pixels 15.
  • the contact surfaces 49 of the underside of the module 1 are shown, which are arranged centrally at vertices of four pixels 15.
  • the second cover layer 30 can be dispensed with.
  • the Fig. 16 shows the underside of the circuit board with the carrier ⁇ layer 7 and to the second metallization layer 19.
  • the second metallization level in place of the second and third wiring lines contact surfaces 49. Via the contact surfaces 49, the module 1 can be electrically contacted from the underside.
  • FIG. 17 shows, in a schematic illustration, a cross-section of the module of FIG. 14 in the plane of the printed circuit board 7.
  • the imaginary grating lines 13, 14 of the pixels 15 are shown schematically again.
  • the fourth plated-through holes 17 and the first through-connections 11 are shown.
  • FIG. 18 shows the upper side of the entire module 1 of FIG. 13 with the topcoat layer 50.
  • the topcoat layer 50 has white openings 53 above the LED chips 2.
  • the further openings 53 may have the same cross-sectional area as the light-emitting diode chips 2.
  • the topcoat layer 50 may be composed of one for the electromagnetic radiation of
  • LED chips 2 non-permeable material may be formed.
  • the openings 53 may be filled with a permeable to the electromagnetic radiation material.
  • FIG. 19 shows a schematic view of a third metallization level 46 of a module 1 with the representation of the column lines 6 and the third vias 47.
  • the illustration shows an enlarged detail of the arrangement of the column lines 6.
  • the column lines 6 are arranged laterally offset relative to the second through-contacts 46 and connected via a transverse line 54 with the through-contacts 46.
  • FIG. 20 shows a schematic representation of the arrangement of the third vias 47 in the first cover layer 26 of the module 1 of FIG. 13.
  • the imaginary grating lines 13, 14 of the pixels 15 are shown schematically again.
  • FIG. 21 shows a schematic partial sectional view of a first embodiment of the column lines 6, wherein the column lines 6 are guided centrally over the light-emitting diode chips 2.
  • FIG. 22 shows an enlarged view again of the column lines 6 according to the embodiment of FIG. 19, in which the column lines 6 are arranged laterally offset between two light-emitting diode chips 2. In this exporting ⁇ approximate shape less top surface of the LED chip 2 is covered by the column lines. 6 This will reduced shading of the electromagnetic radiation.
  • Fig. 23 shows a schematic illustration of a detail section of an embodiment of a module 1, with Erasmusnlei ⁇ obligations 9, column lines 6 and first Umverdrahtungs- lines 12.
  • the column lines 6 are arranged laterally adjacent to the not shown light-emitting diode chips 2.
  • Fig. 24 shows a detail of another embodiment of a layout of a module for the column lines 6 of the LED chips 2.
  • the column lines 6 are approxi- hernd performed as wide as the light emitting diode chips 2. Be ⁇ reaching the Abstrahltress of the LED chips 2, the column lines 6 Openings 53 for the LED chips 2 for emitting the electromagnetic radiation.
  • the column lines 6 are separated from each other by narrow spacer surfaces.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Led Device Packages (AREA)

Abstract

L'invention concerne un module comprenant des puces de diode électroluminescente. Les puces de diode électroluminescente comportent chacune sur des côtés opposés une première et une seconde électrode de contact. Un premier niveau de métallisation comportant des lignes de rangée et des premières lignes de câblage est disposé sur un côté supérieur d'une couche de support. Les puces de diodes électroluminescentes comportant les premières électrodes de contact sont disposées sur les lignes de rangée. La couche de support comporte des premiers contacts traversants qui vont d'un côté supérieur de la couche de support à un côté inférieur de la couche de support. Un deuxième niveau de métallisation comportant des premières surfaces de contact et d'autres surfaces de contact est disposé sur le côté inférieur de la couche de support. Les lignes de rangée sont reliées aux premières surfaces de contact du deuxième niveau de métallisation par le biais des premiers contacts traversants. Une première couche de recouvrement est disposée sur la couche de support. La première couche de recouvrement entoure et recouvre au moins partiellement les puces de diodes électroluminescentes. Un troisième niveau de métallisation comportant des lignes de colonnes est disposé sur la première couche de recouvrement. Les deuxièmes contacts traversants sont reliés électriquement aux lignes de colonne. Les troisièmes contacts traversants vont du côté supérieur de la première couche de recouvrement aux premières lignes de câblage. Des quatrièmes contacts traversants, qui relient les premières lignes de câblage à des deuxièmes surfaces de contact du deuxième niveau de métallisation, sont prévus dans la couche de support.
PCT/EP2017/082762 2016-12-15 2017-12-14 Module comprenant des puces de diode électroluminescente WO2018109064A1 (fr)

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DE102016124525.9 2016-12-15
DE102016124525.9A DE102016124525B4 (de) 2016-12-15 2016-12-15 Modul mit Leuchtdiodenchips und Verfahren zum Herstellen eines Moduls mit einer Mehrzahl von Leuchtdiodenchips

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WO2018109064A1 true WO2018109064A1 (fr) 2018-06-21

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DE (1) DE102016124525B4 (fr)
TW (1) TW201828450A (fr)
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DE19603444A1 (de) * 1996-01-31 1997-08-07 Siemens Ag LED-Vorrichtung
US20070223226A1 (en) * 2006-03-27 2007-09-27 Dong Wook Park Light Emitting Diode Illuminating Apparatus and Method of Manufacturing the Same
EP1876653A2 (fr) * 2006-07-07 2008-01-09 LG Electronics Inc. Sous-montage pour le montage d'un dispositif électroluminescent et emballage de dispositif électroluminescent
US20090278142A1 (en) * 2008-05-12 2009-11-12 Sony Corporation Light-emitting diode display and method for manufacturing the same
WO2011015449A1 (fr) * 2009-08-07 2011-02-10 Osram Opto Semiconductors Gmbh Procédé de fabrication d'un composant semiconducteur optoélectronique et composant semiconducteur optoélectronique
US20150169011A1 (en) * 2013-12-17 2015-06-18 LuxVue Technology Corporation Display module and system applications
US20150294896A1 (en) * 2014-04-09 2015-10-15 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Method for fabricating embedded chips
US20160181476A1 (en) * 2014-12-17 2016-06-23 Apple Inc. Micro led with dielectric side mirror

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JPS575083A (en) * 1980-06-13 1982-01-11 Tokyo Shibaura Electric Co Display unit
JP2877611B2 (ja) * 1991-06-07 1999-03-31 株式会社東芝 光半導体装置
US5886401A (en) * 1997-09-02 1999-03-23 General Electric Company Structure and fabrication method for interconnecting light emitting diodes with metallization extending through vias in a polymer film overlying the light emitting diodes

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19603444A1 (de) * 1996-01-31 1997-08-07 Siemens Ag LED-Vorrichtung
US20070223226A1 (en) * 2006-03-27 2007-09-27 Dong Wook Park Light Emitting Diode Illuminating Apparatus and Method of Manufacturing the Same
EP1876653A2 (fr) * 2006-07-07 2008-01-09 LG Electronics Inc. Sous-montage pour le montage d'un dispositif électroluminescent et emballage de dispositif électroluminescent
US20090278142A1 (en) * 2008-05-12 2009-11-12 Sony Corporation Light-emitting diode display and method for manufacturing the same
WO2011015449A1 (fr) * 2009-08-07 2011-02-10 Osram Opto Semiconductors Gmbh Procédé de fabrication d'un composant semiconducteur optoélectronique et composant semiconducteur optoélectronique
US20150169011A1 (en) * 2013-12-17 2015-06-18 LuxVue Technology Corporation Display module and system applications
US20150294896A1 (en) * 2014-04-09 2015-10-15 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Method for fabricating embedded chips
US20160181476A1 (en) * 2014-12-17 2016-06-23 Apple Inc. Micro led with dielectric side mirror

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DE102016124525A1 (de) 2018-06-21
TW201828450A (zh) 2018-08-01

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