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WO2018182663A1 - Mémoire spintronique avec couche de couverture à oxyde métallique - Google Patents

Mémoire spintronique avec couche de couverture à oxyde métallique Download PDF

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Publication number
WO2018182663A1
WO2018182663A1 PCT/US2017/025247 US2017025247W WO2018182663A1 WO 2018182663 A1 WO2018182663 A1 WO 2018182663A1 US 2017025247 W US2017025247 W US 2017025247W WO 2018182663 A1 WO2018182663 A1 WO 2018182663A1
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WIPO (PCT)
Prior art keywords
layer
oxide
free
tunnel barrier
layers
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Application number
PCT/US2017/025247
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English (en)
Inventor
Md Tofizur Rahman
Christopher J. WIEGAND
Daniel G. OUELLETTE
Angeline K. SMITH
Mark L. Doczy
Kaan OGUZ
Kevin P. O'brien
Brian S. Doyle
Oleg Golonzka
Tahir Ghani
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Intel Corporation
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Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/025247 priority Critical patent/WO2018182663A1/fr
Publication of WO2018182663A1 publication Critical patent/WO2018182663A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Materials of the active region

Definitions

  • Embodiments of the invention are in the field of semiconductor devices and, in particular, memory.
  • FIG. 1 includes spin transfer torque random access memory (STTRAM), a form of STTM.
  • Figure 1 includes a MTJ consisting of ferromagnetic (FM) layers 125, 127 and tunneling barrier 126 (e.g., magnesium oxide (MgO)).
  • the MTJ couples bit line (BL) 105 to selection switch 120 (e.g., transistor), word line (WL) 110, and sense line (SL) 115.
  • Memory 100 is "read” by assessing the change of resistance (e.g., tunneling magnetoresi stance (TMR)) for different relative magnetizations of FM layers 125, 127.
  • TMR tunneling magnetoresi stance
  • MTJ resistance is determined by the relative magnetization directions of layers 125, 127.
  • Layer 127 is the "reference layer” or “fixed layer” because its magnetization direction is fixed.
  • Layer 125 is the "free layer” because its magnetization direction is changed by passing a driving current polarized by the reference layer (e.g., positive voltage applied to layer 127 rotates the magnetization direction of layer 125 opposite to that of layer 127 and negative voltage applied to layer 127 rotates the magnetization direction of layer 125 to the same direction of layer 127).
  • Figure 1 depicts a conventional magnetic memory cell.
  • Figures 2-3 depict conventional MTJs.
  • Figure 4 includes a memory stack in an embodiment.
  • Figures 5A, 5B, 5C, 5D include embodiments of free layers.
  • Figure 6 includes a memory cell in an embodiment.
  • Figure 7 depicts a method of forming a memory in an embodiment.
  • Figures 8, 9, 10 depict systems for use with embodiments.
  • Some embodiments may have some, all, or none of the features described for other embodiments.
  • First, “second”, “third” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.
  • Connected may indicate elements are in direct physical or electrical contact with each other and “coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact.
  • similar or same numbers may be used to designate same or similar parts in different figures, doing so does not mean all figures including similar or same numbers constitute a single or same embodiment.
  • CMOS complementary metal-oxide-semiconductor
  • spin polarization which concerns the degree to which the spin or intrinsic angular momentum of elementary particles is aligned with a given direction
  • spintronics a branch of electronics concerning the intrinsic spin of an electron, its associated magnetic moment, and the electron's fundamental electronic charge
  • TMR Spintronics devices
  • STT spin polarized electrons
  • CMOS devices include, for example, spintronics devices implemented in memory (e.g., 3 terminal STTRAM), spin logic devices (e.g., logic gates), tunnel field-effect transistors (TFETs), impact ionization MOS (JJVIOS) devices, nano-electro-mechanical switches (NEMS), negative common gate FETs, resonant tunneling diodes (RTD), single electron transistors (SET), spin FETs, nanomagnet logic (NML), domain wall logic, domain wall memory, magnetic sensors, and the like.
  • spintronics devices implemented in memory (e.g., 3 terminal STTRAM), spin logic devices (e.g., logic gates), tunnel field-effect transistors (TFETs), impact ionization MOS (JJVIOS) devices, nano-electro-mechanical switches (NEMS), negative common gate FETs, resonant tunneling diodes (RTD), single electron transistors (SET), spin FETs, nanomagnet logic (NML), domain wall logic, domain wall
  • one form of STTM includes perpendicular STTM (pSTTM).
  • pSTTM perpendicular STTM
  • a perpendicular MTJ generates magnetization "out of plane”. This reduces the switching current needed to switch between high and low memory states. This also allows for better scaling (e.g., smaller size memory cells).
  • Traditional MTJs are converted to pMTJs by, for example, thinning the free layer, thereby making the tunnel barrier/free layer interface more dominant in magnetic field influence (and the interface promotes anisotropic out of plane magnetization).
  • Figure 2 includes such a system 200 with cobalt, iron, boron (CoFeB) free layer 225 interfacing magnesium oxide (MgO) tunnel barrier 226, which further couples to CoFeB fixed layer 227 and Tantalum (Ta) contacts 214 (which may couple to a selection switch such as transistor 120 of Figure 1), 216 (which may couple, by way of one or more vias, to a bit line such as bit line 105 of Figure 1).
  • CoFeB cobalt, iron, boron
  • MgO magnesium oxide
  • Ta Tantalum
  • Figure 3 depicts a system 300 with a MTJ, where a second oxidized MgO interface 320 (sometimes referred to as a "cap layer”) contacts CoFeB free layer 325 (which further couples to a tunnel barrier MgO 326, which is formed on CoFeB fixed layer 327).
  • a second oxidized MgO interface 320 (sometimes referred to as a "cap layer”) contacts CoFeB free layer 325 (which further couples to a tunnel barrier MgO 326, which is formed on CoFeB fixed layer 327).
  • Adding cap layer 320 may increase stability (perpendicular magnetic anisotropy (PMA)) for the memory, which is a problem for devices such as the device of Figure 2.
  • PMA perpendicular magnetic anisotropy
  • Figure 3 includes MgO at both free layer interfaces (i.e., layers 320, 326).
  • MgO layer 320 on top of CoFeB free layer 325 increases the memory's total resistance significantly (as compared to having just one oxide layer interface at the free layer as in Figure 2), which makes the design impractical for scaled devices (e.g., 22 nm) because of degradation in resistance-area (RA) product and TMR.
  • RA resistance-area
  • RA product refers to a measurement unequal to resistivity. Resistivity has units in ohm-cm, whereas RA product has units in ohm-um 2 (and is based on material resistivity (p), dot area (A), and MgO thickness (T Mg o) such that increasing MgO thickness exponentially increases the RA of the device). While resistivity represents an "inherent resistance” and is independent of the thickness of a material layer, RA product is exponentially proportional to the thickness of the material (e.g., MgO thickness). (Regarding "thickness", layer 320 is disposed “horizontally” for purposes of discussion herein and has a “thickness” in the vertical orientation. The length and width for layer 320 are “in plane” and the height or thickness is “out of plane”.)
  • Figure 4 includes an embodiment that increases TMR for the memory stack, reduces the RA product for the stack, and maintains PMA for the stack.
  • memory stack 400 includes MTJ 411 including a free magnetic layer 405, a fixed magnetic layer 403, and a tunnel barrier layer 404. Further, stack 400 includes a cap oxide layer 406 directly contacting the free magnetic layer 405.
  • the oxide layer includes a member selected from the group consisting of niobium, molybdenum, tantalum, tungsten, rhenium, titanium, vanadium, chromium, zirconium, hafnium, ruthenium, rhodium, osmium, iridium, or combinations thereof.
  • Applicant determined metals other than magnesium may be included within the oxide cap layer to reduce resistance of the layer while maintaining PMA and lowering TMR for the memory stack.
  • Applicant determined metals other than magnesium may be included within the oxide cap layer to reduce resistance of the layer while maintaining PMA and lowering TMR for the memory stack.
  • including tantalum in the oxide provides several advantages.
  • the oxide of tantalum oxide still provides oxygen to couple with iron from the free layer to promote PMA.
  • the non-magnesium metal reduces resistance of the cap layer.
  • lower RA product for the entire stack may be due to the fact that all of the metal (e.g., tungsten or tantalum) in the cap oxide may not be oxidized.
  • Another benefit may include the robustness of the stack against thermal anneal.
  • tungsten oxide may be more refractory than magnesium oxide.
  • Damping concerns the Gilbert damping coefficient. Using a metal such as tantalum or tungsten may increase damping (i.e., the damping coefficient) for the stack 400. However, Applicant determined any increase in damping due to the non-magnesium metal oxide cap layer may be offset or significantly countered by a related increase in TMR and/or spin polarization. Thus, while conventional wisdom may indicate including a metal with higher damping than magnesium would be inadvisable, Applicant has determined that including the metal in an oxide is indeed advisable in at least some embodiments and leads to increased TMR.
  • the non-magnesium metal also allows for thinning of the cap oxide layer, which further reduces RA product for the cap layer.
  • Applicant determined that including magnesium in the oxide cap layer has advantages in increasing stability/PMA for the memory.
  • Applicant determined the MgO needed to be relatively thick so the oxide cap layer did not disassociate during annealing of the memory, such as annealing of the free layer (e.g., at temperatures above 385 degrees C). In other words, in such a "disassociation" the magnesium may blend with surrounding layers and thereby lose its stabilizing/PMA effects on the stack.
  • MgO cap layer While increasing the thickness of the MgO cap layer helped protect the magnesium and its stabilizing/PMA effects, increasing the thickness of the MgO cap layer also raised RA product values for the stack.
  • Conventional MgO cap layers are 12 angstroms thick or more (see 320' of Figure 3).
  • refractory metals include niobium, molybdenum, tantalum, tungsten, rhenium, titanium, vanadium, chromium, zirconium, hafnium, ruthenium, rhodium, osmium, iridium. Since the refractory metal can better tolerate exposure to high temperatures, the cap layer including the refractory metal can be made thinner to reduce layer resistance while still avoiding disassociation and loss of stability/PMA and/or TMR.
  • the cap oxide layer 406 does not include magnesium.
  • the oxide layer 406 includes a first thickness 406' and the tunnel barrier layer 404 includes a second thickness 404' that is greater than the first thickness.
  • thickness 406' may be less than 10 angstroms and thickness 404' is more than 8 angstroms. In various embodiments, thickness 406' is as thin as 4, 5, 6, 7 or 8 angstroms. This thinness of layer 406 decreases resistance and increases TMR. Again, the use of a refractory metal in layer 406 allows for such a thin layer to be used and to withstand annealing temperatures (as compared to conventional MgO cap layers).
  • the tunnel barrier layer 404 includes magnesium oxide and the oxide layer 406 does not include magnesium oxide (but instead includes, for example, tantalum oxide and/or tungsten oxide). Thus, the two oxides may include different materials.
  • the tunnel barrier layer 404 generally includes a BCC (001) crystal structure (e.g., more than half of the layer has a consistent BCC (001) structure) and the oxide layer 406 generally consist of an inferior BCC (001) crystal structure (e.g., less than half of the layer has a consistent BCC (001) structure).
  • the tantalum oxide or tungsten oxide within cap layer 406 may force crystallization of free layer 405 (which may include CoFeB) to progress from tunnel barrier 404 instead of cap layer 406.
  • tunnel barrier 404 may be thicker than cap layer 406 and may have a more consistent BCC (001) crystal structure from which to grow a well crystallized free layer 405 (which will decrease resistance for free layer 405 and increase TMR for stack 400). Further, use of the above mentioned refractory metals may result in better band matching between barrier layer 404 and the free layer 405.
  • An embodiment includes first and second contact layers 401, 410 (e.g., including tantalum, ruthenium, or combinations thereof) and an additional magnetic layer 407 between the oxide layer 406 and the second contact layer 410.
  • the free magnetic layer 405 and the additional magnetic layer 407 both include cobalt and iron.
  • Such layers may also include boron depending on how much, if any, boron migrates out from one or both layers during annealing of layers in stack 400.
  • the additional magnetic layer 407 instead includes alternating layers that respectively include cobalt and palladium (or cobalt and platinum).
  • Layer 407 may provide stability/PMA (increased TMR) for stack 400. Further, layer 407 may provide protection for layer 406, which may be quite thin (e.g., 6 angstroms) and thus vulnerable during formation of, for example, contact layer 410.
  • An embodiment may include a pinning layer 402, otherwise known as a Synthetic Antiferromagnetic layer (SAF).
  • SAF Synthetic Antiferromagnetic layer
  • the free layer is a single layer 501 (approximately 1.0 nm thick) including CoFeB.
  • Figure 5B includes an embodiment where the free layer is a composite layer including a first layer 511 (approximately 1.55 nm thick) comprising boron and a second layer 512 (approximately 0.3 nm thick) comprising tungsten.
  • Figure 5C includes an embodiment where the free layer is a composite layer including a first layer 521 (approximately 1.55 nm thick) comprising boron, a second layer 522 comprising tungsten (approximately 0.3 nm thick), and a third layer 523 (approximately 0.3 nm thick) comprising boron.
  • Figure 5D includes an embodiment wherein (a) the free layer is a composite layer including first layer 531 (approximately 0.5 nm thick) and second layer 532 (approximately 0.4 nm thick), (b) the first layer is between the second layer and the tunnel barrier layer (not shown), and (c) the first layer includes a chemical composition with a higher percentage of boron (e.g., 30%) than a chemical composition of the second layer (e.g., 20%).
  • a chemical composition with a higher percentage of boron e.g., 30%
  • a chemical composition of the second layer e.g. 20%
  • the free layer is a composite layer including first and second layers, the first layer is between the second layer and the tunnel barrier layer, and the first layer is primarily located in a plane and has a thickness, orthogonal to the plane, that is thicker than the second layer.
  • layer 531 has a thickness 541 (e.g., 0.5 nm) that is thicker than thickness 542 (e.g., 0.4 nm) for layer 532.
  • FIG. 6 depicts an embodiment wherein memory 600 comprises a perpendicular STTM that includes MTJ 611.
  • the MTJ has PMA.
  • the MTJ comprises contacts 601, 610, pinning layer 602, fixed layer 603, tunnel barrier layer 604, free layer 605, cap layer 606 (e.g., tantalum oxide and/or tungsten oxide), and additional magnetic (e.g., CoFeB) layer 607.
  • the MTJ couples bit line 625 to selection switch 621 (e.g., transistor), word line 620, and sense line 615.
  • the MTJ may be located on a substrate.
  • the substrate is a bulk semiconductive material as part of a wafer.
  • the semiconductive substrate is a bulk semiconductive material as part of a chip that has been singulated from a wafer.
  • the semiconductive substrate is a semiconductive material that is formed above an insulator such as a semiconductor on insulator (SOI) substrate. There may be one or more layers between the MTJ and the substrate. There may be one or more layers above the MTJ.
  • Block 701 includes forming a MTJ including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free and fixed layers.
  • Block 702 includes forming an oxide layer in direct contact with the free magnetic layer, wherein: (a) the oxide layer comprises a member selected from the group consisting of tantalum, tungsten, or combinations thereof, and (b) the oxide layer is no thicker than 10 angstroms.
  • the thinness of the oxide cap layer has advantages (e.g., lower resistance) described above.
  • Block 703 includes annealing the free magnetic layer, at a temperature that is at least 390 degrees C, to crystallize the free magnetic layer with a BCC (001) crystal structure. This crystallization may be based on a BCC (001) structure from the tunnel barrier more so than from the cap oxide layer.
  • Block 703 includes subjecting the entire stack to an elevate temperature that is sufficient to cause annealing within the free layer.
  • system 900 may be a smartphone or other wireless communicator or any Internet of Things (IoT) device.
  • a baseband processor 905 is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system.
  • baseband processor 905 is coupled to an application processor 910, which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps.
  • Application processor 910 may further be configured to perform a variety of other computing operations for the device.
  • application processor 910 can couple to a user interface/display 920 (e.g., touch screen display).
  • application processor 910 may couple to a memory system including a non-volatile memory, namely a flash memory 930 (which may include memory cells such as those described in Figures 4 and/or 6) and a system memory, namely a DRAM 935 (which may include memory cells such as those described in Figures 4 and/or 6).
  • flash memory 930 may include a secure portion 932 (which may include memory cells such as those described in Figures 4 and/or 6) in which secrets and other sensitive information may be stored.
  • application processor 910 also couples to a capture device 945 such as one or more image capture devices that can record video and/or still images.
  • a universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure storage 942 (which may include memory cells such as those described in Figures 4 and/or 6) to store secure user information.
  • System 900 may further include a security processor 950 (e.g., Trusted Platform Module (TPM)) that may couple to application processor 910.
  • TPM Trusted Platform Module
  • a plurality of sensors 925, including one or more multi-axis accelerometers may couple to application processor 910 to enable input of a variety of sensed information such as motion and other environmental information.
  • one or more authentication devices 995 may be used to receive, for example, user biometric input for use in authentication operations.
  • a near field communication (NFC) contactless interface 960 is provided that communicates in a NFC near field via an NFC antenna 965. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities.
  • NFC near field communication
  • a power management integrated circuit (PMIC) 915 couples to application processor 910 to perform platform level power management. To this end, PMIC 915 may issue power management requests to application processor 910 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 915 may also control the power level of other components of system 900.
  • PMIC power management integrated circuit
  • RF transceiver 970 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol.
  • CDMA code division multiple access
  • GSM global system for mobile communication
  • LTE long term evolution
  • a GPS sensor 980 may be present, with location information being provided to security processor 950 for use as described herein when context information is to be used in a pairing process.
  • Other wireless communications such as receipt or transmission of radio signals (e.g., AM/FM) and other signals may also be provided.
  • radio signals e.g., AM/FM
  • WLAN transceiver 975 local wireless communications, such as according to a BluetoothTM or IEEE 802.11 standard can also be realized.
  • Multiprocessor system 1000 is a point-to-point interconnect system such as a server system, and includes a first processor 1070 and a second processor 1080 coupled via a point-to-point interconnect 1050.
  • processors 1070 and 1080 may be multicore processors such as SoCs, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b), although potentially many more cores may be present in the processors.
  • processors 1070 and 1080 each may include a secure engine 1075 and 1085 to perform security operations such as attestations, IoT network onboarding or so forth.
  • First processor 1070 further includes a memory controller hub (MCH) 1072 and point-to-point (P-P) interfaces 1076 and 1078.
  • second processor 1080 includes a MCH 1082 and P-P interfaces 1086 and 1088.
  • MCH's 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors. These memories may include memory cells such as those described in Figures 4 and/or 6.
  • First processor 1070 and second processor 1080 may be coupled to a chipset 1090 via P-P interconnects 1052 and 1054, respectively.
  • Chipset 1090 includes P-P interfaces 1094 and 1098.
  • chipset 1090 includes an interface 1092 to couple chipset 1090 with a high performance graphics engine 1038, by a P-P interconnect 1039.
  • chipset 1090 may be coupled to a first bus 1016 via an interface 1096.
  • Various input/output (I/O) devices 1014 may be coupled to first bus 1016, along with a bus bridge 1018 which couples first bus 1016 to a second bus 1020.
  • Various devices may be coupled to second bus 1020 including, for example, a keyboard/mouse 1022, communication devices 1026 and a data storage unit 1028 such as a non-volatile storage or other mass storage device (which may include memory cells such as those described in Figures 4 and/or 6).
  • data storage unit 1028 may include code 1030, in one embodiment.
  • data storage unit 1028 also includes a trusted storage 1029 (which may include memory cells such as those described in Figures 4 and/or 6) to store sensitive information to be protected.
  • a audio I/O 1024 may be coupled to second bus 1020.
  • module 1300 may be an Intel® CurieTM module that includes multiple components adapted within a single small module that can be implemented as all or part of a wearable device.
  • module 1300 includes a core 1310 (of course in other embodiments more than one core may be present).
  • core 1310 may be a relatively low complexity in-order core, such as based on an Intel Architecture® QuarkTM design.
  • core 1310 may implement a TEE as described herein.
  • Core 1310 couples to various components including a sensor hub 1320, which may be configured to interact with a plurality of sensors 1380, such as one or more biometric, motion environmental or other sensors.
  • a power delivery circuit 1330 is present, along with a non-volatile storage 1340 (which may include memory cells such as those described in Figures 4 and/or 6).
  • this circuit may include a rechargeable battery and a recharging circuit, which may in one embodiment receive charging power wirelessly.
  • One or more input/output (IO) interfaces 1350 such as one or more interfaces compatible with one or more of USB/SPI/I2C/GPIO protocols, may be present.
  • a wireless transceiver 1390 which may be a BluetoothTM low energy or other short-range wireless transceiver is present to enable wireless communications as described herein. Understand that in different implementations a wearable module can take many other forms. Wearable and/or IoT devices have, in comparison with a typical general purpose CPU or a GPU, a small form factor, low power requirements, limited instruction sets, relatively slow computation throughput, or any of the above.
  • an upper layer e.g., layer 406
  • a lower layer e.g., layer 405
  • the upper layer and/or lower layer may include oxidation at its surface/interface to the upper layer. Such a situation would still comprise an upper layer directly contacting the lower layer despite the lower layer including surface oxidation.
  • layers comprising CoFeB include layers 403, 405, 407
  • other embodiments may include some combination of the layers 403, 405, 407 including: CoFe/CoFeB (e.g., two of the three layers include CoFe and the other includes CoFeB or one or more of the layers includes both CoFe and CoFeB); CoFeB/Ta/CoFeB; or CoFe/CoFeB/Ta/CoFeB/CoFe (e.g., one layer includes sublayers of CoFe and CoFeB, another layer includes Ta, and another layer includes sublayers of CoFe and CoFeB).
  • other embodiments may include tunnel barriers having something other than MgO, such as other oxides (e.g., aluminum oxide).
  • layers 403, 405, 407 may include FeB with little to no cobalt in any of the layers.
  • Example 1 includes an apparatus comprising: a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free and fixed magnetic layers; and an oxide layer, directly contacting the free magnetic layer, comprising a member selected from the group consisting of niobium, molybdenum, tantalum, tungsten, rhenium, titanium, vanadium, chromium, zirconium, hafnium, ruthenium, rhodium, osmium, iridium, or combinations thereof.
  • MTJ magnetic tunnel junction
  • Example 2 includes the apparatus of example 1 wherein the oxide layer does not include magnesium.
  • Example 3 includes the apparatus of example 1 wherein the member is selected from the group consisting of tungsten, tantalum, or combinations thereof.
  • Example 4 includes the apparatus of example 3, wherein: the oxide layer is primarily located in a plane and includes a first thickness measured orthogonal to the plane; and the tunnel barrier layer includes a second thickness that is greater than the first thickness.
  • Example 5 includes the apparatus of example 4 wherein the member includes tungsten.
  • Example 6 includes the apparatus of example 4 wherein the member includes tantalum.
  • Example 7 includes the apparatus of example 4 wherein the tunnel barrier layer includes magnesium oxide and the oxide layer does not include magnesium oxide.
  • Example 7 includes the apparatus of example 4 wherein: the tunnel barrier layer includes at least one of magnesium oxide and aluminum oxide; and the oxide layer does not include magnesium oxide.
  • Example 8 includes the apparatus of example 4 wherein the tunnel barrier layer generally includes a BCC (001) crystal structure and the oxide layer generally does not include a BCC (001) crystal structure.
  • Another version of example 8 includes the apparatus of example 4 wherein the tunnel barrier layer generally includes a BCC (001) crystal structure and the oxide layer generally includes an inferior BCC (001) crystal structure.
  • example 8 includes the apparatus of example 4 wherein the tunnel barrier layer generally includes a BCC (001) crystal structure and no more than half of the oxide layer generally includes a BCC (001) crystal structure.
  • the oxide layer may include 0% BCC (001) crystal structure.
  • Example 9 includes the apparatus of example 4 wherein the oxide layer is more amorphous than the tunnel barrier layer.
  • Another version of example 9 includes the apparatus of example 4 wherein the oxide layer is less BCC (001) crystallized than the tunnel barrier layer.
  • Example 10 includes the apparatus of example 4 wherein the first thickness is less than 10 angstroms and the second thickness is more than 8 angstroms.
  • Example 10 includes the apparatus of example 4 wherein the first thickness is less than 8 angstroms and the second thickness is more than 8 angstroms.
  • Example 11 includes the apparatus of example 10 comprising: first and second contact layers; and an additional magnetic layer between the oxide layer and the second contact layer.
  • Example 12 includes the apparatus of example 11 wherein the free magnetic layer and the additional magnetic layer both include cobalt and iron.
  • the free layer may not include cobalt.
  • Example 13 includes the apparatus of example 11 wherein the additional magnetic layer is a composite layer including alternating layers that respectively include cobalt and palladium.
  • Another version of claim 13 includes the apparatus of example 11 wherein the additional magnetic layer is a composite layer including alternating layers that respectively include cobalt and platinum.
  • Example 14 includes the apparatus of example 4 wherein the free magnetic layer is a composite layer including a first layer comprising cobalt and iron and a second layer comprising tungsten.
  • the first layer may not include cobalt.
  • Example 15 includes the apparatus of example 4 wherein (a) the free layer is a composite layer including first and second layers, (b) the first layer is between the second layer and the tunnel barrier layer, and (c) the first layer includes a chemical composition with a higher percentage of boron than a chemical composition of the second layer.
  • Example 16 includes the apparatus of example 4 wherein: (a) the free layer is a composite layer including first and second layers, (b) the first layer is between the second layer and the tunnel barrier layer, and (c) the first layer is primarily located in a plane and has a thickness, orthogonal to the plane, that is thicker than the second layer.
  • Example 17 includes the apparatus of example 4 wherein the free layer is not a composite layer and includes a single layer.
  • Example 18 includes the apparatus of example 1 comprising a perpendicular spin torque transfer memory (STTM) that includes the MTJ.
  • Example 19 includes the apparatus of example 1, wherein the MTJ has perpendicular anisotropy.
  • Example 20 includes a method comprising: forming a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free and fixed layers; and forming an oxide layer in direct contact with the free magnetic layer, wherein: (a) the oxide layer comprises a member selected from the group consisting of tantalum, tungsten, or combinations thereof, and (b) the oxide layer no thicker than 10 angstroms; and annealing the free magnetic layer, at a temperature that is at least 390 degrees C, to crystallize the free magnetic layer with a BCC (001) crystal structure.
  • MTJ magnetic tunnel junction
  • To "crystallize the free magnetic layer with a BCC (001) crystal structure” includes crystallizing at least a half of the free layer with a BCC (001) structure.
  • An embodiment includes crystallizing the free layer primarily in response to the tunnel barrier and not primarily in response to the cap oxide layer.
  • Example 21 includes the method of example 20 comprising: forming an additional magnetic layer on the oxide layer; and forming a contact layer on the additional magnetic layer; wherein the free magnetic layer and the additional magnetic layer both include cobalt and iron.
  • the free magnetic layer and the additional magnetic layer do not include cobalt.
  • Example 22 includes the method of example 21 wherein the free layer includes tungsten.
  • Example 23 includes an apparatus comprising: a magnetic tunnel junction (MTJ) including free and fixed layers and a tunnel barrier layer; and an oxide layer, directly contacting the free layer, comprising a member selected from the group consisting of tantalum, tungsten, or combinations thereof; wherein the oxide layer is thinner than 10 angstroms and the tunnel barrier layer is thicker than 8 angstroms; wherein the tunnel barrier layer includes magnesium oxide and the oxide layer does not include magnesium oxide.
  • MTJ magnetic tunnel junction
  • the tunnel barrier may be thicker than 8 Angstroms and the cap oxide layer may be 3, 4, 5, 6, or 7 Angstroms.
  • Example 24 includes the apparatus of example 23 comprising: first and second contact layers; and an additional magnetic layer between the oxide layer and the second contact layer.
  • Example 25 includes the apparatus of example 24 wherein the oxide layer is more amorphous than the tunnel barrier layer.
  • Another version of example 25 includes the apparatus of example 24 wherein the oxide layer is less BCC (001) crystallized than the tunnel barrier layer.
  • Example 26 includes a system comprising: a processor; and a memory, coupled to the processor, according to any one of examples 1 to 18.
  • Example 27 includes a system comprising: a processor; and a memory, coupled to the processor, according to example 1.
  • Another version of example 27 includes the apparatus according to any of examples 3 to 18 wherein the oxide layer does not include magnesium.
  • Example 28 includes the apparatus according to any of examples 2 and 4 to 18 wherein the member is selected from the group consisting of tungsten, tantalum, or combinations thereof.
  • Example 29 includes the apparatus according to any of examples 2 to 3 and 5 to 18, wherein: the oxide layer is primarily located in a plane and includes a first thickness measured orthogonal to the plane; and the tunnel barrier layer includes a second thickness that is greater than the first thickness.
  • Example 30 includes the apparatus according to any of examples 2, 4 and 7 to 18 wherein the member includes tungsten.
  • Example 31 includes the apparatus according to any of examples 2, 4 and 7 to 18 wherein the member includes tantalum.
  • Example 32 includes the apparatus according to any of examples 2 to 6 and 8 to 18 wherein: the tunnel barrier layer includes at least one of magnesium oxide and aluminum oxide; and the oxide layer does not include magnesium oxide.
  • Example 33 includes the apparatus according to any of examples 2 to 7 and 9 to 18 wherein the tunnel barrier layer generally includes a BCC (001) crystal structure and no more than half of the oxide layer generally includes a BCC (001) crystal structure.
  • Example 34 includes the apparatus according to any of examples 2 to 8 and 10 to 18 wherein the oxide layer is less BCC (001) crystallized than the tunnel barrier layer.
  • Example 35 includes the apparatus according to any of examples 2 to 9 and 11 to 18wherein the first thickness is less than 8 angstroms and the second thickness is more than 8 angstroms.
  • Example 36 includes the apparatus according to any of examples 2 to 10 and 12 to 18 comprising: first and second contact layers; and an additional magnetic layer between the oxide layer and the second contact layer.
  • Example 37 includes the apparatus according to any of examples 2 to 10 and 14 to 18 wherein the free magnetic layer and the additional magnetic layer both include cobalt and iron.
  • Example 38 includes the apparatus according to any of examples 2 to 10 and 14 to 18wherein the additional magnetic layer is a composite layer including alternating layers that respectively include cobalt and palladium.
  • Example 39 includes the apparatus according to any of examples 2 to 13 and 18 wherein the free magnetic layer is a composite layer including a first layer comprising cobalt and iron and a second layer comprising tungsten.
  • Example 40 includes the apparatus according to any of examples 2 to 13 and 18 wherein (a) the free layer is a composite layer including first and second layers, (b) the first layer is between the second layer and the tunnel barrier layer, and (c) the first layer includes a chemical composition with a higher percentage of boron than a chemical composition of the second layer.
  • Example 41 includes the apparatus according to any of examples 2 to 13 and 18 wherein: (a) the free layer is a composite layer including first and second layers, (b) the first layer is between the second layer and the tunnel barrier layer, and (c) the first layer is primarily located in a plane and has a thickness, orthogonal to the plane, that is thicker than the second layer.
  • Example 42 includes the apparatus according to any of examples 2 to 13 and 18 wherein the free layer is not a composite layer and includes a single layer.
  • Example 43 includes the apparatus according to any of examples 2 to 17 comprising a perpendicular spin torque transfer memory (STTM) that includes the MTJ.
  • STTM perpendicular spin torque transfer memory
  • Example 44 includes the apparatus according to any of examples 23 to 24 wherein the oxide layer is less BCC (001) crystallized than the tunnel barrier layer.
  • terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top” surface of that substrate; the substrate may actually be in any orientation so that a "top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.”
  • the term “on” as used herein does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer.
  • the embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

Selon un mode de réalisation, cette invention concerne un appareil comprenant : une jonction tunnel magnétique (MTJ) comprenant une couche magnétique libre, une couche magnétique fixe, et une couche barrière tunnel entre les couches magnétiques libre et fixe; et une couche d'oxyde, en contact direct avec la couche magnétique libre, comprenant un élément choisi dans le groupe constitué par le niobium, le molybdène, le tantale, le tungstène, le rhénium, le titane, le vanadium, le chrome, le zirconium, le hafnium, le ruthénium, le rhodium, l'osmium, l'iridium ou des combinaisons de ceux-ci. L'invention comprend en outre d'autres modes de réalisation.
PCT/US2017/025247 2017-03-31 2017-03-31 Mémoire spintronique avec couche de couverture à oxyde métallique WO2018182663A1 (fr)

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CN111613635B (zh) * 2019-02-22 2024-04-23 桑迪士克科技有限责任公司 垂直自旋转移矩mram存储器单元

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