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WO2018182642A1 - Mémoire spintronique comportant une couche de recouvrement à faible résistance - Google Patents

Mémoire spintronique comportant une couche de recouvrement à faible résistance Download PDF

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Publication number
WO2018182642A1
WO2018182642A1 PCT/US2017/025147 US2017025147W WO2018182642A1 WO 2018182642 A1 WO2018182642 A1 WO 2018182642A1 US 2017025147 W US2017025147 W US 2017025147W WO 2018182642 A1 WO2018182642 A1 WO 2018182642A1
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WIPO (PCT)
Prior art keywords
layer
additional
metal
free
oxide
Prior art date
Application number
PCT/US2017/025147
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English (en)
Inventor
Mark L. Doczy
Brian S. Doyle
Christopher J. WIEGAND
Kevin P. O'brien
Kaan OGUZ
Charles C. Kuo
Ricky J. TSENG
Daniel G. OUELLETTE
Md Tofizur Rahman
Angeline K. SMITH
Justin S. BROCKMAN
Oleg Golonzka
Tahir Ghani
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Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/025147 priority Critical patent/WO2018182642A1/fr
Publication of WO2018182642A1 publication Critical patent/WO2018182642A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Materials of the active region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type

Definitions

  • Embodiments of the invention are in the field of semiconductor devices and, in particular, memory.
  • FIG. 1 includes spin transfer torque random access memory (STTRAM), a form of STTM.
  • Figure 1 includes a MTJ consisting of ferromagnetic (FM) layers 125, 127 and tunneling barrier 126 (e.g., magnesium oxide (MgO)).
  • the MTJ couples bit line (BL) 105 to selection switch 120 (e.g., transistor), word line (WL) 110, and sense line (SL) 115.
  • Memory 100 is "read” by assessing the change of resistance (e.g., tunneling magnetoresi stance (TMR)) for different relative magnetizations of FM layers 125, 127.
  • TMR tunneling magnetoresi stance
  • MTJ resistance is determined by the relative magnetization directions of layers 125, 127.
  • Layer 127 is the "reference layer” or “fixed layer” because its magnetization direction is fixed.
  • Layer 125 is the "free layer” because its magnetization direction is changed by passing a driving current polarized by the reference layer (e.g., positive voltage applied to layer 127 rotates the magnetization direction of layer 125 opposite to that of layer 127 and negative voltage applied to layer 127 rotates the magnetization direction of layer 125 to the same direction of layer 127).
  • Figure 1 depicts a conventional magnetic memory cell.
  • Figures 2-3 depict conventional MTJs.
  • Figure 4 includes a memory stack in an embodiment.
  • Figures 5A, 5B, 5C, 5D include embodiments of free layers.
  • Figure 6 includes a memory cell in an embodiment.
  • Figure 7 depicts a method of forming a memory in an embodiment.
  • Figures 8, 9, 10 depict systems for use with embodiments.
  • Some embodiments may have some, all, or none of the features described for other embodiments.
  • First, “second”, “third” and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.
  • Connected may indicate elements are in direct physical or electrical contact with each other and “coupled” may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact.
  • similar or same numbers may be used to designate same or similar parts in different figures, doing so does not mean all figures including similar or same numbers constitute a single or same embodiment.
  • CMOS complementary metal-oxide-semiconductor
  • spin polarization which concerns the degree to which the spin or intrinsic angular momentum of elementary particles is aligned with a given direction
  • spintronics a branch of electronics concerning the intrinsic spin of an electron, its associated magnetic moment, and the electron's fundamental electronic charge
  • TMR Spintronics devices
  • STT spin polarized electrons
  • CMOS devices include, for example, spintronics devices implemented in memory (e.g., 3 terminal STTRAM), spin logic devices (e.g., logic gates), tunnel field-effect transistors (TFETs), impact ionization MOS (JJVIOS) devices, nano-electro-mechanical switches (NEMS), negative common gate FETs, resonant tunneling diodes (RTD), single electron transistors (SET), spin FETs, nanomagnet logic (NML), domain wall logic, domain wall memory, magnetic sensors, and the like.
  • spintronics devices implemented in memory (e.g., 3 terminal STTRAM), spin logic devices (e.g., logic gates), tunnel field-effect transistors (TFETs), impact ionization MOS (JJVIOS) devices, nano-electro-mechanical switches (NEMS), negative common gate FETs, resonant tunneling diodes (RTD), single electron transistors (SET), spin FETs, nanomagnet logic (NML), domain wall logic, domain wall
  • one form of STTM includes perpendicular STTM (pSTTM).
  • pSTTM perpendicular STTM
  • a perpendicular MTJ generates magnetization "out of plane”. This reduces the switching current needed to switch between high and low memory states. This also allows for better scaling (e.g., smaller size memory cells).
  • Traditional MTJs are converted to pMTJs by, for example, thinning the free layer, thereby making the tunnel barrier/free layer interface more dominant in magnetic field influence (and the interface promotes anisotropic out of plane magnetization).
  • Figure 2 includes such a system 200 with cobalt, iron, boron (CoFeB) free layer 225 interfacing magnesium oxide (MgO) tunnel barrier 226, which further couples to CoFeB fixed layer 227 and Tantalum (Ta) contacts 214 (which may couple to a selection switch such as transistor 120 of Figure 1), 216 (which may couple, by way of one or more vias, to a bit line such as bit line 105 of Figure 1).
  • CoFeB cobalt, iron, boron
  • MgO magnesium oxide
  • Ta Tantalum
  • Figure 3 depicts a system 300 with a MTJ, where a second oxidized MgO interface 320 (sometimes referred to as a "cap layer”) contacts CoFeB free layer 325 (which further couples to a tunnel barrier MgO 326, which is formed on CoFeB fixed layer 327).
  • a second oxidized MgO interface 320 (sometimes referred to as a "cap layer”) contacts CoFeB free layer 325 (which further couples to a tunnel barrier MgO 326, which is formed on CoFeB fixed layer 327).
  • Adding cap layer 320 may increase stability for the memory, which is a problem for devices such as the device of Figure 2.
  • Figure 3 includes MgO at both free layer interfaces (i.e., layers 320, 326).
  • MgO layer 320 on top of CoFeB free layer 325 increases the memory's total resistance significantly (as compared to having just one oxide layer interface the free layer as in Figure 2), which makes the design impractical for scaled devices (e.g., 22 nm) because of degradation in resistance-area (RA) product and TMR.
  • RA resistance-area
  • RA product refers to a measurement unequal to resistivity. Resistivity has units in ohm-cm, whereas RA product has units in ohm-um 2 (and is based on material resistivity (p), dot area (A), and MgO thickness (T Mg o) such that increasing MgO thickness exponentially increases the RA product of the device). While resistivity represents an "inherent resistance” and is independent of the thickness of a material layer, RA product is exponentially proportional to the thickness of the material (e.g., MgO thickness). (Regarding "thickness", layer 320 is disposed “horizontally” for purposes of discussion herein and has a “thickness” in the vertical orientation. The length and width for layer 320 are “in plane” and the height or thickness is “out of plane”.)
  • FIG. 4 includes an embodiment that addresses the problem (identified by Applicant) of low TMR and higher RA product associated with boost magnet layers.
  • Such an embodiment includes a "spike layer” to lower RA product and increase TMR.
  • the spike layer includes a relatively high atomic number (Z) metal, such as tantalum, tungsten, and/or molybdenum.
  • the spike layer may be 0.5 to 12A thick and be located between a stability boost magnet layer and a cap layer (e.g., MgO).
  • the spike layer lowers the resistance of the cap layer MgO by damaging the cap layer with metal atoms from the spike layer.
  • the metal (e.g., Ta) in the spike layer projects from the spike layer into the cap layer, thereby damaging the cap layer.
  • the damaged areas which may include metal atom spikes emanating from the spike layer, consequently have lower series resistance. This causes a greater percentage of the resistance drop to occur across the spin filter (i.e., tunnel barrier), which increases TMR (as discussed above, lowering the RA contribution from the cap layer (e.g., layer 320 in Figure 3) increases TMR for the memory stack).
  • Figure 4 includes a memory in an embodiment.
  • Memory 400 includes a MTJ 411 including a free magnetic layer 405, a fixed magnetic layer 403, and a tunnel barrier layer 404 between the free and fixed layers.
  • the tunnel barrier layer 404 directly contacts a first side 405' of the free layer 405.
  • a first side 406' of an oxide layer 406 directly contacts a second side 405" of the free layer 405.
  • a first side 407' of an additional layer 407 (spike layer) directly contacts a second side 406" of the oxide layer 406.
  • the oxide layer 406 includes a metal and the spike layer 407 also includes the same metal.
  • the metal may include hafnium, tantalum, tungsten, and/or molybdenum.
  • the metal includes tantalum.
  • the metal may be included in a projection 412 that projects from the spike layer 407 into the oxide layer 406. So while the cap layer may include another metal, such as magnesium, it also includes (in the form of atoms from the spike layer) the metal also present in the spike layer.
  • the projection may extend from the spike layer partially into the upper portion of the oxide layer 406 or may extend across a majority of the oxide layer into a lower portion of oxide layer 406 adjacent free layer 405.
  • the projection (or projections) may extend fully from a top 406" of the oxide layer to a bottom 406' of the oxide layer.
  • the projection may be contiguous or non-contiguous.
  • the resulting image may show individual metal atoms that are primarily located within a spike layer (e.g., layer 407).
  • the image may also include clusters of metal atoms and/or individual metal atoms that have moved from the spike layer into the oxide layer (e.g., layer 406).
  • a "spike” as used herein is not to be construed in a literal sense entailing, for example, a mechanical spike used to secure two structures to each other but instead entails atoms projecting through another layer thereby causing damage to the layer and decreasing the resistance of the layer.
  • relatively heavy metals e.g., metals with a Z greater than 42
  • relatively heavy metals are used in some embodiments due to their ability to cause an amount of damage (due to their Z value) to the oxide that reduces the resistance of the oxide while still retaining some or all of the perpendicular anisotropy offered by the oxide cap layer.
  • Increasing the proximity of the spike layer to the target cap layer increases the amount of atoms that will form the projection within the cap layer (thereby decreasing cap layer resistance). Consequently, some embodiments place the spike layer directly over and in direct contact with the cap layer. The spiking may occur primarily during the deposition of the metal (e.g., via a physical vapor deposition (PVD) sputter process) while manufacturing the memory.
  • PVD physical vapor deposition
  • Memory 400 may include first and second contact layers 401, 410 and an additional magnetic layer 408 between the spike layer 407 and the contact layer 410.
  • the additional magnetic layer may be a "stability boost magnet" that helps stabilize the memory state of memory 400.
  • free magnetic layer 405 and the additional magnetic layer 408 both include CoFeB.
  • one or both of layers 405, 408 may be a composite layer including alternating layers that respectively include cobalt and (a) palladium and/or (b) platinum.
  • a second side 407" of the spike layer 407 directly contacts a first side 408' of the additional magnetic layer 408.
  • contact layers 401, 410 each include a metal such as tantalum and/or ruthenium.
  • An embodiment may include a pinning layer 402, otherwise known as a Synthetic Antiferromagnetic layer (SAF).
  • SAF Synthetic Antiferromagnetic layer
  • An embodiment may include a cladding layer 409 between the contact layers 401, 410.
  • a cladding layer may include, for example, tantalum.
  • a cladding layer is a layer that substantially covers a portion of a structure, such as memory 400.
  • layer 409 is shown primarily covering an upper surface of layer 408.
  • Layer 409 is not included in all embodiments. In some embodiments layer 409 serves as a contact layer (so that layer 410 may be unnecessary). Layer 409 may serve as an adhesion layer for the top contact 410 and may include, for example, tantalum.
  • An embodiment may include an additional MgO layer on top of magnet layer 408.
  • a spike layer (similar to spike layer 407) would be directly on top of the additional MgO layer to prevent added RA.
  • This spike layer on the additional MgO layer may include layer 409 (the cladding or adhesion layer), which is often composed of Ta (and Ta may provide the spikes into the additional MgO layer).
  • Figure 4 looks much as Figure 4 looks but includes an additional MgO layer between layers 408 and 409 and an additional spike layer on the additional MgO layer.
  • the first side 407' of the spike layer 407 is primarily located in a plane and the spike layer has a thickness 417, orthogonal to the plane, between 0.5 and 12 angstroms (however in other embodiments the thickness is less than 3, 5, 7, 9, 11, 14, 16, or 18 angstroms).
  • thickness 417 is less than a thickness for oxide layer 406 (see thickness 416).
  • thickness 417 is less than a thickness for free layer 405 (see thickness 415).
  • thickness 417 is less than a thickness for the additional magnetic layer 408 (see thickness 418).
  • thickness 417 is less than each of thicknesses 415, 416, 418.
  • the boost magnet layer 408 may be a composite layer with a thin tungsten layer, and the tungsten layer may be thinner than the spike layer 407 but the magnet layer as a whole would be thicker than the spike layer.
  • These thicknesses are critical values in some embodiments in order to arrive at a proper RA product and TMR levels. However, not all embodiments require that thickness 417 is less than each or any of thicknesses 415, 416, 418.
  • the spike layer thickness may be on the lower end of the above thickness range (e.g., less than 3 angstroms) provided it has enough material to damage the MgO layer.
  • the layer may be difficult to image (e.g., with a TEM image) but the material (e.g., Ta) would still be detectable (e.g., element analysis) in the cap layer 406.
  • Applicant determined forming the boost magnet layer 408 thicker than the spike layer 407 allows the stability contribution by the boost magnet to not be cancelled by an overly thick spike layer.
  • spike layer 407 may not couple magnetically to the free layer 405 due to the distance between layers 405, 408 (which may decrease stability benefits of layer 408).
  • the magnet layer 408 needs to be thick enough so that it is indeed magnetic (e.g., at least 5-6 angstroms thick to be somewhat magnetic and thicker than 10 angstroms where greater magnetic field is beneficial).
  • above embodiments provide for a spike layer 407 as small as .5 angstroms but in other embodiments layer 407 has a minimum thickness of about 5 A. Such a thickness allows magnet layer 408 to couple to free layer 405.
  • the thickness for layer 408 may vary so long as layer 408 acts as a magnet (which may require layer 408 be at least 6 angstroms thick). With good coupling between layers 408 and 405 magnet layer 408 need not necessarily be thicker than spike layer 407.
  • the free layer is a single layer 501 (approximately 1.0 nm thick) including CoFeB.
  • Figure 5B includes an embodiment where the free layer is a composite layer including a first layer 511 (approximately 1.55 nm thick) comprising boron and a second layer 512 (approximately 0.3 nm thick) comprising tungsten.
  • Figure 5C includes an embodiment where the free layer is a composite layer including a first layer 521 (approximately 1.55 nm thick) comprising boron, a second layer 522 comprising tungsten (approximately 0.3 nm thick), and a third layer 523 (approximately 0.3 nm thick) comprising boron.
  • Figure 5D includes an embodiment wherein (a) the free layer is a composite layer including first 531 (approximately 0.5 nm thick) and second layers 532 (approximately 0.4 nm thick), (b) the first layer is between the second layer and the tunnel barrier layer (not shown), and (c) the first layer includes a chemical composition with a higher percentage of boron (e.g., 30%) than a chemical composition of the second layer (e.g., 20%).
  • a chemical composition with a higher percentage of boron e.g., 30%
  • a chemical composition of the second layer e.g. 20%
  • the free layer is a composite layer including first and second layers, the first layer is between the second layer and the tunnel barrier layer, and the first layer is primarily located in a plane and has a thickness, orthogonal to the plane, that is thicker than the second layer.
  • layer 531 has a thickness 541 (e.g., 0.5 nm) that is thicker than thickness 542 (e.g., 0.4 nm) for layer 532.
  • the tunnel barrier layer 404 and the oxide layer 406 both include magnesium oxide.
  • layer 404 and/or layer 406 may include any one or more of the following: tungsten oxide (W0 2 ), vanadium oxide (VO and/or V 2 0 2 ), indium oxide (InOx), aluminum oxide (A1 2 0 3 ), ruthenium oxide (RuOx), MgAlOx, HfOx, and/or TaO.
  • layer 404 includes MgO and layer 406 includes any one or more of the following: W0 2 , VO, V 2 0 2 , InOx, A1 2 0 3 , RuOx, MgAlOx, HfOx, and/or TaO.
  • Figure 4 is an example of an embodiment whereby a high conductivity oxide, such as spiked layer 406, is formed next to a spiking layer such as layer 407, and a boost magnet layer 408.
  • a high conductivity oxide such as spiked layer 406
  • a spiking layer such as layer 407
  • a boost magnet layer 408 Such a combination of layers induces increased stability without unnecessarily increasing RA product and/or decreasing TMR (as is the case with the dual MgO layers found in Figure 3).
  • this arrangement of layers cap layer, spike layer, boost magnet layer
  • FIG. 6 depicts an embodiment wherein memory 800 comprises a perpendicular STTM that includes MTJ 811.
  • the MTJ has perpendicular anisotropy.
  • the MTJ comprises contacts 801, 810, pinning layer 802, fixed layer 803, tunnel barrier layer 804, free layer 805, cap layer 806, spike layer 807, composite stability boost magnet layer 808 (including alternating cobalt and palladium layers to enhance stability for the small film MTJ), and cladding layer 809.
  • composite stability boost magnet layer 808 includes alternating cobalt and platinum layers to enhance stability for the small film MTJ.
  • the MTJ couples bit line 825 to selection switch 821 (e.g., transistor), word line 820, and sense line 815.
  • the MTJ may be located on a substrate.
  • the substrate is a bulk semiconductive material as part of a wafer.
  • the semiconductive substrate is a bulk semiconductive material as part of a chip that has been singulated from a wafer.
  • the semiconductive substrate is a semiconductive material that is formed above an insulator such as a semiconductor on insulator (SOI) substrate. There may be one or more layers between the MTJ and the substrate. There may be one or more layers above the MTJ.
  • SOI semiconductor on insulator
  • Block 701 includes forming a MTJ on a substrate, the MTJ including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer.
  • Block 702 includes forming a first side of an oxide layer directly contacting a second side of the free layer.
  • Block 703 includes sputtering a metal (e.g., with argon gas) to form an additional layer that has a first side directly contacting a second side of the oxide layer.
  • the metal includes one or more of hafnium, tantalum, tungsten, platinum, iridium, molybdenum, and combinations thereof.
  • Block 704 includes forming a projection which includes the metal and projects from the additional layer into the oxide layer. Forming the projection in block 704 may be in response to sputtering the metal (and/or annealing the metal in some embodiments).
  • system 900 may be a smartphone or other wireless communicator or any Internet of Things (IoT) device.
  • a baseband processor 905 is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system.
  • baseband processor 905 is coupled to an application processor 910, which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps.
  • Application processor 910 may further be configured to perform a variety of other computing operations for the device.
  • application processor 910 can couple to a user interface/display 920 (e.g., touch screen display).
  • application processor 910 may couple to a memory system including a non-volatile memory, namely a flash memory 930 (which may include memory cells such as those described in Figures 4 and/or 6) and a system memory, namely a DRAM 935 (which may include memory cells such as those described in Figures 4 and/or 6).
  • flash memory 930 may include a secure portion 932 (which may include memory cells such as those described in Figures 4 and/or 6) in which secrets and other sensitive information may be stored.
  • application processor 910 also couples to a capture device 945 such as one or more image capture devices that can record video and/or still images.
  • a universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure storage 942 (which may include memory cells such as those described in Figures 4 and/or 6) to store secure user information.
  • System 900 may further include a security processor 950 (e.g., Trusted Platform Module (TPM)) that may couple to application processor 910.
  • TPM Trusted Platform Module
  • a plurality of sensors 925, including one or more multi-axis accelerometers may couple to application processor 910 to enable input of a variety of sensed information such as motion and other environmental information.
  • one or more authentication devices 995 may be used to receive, for example, user biometric input for use in authentication operations.
  • a near field communication (NFC) contactless interface 960 is provided that communicates in a NFC near field via an NFC antenna 965. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities.
  • NFC near field communication
  • a power management integrated circuit (PMIC) 915 couples to application processor 910 to perform platform level power management. To this end, PMIC 915 may issue power management requests to application processor 910 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 915 may also control the power level of other components of system 900.
  • PMIC power management integrated circuit
  • RF transceiver 970 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol.
  • CDMA code division multiple access
  • GSM global system for mobile communication
  • LTE long term evolution
  • a GPS sensor 980 may be present, with location information being provided to security processor 950 for use as described herein when context information is to be used in a pairing process.
  • Other wireless communications such as receipt or transmission of radio signals (e.g., AM/FM) and other signals may also be provided.
  • radio signals e.g., AM/FM
  • WLAN transceiver 975 local wireless communications, such as according to a BluetoothTM or IEEE 802.11 standard can also be realized.
  • Multiprocessor system 1000 is a point-to-point interconnect system such as a server system, and includes a first processor 1070 and a second processor 1080 coupled via a point-to-point interconnect 1050.
  • processors 1070 and 1080 may be multicore processors such as SoCs, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b), although potentially many more cores may be present in the processors.
  • processors 1070 and 1080 each may include a secure engine 1075 and 1085 to perform security operations such as attestations, IoT network onboarding or so forth.
  • First processor 1070 further includes a memory controller hub (MCH) 1072 and point-to-point (P-P) interfaces 1076 and 1078.
  • second processor 1080 includes a MCH 1082 and P-P interfaces 1086 and 1088.
  • MCH's 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors. These memories may include memory cells such as those described in Figures 4 and/or 6.
  • First processor 1070 and second processor 1080 may be coupled to a chipset 1090 via P-P interconnects 1052 and 1054, respectively.
  • Chipset 1090 includes P-P interfaces 1094 and 1098.
  • chipset 1090 includes an interface 1092 to couple chipset 1090 with a high performance graphics engine 1038, by a P-P interconnect 1039.
  • chipset 1090 may be coupled to a first bus 1016 via an interface 1096.
  • Various input/output (I/O) devices 1014 may be coupled to first bus 1016, along with a bus bridge 1018 which couples first bus 1016 to a second bus 1020.
  • Various devices may be coupled to second bus 1020 including, for example, a keyboard/mouse 1022, communication devices 1026 and a data storage unit 1028 such as a non-volatile storage or other mass storage device (which may include memory cells such as those described in Figures 4 and/or 6).
  • data storage unit 1028 may include code 1030, in one embodiment.
  • data storage unit 1028 also includes a trusted storage 1029 (which may include memory cells such as those described in Figures 4 and/or 6) to store sensitive information to be protected.
  • a audio I/O 1024 may be coupled to second bus 1020.
  • module 1300 may be an Intel® CurieTM module that includes multiple components adapted within a single small module that can be implemented as all or part of a wearable device.
  • module 1300 includes a core 1310 (of course in other embodiments more than one core may be present).
  • core 1310 may implement a TEE as described herein.
  • Core 1310 couples to various components including a sensor hub 1320, which may be configured to interact with a plurality of sensors 1380, such as one or more biometric, motion environmental or other sensors.
  • a power delivery circuit 1330 is present, along with a non-volatile storage 1340 (which may include memory cells such as those described in Figures 4 and/or 6).
  • this circuit may include a rechargeable battery and a recharging circuit, which may in one embodiment receive charging power wirelessly.
  • One or more input/output (IO) interfaces 1350 such as one or more interfaces compatible with one or more of USB/SPI/I2C/GPIO protocols, may be present.
  • a wireless transceiver 1390 which may be a BluetoothTM low energy or other short-range wireless transceiver is present to enable wireless communications as described herein. Understand that in different implementations a wearable module can take many other forms. Wearable and/or IoT devices have, in comparison with a typical general purpose CPU or a GPU, a small form factor, low power requirements, limited instruction sets, relatively slow computation throughput, or any of the above.
  • a first layer e.g., an oxide layer
  • a second layer e.g., spike layer
  • first layer e.g., an oxide layer
  • second layer e.g., spike layer
  • embodiments include fixed and free layers comprising CoFeB
  • other embodiments may include some combination of the fixed and free layers and boost magnet including CoFe/CoFeB (e.g., two of the three layers include CoFe and the other includes CoFeB or one or more of the layers includes both CoFe and CoFeB); CoFeB/Ta/CoFeB; or CoFe/CoFeB/Ta/CoFeB/CoFe.
  • other embodiments may include tunnel barriers having something other than MgO, such as other oxides (e.g., aluminum oxide).
  • Some embodiments may include magnetic layers 405 and/or 408 that do not include cobalt (e.g., may include FeB).
  • Example 1 includes an apparatus comprising: a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free and fixed layers; the tunnel barrier layer directly contacting a first side of the free layer; and a first side of an oxide layer directly contacting a second side of the free layer; and a first side of an additional layer directly contacting a second side of the oxide layer; wherein the oxide layer includes a metal and the additional layer includes the metal.
  • MTJ magnetic tunnel junction
  • the oxide layer includes an oxynitride layer.
  • Example 2 includes the apparatus of example 1 wherein the metal is selected from the group consisting of hafnium, tantalum, tungsten, molybdenum, zirconium, niobium, titanium, vanadium, or combinations thereof.
  • Example 3 includes the apparatus of example 2 wherein the metal includes tantalum.
  • Example 4 includes the apparatus of example 2 wherein the metal is included in a projection that projects from the additional layer into the oxide layer.
  • Example 5 includes the apparatus of example 2 comprising first and second contact layers and an additional magnetic layer between the additional layer and the second contact layer.
  • Example 6 includes the apparatus of example 5 wherein the free magnetic layer and the additional magnetic layer both include cobalt.
  • Example 7 includes the apparatus of example 6 wherein the additional magnetic layer is a composite layer including alternating layers that respectively include cobalt and palladium.
  • Another version of example 7 includes the apparatus of example 6 wherein the additional magnetic layer is a composite layer including alternating layers that respectively include cobalt and platinum.
  • Example 8 includes the apparatus of example 6 wherein the free magnetic layer and the additional magnetic layer both include iron and boron.
  • Example 9 includes the apparatus of example 5 wherein a second side of the additional layer directly contacts a first side of the additional magnetic layer.
  • Example 10 includes the apparatus of example 5 wherein the first and second contact layers each include an additional metal selected from the group consisting of tantalum or ruthenium.
  • Example 11 includes the apparatus of example 2 wherein the first side of the additional layer is primarily located in a plane and the additional layer has a thickness, orthogonal to the plane, between 0.5 and 12 angstroms.
  • Example 12 includes the apparatus of example 11 wherein the thickness of the additional layer is less than a thickness for each of the oxide layer, the free layer, and the additional magnetic layer.
  • Example 13 includes the apparatus of example 2 wherein the free layer is a composite layer including a first layer comprising boron and a second layer comprising tungsten.
  • Example 14 includes the apparatus of example 2 wherein (a) the free layer is a composite layer including first and second layers, (b) the first layer is between the second layer and the tunnel barrier layer, and (c) the first layer includes a chemical composition with a higher percentage of boron than a chemical composition of the second layer.
  • Example 15 includes the apparatus of example 2 wherein: (a) the free layer is a composite layer including first and second layers, (b) the first layer is between the second layer and the tunnel barrier layer, and (c) the first layer is primarily located in a plane and has a thickness, orthogonal to the plane, that is thicker than the second layer.
  • Example 16 includes the apparatus of example 2 wherein the tunnel barrier layer and the oxide layer both include magnesium oxide.
  • Another version of example 15 includes the apparatus of example 2 wherein the free layer is not a composite layer and includes a single layer.
  • the single layer free layer may offer low resistance but also entail heightened instability due to a lack of layer interfaces associated with composite free layers.
  • the presence of the additional layer and the metal in the additional layer and the free layer helps provide stability along with low resistance, low switching current/voltage, and adequate damping.
  • Example 17 includes the apparatus of example 1 comprising a perpendicular spin torque transfer memory (STTM) that includes the MTJ.
  • STTM perpendicular spin torque transfer memory
  • Example 18 includes the apparatus of example 1, wherein the MTJ has perpendicular anisotropy.
  • Example 19 includes a perpendicular spin torque transfer memory (STTM) that includes the MTJ, the oxide layer, and the additional layer according to any one of examples 1 to 18.
  • STTM perpendicular spin torque transfer memory
  • Example 20 includes a method comprising: forming a magnetic tunnel junction (MTJ) on a substrate, the MTJ including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and forming a first side of an oxide layer directly contacting a second side of the free layer; and forming a first side of an additional layer directly contacting a second side of the oxide layer; wherein the oxide layer includes a metal and the additional layer includes the metal; wherein the metal is selected from the group consisting of hafnium, tantalum, tungsten, platinum, iridium, molybdenum, zirconium, niobium, titanium, or vanadium.
  • MTJ magnetic tunnel junction
  • Example 21 includes the method of example 20 comprising sputtering the metal, with argon gas, to form the additional layer.
  • Another version of example 21 includes the method of example 20 comprising sputtering the metal, via physical vapor deposition (PVD), to form the additional layer.
  • PVD physical vapor deposition
  • Example 22 includes the method of example 21 comprising forming a projection, which includes the metal, that projects from the additional layer into the oxide layer in response to the sputtering the metal.
  • Example 23 includes a system comprising: a processor; and a memory, coupled to the processor, comprising: a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free and fixed magnetic layers; the tunnel barrier layer directly contacting a first side of the free magnetic layer; and a first side of an oxide layer directly contacting a second side of the free magnetic layer; and a first side of an additional layer directly contacting a second side of the oxide layer; wherein (a)(i) the oxide layer includes tantalum and the additional layer includes tantalum; and (a)(ii) a thickness of the additional layer is less than a thickness for each of the oxide layer, the free magnetic layer, and the additional magnetic layer.
  • MTJ magnetic tunnel junction
  • Example 24 includes the system of example 23 wherein the metal is included in a projection that projects from the additional layer into the oxide layer.
  • Example 25 includes the system of example 24 wherein the projection is noncontiguous.
  • Example 26 includes a perpendicular spin torque transfer memory (STTM) that includes the MTJ, oxide layer, and additional layer according to any one of examples 23 to 25.
  • Example 27 includes the apparatus of any of examples 1 to 4 and 11 to 18 comprising: first and second contact layers; and an additional magnetic layer between the additional layer and the second contact layer.
  • STTM perpendicular spin torque transfer memory
  • Example 28 includes the apparatus of any of examples 1 to 10 and 13 to 18 wherein the first side of the additional layer is primarily located in a plane and the additional layer has a thickness, orthogonal to the plane, between 0.5 and 12 angstroms.
  • Example 29 includes the apparatus of any of examples 1 to 11 and 17 to 18 wherein the free magnetic layer is a composite layer including a first layer comprising boron and a second layer comprising tungsten.
  • Example 30 includes the apparatus of any of examples 1 to 11 and 17 to 18 wherein (a) the free magnetic layer is a composite layer including first and second layers, (b) the first layer is between the second layer and the tunnel barrier layer, and (c) the first layer includes a chemical composition with a higher percentage of boron than a chemical composition of the second layer.
  • Example 31 includes the apparatus of any of examples 1 to 11 and 17 to 18 wherein: (a) the free magnetic layer is a composite layer including first and second layers, (b) the first layer is between the second layer and the tunnel barrier layer, and (c) the first layer is primarily located in a plane and has a thickness, orthogonal to the plane, that is thicker than the second layer.
  • Example 32 includes the apparatus of any of examples 1 to 11 and 17 to 18 wherein the free magnetic layer is not a composite layer and includes a single layer.
  • Example 33 includes the apparatus of any of examples 1 to 16 and 18 wherein the tunnel barrier layer and the oxide layer both include magnesium oxide.
  • Example 34 includes the apparatus of any of examples 1 to 17, wherein the MTJ has perpendicular anisotropy.
  • Example 35 includes a perpendicular spin torque transfer memory (STTM) that includes the MTJ, the oxide layer, and the additional layer according to example 1.
  • STTM perpendicular spin torque transfer memory
  • terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top” surface of that substrate; the substrate may actually be in any orientation so that a "top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.”
  • the term “on” as used herein does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer.
  • the embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mram Or Spin Memory Techniques (AREA)
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Abstract

Selon un mode de réalisation, la présente invention concerne un appareil dans lequel : une jonction à effet tunnel magnétique (MTJ) comprend une couche magnétique libre, une couche magnétique fixe, et une couche limite à effet tunnel entre les couches libre et fixe, la couche limite à effet tunnel étant en contact direct avec un premier côté de la couche libre ; un premier côté d'une couche d'oxyde est en contact direct avec un second côté de la couche libre ; et un premier côté d'une couche supplémentaire est en contact direct avec un second côté de la couche d'oxyde, la couche d'oxyde contenant un métal, et la couche supplémentaire contenant ledit métal. D'autres modes de réalisation sont décrits.
PCT/US2017/025147 2017-03-30 2017-03-30 Mémoire spintronique comportant une couche de recouvrement à faible résistance WO2018182642A1 (fr)

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Citations (5)

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US20140038312A1 (en) * 2009-03-02 2014-02-06 Qualcomm Incorporated Fabrication of a magnetic tunnel junction device
US20150028440A1 (en) * 2013-07-26 2015-01-29 Agency For Science, Technology And Research Magnetoresistive device and method of forming the same
US20160055893A1 (en) * 2011-02-16 2016-02-25 Avalanche Technology, Inc. PERPENDICULAR MAGNETIC TUNNEL JUNCTION (pMTJ) WITH IN-PLANE MAGNETO-STATIC SWITCHING-ENHANCING LAYER
US20160133829A1 (en) * 2013-03-28 2016-05-12 Intel Corporation High Stability Spintronic Memory
US20170025602A1 (en) * 2015-07-20 2017-01-26 Headway Technologies, Inc. Magnetic Tunnel Junction with Low Defect Rate after High Temperature Anneal for Magnetic Device Applications

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140038312A1 (en) * 2009-03-02 2014-02-06 Qualcomm Incorporated Fabrication of a magnetic tunnel junction device
US20160055893A1 (en) * 2011-02-16 2016-02-25 Avalanche Technology, Inc. PERPENDICULAR MAGNETIC TUNNEL JUNCTION (pMTJ) WITH IN-PLANE MAGNETO-STATIC SWITCHING-ENHANCING LAYER
US20160133829A1 (en) * 2013-03-28 2016-05-12 Intel Corporation High Stability Spintronic Memory
US20150028440A1 (en) * 2013-07-26 2015-01-29 Agency For Science, Technology And Research Magnetoresistive device and method of forming the same
US20170025602A1 (en) * 2015-07-20 2017-01-26 Headway Technologies, Inc. Magnetic Tunnel Junction with Low Defect Rate after High Temperature Anneal for Magnetic Device Applications

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