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WO2018181019A1 - Dispositif à semiconducteur et son procédé de fabrication - Google Patents

Dispositif à semiconducteur et son procédé de fabrication Download PDF

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Publication number
WO2018181019A1
WO2018181019A1 PCT/JP2018/011766 JP2018011766W WO2018181019A1 WO 2018181019 A1 WO2018181019 A1 WO 2018181019A1 JP 2018011766 W JP2018011766 W JP 2018011766W WO 2018181019 A1 WO2018181019 A1 WO 2018181019A1
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Prior art keywords
electrode
semiconductor device
terminal
layer
resistance change
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PCT/JP2018/011766
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English (en)
Japanese (ja)
Inventor
岡本　浩一郎
宗弘 多田
直樹 伴野
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日本電気株式会社
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Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2019509719A priority Critical patent/JPWO2018181019A1/ja
Publication of WO2018181019A1 publication Critical patent/WO2018181019A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • Examples of functional elements formed inside a copper multilayer wiring structure on a semiconductor device include a variable resistance nonvolatile element (hereinafter referred to as “resistance variable element”) and a capacitor (capacitance element).
  • resistance variable element a variable resistance nonvolatile element
  • capacitor capacitor
  • Capacitors embedded on a logic LSI include an embedded DRAM (Dynamic Random Access Memory) and a decoupling capacitor. By mounting these capacitors on the copper wiring, it is possible to increase the capacity and area of the capacitor.
  • FPGA Field Programmable Gate Array
  • a resistance change element is a generic term for elements that store information by changing a resistance state, and has a three-layer structure in which a resistance change layer is sandwiched between a lower electrode and an upper electrode, and a voltage is applied between the two electrodes. This utilizes the phenomenon that the resistance change of the resistance change layer occurs.
  • a resistance change element using metal bridge formation there are a ReRAM (Resistive RAM) using a metal oxide layer as a resistance change layer, a solid electrolyte switch element using a solid electrolyte, and the like.
  • Non-Patent Document 1 and Non-Patent Document 2 report a resistance change phenomenon using a chalcogenide compound as a solid electrolyte.
  • the solid electrolyte switch element has a structure in which a solid electrolyte layer is sandwiched between two electrodes (a lower electrode and an upper electrode).
  • a metal that is chemically active and can be easily oxidized and reduced by voltage application is used for one of the two electrodes, and a chemically inert metal material is used for the other electrode. Used.
  • a solid electrolyte switch element in an off state when the lower electrode (chemically active electrode) is grounded and a negative voltage is applied to the upper electrode (chemically inactive electrode), Metal atoms constituting the electrode are ionized and eluted into the solid electrolyte layer. The metal ions are attracted to the upper electrode (chemically inactive electrode) side, further receive electrons and become metal atoms, and the metal atoms form conductive metal bridges. When both electrodes are electrically connected by the metal bridge formed in the solid electrolyte, the switch is turned on (low resistance state). The operation of changing from the “off state” to the “on state” by applying the negative voltage is referred to as “set”.
  • the solid electrolyte switch element can hold the “on state” and the “off state” in a non-volatile manner while no voltage is applied, and can repeatedly perform “programming” operation.
  • application to a nonvolatile memory or a nonvolatile switch becomes possible.
  • Patent Document 1 An example of a memory element using a solid electrolyte is disclosed in Patent Document 1.
  • the memory element disclosed in Patent Document 1 has a configuration in which a memory layer in which a resistance change layer and an ion source layer are stacked is provided between a lower electrode and an upper electrode.
  • the resistance change layer corresponds to a solid electrolyte layer
  • the ion source layer corresponds to an electrode that supplies metal ions.
  • the memory element disclosed in Patent Document 1 has a structure in which a vertically active structure is reversed from a structure in which a chemically active electrode is used as a lower electrode, which is employed in the solid electrolyte switch element.
  • the “off state” has a lower leakage current, that is, a higher resistance. Therefore, in order to increase the resistance in the “off state”, a higher positive voltage is generally applied during the “reset” operation. However, when a positive voltage higher than a certain voltage is applied during the “reset” operation, dielectric breakdown occurs in the solid electrolyte layer. Once dielectric breakdown occurs, the state remains in a state of lower resistance than the normal ON state, and thereafter no resistance change is shown. The voltage that causes dielectric breakdown when this positive voltage is applied is called dielectric breakdown voltage. Therefore, a high reset voltage can be applied and a higher resistance OFF state can be obtained by designing and manufacturing the element so that the dielectric breakdown voltage becomes high.
  • Patent Document 2 and Patent Document 3 disclose a two-terminal solid electrolyte switch element provided in a copper multilayer wiring structure on a CMOS substrate and a method for manufacturing the same.
  • an active electrode for supplying metal ions into a solid electrolyte is formed by exposing a copper wiring itself exposed by opening a part of an insulating layer in a copper multilayer wiring structure on a CMOS substrate.
  • a mode for producing a two-terminal solid electrolyte switch element is disclosed.
  • Non-Patent Document 3 in the formation process of the laminated structure of the solid electrolyte switch element, the oxidation free energy is made more negative than copper in order to prevent the copper surface from being oxidized between the lower electrode copper and the solid electrolyte layer. It has been proposed to deposit a large metal as a valve metal and provide a “buffer structure” that suppresses copper oxidation by oxidizing the valve metal.
  • Non-Patent Document 4 includes a complementary resistance change element in which two resistance change elements having a structure in which two lower electrodes exposed in the same opening are opposed to each other are connected in series, and the reliability of the resistance state is improved. Techniques for improving are disclosed.
  • Patent Document 4 relates to a switching element using an ion conductor, and it has been proposed to configure a selector element by connecting a plurality of switch elements in parallel and commonly connecting ion conduction layers and the like.
  • Patent Document 5 relates to a resistance change element using an ionic conductor, and it is proposed that two resistance change elements are connected through a common electrode, thereby functioning as a three-terminal solid electrolyte switch. ing.
  • the present invention has been made to solve the problems of the technology as described above. It is an object of the present invention to provide a semiconductor device that employs a configuration of a variable resistance element in which variation in set voltage between elements is improved and a method for forming the same.
  • a semiconductor device of the present invention provides: A semiconductor device including at least two or more resistance change elements, a first terminal (first wiring), and a second terminal (second wiring),
  • the variable resistance elements are respectively Having a first electrode, a second electrode, and a resistance change layer sandwiched between the first electrode and the second electrode, Based on an electrical signal applied between the first electrode and the second electrode, the resistance value reversibly changes,
  • Each first electrode of the variable resistance element is electrically connected to a first terminal, and each second electrode is electrically connected to a second terminal, and
  • Each resistance change layer is separated from each other between at least two resistance change elements,
  • the second electrodes are separated from each other between the variable resistance elements, and are electrically connected to each other only via the second terminal.
  • a method for manufacturing a semiconductor device of the present invention includes: A method of manufacturing a semiconductor device having a plurality of resistance change elements provided in a multilayer copper wiring layer on a semiconductor substrate, Forming an insulating barrier film on the copper wiring also serving as the first electrode electrically connected to the first terminal; Forming an opening in the insulating barrier film and exposing a copper wiring surface also serving as the first electrode; A step of sequentially forming a buffer layer and a solid electrolyte layer on the entire surface including the opening; Forming a second electrode connected to the second terminal on the solid electrolyte layer.
  • the plurality of resistance change elements are configured as components. Since the set semiconductor device is “set”, variation in the “set voltage” of the semiconductor device can be suppressed. In other words, the variation of the “set voltage” between the plurality of variable resistance elements, which is a component of the semiconductor device, is not suppressed, but the variation of the “set voltage” of the semiconductor device of the present invention is suppressed.
  • FIG. 3 is a circuit diagram showing a configuration example of the semiconductor device of the first embodiment shown in FIG. 2.
  • 6 is a graph comparing standardized set voltage distributions when two 2 Mb variable resistance elements are connected in parallel in the first embodiment.
  • It is a fragmentary sectional view showing an example of 1 composition of a 3 terminal type semiconductor device of a 2nd embodiment.
  • It is a circuit diagram which shows the example of 1 structure of the 3 terminal type semiconductor device of 2nd Embodiment.
  • the semiconductor substrate includes a substrate on which a semiconductor element including a MOS transistor and a resistance element and a semiconductor device in which these semiconductor elements are combined are configured.
  • the semiconductor substrate also includes a substrate such as a single crystal substrate, an SOI (Silicon on Insulator) substrate, a TFT (Thin on Film Transistor) substrate, a liquid crystal manufacturing substrate.
  • the plasma CVD (Chemical Vapor Deposition) method is, for example, a method in which a gaseous material or a vaporized liquid material (gas molecules) is continuously supplied to a reaction chamber under reduced pressure, and the molecules are excited by plasma energy. In this method, a continuous film is formed on a substrate by vapor phase reaction or substrate surface reaction.
  • the CMP (Chemical Mechanical Polishing) method is a method of flattening the unevenness of the wafer surface that occurs during the multilayer wiring formation process by bringing the polishing liquid into contact with a rotating polishing pad while flowing the polishing liquid over the wafer surface and polishing it. .
  • the CMP method is used not only for polishing and planarizing an interlayer insulating film, but also for forming a buried wiring called a damascene wiring.
  • a method of forming damascene wiring will be briefly described in the case of using copper (Cu) as a wiring material.
  • Cu is formed on the insulating film in which the groove is formed in advance. Thereafter, by the CMP method, the Cu buried in the trench is left, and excess Cu on the insulating film is polished and removed. In this way, a damascene wiring in which Cu is embedded in the groove is formed.
  • Barrier metal refers to a conductive film having a barrier property that covers the side and bottom surfaces of the wiring in order to prevent the metal elements constituting the wiring from diffusing into the interlayer insulating film or the lower layer.
  • the material constituting the wiring is a metal containing Cu as a main component, for example, tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), carbonitride is used to prevent diffusion of copper (Cu).
  • a refractory metal such as tungsten (WCN), a nitride thereof, or a laminated film thereof is used as a barrier metal. These films are easy to process by dry etching and have good consistency with the LSI manufacturing process before Cu is used as a wiring material.
  • the barrier insulating film is formed on the upper surface of the Cu wiring and has a function to prevent Cu oxidation and diffusion of Cu into the insulating film and a role as an etching stopper layer during processing.
  • a SiC film, a SiCN film, a SiN film, or a laminated film thereof is used as the barrier insulating film.
  • variable resistance element and a manufacturing method thereof according to a preferred embodiment of the present invention will be described in detail with reference to the drawings.
  • each embodiment will be described in a technically preferable form for carrying out the present invention, the scope of the invention is not limited to the embodiment described below.
  • FIG. 1 is a partial cross-sectional view showing the configuration of a variable resistance element, which is a component of the semiconductor device of the present invention.
  • resistance variable element As a symbol indicating “resistance variable element”, “Rheostat (two-terminal variable resistor)” The notation is adopted.
  • FIG. 2 is a partial cross-sectional view showing a configuration example of the two-terminal semiconductor device according to the first embodiment.
  • FIG. 3 is a circuit diagram showing a circuit configuration of a configuration example of the two-terminal semiconductor device according to the first embodiment shown in FIG.
  • the connection form of the terminals of each variable resistance element is indicated by a symbol.
  • the two-terminal semiconductor device of the first embodiment is a two-terminal semiconductor device 150 including two resistance change elements 151a and 151b, a first terminal 153, and a second terminal 154.
  • Each of the two resistance change elements 151a and 151b includes a first electrode 1, a second electrode 2, and a resistance change layer 3 sandwiched between the first electrode 1 and the second electrode 2, Based on the electrical signal applied between the electrode 1 and the second electrode 2, it has a function of reversibly changing the resistance value, The first electrodes 1 and the first terminals 153 of the two variable resistance elements 151a and 151b are electrically connected, and the second electrodes 2 and the second terminals 154 are electrically connected in parallel.
  • the resistance change layers 3 of the individual resistance change elements 151a and 151b are separated from each other and independent.
  • the resistance change layer 3 and the second electrode 2 are not separated between individual resistance change elements connected in parallel, and the common resistance change layer and the common second electrode are used, respectively, two resistance changes
  • the variation (difference) in characteristics between the two resistance change elements increases due to the difference in shape between the two resistance change elements.
  • the shapes of the individual variable resistance elements connected in parallel can be made uniform, resulting in two resistances. Variation (difference) in characteristics between changing elements can be reduced.
  • both the first terminal 153 and the second terminal 154 are in the form of wiring.
  • the first electrode 1 of each of the resistance change elements 151a and 152b is in direct contact with the first terminal 153
  • the second electrode 2 is connected to the second terminal 154 via each via. It is.
  • the configuration of the two-terminal semiconductor device shown in FIG. 2 is an example of the two-terminal semiconductor device of the first embodiment, and the first electrodes 1 of the two resistance change elements 151a and 151b are both If the second electrode 2 is electrically connected to the first terminal 153 and the second terminal 154, the two resistance change elements are electrically connected in parallel.
  • the first electrode 1 of the two resistance change elements 151 a and 152 b can be selected as a configuration that also serves as the first terminal 153.
  • a configuration in which the second electrode 2 is in direct electrical contact with the second terminal 154 without vias can be selected.
  • the shape of the first terminal 153 or the second terminal 154 may be an island-like terminal shape instead of a wiring shape.
  • the entire two-terminal semiconductor device 150 when a programming voltage is applied between the first terminal 153 and the second terminal 154, of the two resistance change elements 151a and 151b connected in parallel, When one of the resistance change elements having a lower “set voltage” changes from the “off (high resistance) state” to the “on (low resistance) state”, the entire two-terminal semiconductor device 150 is also turned off (high resistance). ) State changes to ON (low resistance) state. That is, when the applied programming voltage reaches a lower “set voltage” of the “set voltages” of the two resistance change elements 151 a and 151 b, the entire two-terminal semiconductor device 150 is “set”.
  • the application condition of the “programming voltage” necessary for the “set” operation of the two-terminal semiconductor device of the first embodiment is the peripheral circuit in addition to the “set voltage” of the two “resistance change elements” And the desired “on-state” resistance value.
  • the application of the “programming voltage” may be a pulse application or a sweep application. Further, as long as the potential of the second terminal 154 becomes a “negative voltage” with respect to the potential of the first terminal 153, the “programming voltage” may be applied in any “applied voltage polarity”.
  • the “reset voltage” is applied between the first terminal 153 and the second terminal 154 in the same manner as in the “set” operation.
  • the “reset current” flows only in one of the resistance change elements that is in the “on state”. Therefore, the “reset operation” is performed in one of the resistance change elements that is in the “on state”.
  • no current is supplied to the other resistance change elements that originally remain in the “off state”.
  • the entire two-terminal semiconductor device 150 in which the resistance change elements 151a and 151b are connected in parallel is also in the “off state”. Return to. In this way, as in the “set” operation, during the “reset” operation, of the two resistance change elements connected in parallel, only one of the resistance change elements having the lower “set voltage” is used. , Causing a resistance change.
  • FIG. 4 shows a case where a single 2 Mb variable resistance element and a two-terminal semiconductor device in which two variable resistance elements are connected in parallel are “set” in the two-terminal semiconductor device of the first embodiment. It is the graph which compared standardized "set voltage” distribution. The median value of the “set voltage” variation (distribution) of the variable resistance element alone is normalized to 0, and the standard deviation is normalized to 1. The standard deviation representing the “set voltage” variation (distribution) of the entire two-terminal semiconductor device in which two variable resistance elements are connected in parallel is reduced from 1 to 0.83.
  • the standardized minimum applied programming voltage required to “set” all the 2Mb elements is 4.8, but the two variable resistance elements are connected in parallel.
  • the normalized minimum applied programming voltage required to “set” all 2 Mb elements is reduced to 3.0.
  • a two-terminal semiconductor device in which two resistance change elements 151a and 151b are connected in parallel is taken as an example. Is explained. Even in the configuration of a two-terminal semiconductor device in which three or more variable resistance elements are connected in parallel, the operation principle is essentially the same. As the number of variable resistance elements that are connected in parallel to configure the two-terminal semiconductor device increases, the probability that a variable resistance element having a lower “set voltage” is included increases. In other words, there is a high probability that a plurality of resistance change elements connected in parallel include a resistance change element having a “set voltage” lower than the median of the “set voltage” distribution of the resistance change element alone. . As a result, when the number of resistance change elements connected in parallel is increased, variation in “set voltage” of the two-terminal semiconductor device to which the resistance change elements are connected in parallel can be further reduced.
  • each first electrode 1 and first terminal 153 of a plurality of resistance change elements are connected, and each second electrode 2 and second terminal 154 are connected. It can be confirmed with various measuring instruments that the configuration is connected.
  • each “resistance change element” is observed by observation with a transmission electron microscope (TEM) or a scanning electron microscope (SEM). By examining the first electrode 1 and the second electrode 2 and the connection form thereof, it can be confirmed that the configuration is as described above.
  • the second embodiment of the present invention is a configuration of a three-terminal semiconductor device configured by the pair of the two-terminal semiconductor device 150 described in the first embodiment.
  • FIG. 5 is a partial cross-sectional view showing a configuration example of the three-terminal semiconductor device according to the second embodiment.
  • FIG. 6 is a circuit diagram showing a configuration example of the three-terminal semiconductor device according to the second embodiment shown in FIG. In the circuit diagram, the connection form of the terminals of each variable resistance element is indicated by the symbols shown in FIG.
  • the three-terminal semiconductor device of this embodiment is configured by the pair of the two-terminal semiconductor devices 150a and 150b described in the first embodiment, and each of the two-terminal semiconductor devices 150a and 150b.
  • the second terminals 154a and 154b constituting the are electrically connected to the control terminal 157.
  • the first terminal 153a of the two-terminal semiconductor device 150a and the first terminal 153b of the two-terminal semiconductor device 150b are electrically connected to the remaining two terminals of the three-terminal semiconductor device, respectively.
  • the two terminals according to the first embodiment when a “programming voltage” is applied between the first terminal 153a and the control terminal 157 constituting the two-terminal semiconductor device 150a, the two terminals according to the first embodiment.
  • one of the two resistance change elements 151a and 151b connected in parallel and constituting the two-terminal type semiconductor device 150a has a lower “set voltage”.
  • the “programming voltage” reaches the “set voltage”
  • the change element changes its resistance from the “off (high resistance) state” to the “on (low resistance) state”.
  • the entire two-terminal semiconductor device 150a is “set”.
  • the programming voltage applied exceeds the “set voltage” of one resistance change element that is already “ON”, but does not reach the “set voltage” of the other resistance change element. Therefore, after the “programming operation”, the other variable resistance element having the higher “set voltage” remains in the “off state”.
  • the two-terminal semiconductor device 150b is the same as the two-terminal semiconductor device 150a described above.
  • the two resistance change elements 151a and 151b that are connected in parallel and constitute 150b one of the resistance change elements having a lower “set voltage” reaches the “programming voltage” of the “set voltage”.
  • the application conditions of the “programming voltage” necessary for the “set” operation of the two-terminal semiconductor devices 150a and 150b are the configurations of the two-terminal semiconductor devices.
  • the “set voltage” of the two “resistance change elements” used in the above it depends on the form of the peripheral circuit, the desired “ON state” resistance value, and the like.
  • the “programming voltage” may be applied by applying a pulse or a sweep.
  • the “programming voltage” is applied in any “applied voltage polarity”. But you can.
  • the two-terminal type semiconductor device 150a and the two-terminal type semiconductor device 150b are sequentially “set”, and both are turned “on”, whereby the first terminal 153a constituting the two-terminal type semiconductor device 150a and the two-terminal type semiconductor device Switching between the two terminals of the first terminal 153b constituting the device 150b is switched from the “high resistance state” to the “low resistance state”. As a result, the two terminals of the first terminal 153a constituting the two-terminal semiconductor device 150a and the first terminal 153b constituting the two-terminal semiconductor device 150b are electrically connected with low resistance. It becomes a state.
  • the two-terminal semiconductor device 150a and the two-terminal semiconductor device 150b both adopt a configuration in which the resistance change elements 151a and 151b are connected in parallel. It is possible to transmit an electrical signal between the first terminal 153a and the first terminal 153b while reducing the variation of the “set voltage”.
  • the operation mechanism of the “reset” operation of the two-terminal semiconductor device 150a and the two-terminal semiconductor device 150b is essentially the same as the operation mechanism described in the two-terminal semiconductor device of the first embodiment.
  • the “reset voltage” is applied between the first terminal 153a or the first terminal 153b and the control terminal 157 as in the “set” operation. At this time, the “reset current” flows only in one of the resistance change elements that is in the “on state”. Therefore, the “reset operation” is performed in one of the resistance change elements that is in the “on state”. On the other hand, since no current is supplied to the other resistance change elements that originally remain in the “off state”, there is no influence.
  • a three-terminal semiconductor device using two-terminal semiconductor devices 150a and 150b in which two resistance change elements 151a and 151b are connected in parallel is used.
  • the operation principle of the semiconductor device of the present invention is described. Even in the configuration of a three-terminal semiconductor device using a two-terminal semiconductor device in which three or more variable resistance elements are connected in parallel, the operation principle is essentially the same. Probability of including a variable resistance element having a lower “set voltage” as the number of variable resistance elements connected in parallel in the two-terminal semiconductor device used in the configuration of the three-terminal semiconductor device increases. Becomes higher.
  • the three-terminal semiconductor device of the second embodiment is an electric signal switch that transmits between the first terminal 153a and the first terminal 153b.
  • the two-terminal semiconductor device 150 described in the first embodiment is similar to the case where a total of four resistance change elements are connected in parallel. It becomes composition.
  • the three-terminal semiconductor device configuration of the second embodiment is also configured by a pair of two two-terminal semiconductor devices 150a and 150b, and the second terminal 154a that constitutes each of the two-terminal semiconductor devices 150a and 150b, It can be confirmed with various measuring instruments that both 154b are electrically connected to the control terminal 157.
  • the three-terminal semiconductor device of the second embodiment is formed in a multilayer copper wiring layer on a semiconductor substrate, the first electrode 1 of each “resistance change element” is observed by TEM observation and SEM observation. And the second electrode 2, the second terminals 154a, 154b, and the control terminal 157 can be checked to confirm the configuration described above.
  • the semiconductor device of the third embodiment is configured to employ a solid electrolyte switch element as a resistance change element used in the configuration of the two-terminal semiconductor device described in the first embodiment.
  • FIG. 7A is a partial cross-sectional view schematically showing a configuration of a solid electrolyte switch element used as a variable resistance element constituting the semiconductor device of the third embodiment.
  • the solid electrolyte switch element 159 used in the third embodiment includes a first electrode 1, a second electrode 2, and a resistance change sandwiched between the first electrode 1 and the second electrode 2.
  • the resistance change layer 3 includes a buffer layer 4 and a solid electrolyte layer 5 capable of conducting metal ions in the order closer to the first electrode 1.
  • the 1st electrode 1 is comprised with the material used as the supply source of metal ion.
  • the 1st electrode 1 consists of a metal material containing copper from a viewpoint of controllability of metal ionization and supply, and the metal ion supplied from this metal material is a copper ion.
  • the second electrode 2 is made of a material containing a metal that is harder to ionize than the metal material used for the first electrode 1.
  • the 2nd electrode 2 is comprised with the material containing Ru from a viewpoint of the ease of electrode processing.
  • the buffer layer 4 is provided in contact with the entire surface of the first electrode 1 and is made of a material capable of suppressing oxidation of the surface of the first electrode 1.
  • the buffer layer 4 is preferably made of a material containing at least one of Al, Hf, Ta, Ti, and Zr.
  • the solid electrolyte layer 5 has a role of dissolving metal ions supplied from the first electrode 1 by applying a voltage between the first electrode 1 and the second electrode 2.
  • Metal ions dissolved in the solid electrolyte layer 5, for example, copper ions, are transported by an electric field caused by a voltage applied between the first electrode 1 and the second electrode 2.
  • the solid electrolyte layer can be obtained by a solid electrolyte material in which copper ions are easily eluted from a metal material containing copper or can be recovered by reducing the copper ions to copper by an electric field caused by an applied voltage. 5 is produced.
  • the solid electrolyte material for producing the solid electrolyte layer 5 is preferably a material with little material deterioration due to switching cycles.
  • the solid electrolyte layer 5 uses, for example, an oxide containing at least one of Al, Co, Fe, Hf, Mn, Si, Ta, Ti, Zn, and Zr, chalcogenide, amorphous Si, SiOCH, or the like. Is produced.
  • the semiconductor device of the third embodiment is a semiconductor device in which at least two solid electrolyte switch elements are connected in parallel as resistance change elements.
  • the semiconductor device of the third embodiment manufactured using a solid electrolyte switch element, as well as the two-terminal semiconductor device having the configuration described in the first embodiment the variation in set voltage is suppressed. Is possible.
  • the semiconductor device according to the fourth embodiment has a configuration in which the two-terminal semiconductor device according to the first embodiment is provided inside a multilayer wiring structure formed on a semiconductor substrate.
  • FIG. 8 schematically shows an example of the configuration of the semiconductor device of the fourth embodiment, in which a solid electrolyte switch element is employed as a variable resistance element and is provided inside a multilayer wiring structure formed on a semiconductor substrate. It is the fragmentary sectional view shown in.
  • a solid electrolyte switch element 159 is provided as a resistance change element on a semiconductor substrate 101 with a first interlayer insulating film 102 interposed therebetween.
  • the solid electrolyte switch element 159 used in the semiconductor device of the fourth embodiment has the same configuration as the solid electrolyte switch element used in the configuration of the semiconductor device of the third embodiment.
  • the solid electrolyte switch element 159 described in the third embodiment includes a first electrode 1 and a second electrode 2, and a variable resistance layer sandwiched between the first electrode 1 and the second electrode 2.
  • the resistance change layer 3 includes a buffer layer 4 and a solid electrolyte layer 5 capable of conducting the metal ions in the order closer to the first electrode 1.
  • the solid electrolyte switch element 159 used in the semiconductor device of the fourth embodiment adopts the configuration shown in FIG. 7B.
  • the buffer layer 4 is composed of a first metal oxide layer 6 and a second metal oxide layer 7.
  • the solid electrolyte switch element 159 used in the semiconductor device of the fourth embodiment includes a lower wiring 106, a first metal oxide layer (not shown), a second metal oxide layer (not shown), and a solid electrolyte layer. 123, a first upper electrode 124, and a second upper electrode 125.
  • the configuration shown in FIG. 8 can be adopted for the lower wiring 106, the first metal oxide layer, the second metal oxide layer, the solid electrolyte layer 123, and the first upper electrode 124.
  • the lower wiring 106 corresponds to the first electrode 1 shown in FIG. 7B.
  • the first metal oxide layer 121 corresponds to the first metal oxide layer 6, and the second metal oxide layer 122 corresponds to the second metal oxide layer 7.
  • the solid electrolyte layer 123 corresponds to the solid electrolyte layer 5, and the first upper electrode 124 corresponds to the second electrode 2.
  • the operation principle of the solid electrolyte switch element having the configuration shown in FIG. 7B is the same as the operation principle of the solid electrolyte switch element having the structure shown in FIG. 7A described in the third embodiment. Therefore, in the fourth embodiment, Detailed description thereof is omitted.
  • the first metal oxide layer 121 is, for example, TiO y1 with an oxygen composition y1 with a thickness of 0.5 nm satisfying 1.5 ⁇ y1 ⁇ 2.0. Can be produced.
  • the second metal oxide layer 127 functions as a passive layer, and can suppress oxidation of the lower wiring 106 containing Cu in the lower layer.
  • the second metal oxide layer 122 is, for example, an AlO x1 having a 0.3 nm-thickness oxygen composition x1 satisfying 1.3 ⁇ x1 ⁇ 1.5. Can be produced.
  • the solid electrolyte layer 123 can be made of, for example, a 6 nm thick SiOCH film.
  • the first upper electrode 124 can be made of, for example, Ru 0.5 Ti 0.5 having a thickness of 10 nm.
  • the second upper electrode 125 is a conductive film having a barrier property, and is formed to prevent the metal contained in the first upper electrode 124 in contact with the lower part from diffusing into the via plug 144 or the like.
  • the second upper electrode 125 can be made of Ta with a film thickness of 25 nm, for example.
  • a second hard mask film 128 and a third hard mask film 129 are formed on the stacked body of the first upper electrode 124 and the second upper electrode 125 in the solid electrolyte switch element 159.
  • the upper surface of the first barrier insulating film 107 is covered with a protective insulating film 130.
  • the lower wiring 106 is a wiring buried in a wiring groove formed in the second interlayer insulating film 103 and the first cap insulating film 104 via the first barrier metal 105.
  • the lower wiring 106 By forming the lower wiring 106 from a metal material whose main component is Cu, it is used as a lower electrode corresponding to the first electrode 1 in the solid electrolyte switch element having the configuration shown in FIG. 7B. With this configuration, the lower wiring 106 can have a function of ionizing Cu atoms in the lower wiring 106 and eluting them into the solid electrolyte layer 123.
  • the lower wiring 106 by forming the lower wiring 106 with a Cu material structure, a metal component that has not been formed in the first metal oxide layer 121 while being unoxidized can be alloyed with Cu and diffused into the lower wiring 106.
  • the interface between the lower wiring 106 and the first metal oxide layer 121 is An alloy layer mainly composed of Cu and Ti is formed.
  • the solid electrolyte layer 123 and the lower wiring 106 are connected at the opening of the first barrier insulating film 107 via the first metal oxide layer 121 and the second metal oxide layer 122. At this time, the width of the lower wiring 106 connected to the solid electrolyte layer 123 through the metal oxide layer is preferably larger than the diameter of the opening of the barrier insulating film 107.
  • the first barrier metal 105 is a conductive film having a barrier property similar to that of the second upper electrode 125.
  • the first barrier metal 105 covers the side surface and the bottom surface of the lower wiring 106.
  • the metal contained in the lower wiring 106 diffuses into the first interlayer insulating film 102, the second interlayer insulating film 103, the first cap insulating film 104, and the like.
  • a refractory metal such as Ta, TaN, TiN, WCN, nitride thereof, or the like
  • a laminated film is used for the formation of the first barrier metal 105.
  • the upper wiring 145 is a wiring buried in a wiring groove formed in the third interlayer insulating film 141 and the second cap insulating film 142 via the second barrier metal 143.
  • the upper wiring 145 is integrated with the via plug 144.
  • the via plug 144 is embedded in a prepared hole formed in the protective insulating film 130, the third hard mask film 129, and the second hard mask film 128 via the second barrier metal 143.
  • the via plug 144 is electrically connected to the first upper electrode 124 and the second upper electrode 125 of the solid electrolyte switch element 159 via the second barrier metal 143.
  • Cu is used to manufacture the upper wiring 145 and the via plug 144.
  • the second barrier metal 143 is a conductive film having the same barrier properties as the first barrier metal 105.
  • the second barrier metal 143 covers the side surfaces and the bottom surface of the upper wiring 145 and the via plug 144.
  • the second barrier metal 143 formed of a conductive film having a barrier property is such that the metal included in the upper wiring 145 and the via plug 144 is the first via interlayer insulating film 140, the third interlayer insulating film 141, and the second cap insulating film. The diffusion to 142 is prevented.
  • the upper wiring 145 and the via plug 144 are made of a metal material containing Cu as a main component, Ta, TaN, TiN, WCN are formed as in the first barrier metal 105.
  • Such a refractory metal, a nitride thereof, or a laminated film thereof is used.
  • the second barrier metal 143 is preferably made of the same material as the second upper electrode 125 which is a part of the configuration of the solid electrolyte switch element 159 from the viewpoint of reducing the contact resistance.
  • the second upper electrode 125 is made of Ta, it is preferable to use Ta also for the production of the second barrier metal 143 in contact with the upper portion thereof.
  • the third hard mask film 129 is a film that serves as a hard mask when the second hard mask film 128 is etched.
  • the third hard mask film 129 is preferably a different type of film from the second hard mask film 128.
  • the second hard mask film 128 is a SiCN film
  • a SiO 2 film can be used for the third hard mask film 129.
  • the protective insulating film 130 further prevents diffusion of constituent atoms (for example, copper ions) from the solid electrolyte switch element 159 to the first via interlayer insulating film 140 without damaging the solid electrolyte switch element 159 whose side surface is exposed.
  • This is an insulating film having a function.
  • a SiN film, a SiCN film, or the like can be used for the production of the protective insulating film 130.
  • the first barrier insulating film 107 and the second barrier insulating film 146 are insulating films having a function of preventing diffusion of metal (for example, copper ions).
  • the lower wiring 106 corresponding to the first electrode 1 and the first metal oxide layer through the opening provided in the first barrier insulating film 107 121 is in contact.
  • a Cu electrode serving also as a Cu wiring can be used as the first electrode 1, and a resistance change element using a Cu electrode can be formed in the multilayer wiring structure on the CMOS substrate. Since the lower electrode of the variable resistance element also functions as a Cu wiring, the manufacturing process can be simplified.
  • the semiconductor device of the fourth embodiment shown in FIG. 8 can be manufactured by applying the manufacturing method of FIGS. 9A to 9J in which the variable resistance element is provided inside the multilayer wiring structure on the semiconductor substrate.
  • FIG. 9A to FIG. 9J are partial cross-sectional views for explaining a manufacturing method for providing a solid electrolyte switch element in a multilayer wiring structure on a semiconductor substrate, which employs the configuration shown in FIG. 7B.
  • a first interlayer insulating film 102, a second interlayer insulating film 103, and a first cap insulating film 104 are sequentially formed on the semiconductor substrate 101.
  • the semiconductor substrate 101 here may be the semiconductor substrate itself or a substrate on which a semiconductor element (not shown) is formed on the surface of the substrate.
  • the first interlayer insulating film 102 is a 300 nm thick SiO 2 film
  • the second interlayer insulating film 103 is a 150 nm thick SiOCH film
  • the first cap insulating film 104 is a 100 nm thick SiO 2 film. Can be produced.
  • a wiring trench is formed in the laminated film of the first cap insulating film 104, the second interlayer insulating film 103, and the first interlayer insulating film 102 by using a lithography method.
  • This lithography method includes a photoresist forming process for forming a resist with a predetermined pattern on the first cap insulating film 104, a dry etching process for performing anisotropic etching on the laminated film using the resist as a mask, and an etching process. And a process of removing the resist after forming the wiring trench.
  • the first barrier metal 105 can be formed with, for example, a stacked structure of TaN (film thickness 5 nm) / Ta (film thickness 5 nm).
  • Cu can be used as the material of the lower wiring 106.
  • a first barrier insulating film 107 is formed on the first cap insulating film 104 including the lower wiring 106.
  • the first barrier insulating film 107 can be formed of, for example, a SiCN film having a thickness of 30 nm.
  • a first hard mask film 108 is formed on the first barrier insulating film 107.
  • the first hard mask film 108 is preferably made of a material different from that of the first barrier insulating film 107 from the viewpoint of maintaining a high etching selectivity in the dry etching process.
  • the first hard mask film 108 can be manufactured using, for example, a SiO 2 film.
  • the first hard mask film 108 can be manufactured using, for example, a SiO 2 film having a thickness of 40 nm.
  • a photoresist having a predetermined opening pattern is formed on the first hard mask film 108 and dry etching is performed to form openings in the first hard mask film 108.
  • the photoresist is removed by O 2 plasma ashing or the like.
  • the first barrier insulating film 107 exposed at the bottom of the opening of the first hard mask film 108 is etched back, so that an opening exposing a part of the upper surface of the lower wiring 106 is formed in the first barrier insulating film 107.
  • the first hard mask film 108 is formed by using a SiO 2 film having a thickness of 40 nm, and is removed by etching during this etch back. After this etch-back, as shown in FIG. 9B, the surface of the lower wiring 106 exposed at the bottom of the opening is cleaned by plasma irradiation using an organic solvent or a gas containing H 2 or an inert gas.
  • step A1 9A to 9B are defined as step A1.
  • the etch back for forming the opening of the first barrier insulating film 107 can be performed using plasma containing CF 4 when the first barrier insulating film 107 is a SiN film or a SiCN film. It is.
  • the ionicity at the time of etching can be improved, and the side wall of the first barrier insulating film 107 can be tapered.
  • the first hard mask film 108 can be removed by etching by this etch back.
  • the first metal layer 161 includes at least one of Ti, Zr, and Hf.
  • the second metal layer 162 includes at least one of Al, Nb, and Ta.
  • the first metal layer 161 can be formed using a Ti film having a thickness of 0.5 nm
  • the second metal layer can be formed using an Al film having a thickness of 0.2 nm.
  • the first metal layer 161 and the second metal layer 162 are deposited, the first metal layer 161 and the second metal layer 162 are irradiated with a gas containing O 2 under reduced pressure without being exposed to the atmosphere. Oxidation treatment is performed. Subsequently, by performing vacuum heat treatment at a temperature higher than the film formation temperature under reduced pressure, the first metal oxide layer 121 and the second metal oxide layer 122 are simultaneously formed as shown in FIG. 9C.
  • a solid electrolyte layer 123 is deposited on the formed second metal oxide layer 122.
  • a 6-nm-thick SiOCH film can be used.
  • the solid electrolyte layer 123 is deposited by a plasma CVD method, and then an inert gas plasma process is performed.
  • the first upper electrode 124 and the second upper electrode 125 are formed in this order on the solid electrolyte layer 123 by DC sputtering.
  • the lower wiring 106, the first metal oxide layer 121, the second metal oxide layer 122, the solid electrolyte layer 123, the first upper electrode 124, and the second upper electrode 125 constitute a stacked body that becomes the solid electrolyte switch element 159.
  • the first upper electrode 124 can be formed of, for example, a Ru 0.5 Ti 0.5 film having a thickness of 10 nm.
  • the second upper electrode 125 can be formed of, for example, a Ta film having a thickness of 25 nm.
  • the first upper electrode 124 is made of Ru or a Ru alloy
  • the first upper electrode 124 is continuously deposited without being exposed to the atmosphere after the deposition of the first upper electrode 124 in order to prevent surface oxidation of the first upper electrode 124.
  • two upper electrodes 125 are deposited.
  • the second hard mask film 128 and the third hard mask film 129 are stacked in this order on the second upper electrode 125.
  • the second hard mask film 128 is preferably made of the same material as that of the first barrier insulating film 107 from the viewpoint of adhesion, and can be made of, for example, a SiCN film having a thickness of 30 nm.
  • the third hard mask film 129 can be made of, for example, a 100 nm thick SiO 2 film.
  • step A2 9A to 9D is referred to as step A2.
  • the first metal layer 161 and the second metal layer 162 can be deposited by resistance heating of a metal raw material, electron beam irradiation, laser vapor deposition, DC sputtering, or the like.
  • a metal raw material electron beam irradiation, laser vapor deposition, DC sputtering, or the like.
  • DC sputtering is used with Ti as a target, sputtering power of 100 W, substrate temperature at room temperature, Ar flow rate of 20 sccm, and pressure of 0.5 Pa.
  • a Ti film having a thickness of 0.5 nm for the first metal layer 161 can be deposited.
  • the second metal layer 162 is formed of an Al film
  • DC sputtering is used, using Al as a target, sputtering power of 150 W, substrate temperature at room temperature, Ar flow rate of 20 sccm, and pressure of 0.5 Pa.
  • sputtering power 150 W
  • substrate temperature at room temperature Ar flow rate of 20 sccm
  • pressure 0.5 Pa.
  • an Al film having a thickness of 0.2 nm for the second metal layer 162 can be deposited.
  • the first metal oxide layer 121 formed by oxidation of the first metal layer 161 and the second metal oxide layer 161 are oxidized by irradiating with gas containing O 2 without being exposed to the atmosphere.
  • the degree of oxidation of the second metal oxide layer 122 formed by the oxidation of the metal layer 162 can be accurately controlled.
  • the substrate temperature is set to room temperature.
  • the heat treatment after the above-described oxidation treatment is performed by, for example, forming the first metal layer 161 with a 0.5 nm-thick Ti film and the second metal layer 162 with a 0.2 nm-thickness.
  • the N 2 and O 2 flow rate is 10/10 sccm
  • the pressure is 900 Pa
  • the processing time is 30 seconds at a substrate temperature of 400 ° C. or lower.
  • the vacuum means a state where the atmospheric pressure in the chamber is as low as possible, and is at least a lower pressure than the above-described oxidation treatment.
  • the film thickness of the first metal oxide layer 121 is preferably 1.0 nm or less, and the film thickness of the second metal oxide layer 122 is preferably 0.8 nm or less.
  • step A2 when a SiOCH film is used for the solid electrolyte layer 123, the SiOCH film is formed by the plasma CVD method under the following conditions.
  • the raw material is liquid SiOCH monomer molecules
  • the substrate temperature is 400 ° C. or less
  • the He flow rate is 500 to 2000 sccm
  • the raw material flow rate is 0.1 to 0.8 g / min
  • the plasma CVD chamber pressure is 360 to 700 Pa
  • the RF power is 20 to 100 W.
  • the SiOCH film for the solid electrolyte layer 123 can be deposited under the conditions of a substrate temperature of 350 ° C., a He flow rate of 1500 sccm, a raw material flow rate of 0.75 g / min, a plasma CVD chamber pressure of 470 Pa, and an RF power of 50 W.
  • the inert plasma treatment after depositing the SiOCH film for the solid electrolyte layer 123 uses He as an inert gas
  • the substrate temperature is set to 400 ° C. or less
  • the He flow rate is 500 to 1500 sccm
  • the plasma chamber pressure is 2.7 to 3. This can be done by setting 5 Torr and RF power 20 to 200 W, respectively.
  • the adhesion with the first upper electrode 124 to be deposited next can be improved.
  • the Ru 0.5 Ti 0.5 alloy film may be deposited by simultaneous DC sputtering using Ru and Ti as targets. It can.
  • a Ru 0.5 Ti 0.5 alloy film can be deposited by using the conditions of Ru sputtering power 120 W, Ti sputtering power 150 W, substrate temperature at room temperature, Ar flow rate 20 sccm, and pressure 0.5 Pa. Further, after the first upper electrode 124 is deposited, the second upper electrode 125 is continuously deposited without being exposed to the atmosphere.
  • the second upper electrode 125 is made of Ta with a film thickness of 25 nm
  • the sputtering power is 300 W
  • the substrate temperature is room temperature
  • the Ar flow rate is 25 sccm
  • the pressure is 0.5 Pa by DC sputtering.
  • both the second hard mask film 128 and the third hard mask film 129 can be formed using a general plasma CVD method in the technical field of semiconductor manufacturing.
  • the film formation temperature can be selected in the range of 200 ° C. to 400 ° C.
  • the film formation temperature can be selected to be 350 ° C. during the film formation by the plasma CVD method.
  • the third hard mask film 129 is dry-etched until the second hard mask film 128 appears. Subsequently, after removing the photoresist by O 2 plasma ashing, the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, and the third hard mask film 129 are used as a mask. The second metal oxide layer 122 and the first metal oxide layer 121 are continuously dry etched. FIG. 9E shows the state after the etching.
  • Step A2 the process until the structure shown in FIG. 9E is formed is referred to as Step A3.
  • step A3 the dry etching of the third hard mask film 129 is preferably stopped on the upper surface or inside the second hard mask film 128.
  • the solid electrolyte switch element 159 is covered with the second hard mask film 128, it is not exposed to O 2 plasma.
  • the first upper electrode 124 containing Ru is not exposed to O 2 plasma. Therefore, the occurrence of side etching with respect to the first upper electrode 124 can be suppressed.
  • a general parallel plate type dry etching apparatus can be used for the dry etching of the third hard mask film 129.
  • Step A3 each etching of the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, the second metal oxide layer 122, and the first metal oxide layer 121 is performed. Also, it can be performed collectively using a parallel plate type dry etcher.
  • the substrate bias power can be 100 to 300 W.
  • the solid electrolyte layer 123 eg, SiOCH film
  • the first upper electrode 124 Ru 0.5 Ti 0.5 alloy film
  • the second metal oxide layer 122 for example, an AlO x1 film having a thickness of 0.3 nm where the oxygen composition x1 satisfies 1.3 ⁇ x1 ⁇ 1.5
  • the first metal oxide layer 121 for example, In the etching of a 0.5 nm-thick TiO y1 film in which the oxygen composition y1 satisfies 1.5 ⁇ y1 ⁇ 2.0, when a Ru 0.5 Ti 0.5 alloy film is used for the first upper electrode 124, the solid electrolyte layer Similarly to 123 (SiOCH film), the etching can be performed under the same conditions as those for etching the first upper electrode 124 (Ru 0.5 Ti 0.5 alloy film).
  • the second metal oxide layer 122 (AlO x1 film) and the first metal oxide layer 121 (TiO y1 film) are replaced with the first upper electrode 124 (Ru 0.5 Ti 0.5 alloy film) and the solid electrolyte layer 123 (SiOCH film). Etching can be performed at once.
  • the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, the second metal oxide layer 122, and the first metal oxide are formed under the above-described conditions.
  • the remaining thickness of the third hard mask film 129 made of a 100 nm thick SiO 2 film can be set to 50 nm.
  • a third hard mask film 129, a second hard mask film 128, a second upper electrode 125, a first upper electrode 124, a solid electrolyte layer 123, a second metal oxide layer 122, and A protective insulating film 130 is deposited on the top and side walls of the laminated structure composed of the first metal oxide layer 121 and the first barrier insulating film 107.
  • the protective insulating film 130 is preferably made of the same material as the first barrier insulating film 107 and the second hard mask film 128, and can be made of, for example, a SiCN film having a thickness of 30 nm.
  • a first via interlayer insulating film 140 is deposited on the protective insulating film 130 by using a plasma CVD method.
  • the first via interlayer insulating film 140 can be made of, for example, a SiO 2 film having a thickness of 210 nm.
  • the first via interlayer insulating film 140 is planarized using a CMP method.
  • a third interlayer insulating film 141 and a second cap insulating film 142 are deposited in this order on the first via interlayer insulating film 140 as shown in FIG. 9G.
  • the third interlayer insulating film 141 is formed of a material different from that of the first via interlayer insulating film 140 in order to use the first via interlayer insulating film 140 that is in contact with the lower portion during etching processing as an etching stopper layer.
  • the third interlayer insulating film 141 can be formed by a SiOCH film having a film thickness of 150 nm, for example.
  • step S3 the process until the structure shown in FIG. 9G is formed is referred to as step A4.
  • step A4 for example, when a SiCN film is used to form the protective insulating film 130, it can be formed using plasma CVD at a substrate temperature of 200 ° C. using tetramethylsilane and ammonia as source gases.
  • the protective insulating film 130 By forming the protective insulating film 130 using the SiCN film, the first barrier insulating film 107, the protective insulating film 130, and the second hard mask film 128 can all be formed of the SiCN film.
  • the first barrier insulating film 107, the protective insulating film 130, and the second hard mask film 128 are formed of the same material, and the periphery of the solid electrolyte switch element 159 is integrated and protected, thereby improving the adhesion at the interface and absorbing moisture. Performance, water resistance and oxygen desorption resistance can be improved, and the yield and reliability of the device can be improved.
  • step A4 in the planarization of the first via interlayer insulating film 140, about 100 nm can be removed from the top surface of the first via interlayer insulating film 140, and the remaining film thickness can be set to about 110 nm.
  • CMP chemical-mechanical polishing
  • for the first via interlayer insulating film 140 can be polished using a general colloidal silica or ceria-based slurry.
  • Step A4 the third interlayer insulating film 141 and the second cap insulating film 142 can be deposited using a general plasma CVD method.
  • the upper wiring 145 and the via plug 144 shown in FIG. 9J are formed by using the dual damascene via first method.
  • a photoresist having the pattern of the via hole 147 for the via plug 144 shown in FIG. 9J is formed on the second cap insulating film 142.
  • the second cap insulating film 142, the third interlayer insulating film 141, the first via interlayer insulating film 140, the protective insulating film 130, and the third hard mask film 129 are penetrated by dry etching, as shown in FIG. 9H.
  • a via hole 147 for the via plug 144 is formed.
  • the photoresist is removed by performing plasma ashing including H 2 gas and organic peeling.
  • the second cap insulating film 142 and the third interlayer insulating film are formed by dry etching.
  • a wiring groove 148 for the upper wiring 145 shown in FIG. 9J is formed in the film 141.
  • plasma ashing including H 2 gas and organic peeling are performed to remove the photoresist.
  • Step A5 the process until the structure shown in FIG. 9I is formed is referred to as Step A5.
  • step A5 after forming the via hole 147, an ARC (Anti-Reflection Coating: antireflection film) or the like is buried on the via hole 147, thereby preventing the bottom of the via hole 147 from penetrating when the wiring trench 148 is formed by dry etching. can do.
  • ARC Anti-Reflection Coating: antireflection film
  • the second upper electrode 125 is exposed from the via hole 147 by etching the second hard mask film 128 at the bottom of the via hole 147.
  • an upper wiring 145 for example, Cu
  • a via plug 144 for example, Cu
  • a second barrier metal 143 for example, a Ta film having a thickness of 10 nm.
  • a second barrier insulating film 146 is deposited on the second cap insulating film 142 including the upper wiring 145, thereby forming the structure shown in FIG. 9J.
  • step A6 the process until the structure shown in FIG. 9J is formed is referred to as step A6.
  • the upper wiring 145 can be formed by using the same process as the formation of the lower wiring 106 in the lower layer.
  • the diameter of the bottom of the via plug 144 is preferably smaller than the diameter of the opening of the first barrier insulating film 107.
  • the diameter of the bottom of the via plug 144 is selected to be 60 nm, and the diameter of the opening of the first barrier insulating film 107 is selected to be 100 nm. be able to.
  • step A6 the second barrier metal 143 and the second upper electrode 125 are made of the same material, so that the contact resistance between the via plug 144 and the second upper electrode 125 is reduced, and the solid electrolyte switch element in the on state is turned on.
  • the resistance of 159 can be reduced. As a result, device performance can be improved.
  • variable resistance element Next, an embodiment of the above-described variable resistance element will be described.
  • the first metal oxide layer 6 and the second metal shown in FIG. 7B are used for the variable resistance element 126 of the third embodiment that employs a variable resistance layer composed of a buffer layer and a solid electrolyte layer.
  • the buffer layer 4 composed of the oxide layer 7 is employed.
  • the configuration of the solid electrolyte switch element 159 shown in FIG. 9J is adopted, elements having different combinations of the first metal oxide layer 121 and the second metal oxide layer 122 are manufactured, and the characteristics of the manufactured variable resistance element are evaluated. did.
  • the first embodiment a total of nine types including different combinations of the first metal oxide layer 121 and the second metal oxide layer 122 constituting the buffer layer with the resistance change element 126 of the third embodiment as a basic structure.
  • the variable resistance element was manufactured. Specifically, the following nine types of combinations of the first metal oxide layer 121 and the second metal oxide layer 122 formed on the lower wiring 106 mainly composed of Cu are provided.
  • the film thickness of the first metal layer 161 for forming the first metal oxide layer 121 is 0.5 nm, and the film thickness of the second metal layer 162 for forming the second metal oxide layer 122 is , 0.2 nm is selected.
  • the second metal layer of the first metal layer After forming the second metal layer of the first metal layer and the thickness 0.2nm in thickness 0.5 nm, without exposure to the atmosphere, pressure 0.5 Pa, at room temperature, O 2 in the O 2 flow rate 10sccm To oxidize.
  • the first metal layer becomes the first metal oxide layer 121
  • the second metal layer becomes the second metal oxide layer 122.
  • the solid electrolyte layer is formed using a SiOCH film having a thickness of 6 nm.
  • the atomic radius of Cu is 128 pm, and the covalent bond radius is 132 ⁇ 4 pm;
  • the atomic radius of Al is 143 pm, and the covalent bond radius is 121 ⁇ 4 pm;
  • Nb has an atomic radius of 146 pm and a covalent bond radius of 164 ⁇ 6 pm;
  • the atomic radius of Ta is 146 pm, and the covalent bond radius is 170 ⁇ 8 pm;
  • Ti has an atomic radius of 147 pm and a covalent bond radius of 160 ⁇ 8 pm;
  • the atomic radius of Zr is 160 pm, the covalent bond radius is 175 ⁇ 7 pm;
  • the atomic radius of Hf is reported to be 159 pm, and the covalent bond radius is 175 ⁇ 10 pm.
  • the film thickness of 0.2 nm of the second metal layer is a value not exceeding twice the atomic radius of Al, Nb, and Ta.
  • the film thickness of 0.5 nm of the first metal layer is a value that does not exceed four times the atomic radius of Ti, Zr, and Hf.
  • variable resistance element selected in the first embodiment in order to compare the characteristics of the variable resistance element selected in the first embodiment with the variable resistance element for selecting the combination of the first metal oxide layer 121 and the second metal oxide layer 122, a variable resistance element as a comparative example below is used. Got ready.
  • the variable resistance element as a comparative example employs a structure in which the buffer layer is composed of one kind of metal oxide layer.
  • the metal oxide layer (TiO y1 , ZrO y2 , and HfO y3 ) used for the first metal oxide layer 121 and the first metal oxide layer formed on the lower wiring 106 containing Cu as a main component are used.
  • the metal oxides (AlO x1 , NbO x2 , and TaO x3 ) used for the two-metal oxide layer 122 only one kind of metal oxide is formed.
  • the thickness of the metal layer for forming one kind of metal oxide layer is selected to be 0.7 nm.
  • oxidation treatment is performed by irradiating O 2 at a pressure of 0.5 Pa and an O 2 flow rate of 10 sccm at a room temperature without exposing to the atmosphere.
  • O 2 irradiating O 2 at a pressure of 0.5 Pa and an O 2 flow rate of 10 sccm at a room temperature without exposing to the atmosphere.
  • the oxidation treatment the metal layer becomes a metal oxide layer.
  • the solid electrolyte layer is formed using a SiOCH film having a thickness of 6 nm.
  • FIG. 11 is a table showing the results of measuring the off-leakage current when set, specifically, the off-leakage current when applying a negative voltage of 1 V, for the resistance change element of Embodiment 1 and the resistance change element as a comparative example. It is.
  • the unit of numerical values shown in FIG. 11 is ampere (A).
  • any combination of the first metal oxide layer 121 and the second metal oxide layer 122 is the same as the first metal oxide layer 121.
  • a reduction in off-leakage current at the time of setting is recognized as compared with a resistance change element as a comparative example that employs a buffer layer made of only a kind of metal oxide.
  • FIG. 12 is a table showing the results of measuring the dielectric breakdown voltage at reset for the variable resistance element of Embodiment 1 and the variable resistance element as a comparative example.
  • the unit of the numerical values shown in FIG. 12 is volts (V).
  • the configuration of the second embodiment that employs a variable resistance layer including a buffer layer and a solid electrolyte layer is applied.
  • the buffer layer 4 composed of the first metal oxide layer 6 and the second metal oxide layer 7 shown in FIG. 7B is employed. Therefore, the resistance change layer includes the first metal oxide layer 121, the second metal oxide layer 122, and the solid electrolyte layer 123.
  • variable resistance element 126 of the third embodiment is used as a basic structure, and the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8 shown in FIG. 7C.
  • a total of seven types of variable resistance elements with different combinations were prepared.
  • the combinations of the first metal oxide layer 6, the second metal oxide layer 7 and the third metal oxide layer 8 formed on the lower wiring mainly composed of Cu include the following seven types: It is.
  • TiO y1 / AlO x1 / TiO y4 , TiO y1 / NbO x2 / TiO y4, TiO y1 / TaO x3 / TiO y4, ZrO y2 / AlO x1 / ZrO y5, ZrO y2 / NbO x2, ZrO y2 / TaO x3 / ZrO y5 , HfO y3 / AlO x1 / HfO y6 y4, y5, and y6 are the oxygen compositions in the oxides of Ti, Zr, and Hf (TiO y4 , ZrO y5 , HfO y6 ) constituting the third metal oxide layer 8, respectively.
  • the third metal layer for forming the third metal oxide layer 8 was continuously deposited on the second metal layer for forming the second metal oxide layer 7.
  • the film thickness of the third metal layer for forming the third metal oxide layer 8 is selected to be 0.2 nm.
  • the variable resistance element according to Embodiment 2 has the basic structure except that the buffer layer is composed of the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8. , which is the same as the variable resistance element 126 shown in FIG. 9J.
  • the resistance change element of the comparative example which employs the seven variable resistance elements of Embodiment 2 and a buffer layer made of only the same type of metal oxide as the first metal oxide layer 121, respectively. It was confirmed that the off-leakage and the breakdown voltage were improved to the same extent as the evaluation results of the resistance change element of the first embodiment.
  • the off-leakage current measured when a voltage of 1 V was applied was 7 ⁇ 10 ⁇ 7 A.
  • the combination of the first metal oxide layer 6, the second metal oxide layer 7 and the third metal oxide layer 8 constituting the buffer layer is TiO y1 /
  • the off-leakage current measured when applying a negative voltage of 1 V was reduced to 4 ⁇ 10 ⁇ 8 A.
  • a resistance change element as a comparative example, which is composed of only the same type of metal oxide (TiO y1 ) as the first metal oxide layer 121 (TiO y1 ), as shown in FIG.
  • the measured breakdown voltage is 3.5V.
  • the variable resistance element according to Embodiment 2 for example, a combination of the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8 constituting the buffer layer.
  • TiO y1 / AlO x1 / TiO y4 the dielectric breakdown voltage measured when a positive voltage is applied rises to 4.5V.
  • the third embodiment is based on the variable resistance element having the configuration shown in FIG. 9J and the manufacturing method thereof described in the fourth embodiment, and a three-terminal variable resistance element in a multilayer wiring structure on a semiconductor substrate. Is provided.
  • FIG. 10 is a partial cross-sectional view schematically showing a configuration in which the three-terminal variable resistance element according to Embodiment 3 is provided inside a multilayer wiring structure on a semiconductor substrate.
  • a first lower wiring 206a and a second lower wiring 206b are provided as lower electrodes.
  • the upper surfaces of the first lower wiring 206a and the second lower wiring 206b that are separated from each other with the first cap insulating film 104 interposed therebetween are partially exposed in one opening formed in the first barrier insulating film 107. is doing.
  • the exposed portions of the upper surfaces of the first lower wiring 206a and the second lower wiring 206b are in contact with the upper first metal oxide layer 121 through the opening together with the upper surface of the first cap insulating film 104.
  • the area of the copper surface of the first lower wiring 206a and the area of the copper surface of the second lower wiring 206b exposed in the opening are both less than half of the opening area.
  • both the first lower wiring 206a and the second lower wiring 206b are made of, for example, Cu
  • the same configuration as the lower wiring 106 having the configuration shown in FIG. It can be formed by the method described in the manufacturing process of the variable resistance element having the configuration shown in FIG. 9J described in the fourth embodiment.
  • the first electrode and the third electrode are provided in the same layer.
  • the second electrode is provided in a different layer from the first electrode and the third electrode.
  • the surface of the first cap insulating film 104 sandwiched between the first lower wiring 206a and the second lower wiring 206b is dry etched.
  • the first metal layer used for forming the first metal oxide layer 121 is formed on the opening including the surfaces of the first lower wiring 206a and the second lower wiring 206b by DC sputtering. 161 and the second metal layer 162 used to form the second metal oxide layer 122 were successively deposited in this order.
  • Zr having a thickness of 0.5 nm is selected as the first metal layer 161
  • Al having a thickness of 0.2 nm is selected as the second metal layer 162.
  • the first metal layer 161 and the second metal layer 162 are formed by O 2 gas irradiation at an O 2 flow rate of 10 sccm, a pressure of 0.5 Pa, and an irradiation time of 60 seconds without exposing to the atmosphere at room temperature.
  • Oxidation treatment was performed to form ZrO y2 as the first metal oxide layer 121 and AlO x1 as the second metal oxide layer 122.
  • heat treatment was performed at a substrate temperature of 400 ° C.
  • the Zr metal component remaining unreacted between the first lower wiring 206a and the second lower wiring 206b and ZrO y2 which is the first metal oxide layer 121 is the first metal composed of Cu. It is removed by alloying and diffusion to the surfaces of the lower wiring 206a and the second lower wiring 206b.
  • a solid electrolyte layer 123 was deposited on the second metal oxide layer 122.
  • a formation method similar to that of the resistance change element 126 having the configuration shown in FIG. 9J is used, so that a three-terminal resistance change element is formed in the multilayer wiring structure as shown in FIG. 224 can be formed.
  • variable resistance layer adopts a configuration in which it is integrally formed.
  • 2nd electrode also employ
  • variable resistance element of the first embodiment also in the three-terminal variable resistance element 224 of the third embodiment, which is formed by the above manufacturing process, only the same type of metal oxide as the first metal oxide layer 121 is used. Compared with the three-terminal variable resistance element according to the comparative example that employs the buffer layer, the reduction of off-leakage and the improvement of the dielectric breakdown voltage were confirmed.
  • a three-terminal variable resistance element as a comparative example that employs a 0.7 nm-thick buffer layer made of only the same type of metal oxide (ZrO y2 ) as the first metal oxide layer 121 is used.
  • the off-leakage current measured when applying a negative voltage of 1 V is 5 ⁇ 10 ⁇ 7 A.
  • a negative voltage is applied in the case of the three-terminal resistance change element 224 of the third embodiment in which ZrO y2 is used as the first metal oxide layer 121 and AlO x1 is used as the second metal oxide layer 122.
  • the off-leakage current measured when 1 V was applied was 8 ⁇ 10 ⁇ 8 A, which was confirmed to be sufficiently reduced.
  • the dielectric breakdown voltage measured when a positive voltage is applied is 3.6V.
  • the dielectric breakdown voltage measured when a positive voltage was applied increased to 4.3V.
  • the three-terminal variable resistance element 224 using ZrO y2 as the first metal oxide layer 121 and AlO x1 as the second metal oxide layer 122 has been described.
  • the combination of the first metal oxide layer 121 and the second metal oxide layer 122 constituting the buffer layer is not limited to this combination of material configurations (ZrO y2 / AlO x1 ), and is exemplified in Embodiment 1. Other 8 types of combinations may be used.
  • variable resistance element of the present invention by applying the variable resistance element of the present invention and the manufacturing method thereof not only to the two-terminal variable resistance element but also to the three-terminal variable resistance element, the off-leakage current when applying a negative voltage is reduced, It was also found that the dielectric breakdown voltage was improved when a positive voltage was applied (at reset).
  • the present invention relates to semiconductor products having memory circuits such as DRAM, SRAM (Static RAM), flash memory, FRAM (Ferro-Electric RAM), capacitors, bipolar transistors, etc., and semiconductor products having logic circuits such as microprocessors.
  • the present invention can also be applied to a metal wiring forming process of a board or package on which they are simultaneously mounted.
  • the present invention can also be applied to a wiring formation process for connecting a semiconductor device to an electronic circuit device, an optical circuit device, a quantum circuit device, a micromachine, a MEMS (Micro-Electro-Mechanical Systems), or the like.
  • the solid electrolyte switching element produced in the copper wiring layer according to the present invention and formed by connecting a plurality of resistance change elements in parallel is, for example, a programmable element used in the configuration of an FPGA (Field Programmable Gate Array). As used.
  • FPGA Field Programmable Gate Array
  • the solid electrolyte switching element type semiconductor device uses a non-volatile memory or a non-volatile switch by using its “programming” operation, in particular, the effect of suppressing variation in set voltage during the “set” operation.
  • the present invention can be applied to logic circuits such as semiconductor products having a memory circuit and microprocessors.

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  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un élément de changement de résistance qui améliore la variation de tension réglée entre des éléments. L'invention concerne un dispositif à semiconducteur qui comprend au moins deux éléments de changement de résistance, une premiere borne et une seconde borne. Les éléments de changement de résistance comprennent chacun une première électrode, une seconde électrode et une couche de changement de résistance interposée entre la première électrode et la seconde électrode, et a pour fonction de modifier une valeur de résistance de manière réversible sur la base d'un signal électrique appliqué entre deux électrodes, c'est-à-dire la première électrode et la seconde électrode. La première électrode de chaque élément de changement de résistance est électroconnectée à la première borne, la seconde électrode de chaque élément de changement de résistance est électroconnectée à la seconde borne, les couches de changement de résistance sont séparées les unes des autres entre les éléments de changement de résistance, et les secondes électrodes sont séparées les unes des autres entre les éléments de changement de résistance et sont électroconnectées les unes aux autres uniquement par l'intermédiaire des secondes bornes.
PCT/JP2018/011766 2017-03-31 2018-03-23 Dispositif à semiconducteur et son procédé de fabrication WO2018181019A1 (fr)

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