WO2018181019A1 - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

The present invention provides a resistance change element that improves set voltage variation between elements. Provided is a semiconductor device that includes at least two resistance change elements, a first terminal, and a second terminal. The resistance change elements each have a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode, and has a function of changing a resistance value reversibly on the basis of an electric signal applied between two electrodes, that is to say, the first electrode and the second electrode. The first electrode of each resistance change element is electrically connected to the first terminal, the second electrode of each resistance change element is electrically connected to the second terminal, the resistance change layers are separated from each other between the resistance change elements, and the second electrodes are separated from each other between the resistance change elements and are electrically connected to each other only via the second terminals.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof.

Semiconductor devices (especially silicon devices) have been developed at a pace of 3 years, with the integration and low power consumption of the devices advanced by miniaturization (scaling law: Moore's law). In recent years, the gate length of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has become 20 nm or less, so far due to soaring lithography process (apparatus price and mask set price), and physical limits (operation limits and dispersion limits) of device dimensions. There is a need to improve device performance with an approach different from the scaling law.

Examples of functional elements formed inside a copper multilayer wiring structure on a semiconductor device include a variable resistance nonvolatile element (hereinafter referred to as “resistance variable element”) and a capacitor (capacitance element).

Capacitors embedded on a logic LSI (Large Scale Integration) include an embedded DRAM (Dynamic Random Access Memory) and a decoupling capacitor. By mounting these capacitors on the copper wiring, it is possible to increase the capacity and area of the capacitor.

A device called FPGA (Field Programmable Gate Array) has been developed as an intermediate position between the gate array and the standard cell. This makes it possible for the customer himself to perform an arbitrary circuit configuration after manufacturing the chip. As the programmable element, a resistance change element or the like is interposed in the wiring connection portion, so that the customer himself can arbitrarily connect the wiring. By using such a semiconductor device, the degree of freedom of the circuit can be improved.

A resistance change element is a generic term for elements that store information by changing a resistance state, and has a three-layer structure in which a resistance change layer is sandwiched between a lower electrode and an upper electrode, and a voltage is applied between the two electrodes. This utilizes the phenomenon that the resistance change of the resistance change layer occurs. For example, as a resistance change element using metal bridge formation, there are a ReRAM (Resistive RAM) using a metal oxide layer as a resistance change layer, a solid electrolyte switch element using a solid electrolyte, and the like.

Several studies on solid electrolyte switch elements have been reported since the late 1990s, and resistance change phenomena due to various solid electrolyte materials have been confirmed. For example, Non-Patent Document 1 and Non-Patent Document 2 report a resistance change phenomenon using a chalcogenide compound as a solid electrolyte.

Hereinafter, the structure and switching operation of a solid electrolyte switch element, which is an example of a resistance change element, will be briefly described.

The solid electrolyte switch element has a structure in which a solid electrolyte layer is sandwiched between two electrodes (a lower electrode and an upper electrode). Here, a metal that is chemically active and can be easily oxidized and reduced by voltage application is used for one of the two electrodes, and a chemically inert metal material is used for the other electrode. Used.

Next, the operation of the solid electrolyte switch element will be described. As an example, a structure using a chemically active electrode as the lower electrode will be described below.

For example, in a solid electrolyte switch element in an off state (high resistance state), when the lower electrode (chemically active electrode) is grounded and a negative voltage is applied to the upper electrode (chemically inactive electrode), Metal atoms constituting the electrode are ionized and eluted into the solid electrolyte layer. The metal ions are attracted to the upper electrode (chemically inactive electrode) side, further receive electrons and become metal atoms, and the metal atoms form conductive metal bridges. When both electrodes are electrically connected by the metal bridge formed in the solid electrolyte, the switch is turned on (low resistance state). The operation of changing from the “off state” to the “on state” by applying the negative voltage is referred to as “set”.

On the other hand, when the lower electrode is grounded again and a positive voltage is applied to the upper electrode in the ON state, the metal atoms constituting the metal bridge are ionized and dissolved in the solid electrolyte layer. Then, the metal ions are pulled back to the lower electrode side, receive electrons, and become metal atoms. As a result, the connection due to the metal bridge disappears, and both the electrodes are electrically insulated, so that the switch changes to a high resistance OFF state. The operation of changing from the “on state” to the “off state” by applying the positive voltage is referred to as “reset”. The “set” operation and the “reset” operation are collectively referred to as a “programming” operation.

As described above, the solid electrolyte switch element can hold the “on state” and the “off state” in a non-volatile manner while no voltage is applied, and can repeatedly perform “programming” operation. By utilizing the characteristics of the solid electrolyte switch element, application to a nonvolatile memory or a nonvolatile switch becomes possible.

An example of a memory element using a solid electrolyte is disclosed in Patent Document 1. The memory element disclosed in Patent Document 1 has a configuration in which a memory layer in which a resistance change layer and an ion source layer are stacked is provided between a lower electrode and an upper electrode. When the configuration of the memory element is compared with the configuration of the solid electrolyte switch element, the resistance change layer corresponds to a solid electrolyte layer, and the ion source layer corresponds to an electrode that supplies metal ions. The memory element disclosed in Patent Document 1 has a structure in which a vertically active structure is reversed from a structure in which a chemically active electrode is used as a lower electrode, which is employed in the solid electrolyte switch element.

In application of the solid electrolyte switch element to a nonvolatile memory and a nonvolatile switch, it is preferable that the “off state” has a lower leakage current, that is, a higher resistance. Therefore, in order to increase the resistance in the “off state”, a higher positive voltage is generally applied during the “reset” operation. However, when a positive voltage higher than a certain voltage is applied during the “reset” operation, dielectric breakdown occurs in the solid electrolyte layer. Once dielectric breakdown occurs, the state remains in a state of lower resistance than the normal ON state, and thereafter no resistance change is shown. The voltage that causes dielectric breakdown when this positive voltage is applied is called dielectric breakdown voltage. Therefore, a high reset voltage can be applied and a higher resistance OFF state can be obtained by designing and manufacturing the element so that the dielectric breakdown voltage becomes high.

A method of forming a resistance change element utilizing metal bridge formation, in particular, these solid electrolyte switch elements inside a copper multilayer wiring on a semiconductor device is known. For example, Patent Document 2 and Patent Document 3 disclose a two-terminal solid electrolyte switch element provided in a copper multilayer wiring structure on a CMOS substrate and a method for manufacturing the same. In Patent Document 2 and Patent Document 3, an active electrode for supplying metal ions into a solid electrolyte is formed by exposing a copper wiring itself exposed by opening a part of an insulating layer in a copper multilayer wiring structure on a CMOS substrate. A mode for producing a two-terminal solid electrolyte switch element is disclosed.

When a copper electrode is used as the lower electrode in manufacturing a solid electrolyte switch element, if the surface of the copper electrode is oxidized, variations in leakage current and off-leakage current in the “off state” when a negative voltage is applied increase. Furthermore, the breakdown voltage during the “reset” operation is lowered due to the positive voltage application. A method for solving this problem is disclosed in Non-Patent Document 3. In Non-Patent Document 3, in the formation process of the laminated structure of the solid electrolyte switch element, the oxidation free energy is made more negative than copper in order to prevent the copper surface from being oxidized between the lower electrode copper and the solid electrolyte layer. It has been proposed to deposit a large metal as a valve metal and provide a “buffer structure” that suppresses copper oxidation by oxidizing the valve metal.

Non-Patent Document 4 includes a complementary resistance change element in which two resistance change elements having a structure in which two lower electrodes exposed in the same opening are opposed to each other are connected in series, and the reliability of the resistance state is improved. Techniques for improving are disclosed.

Patent Document 4 relates to a switching element using an ion conductor, and it has been proposed to configure a selector element by connecting a plurality of switch elements in parallel and commonly connecting ion conduction layers and the like. Patent Document 5 relates to a resistance change element using an ionic conductor, and it is proposed that two resistance change elements are connected through a common electrode, thereby functioning as a three-terminal solid electrolyte switch. ing.

JP 2011-187925 A JP 2011-91317 A International Publication No. 2010/0779816 International Publication No. 2008/001712 JP 2014-38984 A

In order to improve the operation yield of the resistance change element formed in the multilayer copper wiring layer, it is necessary to suppress variations in the “set voltage” necessary for changing from the “off state” to the “on state”. Desired.

However, in the configurations disclosed in Non-Patent Document 3 and Non-Patent Document 4, an effect of improving variation in “set voltage” has not been obtained.

Also, due to variations in “set voltage” between complementary elements, when the voltage required for setting is higher than a predetermined applied programming voltage, it cannot be set, and the operation yield of the element cannot be improved.

Therefore, there is a need for a complementary resistance change element that suppresses variations in “set voltage” between complementary resistance change elements and has improved operation yield.

The present invention has been made to solve the problems of the technology as described above. It is an object of the present invention to provide a semiconductor device that employs a configuration of a variable resistance element in which variation in set voltage between elements is improved and a method for forming the same.

In order to achieve the above object, a semiconductor device of the present invention provides:
A semiconductor device including at least two or more resistance change elements, a first terminal (first wiring), and a second terminal (second wiring),
The variable resistance elements are respectively
Having a first electrode, a second electrode, and a resistance change layer sandwiched between the first electrode and the second electrode,
Based on an electrical signal applied between the first electrode and the second electrode, the resistance value reversibly changes,
Each first electrode of the variable resistance element is electrically connected to a first terminal, and each second electrode is electrically connected to a second terminal, and
Each resistance change layer is separated from each other between at least two resistance change elements,
The second electrodes are separated from each other between the variable resistance elements, and are electrically connected to each other only via the second terminal.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
A method of manufacturing a semiconductor device having a plurality of resistance change elements provided in a multilayer copper wiring layer on a semiconductor substrate,
Forming an insulating barrier film on the copper wiring also serving as the first electrode electrically connected to the first terminal;
Forming an opening in the insulating barrier film and exposing a copper wiring surface also serving as the first electrode;
A step of sequentially forming a buffer layer and a solid electrolyte layer on the entire surface including the opening;
Forming a second electrode connected to the second terminal on the solid electrolyte layer.

According to the present invention, when a programming voltage is simultaneously applied to a plurality of resistance change elements connected in parallel, and the resistance change element having the lowest set voltage is in an “on state”, the plurality of resistance change elements are configured as components. Since the set semiconductor device is “set”, variation in the “set voltage” of the semiconductor device can be suppressed. In other words, the variation of the “set voltage” between the plurality of variable resistance elements, which is a component of the semiconductor device, is not suppressed, but the variation of the “set voltage” of the semiconductor device of the present invention is suppressed.

It is a fragmentary sectional view which shows the resistance change element which is a component of the semiconductor device of this invention. It is a fragmentary sectional view showing an example of 1 composition of a 2 terminal type semiconductor device of a 1st embodiment. FIG. 3 is a circuit diagram showing a configuration example of the semiconductor device of the first embodiment shown in FIG. 2. 6 is a graph comparing standardized set voltage distributions when two 2 Mb variable resistance elements are connected in parallel in the first embodiment. It is a fragmentary sectional view showing an example of 1 composition of a 3 terminal type semiconductor device of a 2nd embodiment. It is a circuit diagram which shows the example of 1 structure of the 3 terminal type semiconductor device of 2nd Embodiment. It is the fragmentary sectional view which showed typically the structure of the solid electrolyte switch element provided with the buffer layer used as a resistance change element which comprises the semiconductor device of 3rd Embodiment. The structure of the solid electrolyte switch element provided with the buffer layer comprised by the 1st metal oxide layer and the 2nd metal oxide layer which can be utilized as a resistance change element which comprises the semiconductor device of 3rd Embodiment is typically shown. It is the fragmentary sectional view shown in. A solid electrolyte comprising a buffer layer composed of a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer, which can be used as a variable resistance element constituting the semiconductor device of the third embodiment It is the fragmentary sectional view which showed the structure of the switch element typically. It is the fragmentary sectional view which showed typically an example of the structure provided in the inside of the multilayer wiring structure formed on the semiconductor substrate about the semiconductor device of 4th Embodiment. It is a fragmentary sectional view for demonstrating the manufacturing process of a resistance change element applied when providing the semiconductor device of 4th Embodiment in the inside of the multilayer wiring structure on a semiconductor substrate. It is a fragmentary sectional view for demonstrating the manufacturing process of a resistance change element applied when providing the semiconductor device of 4th Embodiment in the inside of the multilayer wiring structure on a semiconductor substrate. It is a fragmentary sectional view for demonstrating the manufacturing process of a resistance change element applied when providing the semiconductor device of 4th Embodiment in the inside of the multilayer wiring structure on a semiconductor substrate. It is a fragmentary sectional view for demonstrating the manufacturing process of a resistance change element applied when providing the semiconductor device of 4th Embodiment in the inside of the multilayer wiring structure on a semiconductor substrate. It is a fragmentary sectional view for demonstrating the manufacturing process of a resistance change element applied when providing the semiconductor device of 4th Embodiment in the inside of the multilayer wiring structure on a semiconductor substrate. It is a fragmentary sectional view for demonstrating the manufacturing process of a resistance change element applied when providing the semiconductor device of 4th Embodiment in the inside of the multilayer wiring structure on a semiconductor substrate. It is a fragmentary sectional view for demonstrating the manufacturing process of a resistance change element applied when providing the semiconductor device of 4th Embodiment in the inside of the multilayer wiring structure on a semiconductor substrate. It is a fragmentary sectional view for demonstrating the manufacturing process of a resistance change element applied when providing the semiconductor device of 4th Embodiment in the inside of the multilayer wiring structure on a semiconductor substrate. It is a fragmentary sectional view for demonstrating the manufacturing process of a resistance change element applied when providing the semiconductor device of 4th Embodiment in the inside of the multilayer wiring structure on a semiconductor substrate. It is a fragmentary sectional view for demonstrating the manufacturing process of a resistance change element applied when providing the semiconductor device of 4th Embodiment in the inside of the multilayer wiring structure on a semiconductor substrate. It is sectional drawing which shows typically the structure of the 3 terminal type resistance change element provided in the inside of the multilayer wiring structure formed on the semiconductor substrate based on the resistance change element of 3rd Embodiment, and its manufacturing method. . It is a table | surface which shows the result of having measured the off-leakage current at the time of applying a negative voltage 1V about the resistance change element of this Embodiment 1, and the resistance change element used as a comparative example. It is a table | surface which shows the result of having measured the dielectric breakdown voltage at the time of reset about the resistance change element of this Embodiment 1, and the resistance change element used as a comparative example.

Before describing embodiments of the present invention in detail, the meanings of terms used in the specification will be described.

The semiconductor substrate includes a substrate on which a semiconductor element including a MOS transistor and a resistance element and a semiconductor device in which these semiconductor elements are combined are configured. The semiconductor substrate also includes a substrate such as a single crystal substrate, an SOI (Silicon on Insulator) substrate, a TFT (Thin on Film Transistor) substrate, a liquid crystal manufacturing substrate.

The plasma CVD (Chemical Vapor Deposition) method is, for example, a method in which a gaseous material or a vaporized liquid material (gas molecules) is continuously supplied to a reaction chamber under reduced pressure, and the molecules are excited by plasma energy. In this method, a continuous film is formed on a substrate by vapor phase reaction or substrate surface reaction.

The CMP (Chemical Mechanical Polishing) method is a method of flattening the unevenness of the wafer surface that occurs during the multilayer wiring formation process by bringing the polishing liquid into contact with a rotating polishing pad while flowing the polishing liquid over the wafer surface and polishing it. . The CMP method is used not only for polishing and planarizing an interlayer insulating film, but also for forming a buried wiring called a damascene wiring. A method of forming damascene wiring will be briefly described in the case of using copper (Cu) as a wiring material. Cu is formed on the insulating film in which the groove is formed in advance. Thereafter, by the CMP method, the Cu buried in the trench is left, and excess Cu on the insulating film is polished and removed. In this way, a damascene wiring in which Cu is embedded in the groove is formed.

Barrier metal refers to a conductive film having a barrier property that covers the side and bottom surfaces of the wiring in order to prevent the metal elements constituting the wiring from diffusing into the interlayer insulating film or the lower layer. For example, when the material constituting the wiring is a metal containing Cu as a main component, for example, tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), carbonitride is used to prevent diffusion of copper (Cu). A refractory metal such as tungsten (WCN), a nitride thereof, or a laminated film thereof is used as a barrier metal. These films are easy to process by dry etching and have good consistency with the LSI manufacturing process before Cu is used as a wiring material.

The barrier insulating film is formed on the upper surface of the Cu wiring and has a function to prevent Cu oxidation and diffusion of Cu into the insulating film and a role as an etching stopper layer during processing. For example, a SiC film, a SiCN film, a SiN film, or a laminated film thereof is used as the barrier insulating film.

Hereinafter, a variable resistance element and a manufacturing method thereof according to a preferred embodiment of the present invention will be described in detail with reference to the drawings. However, although each embodiment will be described in a technically preferable form for carrying out the present invention, the scope of the invention is not limited to the embodiment described below.

(First embodiment)
The configuration of the semiconductor device according to the first embodiment of the present invention will be described.

FIG. 1 is a partial cross-sectional view showing the configuration of a variable resistance element, which is a component of the semiconductor device of the present invention. As a symbol indicating “resistance variable element”, “Rheostat (two-terminal variable resistor)” The notation is adopted.

FIG. 2 is a partial cross-sectional view showing a configuration example of the two-terminal semiconductor device according to the first embodiment.

FIG. 3 is a circuit diagram showing a circuit configuration of a configuration example of the two-terminal semiconductor device according to the first embodiment shown in FIG. In the circuit diagram, the connection form of the terminals of each variable resistance element is indicated by a symbol.

The two-terminal semiconductor device of the first embodiment is a two-terminal semiconductor device 150 including two resistance change elements 151a and 151b, a first terminal 153, and a second terminal 154.
Each of the two resistance change elements 151a and 151b includes a first electrode 1, a second electrode 2, and a resistance change layer 3 sandwiched between the first electrode 1 and the second electrode 2, Based on the electrical signal applied between the electrode 1 and the second electrode 2, it has a function of reversibly changing the resistance value,
The first electrodes 1 and the first terminals 153 of the two variable resistance elements 151a and 151b are electrically connected, and the second electrodes 2 and the second terminals 154 are electrically connected in parallel.

Also, as shown in FIG. 2, the resistance change layers 3 of the individual resistance change elements 151a and 151b are separated from each other and independent. When the resistance change layer 3 and the second electrode 2 are not separated between individual resistance change elements connected in parallel, and the common resistance change layer and the common second electrode are used, respectively, two resistance changes When the shapes of the elements are different from each other, the variation (difference) in characteristics between the two resistance change elements increases due to the difference in shape between the two resistance change elements. By separating the variable resistance layer 3 and the second electrode 2 between a plurality of variable resistance elements, the shapes of the individual variable resistance elements connected in parallel can be made uniform, resulting in two resistances. Variation (difference) in characteristics between changing elements can be reduced.

In the configuration example of the two-terminal semiconductor device shown in FIG. 2, both the first terminal 153 and the second terminal 154 are in the form of wiring. At that time, the first electrode 1 of each of the resistance change elements 151a and 152b is in direct contact with the first terminal 153, and the second electrode 2 is connected to the second terminal 154 via each via. It is. The configuration of the two-terminal semiconductor device shown in FIG. 2 is an example of the two-terminal semiconductor device of the first embodiment, and the first electrodes 1 of the two resistance change elements 151a and 151b are both If the second electrode 2 is electrically connected to the first terminal 153 and the second terminal 154, the two resistance change elements are electrically connected in parallel. For example, the first electrode 1 of the two resistance change elements 151 a and 152 b can be selected as a configuration that also serves as the first terminal 153. In addition, a configuration in which the second electrode 2 is in direct electrical contact with the second terminal 154 without vias can be selected. Furthermore, the shape of the first terminal 153 or the second terminal 154 may be an island-like terminal shape instead of a wiring shape.

In the two-terminal semiconductor device of the first embodiment, when a programming voltage is applied between the first terminal 153 and the second terminal 154, of the two resistance change elements 151a and 151b connected in parallel, When one of the resistance change elements having a lower “set voltage” changes from the “off (high resistance) state” to the “on (low resistance) state”, the entire two-terminal semiconductor device 150 is also turned off (high resistance). ) State changes to ON (low resistance) state. That is, when the applied programming voltage reaches a lower “set voltage” of the “set voltages” of the two resistance change elements 151 a and 151 b, the entire two-terminal semiconductor device 150 is “set”. When one of the two resistance change elements connected in parallel enters the “ON state”, it is difficult to further increase the applied “programming voltage” to the “set voltage” of the other resistance change elements. As a result, the programming voltage applied exceeds the “set voltage” of one resistance change element that is already “ON”, but does not reach the “set voltage” of the other resistance change element. Therefore, even after the programming operation, the other variable resistance element having the higher “set voltage” remains in the “off state”.

Here, the application condition of the “programming voltage” necessary for the “set” operation of the two-terminal semiconductor device of the first embodiment is the peripheral circuit in addition to the “set voltage” of the two “resistance change elements” And the desired “on-state” resistance value. The application of the “programming voltage” may be a pulse application or a sweep application. Further, as long as the potential of the second terminal 154 becomes a “negative voltage” with respect to the potential of the first terminal 153, the “programming voltage” may be applied in any “applied voltage polarity”.

Next, in the case of the “reset” operation, the “reset voltage” is applied between the first terminal 153 and the second terminal 154 in the same manner as in the “set” operation. At this time, the “reset current” flows only in one of the resistance change elements that is in the “on state”. Therefore, the “reset operation” is performed in one of the resistance change elements that is in the “on state”. On the other hand, since no current is supplied to the other resistance change elements that originally remain in the “off state”, there is no influence. As a result, when one resistance change element that has been in the “on state” returns to the “off state”, the entire two-terminal semiconductor device 150 in which the resistance change elements 151a and 151b are connected in parallel is also in the “off state”. Return to. In this way, as in the “set” operation, during the “reset” operation, of the two resistance change elements connected in parallel, only one of the resistance change elements having the lower “set voltage” is used. , Causing a resistance change.

FIG. 4 shows a case where a single 2 Mb variable resistance element and a two-terminal semiconductor device in which two variable resistance elements are connected in parallel are “set” in the two-terminal semiconductor device of the first embodiment. It is the graph which compared standardized "set voltage" distribution. The median value of the “set voltage” variation (distribution) of the variable resistance element alone is normalized to 0, and the standard deviation is normalized to 1. The standard deviation representing the “set voltage” variation (distribution) of the entire two-terminal semiconductor device in which two variable resistance elements are connected in parallel is reduced from 1 to 0.83. At the same time, in the case of a variable resistance element alone, the standardized minimum applied programming voltage required to “set” all the 2Mb elements is 4.8, but the two variable resistance elements are connected in parallel. In the case of a semiconductor device, it is confirmed that the normalized minimum applied programming voltage required to “set” all 2 Mb elements is reduced to 3.0.

In the first embodiment, as shown in FIGS. 2 and 3, a two-terminal semiconductor device in which two resistance change elements 151a and 151b are connected in parallel is taken as an example. Is explained. Even in the configuration of a two-terminal semiconductor device in which three or more variable resistance elements are connected in parallel, the operation principle is essentially the same. As the number of variable resistance elements that are connected in parallel to configure the two-terminal semiconductor device increases, the probability that a variable resistance element having a lower “set voltage” is included increases. In other words, there is a high probability that a plurality of resistance change elements connected in parallel include a resistance change element having a “set voltage” lower than the median of the “set voltage” distribution of the resistance change element alone. . As a result, when the number of resistance change elements connected in parallel is increased, variation in “set voltage” of the two-terminal semiconductor device to which the resistance change elements are connected in parallel can be further reduced.

In a two-terminal semiconductor device in which actual resistance change elements are connected in parallel, each first electrode 1 and first terminal 153 of a plurality of resistance change elements are connected, and each second electrode 2 and second terminal 154 are connected. It can be confirmed with various measuring instruments that the configuration is connected. For example, when the two-terminal type semiconductor device 150 is formed in a multilayer copper wiring layer on a semiconductor substrate, each “resistance change element” is observed by observation with a transmission electron microscope (TEM) or a scanning electron microscope (SEM). By examining the first electrode 1 and the second electrode 2 and the connection form thereof, it can be confirmed that the configuration is as described above.

(Second Embodiment)
The second embodiment of the present invention is a configuration of a three-terminal semiconductor device configured by the pair of the two-terminal semiconductor device 150 described in the first embodiment.

The configuration of the three-terminal semiconductor device of the second embodiment will be described. FIG. 5 is a partial cross-sectional view showing a configuration example of the three-terminal semiconductor device according to the second embodiment.

FIG. 6 is a circuit diagram showing a configuration example of the three-terminal semiconductor device according to the second embodiment shown in FIG. In the circuit diagram, the connection form of the terminals of each variable resistance element is indicated by the symbols shown in FIG.

As shown in FIG. 5, the three-terminal semiconductor device of this embodiment is configured by the pair of the two- terminal semiconductor devices 150a and 150b described in the first embodiment, and each of the two- terminal semiconductor devices 150a and 150b. The second terminals 154a and 154b constituting the are electrically connected to the control terminal 157. On the other hand, the first terminal 153a of the two-terminal semiconductor device 150a and the first terminal 153b of the two-terminal semiconductor device 150b are electrically connected to the remaining two terminals of the three-terminal semiconductor device, respectively.

In the three-terminal semiconductor device according to the second embodiment, when a “programming voltage” is applied between the first terminal 153a and the control terminal 157 constituting the two-terminal semiconductor device 150a, the two terminals according to the first embodiment. As described in the type semiconductor device, one of the two resistance change elements 151a and 151b connected in parallel and constituting the two-terminal type semiconductor device 150a has a lower “set voltage”. When the “programming voltage” reaches the “set voltage”, the change element changes its resistance from the “off (high resistance) state” to the “on (low resistance) state”. That is, when the applied “programming voltage” reaches a lower “set voltage” of the “set voltages” of the two resistance change elements 151a and 151b, the entire two-terminal semiconductor device 150a is “set”. The When one of the two resistance change elements connected in parallel enters the “ON state”, it is difficult to further increase the applied “programming voltage” to the “set voltage” of the other resistance change elements. As a result, the programming voltage applied exceeds the “set voltage” of one resistance change element that is already “ON”, but does not reach the “set voltage” of the other resistance change element. Therefore, after the “programming operation”, the other variable resistance element having the higher “set voltage” remains in the “off state”.

Next, when a “programming voltage” is applied between the first terminal 153a and the control terminal 157 constituting the two-terminal semiconductor device 150b, the two-terminal semiconductor device is the same as the two-terminal semiconductor device 150a described above. Of the two resistance change elements 151a and 151b that are connected in parallel and constitute 150b, one of the resistance change elements having a lower “set voltage” reaches the “programming voltage” of the “set voltage”. Then, the resistance changes from the “off (high resistance) state” to the “on (low resistance) state”. That is, when the applied “programming voltage” reaches a lower “set voltage” of the “set voltages” of the two resistance change elements 151 a and 151 b, the entire two-terminal semiconductor device 150 b is “set”. The

Also in the three-terminal semiconductor device of the second embodiment, the application conditions of the “programming voltage” necessary for the “set” operation of the two- terminal semiconductor devices 150a and 150b are the configurations of the two-terminal semiconductor devices. In addition to the “set voltage” of the two “resistance change elements” used in the above, it depends on the form of the peripheral circuit, the desired “ON state” resistance value, and the like. During the “set” operation of each of the two- terminal semiconductor devices 150a and 150b, the “programming voltage” may be applied by applying a pulse or a sweep. In addition, as long as the potential of the first terminal 153a or the potential of the first terminal 153b is used as a reference and the potential of the control terminal 157 is a “negative voltage”, the “programming voltage” is applied in any “applied voltage polarity”. But you can.

The two-terminal type semiconductor device 150a and the two-terminal type semiconductor device 150b are sequentially “set”, and both are turned “on”, whereby the first terminal 153a constituting the two-terminal type semiconductor device 150a and the two-terminal type semiconductor device Switching between the two terminals of the first terminal 153b constituting the device 150b is switched from the “high resistance state” to the “low resistance state”. As a result, the two terminals of the first terminal 153a constituting the two-terminal semiconductor device 150a and the first terminal 153b constituting the two-terminal semiconductor device 150b are electrically connected with low resistance. It becomes a state.

In the three-terminal semiconductor device of the second embodiment, the two-terminal semiconductor device 150a and the two-terminal semiconductor device 150b both adopt a configuration in which the resistance change elements 151a and 151b are connected in parallel. It is possible to transmit an electrical signal between the first terminal 153a and the first terminal 153b while reducing the variation of the “set voltage”.

The operation mechanism of the “reset” operation of the two-terminal semiconductor device 150a and the two-terminal semiconductor device 150b is essentially the same as the operation mechanism described in the two-terminal semiconductor device of the first embodiment.

In the “reset” operation, the “reset voltage” is applied between the first terminal 153a or the first terminal 153b and the control terminal 157 as in the “set” operation. At this time, the “reset current” flows only in one of the resistance change elements that is in the “on state”. Therefore, the “reset operation” is performed in one of the resistance change elements that is in the “on state”. On the other hand, since no current is supplied to the other resistance change elements that originally remain in the “off state”, there is no influence. As a result, when one resistance change element that has been in the “on state” returns to the “off state”, the two-terminal semiconductor device 150a in which the resistance change elements 151a and 151b are connected in parallel, or the two-terminal type The entire semiconductor device 150b also returns to the “off state”. In this way, as in the “set” operation, during the “reset” operation, of the two resistance change elements connected in parallel, only one of the resistance change elements having the lower “set voltage” is used. , Causing a resistance change.

In the second embodiment, as shown in FIGS. 5 and 6, a three-terminal semiconductor device using two- terminal semiconductor devices 150a and 150b in which two resistance change elements 151a and 151b are connected in parallel is used. Taking the example, the operation principle of the semiconductor device of the present invention is described. Even in the configuration of a three-terminal semiconductor device using a two-terminal semiconductor device in which three or more variable resistance elements are connected in parallel, the operation principle is essentially the same. Probability of including a variable resistance element having a lower “set voltage” as the number of variable resistance elements connected in parallel in the two-terminal semiconductor device used in the configuration of the three-terminal semiconductor device increases. Becomes higher. In other words, there is a high probability that a plurality of resistance change elements connected in parallel include a resistance change element having a “set voltage” lower than the median of the “set voltage” distribution of the resistance change element alone. . As a result, when the number of resistance change elements connected in parallel is increased, variation in “set voltage” of the two-terminal semiconductor device to which the resistance change elements are connected in parallel can be further reduced.

Note that the three-terminal semiconductor device of the second embodiment is an electric signal switch that transmits between the first terminal 153a and the first terminal 153b. On the other hand, when the first terminal 153a and the first terminal 153b are electrically connected, the two-terminal semiconductor device 150 described in the first embodiment is similar to the case where a total of four resistance change elements are connected in parallel. It becomes composition.

The three-terminal semiconductor device configuration of the second embodiment is also configured by a pair of two two- terminal semiconductor devices 150a and 150b, and the second terminal 154a that constitutes each of the two- terminal semiconductor devices 150a and 150b, It can be confirmed with various measuring instruments that both 154b are electrically connected to the control terminal 157. For example, when the three-terminal semiconductor device of the second embodiment is formed in a multilayer copper wiring layer on a semiconductor substrate, the first electrode 1 of each “resistance change element” is observed by TEM observation and SEM observation. And the second electrode 2, the second terminals 154a, 154b, and the control terminal 157 can be checked to confirm the configuration described above.

(Third embodiment)
The semiconductor device of the third embodiment is configured to employ a solid electrolyte switch element as a resistance change element used in the configuration of the two-terminal semiconductor device described in the first embodiment.

FIG. 7A is a partial cross-sectional view schematically showing a configuration of a solid electrolyte switch element used as a variable resistance element constituting the semiconductor device of the third embodiment.

As shown in FIG. 7A, the solid electrolyte switch element 159 used in the third embodiment includes a first electrode 1, a second electrode 2, and a resistance change sandwiched between the first electrode 1 and the second electrode 2. Layer 3. The resistance change layer 3 includes a buffer layer 4 and a solid electrolyte layer 5 capable of conducting metal ions in the order closer to the first electrode 1.

1st electrode 1 is comprised with the material used as the supply source of metal ion. Preferably, the 1st electrode 1 consists of a metal material containing copper from a viewpoint of controllability of metal ionization and supply, and the metal ion supplied from this metal material is a copper ion.

The second electrode 2 is made of a material containing a metal that is harder to ionize than the metal material used for the first electrode 1. Preferably, the 2nd electrode 2 is comprised with the material containing Ru from a viewpoint of the ease of electrode processing.

The buffer layer 4 is provided in contact with the entire surface of the first electrode 1 and is made of a material capable of suppressing oxidation of the surface of the first electrode 1. For the purpose of suppressing oxidation of a metal material containing copper, the buffer layer 4 is preferably made of a material containing at least one of Al, Hf, Ta, Ti, and Zr.

The solid electrolyte layer 5 has a role of dissolving metal ions supplied from the first electrode 1 by applying a voltage between the first electrode 1 and the second electrode 2. Metal ions dissolved in the solid electrolyte layer 5, for example, copper ions, are transported by an electric field caused by a voltage applied between the first electrode 1 and the second electrode 2. In addition, the solid electrolyte layer can be obtained by a solid electrolyte material in which copper ions are easily eluted from a metal material containing copper or can be recovered by reducing the copper ions to copper by an electric field caused by an applied voltage. 5 is produced. The solid electrolyte material for producing the solid electrolyte layer 5 is preferably a material with little material deterioration due to switching cycles. Therefore, the solid electrolyte layer 5 uses, for example, an oxide containing at least one of Al, Co, Fe, Hf, Mn, Si, Ta, Ti, Zn, and Zr, chalcogenide, amorphous Si, SiOCH, or the like. Is produced.

The semiconductor device of the third embodiment is a semiconductor device in which at least two solid electrolyte switch elements are connected in parallel as resistance change elements. In the semiconductor device of the third embodiment manufactured using a solid electrolyte switch element, as well as the two-terminal semiconductor device having the configuration described in the first embodiment, the variation in set voltage is suppressed. Is possible.

(Fourth embodiment)
The semiconductor device according to the fourth embodiment has a configuration in which the two-terminal semiconductor device according to the first embodiment is provided inside a multilayer wiring structure formed on a semiconductor substrate.

FIG. 8 schematically shows an example of the configuration of the semiconductor device of the fourth embodiment, in which a solid electrolyte switch element is employed as a variable resistance element and is provided inside a multilayer wiring structure formed on a semiconductor substrate. It is the fragmentary sectional view shown in.

As shown in FIG. 8, a solid electrolyte switch element 159 is provided as a resistance change element on a semiconductor substrate 101 with a first interlayer insulating film 102 interposed therebetween. The solid electrolyte switch element 159 used in the semiconductor device of the fourth embodiment has the same configuration as the solid electrolyte switch element used in the configuration of the semiconductor device of the third embodiment.

As shown in FIG. 7A, the solid electrolyte switch element 159 described in the third embodiment includes a first electrode 1 and a second electrode 2, and a variable resistance layer sandwiched between the first electrode 1 and the second electrode 2. The resistance change layer 3 includes a buffer layer 4 and a solid electrolyte layer 5 capable of conducting the metal ions in the order closer to the first electrode 1. The solid electrolyte switch element 159 used in the semiconductor device of the fourth embodiment adopts the configuration shown in FIG. 7B. In the configuration shown in FIG. 7B, the buffer layer 4 is composed of a first metal oxide layer 6 and a second metal oxide layer 7. Therefore, the solid electrolyte switch element 159 used in the semiconductor device of the fourth embodiment includes a lower wiring 106, a first metal oxide layer (not shown), a second metal oxide layer (not shown), and a solid electrolyte layer. 123, a first upper electrode 124, and a second upper electrode 125.

As an example, the configuration shown in FIG. 8 can be adopted for the lower wiring 106, the first metal oxide layer, the second metal oxide layer, the solid electrolyte layer 123, and the first upper electrode 124. The lower wiring 106 corresponds to the first electrode 1 shown in FIG. 7B. The first metal oxide layer 121 corresponds to the first metal oxide layer 6, and the second metal oxide layer 122 corresponds to the second metal oxide layer 7. The solid electrolyte layer 123 corresponds to the solid electrolyte layer 5, and the first upper electrode 124 corresponds to the second electrode 2. The operation principle of the solid electrolyte switch element having the configuration shown in FIG. 7B is the same as the operation principle of the solid electrolyte switch element having the structure shown in FIG. 7A described in the third embodiment. Therefore, in the fourth embodiment, Detailed description thereof is omitted.

Also in the solid electrolyte switch element used in the fourth embodiment, by providing the first metal oxide layer 121, the leakage current can be reduced more effectively and the characteristic variation between elements can be reduced. can do. In the solid electrolyte switch element used in the fourth embodiment, the first metal oxide layer 121 is, for example, TiO _y1 with an oxygen composition y1 with a thickness of 0.5 nm satisfying 1.5 ≦ y1 ≦ 2.0. Can be produced.

Further, the second metal oxide layer 127 functions as a passive layer, and can suppress oxidation of the lower wiring 106 containing Cu in the lower layer. In the solid electrolyte switch element used in the fourth embodiment, the second metal oxide layer 122 is, for example, an AlO _x1 having a 0.3 nm-thickness oxygen composition x1 satisfying 1.3 ≦ x1 ≦ 1.5. Can be produced.

The solid electrolyte layer 123 can be made of, for example, a 6 nm thick SiOCH film. The first upper electrode 124 can be made of, for example, Ru _0.5 Ti _0.5 having a thickness of 10 nm.

The second upper electrode 125 is a conductive film having a barrier property, and is formed to prevent the metal contained in the first upper electrode 124 in contact with the lower part from diffusing into the via plug 144 or the like. The second upper electrode 125 can be made of Ta with a film thickness of 25 nm, for example.

As shown in FIG. 8, a second hard mask film 128 and a third hard mask film 129 are formed on the stacked body of the first upper electrode 124 and the second upper electrode 125 in the solid electrolyte switch element 159. Side surfaces of the first metal oxide layer 121, the second metal oxide layer 122, the solid electrolyte layer 123, the first upper electrode 124, the second upper electrode 125, the second hard mask film 128, and the third hard mask film 129; The upper surface of the first barrier insulating film 107 is covered with a protective insulating film 130.

The lower wiring 106 is a wiring buried in a wiring groove formed in the second interlayer insulating film 103 and the first cap insulating film 104 via the first barrier metal 105. By forming the lower wiring 106 from a metal material whose main component is Cu, it is used as a lower electrode corresponding to the first electrode 1 in the solid electrolyte switch element having the configuration shown in FIG. 7B. With this configuration, the lower wiring 106 can have a function of ionizing Cu atoms in the lower wiring 106 and eluting them into the solid electrolyte layer 123. Furthermore, by forming the lower wiring 106 with a Cu material structure, a metal component that has not been formed in the first metal oxide layer 121 while being unoxidized can be alloyed with Cu and diffused into the lower wiring 106. For example, when Cu is used for the lower wiring 106 and the main component constituting the first metal oxide layer 121 is an oxide made of Ti, the interface between the lower wiring 106 and the first metal oxide layer 121 is An alloy layer mainly composed of Cu and Ti is formed.

The solid electrolyte layer 123 and the lower wiring 106 are connected at the opening of the first barrier insulating film 107 via the first metal oxide layer 121 and the second metal oxide layer 122. At this time, the width of the lower wiring 106 connected to the solid electrolyte layer 123 through the metal oxide layer is preferably larger than the diameter of the opening of the barrier insulating film 107.

The first barrier metal 105 is a conductive film having a barrier property similar to that of the second upper electrode 125. The first barrier metal 105 covers the side surface and the bottom surface of the lower wiring 106. In the first barrier metal 105 formed of a conductive film having a barrier property, the metal contained in the lower wiring 106 diffuses into the first interlayer insulating film 102, the second interlayer insulating film 103, the first cap insulating film 104, and the like. To prevent. For the formation of the first barrier metal 105, for example, when the lower wiring 106 is made of a metal material mainly composed of Cu, a refractory metal such as Ta, TaN, TiN, WCN, nitride thereof, or the like A laminated film is used.

The upper wiring 145 is a wiring buried in a wiring groove formed in the third interlayer insulating film 141 and the second cap insulating film 142 via the second barrier metal 143. The upper wiring 145 is integrated with the via plug 144. The via plug 144 is embedded in a prepared hole formed in the protective insulating film 130, the third hard mask film 129, and the second hard mask film 128 via the second barrier metal 143. The via plug 144 is electrically connected to the first upper electrode 124 and the second upper electrode 125 of the solid electrolyte switch element 159 via the second barrier metal 143. For example, Cu is used to manufacture the upper wiring 145 and the via plug 144.

The second barrier metal 143 is a conductive film having the same barrier properties as the first barrier metal 105. The second barrier metal 143 covers the side surfaces and the bottom surface of the upper wiring 145 and the via plug 144. The second barrier metal 143 formed of a conductive film having a barrier property is such that the metal included in the upper wiring 145 and the via plug 144 is the first via interlayer insulating film 140, the third interlayer insulating film 141, and the second cap insulating film. The diffusion to 142 is prevented. For the formation of the second barrier metal 143, for example, when the upper wiring 145 and the via plug 144 are made of a metal material containing Cu as a main component, Ta, TaN, TiN, WCN are formed as in the first barrier metal 105. Such a refractory metal, a nitride thereof, or a laminated film thereof is used.

The second barrier metal 143 is preferably made of the same material as the second upper electrode 125 which is a part of the configuration of the solid electrolyte switch element 159 from the viewpoint of reducing the contact resistance. For example, when the second upper electrode 125 is made of Ta, it is preferable to use Ta also for the production of the second barrier metal 143 in contact with the upper portion thereof.

The third hard mask film 129 is a film that serves as a hard mask when the second hard mask film 128 is etched. The third hard mask film 129 is preferably a different type of film from the second hard mask film 128. For example, when the second hard mask film 128 is a SiCN film, a SiO ₂ film can be used for the third hard mask film 129.

The protective insulating film 130 further prevents diffusion of constituent atoms (for example, copper ions) from the solid electrolyte switch element 159 to the first via interlayer insulating film 140 without damaging the solid electrolyte switch element 159 whose side surface is exposed. This is an insulating film having a function. For the production of the protective insulating film 130, for example, a SiN film, a SiCN film, or the like can be used. The first barrier insulating film 107 and the second barrier insulating film 146 are insulating films having a function of preventing diffusion of metal (for example, copper ions).

In the semiconductor device of the fourth embodiment, as shown in FIG. 8, the lower wiring 106 corresponding to the first electrode 1 and the first metal oxide layer through the opening provided in the first barrier insulating film 107 121 is in contact. With this configuration, a Cu electrode serving also as a Cu wiring can be used as the first electrode 1, and a resistance change element using a Cu electrode can be formed in the multilayer wiring structure on the CMOS substrate. Since the lower electrode of the variable resistance element also functions as a Cu wiring, the manufacturing process can be simplified.

Next, a method for manufacturing a solid electrolyte switch element that can be used as a component of the semiconductor device of the fourth embodiment will be described in the case of the solid electrolyte switch element shown in FIG. 9J that employs the configuration shown in FIG. 7B. To do. The semiconductor device of the fourth embodiment shown in FIG. 8 can be manufactured by applying the manufacturing method of FIGS. 9A to 9J in which the variable resistance element is provided inside the multilayer wiring structure on the semiconductor substrate.

FIG. 9A to FIG. 9J are partial cross-sectional views for explaining a manufacturing method for providing a solid electrolyte switch element in a multilayer wiring structure on a semiconductor substrate, which employs the configuration shown in FIG. 7B.

First, a first interlayer insulating film 102, a second interlayer insulating film 103, and a first cap insulating film 104 are sequentially formed on the semiconductor substrate 101. The semiconductor substrate 101 here may be the semiconductor substrate itself or a substrate on which a semiconductor element (not shown) is formed on the surface of the substrate. For example, the first interlayer insulating film 102 is a 300 nm thick SiO ₂ film, the second interlayer insulating film 103 is a 150 nm thick SiOCH film, and the first cap insulating film 104 is a 100 nm thick SiO ₂ film. Can be produced.

Subsequently, a wiring trench is formed in the laminated film of the first cap insulating film 104, the second interlayer insulating film 103, and the first interlayer insulating film 102 by using a lithography method. This lithography method includes a photoresist forming process for forming a resist with a predetermined pattern on the first cap insulating film 104, a dry etching process for performing anisotropic etching on the laminated film using the resist as a mask, and an etching process. And a process of removing the resist after forming the wiring trench.

Thereafter, a metal is buried in the wiring trench through the first barrier metal 105 to form the lower wiring 106. The first barrier metal 105 can be formed with, for example, a stacked structure of TaN (film thickness 5 nm) / Ta (film thickness 5 nm). For example, Cu can be used as the material of the lower wiring 106.

Subsequently, a first barrier insulating film 107 is formed on the first cap insulating film 104 including the lower wiring 106. The first barrier insulating film 107 can be formed of, for example, a SiCN film having a thickness of 30 nm. Next, as shown in FIG. 9A, a first hard mask film 108 is formed on the first barrier insulating film 107. The first hard mask film 108 is preferably made of a material different from that of the first barrier insulating film 107 from the viewpoint of maintaining a high etching selectivity in the dry etching process. Here, when the first barrier insulating film 107 is formed of a SiCN film, the first hard mask film 108 can be manufactured using, for example, a SiO ₂ film. When the first barrier insulating film 107 is formed of a SiCN film having a thickness of 30 nm, the first hard mask film 108 can be manufactured using, for example, a SiO ₂ film having a thickness of 40 nm.

Subsequently, a photoresist having a predetermined opening pattern is formed on the first hard mask film 108 and dry etching is performed to form openings in the first hard mask film 108. The photoresist is removed by O ₂ plasma ashing or the like. Then, the first barrier insulating film 107 exposed at the bottom of the opening of the first hard mask film 108 is etched back, so that an opening exposing a part of the upper surface of the lower wiring 106 is formed in the first barrier insulating film 107. Form. The first hard mask film 108 is formed by using a SiO ₂ film having a thickness of 40 nm, and is removed by etching during this etch back. After this etch-back, as shown in FIG. 9B, the surface of the lower wiring 106 exposed at the bottom of the opening is cleaned by plasma irradiation using an organic solvent or a gas containing H ₂ or an inert gas.

9A to 9B are defined as step A1.

In step A1, the etch back for forming the opening of the first barrier insulating film 107 can be performed using plasma containing CF ₄ when the first barrier insulating film 107 is a SiN film or a SiCN film. It is. The conditions are, for example, the conditions of CF ₄ / Ar gas flow rate = 25/50 sccm, pressure 0.53 Pa, source power 400 W, and substrate bias power 90 W. By reducing the source power or increasing the substrate bias, the ionicity at the time of etching can be improved, and the side wall of the first barrier insulating film 107 can be tapered. Further, the first hard mask film 108 can be removed by etching by this etch back.

Next, as shown in FIG. 9C, the first metal layer 161 used for forming the first metal oxide layer 121 on the first barrier insulating film 107 including the opening from which the lower wiring 106 is exposed, and A second metal layer 162 used to form the second metal oxide layer 122 is deposited in this order. The first metal layer 161 includes at least one of Ti, Zr, and Hf. The second metal layer 162 includes at least one of Al, Nb, and Ta. As an example, the first metal layer 161 can be formed using a Ti film having a thickness of 0.5 nm, and the second metal layer can be formed using an Al film having a thickness of 0.2 nm.

After the first metal layer 161 and the second metal layer 162 are deposited, the first metal layer 161 and the second metal layer 162 are irradiated with a gas containing O ₂ under reduced pressure without being exposed to the atmosphere. Oxidation treatment is performed. Subsequently, by performing vacuum heat treatment at a temperature higher than the film formation temperature under reduced pressure, the first metal oxide layer 121 and the second metal oxide layer 122 are simultaneously formed as shown in FIG. 9C.

Next, a solid electrolyte layer 123 is deposited on the formed second metal oxide layer 122. For production of the solid electrolyte layer 123, for example, a 6-nm-thick SiOCH film can be used. In this case, the solid electrolyte layer 123 is deposited by a plasma CVD method, and then an inert gas plasma process is performed.

Subsequently, the first upper electrode 124 and the second upper electrode 125 are formed in this order on the solid electrolyte layer 123 by DC sputtering. The lower wiring 106, the first metal oxide layer 121, the second metal oxide layer 122, the solid electrolyte layer 123, the first upper electrode 124, and the second upper electrode 125 constitute a stacked body that becomes the solid electrolyte switch element 159. . The first upper electrode 124 can be formed of, for example, a Ru _0.5 Ti _0.5 film having a thickness of 10 nm. The second upper electrode 125 can be formed of, for example, a Ta film having a thickness of 25 nm. When the first upper electrode 124 is made of Ru or a Ru alloy, the first upper electrode 124 is continuously deposited without being exposed to the atmosphere after the deposition of the first upper electrode 124 in order to prevent surface oxidation of the first upper electrode 124. Preferably, two upper electrodes 125 are deposited.

Subsequently, as illustrated in FIG. 9D, the second hard mask film 128 and the third hard mask film 129 are stacked in this order on the second upper electrode 125. The second hard mask film 128 is preferably made of the same material as that of the first barrier insulating film 107 from the viewpoint of adhesion, and can be made of, for example, a SiCN film having a thickness of 30 nm. The third hard mask film 129 can be made of, for example, a 100 nm thick SiO ₂ film.

9A to 9D is referred to as step A2.

In step A2, the first metal layer 161 and the second metal layer 162 can be deposited by resistance heating of a metal raw material, electron beam irradiation, laser vapor deposition, DC sputtering, or the like. As an example, when the first metal layer 161 is formed of a Ti film, DC sputtering is used with Ti as a target, sputtering power of 100 W, substrate temperature at room temperature, Ar flow rate of 20 sccm, and pressure of 0.5 Pa. Thus, a Ti film having a thickness of 0.5 nm for the first metal layer 161 can be deposited. When the second metal layer 162 is formed of an Al film, DC sputtering is used, using Al as a target, sputtering power of 150 W, substrate temperature at room temperature, Ar flow rate of 20 sccm, and pressure of 0.5 Pa. Thus, an Al film having a thickness of 0.2 nm for the second metal layer 162 can be deposited.

In step A2, the first metal oxide layer 121 formed by oxidation of the first metal layer 161 and the second metal oxide layer 161 are oxidized by irradiating with gas containing O ₂ without being exposed to the atmosphere. The degree of oxidation of the second metal oxide layer 122 formed by the oxidation of the metal layer 162 can be accurately controlled. As an example, when the first metal layer 161 is formed of a 0.5 nm thick Ti film and the second metal layer 162 is formed of a 0.2 nm thick Al film, the substrate temperature is set to room temperature. The first metal oxide layer 121 made of an oxide of Ti and the second metal oxide layer made of an oxide of Al by O ₂ gas irradiation with an O ₂ flow rate of 10 sccm, a pressure of 0.5 Pa, and an irradiation time of 60 seconds. 122 can be formed.

Further, in step A2, the heat treatment after the above-described oxidation treatment is performed by, for example, forming the first metal layer 161 with a 0.5 nm-thick Ti film and the second metal layer 162 with a 0.2 nm-thickness. In the case where the Al film is formed, it is preferable that the N ₂ and O ₂ flow rate is 10/10 sccm, the pressure is 900 Pa, and the processing time is 30 seconds at a substrate temperature of 400 ° C. or lower. By this heat treatment, the metal component Ti in the first metal oxide layer 121 remaining unreacted in the above-described oxidation treatment is transformed into the first metal oxide by alloying diffusion on the surface of the lower wiring 106 made of Cu. It can be removed from layer 121. Further, the vacuum means a state where the atmospheric pressure in the chamber is as low as possible, and is at least a lower pressure than the above-described oxidation treatment. The film thickness of the first metal oxide layer 121 is preferably 1.0 nm or less, and the film thickness of the second metal oxide layer 122 is preferably 0.8 nm or less.

In step A2, when a SiOCH film is used for the solid electrolyte layer 123, the SiOCH film is formed by the plasma CVD method under the following conditions. The raw material is liquid SiOCH monomer molecules, the substrate temperature is 400 ° C. or less, the He flow rate is 500 to 2000 sccm, the raw material flow rate is 0.1 to 0.8 g / min, the plasma CVD chamber pressure is 360 to 700 Pa, and the RF power is 20 to 100 W. By setting respectively, the SiOCH film for the solid electrolyte layer 123 can be deposited. Specifically, the SiOCH film for the solid electrolyte layer 123 can be deposited under the conditions of a substrate temperature of 350 ° C., a He flow rate of 1500 sccm, a raw material flow rate of 0.75 g / min, a plasma CVD chamber pressure of 470 Pa, and an RF power of 50 W. In addition, the inert plasma treatment after depositing the SiOCH film for the solid electrolyte layer 123 uses He as an inert gas, the substrate temperature is set to 400 ° C. or less, the He flow rate is 500 to 1500 sccm, and the plasma chamber pressure is 2.7 to 3. This can be done by setting 5 Torr and RF power 20 to 200 W, respectively. Specifically, it can be performed under the conditions of a substrate temperature of 350 ° C., a He flow rate of 1000 sccm, a plasma chamber pressure of 360 Pa, an RF power of 50 W, and a processing time of 30 seconds. By this inert plasma treatment, the adhesion with the first upper electrode 124 to be deposited next can be improved.

Further, in Step A2, for example, when using a Ru _0.5 Ti _0.5 alloy film to manufacture the first upper electrode 124, the Ru _0.5 Ti _0.5 alloy film may be deposited by simultaneous DC sputtering using Ru and Ti as targets. it can. A Ru _0.5 Ti _0.5 alloy film can be deposited by using the conditions of Ru sputtering power 120 W, Ti sputtering power 150 W, substrate temperature at room temperature, Ar flow rate 20 sccm, and pressure 0.5 Pa. Further, after the first upper electrode 124 is deposited, the second upper electrode 125 is continuously deposited without being exposed to the atmosphere. For example, when the second upper electrode 125 is made of Ta with a film thickness of 25 nm, the sputtering power is 300 W, the substrate temperature is room temperature, the Ar flow rate is 25 sccm, and the pressure is 0.5 Pa by DC sputtering. By using it, a Ta film can be continuously deposited without being exposed to the atmosphere after the Ru _0.5 Ti _0.5 alloy film is deposited.

In Step A2, both the second hard mask film 128 and the third hard mask film 129 can be formed using a general plasma CVD method in the technical field of semiconductor manufacturing. At the time of film formation by the plasma CVD method, the film formation temperature can be selected in the range of 200 ° C. to 400 ° C. Here, the film formation temperature can be selected to be 350 ° C. during the film formation by the plasma CVD method.

Next, after forming a photoresist having a processing pattern of the resistance change element 126 on the third hard mask film 129, the third hard mask film 129 is dry-etched until the second hard mask film 128 appears. Subsequently, after removing the photoresist by O ₂ plasma ashing, the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, and the third hard mask film 129 are used as a mask. The second metal oxide layer 122 and the first metal oxide layer 121 are continuously dry etched. FIG. 9E shows the state after the etching.

After Step A2, the process until the structure shown in FIG. 9E is formed is referred to as Step A3.

In step A3, the dry etching of the third hard mask film 129 is preferably stopped on the upper surface or inside the second hard mask film 128. In this case, since the solid electrolyte switch element 159 is covered with the second hard mask film 128, it is not exposed to O ₂ plasma. Also, the first upper electrode 124 containing Ru is not exposed to O ₂ plasma. Therefore, the occurrence of side etching with respect to the first upper electrode 124 can be suppressed. For the dry etching of the third hard mask film 129, a general parallel plate type dry etching apparatus can be used.

In Step A3, each etching of the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, the second metal oxide layer 122, and the first metal oxide layer 121 is performed. Also, it can be performed collectively using a parallel plate type dry etcher.

Etching of the second hard mask film 128 (for example, SiCN film) can be performed under the conditions of a gas flow rate of CF ₄ / Ar = 25/50 sccm, a pressure of 0.53 Pa, a source power of 400 W, and a substrate bias power of 90 W.

In step A3, the etching of the second upper electrode 125 (eg, Ta film) is performed under the conditions of a substrate temperature of 90 ° C., a Cl ₂ gas flow rate = 50 sccm, a pressure of 0.53 Pa, a source power of 400 W, and a substrate bias power of 60 W. It can be carried out.

Etching of the first upper electrode 124 (for example, Ru _0.5 Ti _0.5 alloy film) is performed at a substrate temperature of room temperature, an O ₂ / Cl ₂ gas flow rate = 160/30 sccm, a pressure of 0.53 Pa, a source power of 300 to 600 W, The substrate bias power can be 100 to 300 W.

In addition, when the Ru _0.5 Ti _0.5 alloy film is used for the first upper electrode 124, the solid electrolyte layer 123 (eg, SiOCH film) can be etched under the same conditions as the etching of the first upper electrode 124. Therefore, the solid electrolyte layer 123 (SiOCH film) and the first upper electrode 124 (Ru _0.5 Ti _0.5 alloy film) can be etched together.

In addition, the second metal oxide layer 122 (for example, an AlO _x1 film having a thickness of 0.3 nm where the oxygen composition x1 satisfies 1.3 ≦ x1 ≦ 1.5), and the first metal oxide layer 121 (for example, In the etching of a 0.5 nm-thick TiO _y1 film in which the oxygen composition y1 satisfies 1.5 ≦ y1 ≦ 2.0, when a Ru _0.5 Ti _0.5 alloy film is used for the first upper electrode 124, the solid electrolyte layer Similarly to 123 (SiOCH film), the etching can be performed under the same conditions as those for etching the first upper electrode 124 (Ru _0.5 Ti _0.5 alloy film). Therefore, the second metal oxide layer 122 (AlO _x1 film) and the first metal oxide layer 121 (TiO _y1 film) are _replaced with the first upper electrode 124 (Ru _0.5 Ti _0.5 alloy film) and the solid electrolyte layer 123 (SiOCH film). Etching can be performed at once.

In Step A3, the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, the second metal oxide layer 122, and the first metal oxide are formed under the above-described conditions. After each etching of the layer 121, the remaining thickness of the third hard mask film 129 made of a 100 nm thick SiO ₂ film can be set to 50 nm.

Next, as shown in FIG. 9F, a third hard mask film 129, a second hard mask film 128, a second upper electrode 125, a first upper electrode 124, a solid electrolyte layer 123, a second metal oxide layer 122, and A protective insulating film 130 is deposited on the top and side walls of the laminated structure composed of the first metal oxide layer 121 and the first barrier insulating film 107. The protective insulating film 130 is preferably made of the same material as the first barrier insulating film 107 and the second hard mask film 128, and can be made of, for example, a SiCN film having a thickness of 30 nm.

Subsequently, as shown in FIG. 9F, a first via interlayer insulating film 140 is deposited on the protective insulating film 130 by using a plasma CVD method. The first via interlayer insulating film 140 can be made of, for example, a SiO ₂ film having a thickness of 210 nm. Next, the first via interlayer insulating film 140 is planarized using a CMP method. After planarization, a third interlayer insulating film 141 and a second cap insulating film 142 are deposited in this order on the first via interlayer insulating film 140 as shown in FIG. 9G. The third interlayer insulating film 141 is formed of a material different from that of the first via interlayer insulating film 140 in order to use the first via interlayer insulating film 140 that is in contact with the lower portion during etching processing as an etching stopper layer. The third interlayer insulating film 141 can be formed by a SiOCH film having a film thickness of 150 nm, for example.

After step S3, the process until the structure shown in FIG. 9G is formed is referred to as step A4.

In step A4, for example, when a SiCN film is used to form the protective insulating film 130, it can be formed using plasma CVD at a substrate temperature of 200 ° C. using tetramethylsilane and ammonia as source gases. By forming the protective insulating film 130 using the SiCN film, the first barrier insulating film 107, the protective insulating film 130, and the second hard mask film 128 can all be formed of the SiCN film. The first barrier insulating film 107, the protective insulating film 130, and the second hard mask film 128 are formed of the same material, and the periphery of the solid electrolyte switch element 159 is integrated and protected, thereby improving the adhesion at the interface and absorbing moisture. Performance, water resistance and oxygen desorption resistance can be improved, and the yield and reliability of the device can be improved.

Further, in step A4, in the planarization of the first via interlayer insulating film 140, about 100 nm can be removed from the top surface of the first via interlayer insulating film 140, and the remaining film thickness can be set to about 110 nm. At this time, CMP (chemical-mechanical polishing) for the first via interlayer insulating film 140 can be polished using a general colloidal silica or ceria-based slurry.

In Step A4, the third interlayer insulating film 141 and the second cap insulating film 142 can be deposited using a general plasma CVD method.

Next, the upper wiring 145 and the via plug 144 shown in FIG. 9J are formed by using the dual damascene via first method.

In the via first method, first, a photoresist having the pattern of the via hole 147 for the via plug 144 shown in FIG. 9J is formed on the second cap insulating film 142. Subsequently, the second cap insulating film 142, the third interlayer insulating film 141, the first via interlayer insulating film 140, the protective insulating film 130, and the third hard mask film 129 are penetrated by dry etching, as shown in FIG. 9H. A via hole 147 for the via plug 144 is formed. Thereafter, as shown in FIG. 9H, the photoresist is removed by performing plasma ashing including H ₂ gas and organic peeling.

Subsequently, after forming a photoresist having the pattern of the wiring groove 148 for the upper wiring 145 shown in FIG. 9J on the second cap insulating film 142, the second cap insulating film 142 and the third interlayer insulating film are formed by dry etching. A wiring groove 148 for the upper wiring 145 shown in FIG. 9J is formed in the film 141. Thereafter, as shown in FIG. 9I, plasma ashing including H ₂ gas and organic peeling are performed to remove the photoresist.

After Step A5, the process until the structure shown in FIG. 9I is formed is referred to as Step A5.

In step A5, after forming the via hole 147, an ARC (Anti-Reflection Coating: antireflection film) or the like is buried on the via hole 147, thereby preventing the bottom of the via hole 147 from penetrating when the wiring trench 148 is formed by dry etching. can do.

Next, the second upper electrode 125 is exposed from the via hole 147 by etching the second hard mask film 128 at the bottom of the via hole 147. Thereafter, an upper wiring 145 (for example, Cu) and a via plug 144 (for example, Cu) are simultaneously formed in the wiring groove 148 and the via hole 147 through a second barrier metal 143 (for example, a Ta film having a thickness of 10 nm). Thereafter, a second barrier insulating film 146 (for example, a 50 nm SiCN film) is deposited on the second cap insulating film 142 including the upper wiring 145, thereby forming the structure shown in FIG. 9J.

After step A5, the process until the structure shown in FIG. 9J is formed is referred to as step A6.

In step A6, the upper wiring 145 can be formed by using the same process as the formation of the lower wiring 106 in the lower layer. At this time, the diameter of the bottom of the via plug 144 is preferably smaller than the diameter of the opening of the first barrier insulating film 107. In the solid electrolyte switch element 159 used for manufacturing the semiconductor device of the fourth embodiment, for example, the diameter of the bottom of the via plug 144 is selected to be 60 nm, and the diameter of the opening of the first barrier insulating film 107 is selected to be 100 nm. be able to.

In step A6, the second barrier metal 143 and the second upper electrode 125 are made of the same material, so that the contact resistance between the via plug 144 and the second upper electrode 125 is reduced, and the solid electrolyte switch element in the on state is turned on. The resistance of 159 can be reduced. As a result, device performance can be improved.

Next, an embodiment of the above-described variable resistance element will be described.

(Embodiment 1)
In the first embodiment, the first metal oxide layer 6 and the second metal shown in FIG. 7B are used for the variable resistance element 126 of the third embodiment that employs a variable resistance layer composed of a buffer layer and a solid electrolyte layer. The buffer layer 4 composed of the oxide layer 7 is employed. The configuration of the solid electrolyte switch element 159 shown in FIG. 9J is adopted, elements having different combinations of the first metal oxide layer 121 and the second metal oxide layer 122 are manufactured, and the characteristics of the manufactured variable resistance element are evaluated. did.

In the first embodiment, a total of nine types including different combinations of the first metal oxide layer 121 and the second metal oxide layer 122 constituting the buffer layer with the resistance change element 126 of the third embodiment as a basic structure. The variable resistance element was manufactured. Specifically, the following nine types of combinations of the first metal oxide layer 121 and the second metal oxide layer 122 formed on the lower wiring 106 mainly composed of Cu are provided.

TiO _y1 / AlO _x1 , TiO _y1 / NbO _x2 , TiO _y1 / TaO _x3 ,
ZrO _y2 / AlO _x1 , ZrO _y2 / NbO _x2 , ZrO _y2 / TaO _x3 ,
HfO _y3 / AlO _x1 , HfO _y3 / NbO _x2 , HfO _y3 / TaO _x3
The film thickness of the first metal layer 161 for forming the first metal oxide layer 121 is 0.5 nm, and the film thickness of the second metal layer 162 for forming the second metal oxide layer 122 is , 0.2 nm is selected. After forming the second metal layer of the first metal layer and the thickness 0.2nm in thickness 0.5 nm, without exposure to the atmosphere, pressure 0.5 Pa, at room temperature, O ₂ in the O ₂ flow rate 10sccm To oxidize. By the oxidation treatment, the first metal layer becomes the first metal oxide layer 121, and the second metal layer becomes the second metal oxide layer 122. The solid electrolyte layer is formed using a SiOCH film having a thickness of 6 nm.

Note that the atomic radius of Cu is 128 pm, and the covalent bond radius is 132 ± 4 pm;
The atomic radius of Al is 143 pm, and the covalent bond radius is 121 ± 4 pm;
Nb has an atomic radius of 146 pm and a covalent bond radius of 164 ± 6 pm;
The atomic radius of Ta is 146 pm, and the covalent bond radius is 170 ± 8 pm;
Ti has an atomic radius of 147 pm and a covalent bond radius of 160 ± 8 pm;
The atomic radius of Zr is 160 pm, the covalent bond radius is 175 ± 7 pm;
The atomic radius of Hf is reported to be 159 pm, and the covalent bond radius is 175 ± 10 pm.

The film thickness of 0.2 nm of the second metal layer is a value not exceeding twice the atomic radius of Al, Nb, and Ta. The film thickness of 0.5 nm of the first metal layer is a value that does not exceed four times the atomic radius of Ti, Zr, and Hf.

In addition, in order to compare the characteristics of the variable resistance element selected in the first embodiment with the variable resistance element for selecting the combination of the first metal oxide layer 121 and the second metal oxide layer 122, a variable resistance element as a comparative example below is used. Got ready.

The variable resistance element as a comparative example employs a structure in which the buffer layer is composed of one kind of metal oxide layer. Specifically, the metal oxide layer (TiO _y1 , ZrO _y2 , and HfO _y3 ) used for the first metal oxide layer 121 and the first metal oxide layer formed on the lower wiring 106 containing Cu as a main component are used. Of the metal oxides (AlO _x1 , NbO _x2 , and TaO _x3 ) used for the two-metal oxide layer 122, only one kind of metal oxide is formed. The thickness of the metal layer for forming one kind of metal oxide layer is selected to be 0.7 nm. After forming a 0.7 nm-thick metal layer, oxidation treatment is performed by irradiating O ₂ at a pressure of 0.5 Pa and an O ₂ flow rate of 10 sccm at a room temperature without exposing to the atmosphere. By the oxidation treatment, the metal layer becomes a metal oxide layer. The solid electrolyte layer is formed using a SiOCH film having a thickness of 6 nm.

Next, for the variable resistance element of Embodiment 1 and the variable resistance element as a comparative example, the off-leak current at the time of setting and the dielectric breakdown voltage at the time of reset were evaluated. The evaluation results will be described below.

FIG. 11 is a table showing the results of measuring the off-leakage current when set, specifically, the off-leakage current when applying a negative voltage of 1 V, for the resistance change element of Embodiment 1 and the resistance change element as a comparative example. It is. The unit of numerical values shown in FIG. 11 is ampere (A).

As shown in FIG. 11, in the variable resistance element according to Embodiment 1, any combination of the first metal oxide layer 121 and the second metal oxide layer 122 is the same as the first metal oxide layer 121. A reduction in off-leakage current at the time of setting is recognized as compared with a resistance change element as a comparative example that employs a buffer layer made of only a kind of metal oxide.

FIG. 12 is a table showing the results of measuring the dielectric breakdown voltage at reset for the variable resistance element of Embodiment 1 and the variable resistance element as a comparative example. The unit of the numerical values shown in FIG. 12 is volts (V).

As shown in FIG. 12, regarding the breakdown voltage at the time of resetting, in the resistance change element of the first embodiment, in any combination of the first metal oxide layer 121 and the second metal oxide layer 122, respectively. It can be seen that this is an improvement over the resistance change element of the comparative example that employs a buffer layer made of only the same type of metal oxide as the first metal oxide layer 121 or the second metal oxide layer 122.

(Embodiment 2)
Also in the second embodiment, the configuration of the second embodiment that employs a variable resistance layer including a buffer layer and a solid electrolyte layer is applied. In the variable resistance element 126 shown in FIG. 9J, the buffer layer 4 composed of the first metal oxide layer 6 and the second metal oxide layer 7 shown in FIG. 7B is employed. Therefore, the resistance change layer includes the first metal oxide layer 121, the second metal oxide layer 122, and the solid electrolyte layer 123. On the other hand, in the second embodiment, the variable resistance element in which the buffer layer 4 is configured by the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8 shown in FIG. The produced variable resistance element was evaluated.

In the second embodiment, the variable resistance element 126 of the third embodiment is used as a basic structure, and the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8 shown in FIG. 7C. A total of seven types of variable resistance elements with different combinations were prepared. Specifically, the combinations of the first metal oxide layer 6, the second metal oxide layer 7 and the third metal oxide layer 8 formed on the lower wiring mainly composed of Cu include the following seven types: It is. _{TiO y1 / AlO x1 / TiO y4} , TiO y1 / NbO x2 / TiO y4, TiO y1 / TaO x3 / TiO y4, ZrO y2 / AlO x1 / ZrO y5, ZrO y2 / NbO x2, ZrO y2 / TaO x3 / ZrO y5 , HfO _y3 / AlO _x1 / HfO _y6
y4, y5, and y6 are the oxygen compositions in the oxides of Ti, Zr, and Hf (TiO _y4 , ZrO _y5 , HfO _y6 ) constituting the third metal oxide layer 8, respectively.

The third metal layer for forming the third metal oxide layer 8 was continuously deposited on the second metal layer for forming the second metal oxide layer 7. The film thickness of the third metal layer for forming the third metal oxide layer 8 is selected to be 0.2 nm. The variable resistance element according to Embodiment 2 has the basic structure except that the buffer layer is composed of the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8. , Which is the same as the variable resistance element 126 shown in FIG. 9J.

Next, for the variable resistance element of Embodiment 2, the off-leakage current at the time of setting and the breakdown voltage at the time of resetting were evaluated. The evaluation results will be described below.

Compared to the resistance change element of the comparative example, which employs the seven variable resistance elements of Embodiment 2 and a buffer layer made of only the same type of metal oxide as the first metal oxide layer 121, respectively. It was confirmed that the off-leakage and the breakdown voltage were improved to the same extent as the evaluation results of the resistance change element of the first embodiment.

Specifically, in the case of a resistance change element as a comparative example, which is made only of the same type of metal oxide (TiO _y1 ) as the first metal oxide layer 121 (TiO _y1 ), as shown in FIG. The off-leakage current measured when a voltage of 1 V was applied was 7 × 10 ⁻⁷ A. On the other hand, in the variable resistance element according to Embodiment 2, for example, the combination of the first metal oxide layer 6, the second metal oxide layer 7 and the third metal oxide layer 8 constituting the buffer layer is TiO _y1 / In the case of AlO _x1 / TiO _y4 , the off-leakage current measured when applying a negative voltage of 1 V was reduced to 4 × 10 ⁻⁸ A.

In the case of a resistance change element as a comparative example, which is composed of only the same type of metal oxide (TiO _y1 ) as the first metal oxide layer 121 (TiO _y1 ), as shown in FIG. The measured breakdown voltage is 3.5V. On the other hand, in the variable resistance element according to Embodiment 2, for example, a combination of the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8 constituting the buffer layer. However, in the case of TiO _y1 / AlO _x1 / TiO _y4 , the dielectric breakdown voltage measured when a positive voltage is applied rises to 4.5V. This is because, by inserting the third metal oxide layer 8 in addition to the first metal oxide layer 6 and the second metal oxide layer 7, the second metal oxide contacting the lower portion of the third metal oxide layer 8 is used. This is presumably because the oxygen barrier property due to the passive formation of the physical layer 7 is controlled.

(Embodiment 3)
The third embodiment is based on the variable resistance element having the configuration shown in FIG. 9J and the manufacturing method thereof described in the fourth embodiment, and a three-terminal variable resistance element in a multilayer wiring structure on a semiconductor substrate. Is provided.

The configuration of the three-terminal variable resistance element according to Embodiment 3 will be described. In the third embodiment, a configuration different from the variable resistance element having the configuration shown in FIG. 9J, which is mainly described in the fourth embodiment, will be described and described in the fourth embodiment. A detailed description of the same configuration as the variable resistance element having the configuration shown in FIG. 9J is omitted.

FIG. 10 is a partial cross-sectional view schematically showing a configuration in which the three-terminal variable resistance element according to Embodiment 3 is provided inside a multilayer wiring structure on a semiconductor substrate.

As shown in FIG. 10, in the three-terminal variable resistance element 224 of Embodiment 3, a first lower wiring 206a and a second lower wiring 206b are provided as lower electrodes. The upper surfaces of the first lower wiring 206a and the second lower wiring 206b that are separated from each other with the first cap insulating film 104 interposed therebetween are partially exposed in one opening formed in the first barrier insulating film 107. is doing. The exposed portions of the upper surfaces of the first lower wiring 206a and the second lower wiring 206b are in contact with the upper first metal oxide layer 121 through the opening together with the upper surface of the first cap insulating film 104. . The area of the copper surface of the first lower wiring 206a and the area of the copper surface of the second lower wiring 206b exposed in the opening are both less than half of the opening area.

Further, when both the first lower wiring 206a and the second lower wiring 206b are made of, for example, Cu, the same configuration as the lower wiring 106 having the configuration shown in FIG. It can be formed by the method described in the manufacturing process of the variable resistance element having the configuration shown in FIG. 9J described in the fourth embodiment.

In the three-terminal resistance change element 224 of Embodiment 3, if the first lower wiring 206a is the first electrode and the second lower wiring 206b is the third electrode, the first electrode and the third electrode are provided in the same layer. The second electrode is provided in a different layer from the first electrode and the third electrode.

Next, a method for manufacturing the three-terminal variable resistance element 224 of Embodiment 3 will be described. In the third embodiment, processing different from the manufacturing process of the variable resistance element 126 having the configuration shown in FIG. 9J described in the fourth embodiment will be mainly described, and the configuration shown in FIG. 9J will be described. A detailed description of the same process as the manufacturing process of the variable resistance element 126 will be omitted.

In the third embodiment, in the formation of the opening in the first barrier insulating film 107 by dry etching, the surface of the first cap insulating film 104 sandwiched between the first lower wiring 206a and the second lower wiring 206b is dry etched. As a result, film loss occurs. Therefore, after forming the opening, the first metal layer used for forming the first metal oxide layer 121 is formed on the opening including the surfaces of the first lower wiring 206a and the second lower wiring 206b by DC sputtering. 161 and the second metal layer 162 used to form the second metal oxide layer 122 were successively deposited in this order. In the third embodiment, Zr having a thickness of 0.5 nm is selected as the first metal layer 161, and Al having a thickness of 0.2 nm is selected as the second metal layer 162. Thereafter, the first metal layer 161 and the second metal layer 162 are formed by O ₂ gas irradiation at an O ₂ flow rate of 10 sccm, a pressure of 0.5 Pa, and an irradiation time of 60 seconds without exposing to the atmosphere at room temperature. Oxidation treatment was performed to form ZrO _{y2 as} the first metal oxide layer 121 and AlO _x1 as the second metal oxide layer 122. Subsequently, heat treatment was performed at a substrate temperature of 400 ° C. or lower under conditions of N ₂ and O ₂ flow rates of 10/10 sccm, a pressure of 900 Pa, and a treatment time of 30 seconds. By this heat treatment, the Zr metal component remaining unreacted between the first lower wiring 206a and the second lower wiring 206b and ZrO _y2 which is the first metal oxide layer 121 is the first metal composed of Cu. It is removed by alloying and diffusion to the surfaces of the lower wiring 206a and the second lower wiring 206b.

Next, a solid electrolyte layer 123 was deposited on the second metal oxide layer 122. With respect to the steps after the deposition of the solid electrolyte layer 123, a formation method similar to that of the resistance change element 126 having the configuration shown in FIG. 9J is used, so that a three-terminal resistance change element is formed in the multilayer wiring structure as shown in FIG. 224 can be formed.

In the three-terminal variable resistance element 224 shown in FIG. 10, the variable resistance layer adopts a configuration in which it is integrally formed. Moreover, the 2nd electrode also employ | adopts the structure formed integrally.

Similarly to the variable resistance element of the first embodiment, also in the three-terminal variable resistance element 224 of the third embodiment, which is formed by the above manufacturing process, only the same type of metal oxide as the first metal oxide layer 121 is used. Compared with the three-terminal variable resistance element according to the comparative example that employs the buffer layer, the reduction of off-leakage and the improvement of the dielectric breakdown voltage were confirmed.

Specifically, a three-terminal variable resistance element as a comparative example that employs a 0.7 nm-thick buffer layer made of only the same type of metal oxide (ZrO _y2 ) as the first metal oxide layer 121 is used. In this case, the off-leakage current measured when applying a negative voltage of 1 V is 5 × 10 ⁻⁷ A. On the other hand, in the case of the three-terminal resistance change element 224 of the third embodiment in which ZrO _y2 is used as the first metal oxide layer 121 and AlO _x1 is used as the second metal oxide layer 122, a negative voltage is applied. The off-leakage current measured when 1 V was applied was 8 × 10 ⁻⁸ A, which was confirmed to be sufficiently reduced.

Further, in the case of a three-terminal resistance change element as a comparative example that employs a buffer layer made of only ZrO _y2 , the dielectric breakdown voltage measured when a positive voltage is applied is 3.6V. On the other hand, in the case of the three-terminal variable resistance element 224 of Embodiment 3, the dielectric breakdown voltage measured when a positive voltage was applied increased to 4.3V. In the third embodiment, as an example, the three-terminal variable resistance element 224 using ZrO _y2 as the first metal oxide layer 121 and AlO _x1 as the second metal oxide layer 122 has been described. The combination of the first metal oxide layer 121 and the second metal oxide layer 122 constituting the buffer layer is not limited to this combination of material configurations (ZrO _y2 / AlO _x1 ), and is exemplified in Embodiment 1. Other 8 types of combinations may be used.

From the above results, by applying the variable resistance element of the present invention and the manufacturing method thereof not only to the two-terminal variable resistance element but also to the three-terminal variable resistance element, the off-leakage current when applying a negative voltage is reduced, It was also found that the dielectric breakdown voltage was improved when a positive voltage was applied (at reset).

The present invention has been described above based on the embodiments and the embodiments. These embodiments and embodiments are only for the purpose of illustrating the present invention by way of specific examples, and are not meant to limit the technical scope of the present invention. Those skilled in the art will naturally conceive various modifications and improvements based on the above description, and it is understood that these are also included in the technical scope of the present invention.

In the above embodiments and embodiments, as a background of the present invention, a semiconductor device having a CMOS circuit as a field of use of the present invention will be described in detail, and a resistance change element mounted in a multilayer wiring structure on a semiconductor substrate is formed. An example was described. However, the present invention is not limited to the illustrated embodiments and implementations.

The present invention relates to semiconductor products having memory circuits such as DRAM, SRAM (Static RAM), flash memory, FRAM (Ferro-Electric RAM), capacitors, bipolar transistors, etc., and semiconductor products having logic circuits such as microprocessors. Alternatively, the present invention can also be applied to a metal wiring forming process of a board or package on which they are simultaneously mounted. The present invention can also be applied to a wiring formation process for connecting a semiconductor device to an electronic circuit device, an optical circuit device, a quantum circuit device, a micromachine, a MEMS (Micro-Electro-Mechanical Systems), or the like.

The solid electrolyte switching element produced in the copper wiring layer according to the present invention and formed by connecting a plurality of resistance change elements in parallel is, for example, a programmable element used in the configuration of an FPGA (Field Programmable Gate Array). As used.

The solid electrolyte switching element type semiconductor device according to the present invention uses a non-volatile memory or a non-volatile switch by using its “programming” operation, in particular, the effect of suppressing variation in set voltage during the “set” operation. The present invention can be applied to logic circuits such as semiconductor products having a memory circuit and microprocessors.

The present invention has been described above using the above-described embodiment as an exemplary example. However, the present invention is not limited to the above-described embodiment. That is, the present invention can apply various modes that can be understood by those skilled in the art within the scope of the present invention.

This application claims priority based on Japanese Patent Application No. 2017-71485 filed on Mar. 31, 2017, the entire disclosure of which is incorporated herein.

DESCRIPTION OF SYMBOLS 1 1st electrode 2 2nd electrode 3 Variable resistance layer 4 Buffer layer 5 Solid electrolyte layer 101 Semiconductor substrate 102 1st interlayer insulation film 103 2nd interlayer insulation film 104 1st cap insulation film 105 1st barrier metal 106 Lower wiring 107 1st 1 barrier insulating film 108 first hard mask film 120 buffer layer 121 first metal oxide layer 122 second metal oxide layer 123 solid electrolyte layer 124 first upper electrode 125 second upper electrode 128 second hard mask film 129 third Hard mask film 130 Protective insulating film 140 First via interlayer insulating film 141 Third interlayer insulating film 142 Second cap insulating film 143 Second barrier metal 144 Via plug 145 Upper wiring 146 Second barrier insulating film 147 Via hole 148 Wiring for upper wiring Groove 126, 151, 151a 151b Resistance change element 150, 150a, 150b Two-terminal type semiconductor device 153, 153a, 153b First terminal 154, 154a, 154b Second terminal 157 Control terminal 159 Solid electrolyte switch element 161 First metal layer 162 Second metal layer 206a First lower wiring 206b Second lower wiring 224 Three-terminal variable resistance element

Claims (10)

1. A semiconductor device including at least two or more resistance change elements, a first terminal (first wiring), and a second terminal (second wiring),
   The variable resistance elements are respectively
   Having a first electrode, a second electrode, and a resistance change layer sandwiched between the first electrode and the second electrode,
   Based on an electrical signal applied between the first electrode and the second electrode, the resistance value reversibly changes,
   Each first electrode of the variable resistance element is electrically connected to a first terminal, and each second electrode is electrically connected to a second terminal, and
   Each resistance change layer is separated from each other between at least two resistance change elements,
   Each of the second electrodes is separated from each other between the variable resistance elements, and is electrically connected to each other only through the second terminal.
2. A semiconductor device comprising a pair of semiconductor devices according to claim 1 as a component,
   The semiconductor device pair is:
   The semiconductor device, wherein the second terminals constituting each semiconductor device are electrically connected in series.
3. The first electrode of the resistance change element is made of a material containing a metal atom that serves as a supply source of metal ions,
   The second electrode is composed of a material made of a metal atom that is included in the material constituting the first electrode and is less likely to be ionized than the metal atom,
   The resistance change layer includes a buffer layer and a solid electrolyte layer capable of conducting the metal ions,
   The buffer layer is in contact with the first electrode, and the solid electrolyte layer is in contact with the second electrode;
   The variable resistance element is
   When a voltage is applied between the first electrode and the second electrode, the metal atoms contained in the first electrode are ionized,
   The metal ion supplied from the first electrode is a solid electrolyte switch element whose resistance is reversibly changed by being injected into the solid electrolyte layer through the buffer layer. The semiconductor device according to claim 2.
4. The metal ions are copper ions;
   The first electrode of the variable resistance element is made of a material containing copper,
   The second electrode is made of a material containing Ru,
   4. The semiconductor device according to claim 3, wherein the buffer layer contains at least one metal element selected from the group consisting of Al, Hf, Ta, Ti, and Zr.
5. 5. The semiconductor device according to claim 1, wherein the variable resistance element is provided in a multilayer copper wiring layer on a semiconductor substrate.
6. The variable resistance element is provided on a copper wiring,
   The first electrode constituting the variable resistance element also serves as a part of the copper wiring,
   A portion of the insulating barrier film provided on the first electrode has at least one opening;
   The surface of at least one of the first electrodes partially exposed at the bottom of the opening and the buffer layer are in contact with each other through the opening. The semiconductor device according to any one of 5.
7. About each variable resistance element constituting the semiconductor device,
   The semiconductor device according to claim 6, wherein the shape of the copper wiring also serving as the first electrode partially exposed at the bottom of the opening is the same.
8. About each variable resistance element constituting the semiconductor device,
   The shape of the copper wiring also serving as the first electrode partially exposed at the bottom of the opening is:
   8. The semiconductor device according to claim 6, wherein the semiconductor device is oriented in the same direction within the surface of the semiconductor substrate or is rotated by 180 ° to face each other.
9. About each variable resistance element constituting the semiconductor device,
   The shape of the copper wiring also serving as the first electrode partially exposed at the bottom of the opening is:
   The semiconductor device according to claim 8, wherein a tip end portion of the copper wiring has a shape protruding from one end of a bottom portion of the opening portion along the orientation direction.
10. A method of manufacturing a semiconductor device having a plurality of resistance change elements provided in a multilayer copper wiring layer on a semiconductor substrate,
    Forming an insulating barrier film on the copper wiring also serving as the first electrode electrically connected to the first terminal;
    Forming an opening in the insulating barrier film, exposing a copper wiring surface also serving as the first electrode;
    A buffer layer and a solid electrolyte layer are sequentially formed on the entire surface including the opening,
    Forming a second electrode connected to the second terminal on the solid electrolyte layer;
    The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device manufacturing method.

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