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WO2018177752A1 - Module electronique - Google Patents

Module electronique Download PDF

Info

Publication number
WO2018177752A1
WO2018177752A1 PCT/EP2018/056412 EP2018056412W WO2018177752A1 WO 2018177752 A1 WO2018177752 A1 WO 2018177752A1 EP 2018056412 W EP2018056412 W EP 2018056412W WO 2018177752 A1 WO2018177752 A1 WO 2018177752A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrical
mass
electronic
group
component
Prior art date
Application number
PCT/EP2018/056412
Other languages
German (de)
English (en)
Inventor
Peter Bartscherer
Thomas Fellner
Martin Sautter
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Priority to EP18714451.4A priority Critical patent/EP3602619A1/fr
Priority to CN201880020826.0A priority patent/CN110462819B/zh
Publication of WO2018177752A1 publication Critical patent/WO2018177752A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating

Definitions

  • the invention relates to an electronic module, comprising a circuit carrier and enclosing masses enclosed electrical and / or electronic components, according to the preamble of the independent claim.
  • the invention is based on the object to achieve an economical use of encapsulants even in the presence of electrical and / or electronic components with very different component heights.
  • the starting point is an electronic module comprising a circuit carrier having an upper side and a lower side, electrical and / or electronic components being arranged on at least one of the sides. At least one of the electrical and / or electronic components is in each case partially enclosed by a plurality of solidified encapsulant masses, wherein the plurality of encapsulant masses differ from each other in their respective viscosity.
  • the at least one electrical and / or electronic component projects from the at least one side of the circuit carrier with a component height h.
  • the component height h results as the distance of the highest point of the electrical and / or electronic component perpendicular to the side surface of the circuit carrier.
  • a first encapsulation compound Adjacent to the at least one side of the circuit carrier, a first encapsulation compound is arranged at least in the region of the one electrical and / or electronic component.
  • said region above the first cladding mass is associated with said first cladding mass. bordering a second coating mass arranged.
  • the second encapsulant mass can cover only a part of the electrical and / or electronic component protruding from the first encapsulant. This is suitable, for example, when the electronic and / or electrical component is already packed, but at least one electrical connection is arranged above the first encapsulation compound, which is then completely covered by the second encapsulation compound and projectingly overlapping it.
  • the second cladding composition overhangs the component height h.
  • the at least one electrical and / or electronic component is completely embedded in the first and second encapsulant.
  • the embedding in both cladding masses takes place in particular such that the at least one electrical and / or electronic component is enclosed at a partial height th below the component height h of the first cladding mass and above the partial height th of the second cladding mass, wherein the first cladding mass at least before a Solidification of both coating compositions has a lower viscosity than the second coating composition.
  • the viscosity of the second coating mass is selected such that it remains stable until it solidifies against gravitational force on the at least one electrical and / or electronic component.
  • the second wrapping mass can be applied, for example, by a dispensing method, whereas the first wrapping mass is preferably applied by a potting method, in particular covering the whole area.
  • the low-viscosity coating mass shows the peculiarity of being unable to maintain its shape stability before solidification and to deliquescing. In the solidified state The low-viscosity encapsulation compound therefore exhibits a termination surface which faces away from the circuit carrier and which is leveled out in its lateral extent, ie which is flat due to deliquescence.
  • the higher-viscosity encapsulant remains in a dimensionally stable state even before solidification, so that, in contrast to the low-viscosity encapsulant, no leveling takes place due to deliquescence.
  • a protrusion then emerges from the highly viscous coating mass, which protrudes in relation to a surrounding leveled finishing surface, in particular from the solidified, low-viscosity coating mass.
  • the base material for the encapsulants for example, epoxy
  • PU or silicone materials may be provided.
  • the encapsulants may have the same or a different base material.
  • the encapsulant masses may comprise fillers, by means of which a viscosity of the encapsulant mass is adjustable. The higher-viscosity encapsulant has a higher level both before and after solidification
  • Suitable 2 K epoxy materials are, for example, XNR 5021 from Fa. Denatite (low viscosity fill without thixotroping) and T-919 / RH-128 from Denatite (DAM highly viscous with thixotroping). These base materials are characterized by a trimodal filler distribution.
  • the second cladding mass encloses the at least one electrical and / or electronic component above the partial height th in the form of a cap.
  • the second cladding mass thus completely covers the component end projecting from the circuit carrier.
  • it encloses lateral component areas in the direction of the circuit carrier starting from the said component end.
  • Circuit carrier facing outer portion of the electrical and / or electronic component is considered as a lower area.
  • the cap is in the form of a thimble.
  • the lateral shape curve of a corresponding thimble of the present cross-sectional shape fits over the correspondingly covered component height.
  • a potting surface can thereby be lowered from the first wrapping mass to a height level up to which the lower region of the at least one electrical and / or electronic component is not enclosed by the second wrapping mass. This leads to a significant saving of the first wrapping mass.
  • a development of the electronic module provides that the at least one side of the circuit carrier and all the electrical and / or electronic components arranged thereon are completely or indirectly covered completely or indirectly by a layer of the second encapsulation compound.
  • the present electronic module advantageously has a hard packaging surface which encloses on all sides and which ensures holistic mechanical and electrical protection of all electrical and / or electronic components.
  • the design of the electronic module is preferably such that the second encapsulation compound follows an equipping topology of the at least one side of the circuit carrier.
  • the second cladding mass follows the component topology of those components which have a component height above a specified minimum height dimension, the second cladding mass completely covering it with a finished end surface with respect to all other electrical and / or electronic components having a component height up to the minimum height dimension.
  • FIGS. 1 to 3 show different possible embodiments of an electronic module 100. All embodiments have in common that the electronic module 100 has a circuit carrier 10 with an upper side and a lower side 11, 12. At least for example on the upper side 11, a plurality of electrical and / or electronic components 20 are arranged. They are electrically connected to a conductor structure (not shown), which is formed at least on the upper side 11 and / or lower side 12 of the circuit carrier 10. Overall, the electrical and / or electronic components 20 and the conductor structure form an electrical circuit of the electronic module 100. For protection against external influences, for example mechanical stresses and / or chemical media contact, individual electrical and / or electronic components 20, preferably all, of at least enclosed a solidified wrapping mass.
  • At least one electrical and / or electronic component 21 is in each case partially enclosed by a first and a second cladding mass 31, 32.
  • the at least one electrical and / or electronic component 21 terminates with a component height h with respect to the upper side 11 of the circuit carrier 10.
  • a lower outer section region of the electrical and / or electronic component 21 facing the upper side 11 is enclosed by the first encapsulation compound 31 up to a partial height th.
  • the first wrapping mass 31 is also adjacent to the Top 11 of the circuit substrate 10 is arranged.
  • a second cladding mass 32 is applied to these adjacent. This encloses completely also an upper side 11 facing away from the upper outer portion region of the electrical and / or electronic component 21 above the partial height th.
  • the end of the component is also completely covered, so that the second encapsulation compound 32 ends abruptly above the component height h.
  • the first cladding mass 31 has a lower viscosity prior to solidification, for example 1-10 Pas, than the second cladding mass 32 with, for example, 300-600 Pas. Due to the choice of viscosity, the second wrapping mass 32 can be opposite to the
  • the first embodiment of an electronic module according to FIG. 1 provides that the second encapsulation compound 32 encloses the at least one electrical and / or electronic component 21 above the partial height th in the form of a cap 35.
  • the second encapsulation compound 32 can be applied, for example, by a spatially fixed or movable dispensing nozzle 40 on the highly projecting region of the electrical and / or electronic component 21 and pressed down by a corresponding section of the dispensing nozzle 40 or another molding tool, so that as well a lateral section region encompassing up to partial height th is covered or enclosed by the second encapsulation compound 32. It is conceivable to carry out the cap-shaped shaping also by another method.
  • the second cladding mass 32 at least in the region of at least one electrical and / or electronic component 21 partially into the Layer of the first cladding mass 31 inside.
  • an overlapping area a is formed between the partial height th and the layer finishing height slh between the first and second wrapping masses 31, 32.
  • At least one further such electrical and / or electronic component 21 may be enclosed in the same manner by two encapsulants 31, 32 in certain areas.
  • at least one further electrical and / or electronic components 22 arranged on the upper side 11 of the circuit substrate 10 are at least partially, preferably completely, enclosed by the first encapsulation compound 31 or embedded therein. If there is a gap between a body of one of the electrical and / or electronic components 20 and the circuit carrier 10 (not shown), then this is completely filled by the first cladding mass 31.
  • the first and second wrapping masses 31, 32 can be in one
  • Solidification can be achieved by a curing process, for example as a result of a temperature treatment, a drying process, a radiation with non-ionic and / or ionic radiation or otherwise.
  • a production process can also be provided only by a potting of the first wrapping mass 31 and subsequent dispensing of the second wrapping mass 32, but is more complicated and more difficult in the embodiment.
  • FIG. 2 A further embodiment of the electronic module 100 is shown in FIG. 2.
  • This embodiment differs from the embodiment according to FIG. 1 only in that an additional layer of the second cladding mass 32 is applied adjacently to the first layer formed from the first cladding mass 31, which then terminates at a slice end height s2h.
  • This layer of the second wrapping mass 32 then also encloses the formed cap 35 (dashed lines) on the at least one electrical and / or electronic component 21.
  • the second encapsulant mass 32 may also be applied to the layer of the first encapsulant 31 by a potting process. Shown, however, is the formation of the layer by an alternative application method, for example by dispensing, whereby the cap 35 without a
  • Protruding into the layer of the first wrapping mass can be formed continuing.
  • Component 21 also protrudes into the layer of second cladding mass 32, even below cladding level s2h.
  • at least one first group 20A and a second group 20B preferably show at electrical and / or electronic components 20, which are partially enclosed by two cladding masses 31, 32, but only the electrical and / or electronic components 20 of the second group 20B over survive the Schichtab gleich Why s2h.
  • the electrical and / or electronic components 20 of the second group 20B have a higher component height than that of the first group
  • the electronic module 10 may be executed in the same way on the underside 12 of the circuit substrate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

L'invention concerne un module électronique, comprenant un support de circuit avec une face supérieure et une face inférieure, des composants électriques et/ou électroniques étant disposés sur au moins une des faces. Au moins un des composants électriques et/ou électroniques est respectivement entouré par zones par une pluralité de masses d'enrobage solidifiées, la pluralité de masses d'enrobage se différenciant entre elles par leur viscosité respective. Une première masse d'enrobage est disposée au moins dans la zone dudit composant électrique et/ou électronique, à proximité de l'au moins une face du support de circuit. En outre, une deuxième masse d'enrobage est disposée à proximité de ladite zone, au-dessus de la première masse d'enrobage. Cela s'effectue en particulier de telle façon que l'au moins un composant électrique et/ou électronique est entouré sur une hauteur partielle th inférieure à la hauteur de composant h par la première masse d'enrobage et au-dessus de la hauteur partielle th par la deuxième masse d'enrobage, la première masse d'enrobage présentant au moins avant la solidification une viscosité inférieure à celle de la deuxième masse d'enrobage.
PCT/EP2018/056412 2017-03-28 2018-03-14 Module electronique WO2018177752A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP18714451.4A EP3602619A1 (fr) 2017-03-28 2018-03-14 Module electronique
CN201880020826.0A CN110462819B (zh) 2017-03-28 2018-03-14 电子模块

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102017205247.3 2017-03-28
DE102017205247.3A DE102017205247A1 (de) 2017-03-28 2017-03-28 Elektronikmodul

Publications (1)

Publication Number Publication Date
WO2018177752A1 true WO2018177752A1 (fr) 2018-10-04

Family

ID=61832471

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2018/056412 WO2018177752A1 (fr) 2017-03-28 2018-03-14 Module electronique

Country Status (4)

Country Link
EP (1) EP3602619A1 (fr)
CN (1) CN110462819B (fr)
DE (1) DE102017205247A1 (fr)
WO (1) WO2018177752A1 (fr)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19518027A1 (de) 1995-05-17 1996-11-21 Lust Hybrid Technik Gmbh Verfahren zur abstandsgenauen Umhüllung mit funktionstragenden Schichten versehener Bauelemente und danach hergestellte Bauelemente
US20010040280A1 (en) * 2000-05-15 2001-11-15 Kabushiki Kaisha Toshiba Semiconductor apparatus and manufacturing method therefor
US6888259B2 (en) 2001-06-07 2005-05-03 Denso Corporation Potted hybrid integrated circuit
DE102004039693A1 (de) 2004-08-16 2006-02-23 Infineon Technologies Ag Chipmodul
US20060244128A1 (en) * 2005-04-19 2006-11-02 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US20120119372A1 (en) * 2010-11-11 2012-05-17 Sony Corporation Semiconductor device and method of manufacturing the same
US20130241044A1 (en) * 2012-03-16 2013-09-19 Samsung Electronics Co., Ltd. Semiconductor package having protective layer and method of forming the same
WO2016022375A1 (fr) * 2014-08-06 2016-02-11 Invensas Corporation Dispositif et procédé de remplissage sous-jacent localisé

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19518027A1 (de) 1995-05-17 1996-11-21 Lust Hybrid Technik Gmbh Verfahren zur abstandsgenauen Umhüllung mit funktionstragenden Schichten versehener Bauelemente und danach hergestellte Bauelemente
US20010040280A1 (en) * 2000-05-15 2001-11-15 Kabushiki Kaisha Toshiba Semiconductor apparatus and manufacturing method therefor
US6888259B2 (en) 2001-06-07 2005-05-03 Denso Corporation Potted hybrid integrated circuit
DE102004039693A1 (de) 2004-08-16 2006-02-23 Infineon Technologies Ag Chipmodul
US20060244128A1 (en) * 2005-04-19 2006-11-02 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US20120119372A1 (en) * 2010-11-11 2012-05-17 Sony Corporation Semiconductor device and method of manufacturing the same
US20130241044A1 (en) * 2012-03-16 2013-09-19 Samsung Electronics Co., Ltd. Semiconductor package having protective layer and method of forming the same
WO2016022375A1 (fr) * 2014-08-06 2016-02-11 Invensas Corporation Dispositif et procédé de remplissage sous-jacent localisé

Also Published As

Publication number Publication date
DE102017205247A1 (de) 2018-10-04
EP3602619A1 (fr) 2020-02-05
CN110462819A (zh) 2019-11-15
CN110462819B (zh) 2023-05-12

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