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WO2018168185A1 - Dispositif semiconducteur - Google Patents

Dispositif semiconducteur Download PDF

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Publication number
WO2018168185A1
WO2018168185A1 PCT/JP2018/001318 JP2018001318W WO2018168185A1 WO 2018168185 A1 WO2018168185 A1 WO 2018168185A1 JP 2018001318 W JP2018001318 W JP 2018001318W WO 2018168185 A1 WO2018168185 A1 WO 2018168185A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
semiconductor chip
sintered
bonding
joint
Prior art date
Application number
PCT/JP2018/001318
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English (en)
Japanese (ja)
Inventor
高彰 宮崎
中村　真人
靖 池田
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株式会社日立パワーデバイス
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Application filed by 株式会社日立パワーデバイス filed Critical 株式会社日立パワーデバイス
Publication of WO2018168185A1 publication Critical patent/WO2018168185A1/fr

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F1/00—Metallic powder; Treatment of metallic powder, e.g. to facilitate working or to improve properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a power semiconductor device used in an inverter.
  • power semiconductor devices have a structure in which a semiconductor element (hereinafter, also referred to as a semiconductor chip or simply a chip) and an insulating substrate, or an insulating substrate and a metal plate for heat dissipation are bonded with a bonding material. .
  • solder containing lead (Pb) has been used as a connecting member for semiconductor devices that require high reliability, particularly semiconductor devices used in the fields of automobiles, construction equipment, railways, and information equipment. For reduction, devices using lead-free connecting members are also widely used.
  • Si (silicon) semiconductor elements In recent years, development of wide gap semiconductors such as SiC and GaN capable of operating at high temperatures and reducing the size and weight of devices has been promoted.
  • the upper limit of the operating temperature of Si (silicon) semiconductor elements is 150 to 175 ° C., whereas SiC semiconductor elements can be used at 175 ° C. or higher.
  • the bonding material used for the semiconductor device is also required to have a heat resistance of 175 ° C. or higher.
  • Development of heat-resistant joints is progressing.
  • the sinterable metal joining technique using the sintering phenomenon has properties suitable for power modules that require high heat resistance.
  • Sintered bonding using the low-temperature firing function of metal fine particles is expected as a highly heat-resistant and highly reliable bonding material.
  • metal nanoparticles having a particle size of several hundred nm or less the number of constituent atoms decreases, the surface area ratio with respect to the volume of the particles increases rapidly, and the sintering temperature decreases significantly compared to the bulk state.
  • the metal fine particles are very reactive, and in order to prevent the progress of sintering during storage, generally, metal fine particles having a surface formed with an organic coating or a metal oxide layer are used.
  • a sintered bonding material paste obtained by mixing metal fine particles with a solvent to form a paste is generally used.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2012-28674 discloses a technique for increasing the bonding reliability by interposing a stress buffer plate in a portion of a bonding material (sintering silver fine particles) of a semiconductor element. ing. Although peeling is likely to occur at the bonding interface between the bonding material and the member to be bonded, the above Patent Document 1 does not consider such peeling.
  • Patent Document 3 discloses a technique capable of improving the bonding strength and preventing peeling by bonding the conductor layer of the insulating substrate and the electrode of the semiconductor element using sinterable metal bonding materials having different particle sizes. (Japanese Unexamined Patent Publication No. 2016-1000042). However, the technique has a problem that the process time increases because it is necessary to supply a metal joining material that is sinterable at least twice.
  • An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device in which a semiconductor chip is bonded by a sintered bonding material.
  • a semiconductor device includes a semiconductor chip, a wiring board that supports the semiconductor chip and is electrically connected to the semiconductor chip, and is disposed between the semiconductor chip and the wiring board. And a sintered bonding material for bonding the wiring board. Further, a plurality of spherical protrusions are formed on at least one of the first joint surface that joins the sintered joint material of the semiconductor chip and the second joint surface that joins the sintered joint material of the wiring board. The part is formed.
  • Another semiconductor device includes a semiconductor chip, a wiring board that supports the semiconductor chip, is electrically connected to the semiconductor chip, and has a conductor film formed on both front and back surfaces, and the semiconductor chip and the wiring. And a sintered bonding material that is disposed between the semiconductor chip and the wiring substrate. And a metal plate on which the semiconductor chip and the wiring board are mounted, and another bonding material that is disposed between the wiring board and the metal plate and joins the wiring board and the metal plate. A plurality of spherical concave and convex portions are formed on the first joint surface of the semiconductor chip joined to the sintered joint material and the second joint surface of the conductor film joined to the sintered joint material.
  • FIG. 2 is an enlarged partial cross-sectional view illustrating an example of a structure of a chip bonding portion made of a sintered bonding material of the semiconductor device illustrated in FIG. 1. It is a schematic diagram which shows the curvature radius of the convex part shown to the A section of FIG. It is an expanded partial sectional view which shows the structure of the chip joint part by the sintered joining material of a comparative example.
  • FIG. 2 is a partial side view showing an example of a railway vehicle on which the semiconductor device shown in FIG. 1 is mounted. It is a top view which shows an example of the internal structure of the inverter installed in the rail vehicle shown in FIG. It is a perspective view which shows an example of the motor vehicle carrying the semiconductor device shown in FIG.
  • FIG. 1 is a sectional view showing an example of the structure of a semiconductor device (power module) according to the first embodiment of the present invention.
  • FIG. 2 shows an example of the structure of a wiring board used in the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3 is an enlarged partial cross-sectional view showing an example of the structure of the chip joint portion by the sintered joining material of the semiconductor device shown in FIG. 1, and
  • FIG. 4 is a schematic diagram showing the curvature radius of the convex portion shown in part A of FIG. FIG.
  • the semiconductor device is, for example, a semiconductor module (power module) mounted on a railway vehicle, an automobile body, or the like. Therefore, the semiconductor device includes a plurality of power semiconductor chips (semiconductor elements) 1.
  • the semiconductor chip 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOS (Metal Oxide Semiconductor), a diode, or the like, but is not limited thereto.
  • the configuration of the power module (semiconductor device) 20 shown in FIG. 1 will be described.
  • the power module 20 includes a semiconductor chip 1, and the semiconductor chip 1 includes an upper surface 1 a and a back surface (first bonding surface) 1 b that is the opposite surface.
  • the semiconductor chip 1 is bonded to a ceramic substrate (wiring substrate) 3 via a sintered bonding material 2. That is, the back surface 1 b of the semiconductor chip 1 is bonded to the sintered bonding material 2.
  • the semiconductor chip 1 is preferably made of SiC or GaN that can operate at a high temperature of 175 ° C. or higher, but may be made of, for example, silicon.
  • the power module 20 is a conductive wire that electrically connects the electrode 1d provided on the upper surface 1a of the semiconductor chip 1 and the wiring 3cc (3c) of the upper surface (second bonding surface) 3a of the ceramic substrate 3. 6 and a terminal 7 which is electrically connected to the wiring 3cc of the ceramic substrate 3 and is drawn to the outside.
  • a plurality of (for example, three) semiconductor chips 1 are mounted on one ceramic substrate 3. Specifically, a plurality of semiconductor chips 1 are mounted on the wiring 3 cb provided on the upper surface 3 a of the ceramic substrate 3.
  • a plurality of terminals 7 that are external terminals of the power module 20 are connected to the wiring 3 cc on the upper surface 3 a of the ceramic substrate 3.
  • the ceramic substrate 3 on which the plurality of semiconductor chips 1 and the plurality of terminals 7 are mounted is mounted on a base plate (metal plate) 4 via a bonding material (another bonding material such as a solder alloy) 5.
  • a bonding material another bonding material such as a solder alloy
  • the ceramic substrate 3 has a plurality of wirings (conductor films) 3c formed on the upper surface 3a thereof.
  • a wiring 3cb which is a conductor film, is arranged at the center of the upper surface 3a, and the wiring (conductor film) 3ca to which the wires 6 shown in FIG. A wiring (conductor film) 3cc is formed, while a wiring 3cd is also formed on the lower surface 3b.
  • These wirings 3ca, 3cb, 3cc, 3cd are made of, for example, Cu (copper) or Al (aluminum), and the ceramic substrate 3 is made of silicon nitride, alumina, aluminum nitride, or the like.
  • the wiring 3 cd formed on the lower surface 3 b of the ceramic substrate 3 is bonded to the base plate 4 by the bonding material 5.
  • a gate electrode 1 c is formed on the upper surface 1 a of the semiconductor chip 1 and is electrically connected to the wiring 3 ca of the ceramic substrate 3 via the wire 6. Furthermore, another electrode 1 d formed on the upper surface 1 a of the semiconductor chip 1 is electrically connected to the wiring 3 cc of the ceramic substrate 3 via the wire 6.
  • the base plate 4 is a metal plate for heat dissipation.
  • the base plate 4 that is also a heat sink is provided with a case 8 that covers the plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3.
  • the case 8 is filled with a sealing resin 11. Has been. That is, the plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3 are sealed with the sealing resin 11.
  • the resin 11 for example, a gel-like resin material is preferably used.
  • each of the plurality of wires 6 is a metal wire such as an Al wire or a Cu wire, for example.
  • the sintered bonding material 2 is a member that is disposed between the semiconductor chip 1 and the ceramic substrate 3 and bonds the semiconductor chip 1 and the ceramic substrate 3 and is a bonding material based on sintered bonding. It is desirable.
  • the bonding material 5 is a member that is disposed between the ceramic substrate 3 and the base plate 4 and bonds the ceramic substrate 3 and the base plate 4.
  • the bonding material 5 is preferably a solder alloy containing Sn as a main component or a solder alloy containing Pb as a main component.
  • a bonding material such as Zn—Al, Au—Ge, Au—Si, sintered Ag, and sintered Cu may be used.
  • the base plate 4 may be Cu, Al, Al alloy, Cu alloy, a composite material of Al and SiC, or a composite material of Mg (magnesium) and SiC.
  • the semiconductor chip 1 mounted on the power module 20 of the first embodiment is preferably made of a material such as high heat-resistant SiC or GaN, and the semiconductor chip 1 is made of a material such as SiC or GaN. Therefore, it is possible to cope with further increase in operating temperature.
  • a plurality of spherical surfaces are formed on the back surface (first bonding surface) 1 b bonded to the sintered bonding material 2 of the semiconductor chip 1.
  • Convex part 9a (9) is formed.
  • a plurality of spherical convex portions 9b (9) are formed on the surface of the wiring 3cb of the upper surface (second bonding surface) 3a to be bonded to the sintered bonding material 2 of the ceramic substrate 3, respectively.
  • the plurality of spherical convex portions 9 only need to be formed on at least one of the back surface 1b of the semiconductor chip 1 or the wiring 3cb on the top surface 3a of the ceramic substrate 3. However, since it is more effective to be provided on both the back surface 1b of the semiconductor chip 1 and the wiring 3cb on the top surface 3a of the ceramic substrate 3, in the first embodiment, the back surface 1b of the semiconductor chip 1 and the ceramic substrate 3 A case where a plurality of spherical convex portions 9 are formed on each of the wirings 3cb on the upper surface 3a will be described.
  • each of the plurality of spherical convex portions 9 is formed in a substantially hemispherical shape as shown in FIGS.
  • the sintering density of the sintered bonding material 2 in the vicinity of the bonding interface with the semiconductor chip 1 and the ceramic substrate 3 can be increased, and the bonding reliability of the sintered bonding material 2 can be increased.
  • a plurality of spherical irregularities are formed on the back surface 1b of the semiconductor chip 1 and the wiring 3cb on the top surface 3a of the ceramic substrate 3, respectively. It may be expressed as
  • FIG. 5 is an enlarged partial cross-sectional view showing a structure of a chip joint portion made of a sintered joining material of a comparative example.
  • the sintered joining material 2 after joining has a large number of particles having a diameter of 1 ⁇ m to 10 ⁇ m. I found it.
  • the shape after joining is more stable in terms of energy as the particle surface area becomes smaller, it becomes a shape in which spheres are combined.
  • the present inventor examined the structure of the power module that can realize the high reliability of the bonding interface of the sintered bonding material 2 without increasing the assembly process of the semiconductor device. As a result, as shown in FIG. 3, a plurality of convex portions 9 each having a spherical shape are provided on the back surface 1 b of the semiconductor chip 1 and the wiring 3 cb on the upper surface 3 a of the ceramic substrate 3. It has been found that the sintered density in the vicinity of the interface can be increased.
  • a plurality of spherical convex portions 9 are respectively provided on the back surface 1 b of the semiconductor chip 1 and the wiring 3 cb on the upper surface 3 a of the ceramic substrate 3, so that adjacent spherical convex portions are provided.
  • Part (particles) of the sintered bonding material 2 can be inserted into the gap between the portions 9. Accordingly, the first bonding portion 2b including the bonding boundary portion 2a of the sintered bonding material 2 with the semiconductor chip 1 and the second bonding portion 2d including the bonding boundary portion 2c of the sintered bonding material 2 with the ceramic substrate 3 are obtained.
  • Each sintered density is larger than the sintered density in the sintered joint material 2 excluding the first joint portion 2b and the second joint portion 2d, that is, in the vicinity of the central portion 2e in the thickness direction of the sintered joint material 2 ( Can be high). That is, in the cross-sectional view cut along the thickness direction of the sintered bonding material 2 (the same direction as the thickness direction of the semiconductor chip 1), the sintering density of each of the first bonding portion 2b and the second bonding portion 2d is determined. The sintering density of the central portion 2e located between the first joint portion 2b and the second joint portion 2d can be made larger (higher).
  • the sintered density in the vicinity of the bonding interface between the semiconductor chip 1 and the ceramic substrate 3 in the sintered bonding material 2 can be increased (increased), high reliability can be obtained without breaking at the bonding interface. it can. In other words, it is possible to suppress or prevent the peeling that occurs at the bonding interface between the sintered bonding material 2 and the semiconductor chip 1 or the ceramic substrate 3.
  • the reliability of the power module (semiconductor device) 20 in which the semiconductor chip 1 and the ceramic substrate 3 are joined by the sintered joining material 2 can be improved.
  • the structure of the power module (semiconductor device) 20 having high heat resistance can be realized.
  • the bonding reliability of the bonded portion using the sintered bonding material 2 is enhanced, it can have a great resistance against a temperature load such as a temperature cycle in which a low temperature environment and a high temperature environment are repeated.
  • the spherical radius of each of the plurality of spherical convex portions 9 has a radius of curvature R of 0.5 ⁇ m to 5 ⁇ m, preferably about 3 ⁇ m. That is, since the diameter of the particles of the sintered joining material 2 to be formed is about 6 ⁇ m, a spherical surface having a radius of curvature R of about 3 ⁇ m, which is the same as the size of the particles after joining, is preferable, and various variations are considered. Then, it is preferable that a plurality of spherical convex portions 9 having a radius of curvature R of about 0.5 ⁇ m to 5 ⁇ m are provided.
  • the sintered bonding material 2 is preferably made of a material mainly composed of Cu or Ag. And it is suitable for the wiring 3c which is a conductor film formed in the front and back of the ceramic substrate 3 to be formed from copper foil.
  • the some convex part 9a (9) formed in the back surface 1b of the semiconductor chip 1 can be formed by electroless plating, for example.
  • the plurality of convex portions 9b (9) formed on the wiring 3cb on the upper surface 3a of the ceramic substrate 3 can be similarly formed by electroless plating, or the mold can be formed using a mold (not shown). It can also be formed by a method of pressing and transferring to the wiring 3cb on the upper surface 3a of the ceramic substrate 3.
  • the sintered joining material 2 consists of Cu
  • the some convex part 9 is formed of Cu or Ni.
  • the sintered bonding material 2 is made of Ag
  • the plurality of convex portions 9 are preferably formed of Ag, Au, or Pd.
  • a semiconductor chip 1 having a plurality of spherical convex portions 9a (9) formed on the back surface 1b is prepared, and a plurality of spherical convex portions 9b are formed on the wiring 3cb on the upper surface 3a.
  • a ceramic substrate 3 on which (9) is formed is prepared.
  • a paste material for sintering joining obtained by pasting a minute metal powder with a solvent is applied to the wiring 3cb on the upper surface 3a of the ceramic substrate 3.
  • the semiconductor chip 1 is mounted via the paste material, and the solvent is volatilized by heating to 200 to 400 ° C., and simultaneously pressurizing, whereby the sintering progresses to achieve bonding. That is, the semiconductor chip 1 and the ceramic substrate 3 are joined by the sintered joining material 2.
  • the metal particles change into a bulk metal, and at the same time, joining is performed by metal bonding at the joining interface. Therefore, the joined portion of the sintered joining material 2 has very high heat resistance and reliability.
  • the ceramic substrate 3 is disposed on the base plate 4 via a bonding material (other bonding material) 5 made of a solder alloy, the bonding material 5 is heated and melted, and the ceramic substrate 3 and the base plate (metal plate). 4 is joined.
  • the base plate 4 is a plate material for heat dissipation.
  • the bonding material 5 is melted and the ceramic substrate 3 and the base plate 4 are bonded. Thereby, the solder joint between the ceramic substrate 3 and the base plate 4 in the module structure shown in FIG. 1 is completed.
  • the ceramic substrate 3 and the base plate 4 can be easily bonded using a reflow furnace.
  • the electrode 1 c of the semiconductor chip 1 and the wiring 3 ca of the ceramic substrate 3 are electrically connected by a wire 6. Further, the electrode 1 d of the semiconductor chip 1 and the wiring 3 cc of the ceramic substrate 3 are electrically connected by the wire 6. Further, the terminal 7 serving as an external terminal is connected to the wiring 3 cc of the ceramic substrate 3.
  • the case 8 is attached to the base plate 4 so that a part of the terminal 7 is exposed and the ceramic substrate 3, the semiconductor chip 1, and the plurality of wires 6 are covered.
  • the resin 11 for sealing is filled in the space in the case 8 and the resin 11 is cured to complete the assembly of the power module 20.
  • FIG. 6 is an enlarged partial cross-sectional view showing an example of the structure of a chip joint portion made of a sintered joint material of the semiconductor device (power module) according to the second embodiment of the present invention.
  • a plurality of spherical protrusions are formed on at least one of the back surface (first bonding surface) 1b of the semiconductor chip 1 and the wiring 3cb of the upper surface (second bonding surface) 3a of the ceramic substrate 3.
  • a structure in which a plurality of spherical recesses 10 are formed in addition to the portion 9 will be described.
  • a plurality of spherical convex portions 9a and a plurality of spherical concave portions 10a are formed on the back surface 1b of the semiconductor chip 1 in an adjacent arrangement.
  • a plurality of spherical convex portions 9b and a plurality of spherical concave portions 10b are formed in the wiring 3cb on the upper surface 3a of the ceramic substrate 3 in an adjacent arrangement.
  • a plurality of concave and convex portions (concave portions 10 and convex portions 9) having a spherical shape are formed on the back surface 1b of the semiconductor chip 1 and the wiring 3cb on the top surface 3a of the ceramic substrate 3, respectively.
  • the radius of curvature R of the spherical surface is 0.5 ⁇ m to 5 ⁇ m, preferably about 3 ⁇ m, as in the first embodiment.
  • the concavo-convex part is preferably formed of the same material as in the first embodiment. That is, when the sintered joining material 2 is made of Cu, the plurality of uneven portions are preferably formed of Cu or Ni. On the other hand, when the sintered joining material 2 is made of Ag, the plurality of uneven portions is preferably formed of Ag, Au, or Pd. In addition, when forming on the back surface 1b of the semiconductor chip 1, it is preferable to form the uneven portions by etching after forming a conductor film such as Cu on the back surface 1b.
  • the uneven portions may be formed by etching after forming a conductor film such as Cu on the upper surface 3a of the ceramic substrate 3.
  • a mold (not shown) may be pressed and transferred to the surface to form the plurality of uneven portions.
  • a plurality of spherical concave and convex portions are formed on each of the back surface 1b of the semiconductor chip 1 and the wiring 3cb on the top surface 3a of the ceramic substrate 3, so that The sintered density in the vicinity of the bonding interface of the bonding material 2 can be further increased.
  • the concave curved surface by the concave portion 10 and the convex curved surface by the convex portion 9 can improve the holding power of the paste material for sintering even when pressure is applied at the time of joining. Can be prevented.
  • the value of pressurization can be further increased as compared with the structure of the first embodiment, and the overall sintered density of the sintered bonding material 2 can be increased (increased). Therefore, the structure of the power module 20 (see FIG. 1) having higher reliability than the structure of the first embodiment can be realized. (Embodiment 3)
  • FIG. 7 is an enlarged partial cross-sectional view showing an example of the structure of a chip joint portion made of a sintered joint material of the semiconductor device (power module) according to the third embodiment of the present invention.
  • a plurality of spherical convex portions 9a (9) are formed on the back surface (first bonding surface) 1b of the semiconductor chip 1, and wiring on the upper surface (second bonding surface) 3a of the ceramic substrate 3 is performed.
  • 3cb describes a structure in which a plurality of spherical convex portions 9 and a plurality of spherical concave portions 10 are formed.
  • a plurality of spherical projections 9a are formed on the back surface 1b of the semiconductor chip 1, while a plurality of spherical projections 9b and a plurality of spherical projections are formed on the wiring 3cb on the upper surface 3a of the ceramic substrate 3.
  • the recesses 10b are formed in an array adjacent to each other. That is, the wiring 3cb on the upper surface 3a of the ceramic substrate 3 is formed with a plurality of concave and convex portions (concave portions 10 and convex portions 9) having a spherical shape.
  • FIG. 8 is a partial side view showing an example of a railway vehicle on which the semiconductor device shown in FIG. 1 is mounted
  • FIG. 9 is a plan view showing an example of an internal structure of an inverter installed in the railway vehicle shown in FIG.
  • a railway vehicle 21 shown in FIG. 8 is mounted with, for example, the power module 20 shown in FIG. 1, and includes a vehicle main body 26, a power module 20, a mounting member that supports the power module 20, and a current collector.
  • a pantograph 22 and an inverter 23 are provided.
  • the power module 20 is mounted on an inverter 23 installed at the lower part of the vehicle body 26.
  • a plurality of power modules 20 are mounted on a printed circuit board (mounting member) 25, and a cooling device 24 for cooling these power modules 20 is mounted.
  • the cooling device 24 is attached so that the plurality of power modules 20 can be cooled to cool the inside of the inverter 23.
  • the sintered bonding material 2 is used for chip bonding in the power module 20, and the back surface 1 b of the semiconductor chip 1 and the upper surface 3 a of the ceramic substrate 3 are used.
  • the bonding reliability of the bonding portion by the sintered bonding material 2 can be enhanced.
  • the cooling device 24 shown in FIG. 9 can be downsized, and the inverter 23 can be downsized.
  • resistance to high temperature and low temperature environments can be enhanced, and resistance of the power module 20 to a temperature load such as a temperature cycle can be increased.
  • FIG. 10 is a perspective view showing an example of an automobile on which the semiconductor device shown in FIG. 1 is mounted.
  • the 10 includes, for example, the power module 20 illustrated in FIG. 1, and includes a vehicle body 28, a tire 29, the power module 20, and a mounting unit that is a mounting member that supports the power module 20. 30.
  • the power module 20 is mounted on an inverter included in the mounting unit 30.
  • the mounting unit 30 is, for example, an engine control unit, and in this case, the mounting unit 30 is disposed in the vicinity of the engine. ing. In this case, the mounting unit 30 is used in a high temperature environment, and the power module 20 is also in a high temperature state.
  • the mounting unit 30 is in a high temperature environment by providing an inverter in which a plurality of power modules 20 using the module joining structure shown in FIG.
  • the reliability of the automobile 27 can be improved. That is, in the automobile 27 as well, it is possible to realize the power module 20 that can withstand operation stability under a high temperature environment and a high current load, and an inverter system using the same.
  • the sintered bonding material 2 is used for chip bonding in the power module 20, as in the application example to the railcar 21, and the semiconductor chip. Since the plurality of spherical convex portions 9 or the concave and convex portions are formed on the back surface 1b of 1 and the upper surface 3a of the ceramic substrate 3, the bonding reliability of the bonding portion by the sintered bonding material 2 can be improved.
  • resistance to high and low temperature environments can be increased, and the resistance of the power module 20 to temperature loads such as temperature cycles can be increased.
  • SYMBOLS 1 Semiconductor chip 1a Upper surface 1b Back surface (1st junction surface) 1c, 1d electrode 2 sintered joint material 2a joint boundary 2b first joint 2c joint boundary 2d second joint 2e central part 3 ceramic substrate (wiring substrate) 3a Upper surface (second bonding surface) 3b Lower surface 3c, 3ca, 3cb, 3cc, 3cd Wiring (conductor film) 4 Base plate (metal plate) 5 Bonding materials (other bonding materials) 6 Wire 7 Terminal 8 Case 9, 9a, 9b Convex 10, 10a, 10b Concave 11 Resin 20 Power module (semiconductor device) DESCRIPTION OF SYMBOLS 21 Rail vehicle 22 Pantograph 23 Inverter 24 Cooling device 25 Printed circuit board 26 Vehicle main body 27 Car 28 Car body 29 Tire 30 Mounting unit

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Module de puissance comprenant : une puce semi-conductrice (1) ; un substrat céramique (3) qui supporte la puce semi-conductrice (1) et est électriquement connecté à la puce semi-conductrice (1), tout en étant pourvu de lignes de câblage (3c) sur les surfaces avant et arrière, lesdites lignes de câblage (3c) étant constituées de films conducteurs ; et un matériau de liaison fritté (2) qui est disposé entre la puce semi-conductrice (1) et le substrat céramique (3) et qui relie la puce semi-conductrice (1) et le substrat céramique (3). Dans ce module de puissance, une surface arrière (1b) de la puce semi-conductrice (1), ladite surface arrière (1b) étant liée au matériau de liaison fritté (2), et la ligne de câblage (3c) sur une surface supérieure (3a) du substrat céramique (3,) ladite surface supérieure (3a) étant liée au matériau de liaison fritté (2), sont pourvues d'une pluralité de saillies sphériques (9).
PCT/JP2018/001318 2017-03-15 2018-01-18 Dispositif semiconducteur WO2018168185A1 (fr)

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WO2015052791A1 (fr) * 2013-10-09 2015-04-16 古河電気工業株式会社 Procédé d'assemblage pour corps métallique et structure d'assemblage pour corps métallique
JP2016032051A (ja) * 2014-07-30 2016-03-07 日立化成株式会社 接合材料、電子部品、電気製品及び接合方法
WO2017057645A1 (fr) * 2015-10-02 2017-04-06 三井金属鉱業株式会社 Structure de jonction de soudage

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JP5642336B2 (ja) * 2008-02-06 2014-12-17 富士電機株式会社 半導体装置およびその製造方法
JP2010171271A (ja) * 2009-01-23 2010-08-05 Renesas Technology Corp 半導体装置およびその製造方法
JP6168586B2 (ja) * 2013-02-15 2017-07-26 国立研究開発法人産業技術総合研究所 接合方法及び半導体モジュールの製造方法
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JP2014027095A (ja) * 2012-07-26 2014-02-06 Denso Corp 電子装置およびその製造方法
WO2015052791A1 (fr) * 2013-10-09 2015-04-16 古河電気工業株式会社 Procédé d'assemblage pour corps métallique et structure d'assemblage pour corps métallique
JP2016032051A (ja) * 2014-07-30 2016-03-07 日立化成株式会社 接合材料、電子部品、電気製品及び接合方法
WO2017057645A1 (fr) * 2015-10-02 2017-04-06 三井金属鉱業株式会社 Structure de jonction de soudage

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Publication number Priority date Publication date Assignee Title
US11569169B2 (en) * 2017-03-24 2023-01-31 Mitsubishi Electric Corporation Semiconductor device comprising electronic components electrically joined to each other via metal nanoparticle sintered layer and method of manufacturing the same

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