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WO2018168185A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2018168185A1
WO2018168185A1 PCT/JP2018/001318 JP2018001318W WO2018168185A1 WO 2018168185 A1 WO2018168185 A1 WO 2018168185A1 JP 2018001318 W JP2018001318 W JP 2018001318W WO 2018168185 A1 WO2018168185 A1 WO 2018168185A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
semiconductor chip
sintered
bonding
joint
Prior art date
Application number
PCT/JP2018/001318
Other languages
French (fr)
Japanese (ja)
Inventor
高彰 宮崎
中村　真人
靖 池田
Original Assignee
株式会社日立パワーデバイス
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Filing date
Publication date
Application filed by 株式会社日立パワーデバイス filed Critical 株式会社日立パワーデバイス
Publication of WO2018168185A1 publication Critical patent/WO2018168185A1/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F1/00—Metallic powder; Treatment of metallic powder, e.g. to facilitate working or to improve properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a power semiconductor device used in an inverter.
  • power semiconductor devices have a structure in which a semiconductor element (hereinafter, also referred to as a semiconductor chip or simply a chip) and an insulating substrate, or an insulating substrate and a metal plate for heat dissipation are bonded with a bonding material. .
  • solder containing lead (Pb) has been used as a connecting member for semiconductor devices that require high reliability, particularly semiconductor devices used in the fields of automobiles, construction equipment, railways, and information equipment. For reduction, devices using lead-free connecting members are also widely used.
  • Si (silicon) semiconductor elements In recent years, development of wide gap semiconductors such as SiC and GaN capable of operating at high temperatures and reducing the size and weight of devices has been promoted.
  • the upper limit of the operating temperature of Si (silicon) semiconductor elements is 150 to 175 ° C., whereas SiC semiconductor elements can be used at 175 ° C. or higher.
  • the bonding material used for the semiconductor device is also required to have a heat resistance of 175 ° C. or higher.
  • Development of heat-resistant joints is progressing.
  • the sinterable metal joining technique using the sintering phenomenon has properties suitable for power modules that require high heat resistance.
  • Sintered bonding using the low-temperature firing function of metal fine particles is expected as a highly heat-resistant and highly reliable bonding material.
  • metal nanoparticles having a particle size of several hundred nm or less the number of constituent atoms decreases, the surface area ratio with respect to the volume of the particles increases rapidly, and the sintering temperature decreases significantly compared to the bulk state.
  • the metal fine particles are very reactive, and in order to prevent the progress of sintering during storage, generally, metal fine particles having a surface formed with an organic coating or a metal oxide layer are used.
  • a sintered bonding material paste obtained by mixing metal fine particles with a solvent to form a paste is generally used.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2012-28674 discloses a technique for increasing the bonding reliability by interposing a stress buffer plate in a portion of a bonding material (sintering silver fine particles) of a semiconductor element. ing. Although peeling is likely to occur at the bonding interface between the bonding material and the member to be bonded, the above Patent Document 1 does not consider such peeling.
  • Patent Document 3 discloses a technique capable of improving the bonding strength and preventing peeling by bonding the conductor layer of the insulating substrate and the electrode of the semiconductor element using sinterable metal bonding materials having different particle sizes. (Japanese Unexamined Patent Publication No. 2016-1000042). However, the technique has a problem that the process time increases because it is necessary to supply a metal joining material that is sinterable at least twice.
  • An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device in which a semiconductor chip is bonded by a sintered bonding material.
  • a semiconductor device includes a semiconductor chip, a wiring board that supports the semiconductor chip and is electrically connected to the semiconductor chip, and is disposed between the semiconductor chip and the wiring board. And a sintered bonding material for bonding the wiring board. Further, a plurality of spherical protrusions are formed on at least one of the first joint surface that joins the sintered joint material of the semiconductor chip and the second joint surface that joins the sintered joint material of the wiring board. The part is formed.
  • Another semiconductor device includes a semiconductor chip, a wiring board that supports the semiconductor chip, is electrically connected to the semiconductor chip, and has a conductor film formed on both front and back surfaces, and the semiconductor chip and the wiring. And a sintered bonding material that is disposed between the semiconductor chip and the wiring substrate. And a metal plate on which the semiconductor chip and the wiring board are mounted, and another bonding material that is disposed between the wiring board and the metal plate and joins the wiring board and the metal plate. A plurality of spherical concave and convex portions are formed on the first joint surface of the semiconductor chip joined to the sintered joint material and the second joint surface of the conductor film joined to the sintered joint material.
  • FIG. 2 is an enlarged partial cross-sectional view illustrating an example of a structure of a chip bonding portion made of a sintered bonding material of the semiconductor device illustrated in FIG. 1. It is a schematic diagram which shows the curvature radius of the convex part shown to the A section of FIG. It is an expanded partial sectional view which shows the structure of the chip joint part by the sintered joining material of a comparative example.
  • FIG. 2 is a partial side view showing an example of a railway vehicle on which the semiconductor device shown in FIG. 1 is mounted. It is a top view which shows an example of the internal structure of the inverter installed in the rail vehicle shown in FIG. It is a perspective view which shows an example of the motor vehicle carrying the semiconductor device shown in FIG.
  • FIG. 1 is a sectional view showing an example of the structure of a semiconductor device (power module) according to the first embodiment of the present invention.
  • FIG. 2 shows an example of the structure of a wiring board used in the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3 is an enlarged partial cross-sectional view showing an example of the structure of the chip joint portion by the sintered joining material of the semiconductor device shown in FIG. 1, and
  • FIG. 4 is a schematic diagram showing the curvature radius of the convex portion shown in part A of FIG. FIG.
  • the semiconductor device is, for example, a semiconductor module (power module) mounted on a railway vehicle, an automobile body, or the like. Therefore, the semiconductor device includes a plurality of power semiconductor chips (semiconductor elements) 1.
  • the semiconductor chip 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOS (Metal Oxide Semiconductor), a diode, or the like, but is not limited thereto.
  • the configuration of the power module (semiconductor device) 20 shown in FIG. 1 will be described.
  • the power module 20 includes a semiconductor chip 1, and the semiconductor chip 1 includes an upper surface 1 a and a back surface (first bonding surface) 1 b that is the opposite surface.
  • the semiconductor chip 1 is bonded to a ceramic substrate (wiring substrate) 3 via a sintered bonding material 2. That is, the back surface 1 b of the semiconductor chip 1 is bonded to the sintered bonding material 2.
  • the semiconductor chip 1 is preferably made of SiC or GaN that can operate at a high temperature of 175 ° C. or higher, but may be made of, for example, silicon.
  • the power module 20 is a conductive wire that electrically connects the electrode 1d provided on the upper surface 1a of the semiconductor chip 1 and the wiring 3cc (3c) of the upper surface (second bonding surface) 3a of the ceramic substrate 3. 6 and a terminal 7 which is electrically connected to the wiring 3cc of the ceramic substrate 3 and is drawn to the outside.
  • a plurality of (for example, three) semiconductor chips 1 are mounted on one ceramic substrate 3. Specifically, a plurality of semiconductor chips 1 are mounted on the wiring 3 cb provided on the upper surface 3 a of the ceramic substrate 3.
  • a plurality of terminals 7 that are external terminals of the power module 20 are connected to the wiring 3 cc on the upper surface 3 a of the ceramic substrate 3.
  • the ceramic substrate 3 on which the plurality of semiconductor chips 1 and the plurality of terminals 7 are mounted is mounted on a base plate (metal plate) 4 via a bonding material (another bonding material such as a solder alloy) 5.
  • a bonding material another bonding material such as a solder alloy
  • the ceramic substrate 3 has a plurality of wirings (conductor films) 3c formed on the upper surface 3a thereof.
  • a wiring 3cb which is a conductor film, is arranged at the center of the upper surface 3a, and the wiring (conductor film) 3ca to which the wires 6 shown in FIG. A wiring (conductor film) 3cc is formed, while a wiring 3cd is also formed on the lower surface 3b.
  • These wirings 3ca, 3cb, 3cc, 3cd are made of, for example, Cu (copper) or Al (aluminum), and the ceramic substrate 3 is made of silicon nitride, alumina, aluminum nitride, or the like.
  • the wiring 3 cd formed on the lower surface 3 b of the ceramic substrate 3 is bonded to the base plate 4 by the bonding material 5.
  • a gate electrode 1 c is formed on the upper surface 1 a of the semiconductor chip 1 and is electrically connected to the wiring 3 ca of the ceramic substrate 3 via the wire 6. Furthermore, another electrode 1 d formed on the upper surface 1 a of the semiconductor chip 1 is electrically connected to the wiring 3 cc of the ceramic substrate 3 via the wire 6.
  • the base plate 4 is a metal plate for heat dissipation.
  • the base plate 4 that is also a heat sink is provided with a case 8 that covers the plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3.
  • the case 8 is filled with a sealing resin 11. Has been. That is, the plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3 are sealed with the sealing resin 11.
  • the resin 11 for example, a gel-like resin material is preferably used.
  • each of the plurality of wires 6 is a metal wire such as an Al wire or a Cu wire, for example.
  • the sintered bonding material 2 is a member that is disposed between the semiconductor chip 1 and the ceramic substrate 3 and bonds the semiconductor chip 1 and the ceramic substrate 3 and is a bonding material based on sintered bonding. It is desirable.
  • the bonding material 5 is a member that is disposed between the ceramic substrate 3 and the base plate 4 and bonds the ceramic substrate 3 and the base plate 4.
  • the bonding material 5 is preferably a solder alloy containing Sn as a main component or a solder alloy containing Pb as a main component.
  • a bonding material such as Zn—Al, Au—Ge, Au—Si, sintered Ag, and sintered Cu may be used.
  • the base plate 4 may be Cu, Al, Al alloy, Cu alloy, a composite material of Al and SiC, or a composite material of Mg (magnesium) and SiC.
  • the semiconductor chip 1 mounted on the power module 20 of the first embodiment is preferably made of a material such as high heat-resistant SiC or GaN, and the semiconductor chip 1 is made of a material such as SiC or GaN. Therefore, it is possible to cope with further increase in operating temperature.
  • a plurality of spherical surfaces are formed on the back surface (first bonding surface) 1 b bonded to the sintered bonding material 2 of the semiconductor chip 1.
  • Convex part 9a (9) is formed.
  • a plurality of spherical convex portions 9b (9) are formed on the surface of the wiring 3cb of the upper surface (second bonding surface) 3a to be bonded to the sintered bonding material 2 of the ceramic substrate 3, respectively.
  • the plurality of spherical convex portions 9 only need to be formed on at least one of the back surface 1b of the semiconductor chip 1 or the wiring 3cb on the top surface 3a of the ceramic substrate 3. However, since it is more effective to be provided on both the back surface 1b of the semiconductor chip 1 and the wiring 3cb on the top surface 3a of the ceramic substrate 3, in the first embodiment, the back surface 1b of the semiconductor chip 1 and the ceramic substrate 3 A case where a plurality of spherical convex portions 9 are formed on each of the wirings 3cb on the upper surface 3a will be described.
  • each of the plurality of spherical convex portions 9 is formed in a substantially hemispherical shape as shown in FIGS.
  • the sintering density of the sintered bonding material 2 in the vicinity of the bonding interface with the semiconductor chip 1 and the ceramic substrate 3 can be increased, and the bonding reliability of the sintered bonding material 2 can be increased.
  • a plurality of spherical irregularities are formed on the back surface 1b of the semiconductor chip 1 and the wiring 3cb on the top surface 3a of the ceramic substrate 3, respectively. It may be expressed as
  • FIG. 5 is an enlarged partial cross-sectional view showing a structure of a chip joint portion made of a sintered joining material of a comparative example.
  • the sintered joining material 2 after joining has a large number of particles having a diameter of 1 ⁇ m to 10 ⁇ m. I found it.
  • the shape after joining is more stable in terms of energy as the particle surface area becomes smaller, it becomes a shape in which spheres are combined.
  • the present inventor examined the structure of the power module that can realize the high reliability of the bonding interface of the sintered bonding material 2 without increasing the assembly process of the semiconductor device. As a result, as shown in FIG. 3, a plurality of convex portions 9 each having a spherical shape are provided on the back surface 1 b of the semiconductor chip 1 and the wiring 3 cb on the upper surface 3 a of the ceramic substrate 3. It has been found that the sintered density in the vicinity of the interface can be increased.
  • a plurality of spherical convex portions 9 are respectively provided on the back surface 1 b of the semiconductor chip 1 and the wiring 3 cb on the upper surface 3 a of the ceramic substrate 3, so that adjacent spherical convex portions are provided.
  • Part (particles) of the sintered bonding material 2 can be inserted into the gap between the portions 9. Accordingly, the first bonding portion 2b including the bonding boundary portion 2a of the sintered bonding material 2 with the semiconductor chip 1 and the second bonding portion 2d including the bonding boundary portion 2c of the sintered bonding material 2 with the ceramic substrate 3 are obtained.
  • Each sintered density is larger than the sintered density in the sintered joint material 2 excluding the first joint portion 2b and the second joint portion 2d, that is, in the vicinity of the central portion 2e in the thickness direction of the sintered joint material 2 ( Can be high). That is, in the cross-sectional view cut along the thickness direction of the sintered bonding material 2 (the same direction as the thickness direction of the semiconductor chip 1), the sintering density of each of the first bonding portion 2b and the second bonding portion 2d is determined. The sintering density of the central portion 2e located between the first joint portion 2b and the second joint portion 2d can be made larger (higher).
  • the sintered density in the vicinity of the bonding interface between the semiconductor chip 1 and the ceramic substrate 3 in the sintered bonding material 2 can be increased (increased), high reliability can be obtained without breaking at the bonding interface. it can. In other words, it is possible to suppress or prevent the peeling that occurs at the bonding interface between the sintered bonding material 2 and the semiconductor chip 1 or the ceramic substrate 3.
  • the reliability of the power module (semiconductor device) 20 in which the semiconductor chip 1 and the ceramic substrate 3 are joined by the sintered joining material 2 can be improved.
  • the structure of the power module (semiconductor device) 20 having high heat resistance can be realized.
  • the bonding reliability of the bonded portion using the sintered bonding material 2 is enhanced, it can have a great resistance against a temperature load such as a temperature cycle in which a low temperature environment and a high temperature environment are repeated.
  • the spherical radius of each of the plurality of spherical convex portions 9 has a radius of curvature R of 0.5 ⁇ m to 5 ⁇ m, preferably about 3 ⁇ m. That is, since the diameter of the particles of the sintered joining material 2 to be formed is about 6 ⁇ m, a spherical surface having a radius of curvature R of about 3 ⁇ m, which is the same as the size of the particles after joining, is preferable, and various variations are considered. Then, it is preferable that a plurality of spherical convex portions 9 having a radius of curvature R of about 0.5 ⁇ m to 5 ⁇ m are provided.
  • the sintered bonding material 2 is preferably made of a material mainly composed of Cu or Ag. And it is suitable for the wiring 3c which is a conductor film formed in the front and back of the ceramic substrate 3 to be formed from copper foil.
  • the some convex part 9a (9) formed in the back surface 1b of the semiconductor chip 1 can be formed by electroless plating, for example.
  • the plurality of convex portions 9b (9) formed on the wiring 3cb on the upper surface 3a of the ceramic substrate 3 can be similarly formed by electroless plating, or the mold can be formed using a mold (not shown). It can also be formed by a method of pressing and transferring to the wiring 3cb on the upper surface 3a of the ceramic substrate 3.
  • the sintered joining material 2 consists of Cu
  • the some convex part 9 is formed of Cu or Ni.
  • the sintered bonding material 2 is made of Ag
  • the plurality of convex portions 9 are preferably formed of Ag, Au, or Pd.
  • a semiconductor chip 1 having a plurality of spherical convex portions 9a (9) formed on the back surface 1b is prepared, and a plurality of spherical convex portions 9b are formed on the wiring 3cb on the upper surface 3a.
  • a ceramic substrate 3 on which (9) is formed is prepared.
  • a paste material for sintering joining obtained by pasting a minute metal powder with a solvent is applied to the wiring 3cb on the upper surface 3a of the ceramic substrate 3.
  • the semiconductor chip 1 is mounted via the paste material, and the solvent is volatilized by heating to 200 to 400 ° C., and simultaneously pressurizing, whereby the sintering progresses to achieve bonding. That is, the semiconductor chip 1 and the ceramic substrate 3 are joined by the sintered joining material 2.
  • the metal particles change into a bulk metal, and at the same time, joining is performed by metal bonding at the joining interface. Therefore, the joined portion of the sintered joining material 2 has very high heat resistance and reliability.
  • the ceramic substrate 3 is disposed on the base plate 4 via a bonding material (other bonding material) 5 made of a solder alloy, the bonding material 5 is heated and melted, and the ceramic substrate 3 and the base plate (metal plate). 4 is joined.
  • the base plate 4 is a plate material for heat dissipation.
  • the bonding material 5 is melted and the ceramic substrate 3 and the base plate 4 are bonded. Thereby, the solder joint between the ceramic substrate 3 and the base plate 4 in the module structure shown in FIG. 1 is completed.
  • the ceramic substrate 3 and the base plate 4 can be easily bonded using a reflow furnace.
  • the electrode 1 c of the semiconductor chip 1 and the wiring 3 ca of the ceramic substrate 3 are electrically connected by a wire 6. Further, the electrode 1 d of the semiconductor chip 1 and the wiring 3 cc of the ceramic substrate 3 are electrically connected by the wire 6. Further, the terminal 7 serving as an external terminal is connected to the wiring 3 cc of the ceramic substrate 3.
  • the case 8 is attached to the base plate 4 so that a part of the terminal 7 is exposed and the ceramic substrate 3, the semiconductor chip 1, and the plurality of wires 6 are covered.
  • the resin 11 for sealing is filled in the space in the case 8 and the resin 11 is cured to complete the assembly of the power module 20.
  • FIG. 6 is an enlarged partial cross-sectional view showing an example of the structure of a chip joint portion made of a sintered joint material of the semiconductor device (power module) according to the second embodiment of the present invention.
  • a plurality of spherical protrusions are formed on at least one of the back surface (first bonding surface) 1b of the semiconductor chip 1 and the wiring 3cb of the upper surface (second bonding surface) 3a of the ceramic substrate 3.
  • a structure in which a plurality of spherical recesses 10 are formed in addition to the portion 9 will be described.
  • a plurality of spherical convex portions 9a and a plurality of spherical concave portions 10a are formed on the back surface 1b of the semiconductor chip 1 in an adjacent arrangement.
  • a plurality of spherical convex portions 9b and a plurality of spherical concave portions 10b are formed in the wiring 3cb on the upper surface 3a of the ceramic substrate 3 in an adjacent arrangement.
  • a plurality of concave and convex portions (concave portions 10 and convex portions 9) having a spherical shape are formed on the back surface 1b of the semiconductor chip 1 and the wiring 3cb on the top surface 3a of the ceramic substrate 3, respectively.
  • the radius of curvature R of the spherical surface is 0.5 ⁇ m to 5 ⁇ m, preferably about 3 ⁇ m, as in the first embodiment.
  • the concavo-convex part is preferably formed of the same material as in the first embodiment. That is, when the sintered joining material 2 is made of Cu, the plurality of uneven portions are preferably formed of Cu or Ni. On the other hand, when the sintered joining material 2 is made of Ag, the plurality of uneven portions is preferably formed of Ag, Au, or Pd. In addition, when forming on the back surface 1b of the semiconductor chip 1, it is preferable to form the uneven portions by etching after forming a conductor film such as Cu on the back surface 1b.
  • the uneven portions may be formed by etching after forming a conductor film such as Cu on the upper surface 3a of the ceramic substrate 3.
  • a mold (not shown) may be pressed and transferred to the surface to form the plurality of uneven portions.
  • a plurality of spherical concave and convex portions are formed on each of the back surface 1b of the semiconductor chip 1 and the wiring 3cb on the top surface 3a of the ceramic substrate 3, so that The sintered density in the vicinity of the bonding interface of the bonding material 2 can be further increased.
  • the concave curved surface by the concave portion 10 and the convex curved surface by the convex portion 9 can improve the holding power of the paste material for sintering even when pressure is applied at the time of joining. Can be prevented.
  • the value of pressurization can be further increased as compared with the structure of the first embodiment, and the overall sintered density of the sintered bonding material 2 can be increased (increased). Therefore, the structure of the power module 20 (see FIG. 1) having higher reliability than the structure of the first embodiment can be realized. (Embodiment 3)
  • FIG. 7 is an enlarged partial cross-sectional view showing an example of the structure of a chip joint portion made of a sintered joint material of the semiconductor device (power module) according to the third embodiment of the present invention.
  • a plurality of spherical convex portions 9a (9) are formed on the back surface (first bonding surface) 1b of the semiconductor chip 1, and wiring on the upper surface (second bonding surface) 3a of the ceramic substrate 3 is performed.
  • 3cb describes a structure in which a plurality of spherical convex portions 9 and a plurality of spherical concave portions 10 are formed.
  • a plurality of spherical projections 9a are formed on the back surface 1b of the semiconductor chip 1, while a plurality of spherical projections 9b and a plurality of spherical projections are formed on the wiring 3cb on the upper surface 3a of the ceramic substrate 3.
  • the recesses 10b are formed in an array adjacent to each other. That is, the wiring 3cb on the upper surface 3a of the ceramic substrate 3 is formed with a plurality of concave and convex portions (concave portions 10 and convex portions 9) having a spherical shape.
  • FIG. 8 is a partial side view showing an example of a railway vehicle on which the semiconductor device shown in FIG. 1 is mounted
  • FIG. 9 is a plan view showing an example of an internal structure of an inverter installed in the railway vehicle shown in FIG.
  • a railway vehicle 21 shown in FIG. 8 is mounted with, for example, the power module 20 shown in FIG. 1, and includes a vehicle main body 26, a power module 20, a mounting member that supports the power module 20, and a current collector.
  • a pantograph 22 and an inverter 23 are provided.
  • the power module 20 is mounted on an inverter 23 installed at the lower part of the vehicle body 26.
  • a plurality of power modules 20 are mounted on a printed circuit board (mounting member) 25, and a cooling device 24 for cooling these power modules 20 is mounted.
  • the cooling device 24 is attached so that the plurality of power modules 20 can be cooled to cool the inside of the inverter 23.
  • the sintered bonding material 2 is used for chip bonding in the power module 20, and the back surface 1 b of the semiconductor chip 1 and the upper surface 3 a of the ceramic substrate 3 are used.
  • the bonding reliability of the bonding portion by the sintered bonding material 2 can be enhanced.
  • the cooling device 24 shown in FIG. 9 can be downsized, and the inverter 23 can be downsized.
  • resistance to high temperature and low temperature environments can be enhanced, and resistance of the power module 20 to a temperature load such as a temperature cycle can be increased.
  • FIG. 10 is a perspective view showing an example of an automobile on which the semiconductor device shown in FIG. 1 is mounted.
  • the 10 includes, for example, the power module 20 illustrated in FIG. 1, and includes a vehicle body 28, a tire 29, the power module 20, and a mounting unit that is a mounting member that supports the power module 20. 30.
  • the power module 20 is mounted on an inverter included in the mounting unit 30.
  • the mounting unit 30 is, for example, an engine control unit, and in this case, the mounting unit 30 is disposed in the vicinity of the engine. ing. In this case, the mounting unit 30 is used in a high temperature environment, and the power module 20 is also in a high temperature state.
  • the mounting unit 30 is in a high temperature environment by providing an inverter in which a plurality of power modules 20 using the module joining structure shown in FIG.
  • the reliability of the automobile 27 can be improved. That is, in the automobile 27 as well, it is possible to realize the power module 20 that can withstand operation stability under a high temperature environment and a high current load, and an inverter system using the same.
  • the sintered bonding material 2 is used for chip bonding in the power module 20, as in the application example to the railcar 21, and the semiconductor chip. Since the plurality of spherical convex portions 9 or the concave and convex portions are formed on the back surface 1b of 1 and the upper surface 3a of the ceramic substrate 3, the bonding reliability of the bonding portion by the sintered bonding material 2 can be improved.
  • resistance to high and low temperature environments can be increased, and the resistance of the power module 20 to temperature loads such as temperature cycles can be increased.
  • SYMBOLS 1 Semiconductor chip 1a Upper surface 1b Back surface (1st junction surface) 1c, 1d electrode 2 sintered joint material 2a joint boundary 2b first joint 2c joint boundary 2d second joint 2e central part 3 ceramic substrate (wiring substrate) 3a Upper surface (second bonding surface) 3b Lower surface 3c, 3ca, 3cb, 3cc, 3cd Wiring (conductor film) 4 Base plate (metal plate) 5 Bonding materials (other bonding materials) 6 Wire 7 Terminal 8 Case 9, 9a, 9b Convex 10, 10a, 10b Concave 11 Resin 20 Power module (semiconductor device) DESCRIPTION OF SYMBOLS 21 Rail vehicle 22 Pantograph 23 Inverter 24 Cooling device 25 Printed circuit board 26 Vehicle main body 27 Car 28 Car body 29 Tire 30 Mounting unit

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Abstract

According to the present invention, a power module comprises: a semiconductor chip 1; a ceramic substrate 3 which supports the semiconductor chip 1 and is electrically connected to the semiconductor chip 1, while being provided with wiring lines 3c on both front and back surfaces, said wiring lines 3c being formed of conductive films; and a sintered bonding material 2 which is arranged between the semiconductor chip 1 and the ceramic substrate 3 and bonds the semiconductor chip 1 and the ceramic substrate 3 to each other. In this power module, a back surface 1b of the semiconductor chip 1, said back surface 1b being bonded with the sintered bonding material 2, and the wiring line 3c on an upper surface 3a of the ceramic substrate 3, said upper surface 3a being bonded with the sintered bonding material 2, are provided with a plurality of spherical projections 9.

Description

半導体装置Semiconductor device
　本発明は、半導体装置に関し、特にインバータに使用されるパワー系の半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to a power semiconductor device used in an inverter.
　パワー系の半導体装置（パワーモジュール）は、半導体素子（以下、半導体チップまたは単にチップとも言う）と絶縁基板、もしくは絶縁基板と放熱用金属板を接合材で接合した構造となっているものが多い。 Many power semiconductor devices (power modules) have a structure in which a semiconductor element (hereinafter, also referred to as a semiconductor chip or simply a chip) and an insulating substrate, or an insulating substrate and a metal plate for heat dissipation are bonded with a bonding material. .
　これまで、高信頼性が要求される半導体装置、特に自動車や建機、鉄道、情報機器分野等に用いられる半導体装置の接続部材としては鉛（Ｐｂ）入りはんだが使用されてきたが、環境負荷低減のため、鉛フリーの接続部材を使用した機器も広く使用されている。 Until now, solder containing lead (Pb) has been used as a connecting member for semiconductor devices that require high reliability, particularly semiconductor devices used in the fields of automobiles, construction equipment, railways, and information equipment. For reduction, devices using lead-free connecting members are also widely used.
　近年、高温動作が可能で、かつ機器の小型軽量化が可能なＳｉＣやＧａＮ等のワイドギャップ半導体の開発が推し進められている。なお、一般的にＳｉ（シリコン）の半導体素子は動作温度の上限が１５０～１７５℃であるのに対し、ＳｉＣの半導体素子は１７５℃以上での使用が可能である。 In recent years, development of wide gap semiconductors such as SiC and GaN capable of operating at high temperatures and reducing the size and weight of devices has been promoted. In general, the upper limit of the operating temperature of Si (silicon) semiconductor elements is 150 to 175 ° C., whereas SiC semiconductor elements can be used at 175 ° C. or higher.
　ただし、使用温度が高温になると、半導体装置（パワーモジュール）に使用される接合材についても１７５℃以上の耐熱性が要求されるため、高融点接合材や微小粒子を使用した焼結接合など高耐熱な接合部の開発が進んでいる。このように、焼結現象を利用した焼結性金属接合技術は、高耐熱性能が要求されるパワーモジュールに好適な性質を有するものである。 However, when the operating temperature is high, the bonding material used for the semiconductor device (power module) is also required to have a heat resistance of 175 ° C. or higher. Development of heat-resistant joints is progressing. As described above, the sinterable metal joining technique using the sintering phenomenon has properties suitable for power modules that require high heat resistance.
特開２０１２－２８６７４号公報Japanese Patent Laid-Open No. 2012-28674 特開２０１５－３５４５９号公報JP 2015-35459 A 特開２０１６－１００４２４号公報Japanese Patent Laid-Open No. 2016-1000042
　金属微粒子の低温焼成機能を利用した焼結接合が高耐熱かつ高信頼な接合材料として期待されている。一般に粒径が数１００ｎｍ以下の金属ナノ粒子では、構成原子数が少なくなり粒子の体積に対する表面積比は急激に増大し、焼結温度がバルクの状態に比較して大幅に低下する。金属微粒子は非常に反応性が高く、保管中の焼結進行を防止するため一般的には表面に有機物の被膜を形成したり、金属酸化層を設けた金属微粒子を使用する。また、サンプルに供給しやすくするため、金属微粒子を溶剤と混合してペースト化した焼結接合材ペーストが一般に使用される。 Sintered bonding using the low-temperature firing function of metal fine particles is expected as a highly heat-resistant and highly reliable bonding material. In general, in the case of metal nanoparticles having a particle size of several hundred nm or less, the number of constituent atoms decreases, the surface area ratio with respect to the volume of the particles increases rapidly, and the sintering temperature decreases significantly compared to the bulk state. The metal fine particles are very reactive, and in order to prevent the progress of sintering during storage, generally, metal fine particles having a surface formed with an organic coating or a metal oxide layer are used. Moreover, in order to make it easy to supply to a sample, a sintered bonding material paste obtained by mixing metal fine particles with a solvent to form a paste is generally used.
　接合の際には、被接合材間に焼結接合ペーストを供給して加熱および加圧を加えることで焼結が進行して接合が達成される。接合後は金属微粒子はバルク金属へと変化すると同時に接合界面では金属結合により接合されるため、非常に高い耐熱性および信頼性を有する。 When joining, sintering is progressed by supplying a sintered joining paste between the materials to be joined and applying heating and pressurization to achieve joining. After bonding, the metal fine particles change into a bulk metal and at the same time are bonded by metal bonding at the bonding interface, and thus have extremely high heat resistance and reliability.
　ここで、特許文献１（特開２０１２－２８６７４号公報）には、半導体素子の接合材（焼結性の銀微粒子）の部分に応力緩衝板を介在させて接合信頼性を高める技術が開示されている。なお、接合材と被接合部材との接合界面では剥離が発生し易いが、上記特許文献１ではこのような剥離については考慮されていない。 Here, Patent Document 1 (Japanese Patent Application Laid-Open No. 2012-28674) discloses a technique for increasing the bonding reliability by interposing a stress buffer plate in a portion of a bonding material (sintering silver fine particles) of a semiconductor element. ing. Although peeling is likely to occur at the bonding interface between the bonding material and the member to be bonded, the above Patent Document 1 does not consider such peeling.
　また、パワーモジュールなどの電子機器において被接合材はバルク金属であるため、特に接合界面の強度が低くなることが問題となっている。接合界面の焼結密度が低い場合、接合界面の強度が不足し、接合界面での剥離が発生するため所望の信頼性が得られなくなる。このような課題に対して、特許文献２（特開２０１５－３５４５９号公報）によれば、第１部材と第２部材の少なくとも一方の金属面は、表面粗さを有する粗面に形成されたため、第１部材と第２部材を大型化することなく、第１部材と第２部材の接合面積を増加させることができ、また、アンカー効果に基づいて、十分な接合強度を得ることができる。さらに、粗面は、０．５μｍ～２．０μｍの表面粗さに形成されたため、クラック面積率（剥離面積の割合）を大幅に抑制することができ、第１部材と第２部材を接合する場合の接合信頼性の向上を図ることができる発明が開示されている。しかしながら、焼結接合は液相を介さず、また粗さによる表面の凹凸の大きさや形状については考慮されておらず、接合材の剥離は防ぐことができない。また、異なる粒子径の焼結性金属接合材料を用いて絶縁基板の導体層と半導体素子の電極とを接合することにより、接合強度を向上させ、剥離を防ぐことができる技術が特許文献３（特開２０１６－１００４２４号公報）に開示されている。しかしながら、前記技術では、少なくとも２回焼結性金属接合材料を供給する必要があるためプロセスタイムが増加するという課題がある。 Also, in electronic devices such as power modules, since the material to be joined is a bulk metal, there is a problem that the strength of the joint interface is particularly low. When the sintered density of the bonding interface is low, the strength of the bonding interface is insufficient, and peeling at the bonding interface occurs, so that desired reliability cannot be obtained. With respect to such a problem, according to Patent Document 2 (Japanese Patent Laid-Open No. 2015-35459), at least one metal surface of the first member and the second member is formed as a rough surface having a surface roughness. The joining area between the first member and the second member can be increased without increasing the size of the first member and the second member, and sufficient joining strength can be obtained based on the anchor effect. Furthermore, since the rough surface is formed to have a surface roughness of 0.5 μm to 2.0 μm, the crack area ratio (ratio of the peeled area) can be greatly suppressed, and the first member and the second member are joined. The invention which can aim at the improvement of the joining reliability in a case is disclosed. However, sintering joining does not involve a liquid phase, and the size and shape of surface irregularities due to roughness are not considered, and peeling of the joining material cannot be prevented. Patent Document 3 discloses a technique capable of improving the bonding strength and preventing peeling by bonding the conductor layer of the insulating substrate and the electrode of the semiconductor element using sinterable metal bonding materials having different particle sizes. (Japanese Unexamined Patent Publication No. 2016-1000042). However, the technique has a problem that the process time increases because it is necessary to supply a metal joining material that is sinterable at least twice.
　本発明の目的は、焼結接合材によって半導体チップが接合された半導体装置の信頼性を高めることができる技術を提供することにある。 An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device in which a semiconductor chip is bonded by a sintered bonding material.
　本発明の上記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
　本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、以下のとおりである。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
　本発明に係る半導体装置は、半導体チップと、上記半導体チップを支持し、上記半導体チップと電気的に接続された配線基板と、上記半導体チップと上記配線基板との間に配置され、上記半導体チップと上記配線基板とを接合する焼結接合材と、を有する。さらに、上記半導体チップの上記焼結接合材と接合する第１接合面もしくは上記配線基板の上記焼結接合材と接合する第２接合面のうちの少なくとも何れか一方に、複数の球面状の凸部が形成されている。 A semiconductor device according to the present invention includes a semiconductor chip, a wiring board that supports the semiconductor chip and is electrically connected to the semiconductor chip, and is disposed between the semiconductor chip and the wiring board. And a sintered bonding material for bonding the wiring board. Further, a plurality of spherical protrusions are formed on at least one of the first joint surface that joins the sintered joint material of the semiconductor chip and the second joint surface that joins the sintered joint material of the wiring board. The part is formed.
　本発明に係る他の半導体装置は、半導体チップと、上記半導体チップを支持し、上記半導体チップと電気的に接続され、表裏両面に導体膜が形成された配線基板と、上記半導体チップと上記配線基板との間に配置され、上記半導体チップと上記配線基板とを接合する焼結接合材と、を有する。さらに、上記半導体チップおよび上記配線基板が搭載された金属板と、上記配線基板と上記金属板との間に配置され、上記配線基板と上記金属板とを接合する他の接合材と、を有し、上記半導体チップの上記焼結接合材と接合する第１接合面および上記導体膜の上記焼結接合材と接合する第２接合面に、複数の球面状の凹凸部が形成されている。 Another semiconductor device according to the present invention includes a semiconductor chip, a wiring board that supports the semiconductor chip, is electrically connected to the semiconductor chip, and has a conductor film formed on both front and back surfaces, and the semiconductor chip and the wiring. And a sintered bonding material that is disposed between the semiconductor chip and the wiring substrate. And a metal plate on which the semiconductor chip and the wiring board are mounted, and another bonding material that is disposed between the wiring board and the metal plate and joins the wiring board and the metal plate. A plurality of spherical concave and convex portions are formed on the first joint surface of the semiconductor chip joined to the sintered joint material and the second joint surface of the conductor film joined to the sintered joint material.
　本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下のとおりである。
　半導体装置の信頼性を高めることができる。 Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
The reliability of the semiconductor device can be improved.
本発明の実施の形態１の半導体装置（パワーモジュール）の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the semiconductor device (power module) of Embodiment 1 of this invention. 本発明の実施の形態１の半導体装置に用いられる配線基板の構造の一例を示す平面図である。It is a top view which shows an example of the structure of the wiring board used for the semiconductor device of Embodiment 1 of this invention. 図１に示す半導体装置の焼結接合材によるチップ接合部の構造の一例を示す拡大部分断面図である。FIG. 2 is an enlarged partial cross-sectional view illustrating an example of a structure of a chip bonding portion made of a sintered bonding material of the semiconductor device illustrated in FIG. 1. 図３のＡ部に示す凸部の曲率半径を示す模式図である。It is a schematic diagram which shows the curvature radius of the convex part shown to the A section of FIG. 比較例の焼結接合材によるチップ接合部の構造を示す拡大部分断面図である。It is an expanded partial sectional view which shows the structure of the chip joint part by the sintered joining material of a comparative example. 本発明の実施の形態２の半導体装置（パワーモジュール）の焼結接合材によるチップ接合部の構造の一例を示す拡大部分断面図である。It is an expanded partial sectional view which shows an example of the structure of the chip junction part by the sintered joining material of the semiconductor device (power module) of Embodiment 2 of this invention. 本発明の実施の形態３の半導体装置（パワーモジュール）の焼結接合材によるチップ接合部の構造の一例を示す拡大部分断面図である。It is an expanded partial sectional view which shows an example of the structure of the chip junction part by the sintered joining material of the semiconductor device (power module) of Embodiment 3 of this invention. 図１に示す半導体装置が搭載された鉄道車両の一例を示す部分側面図である。FIG. 2 is a partial side view showing an example of a railway vehicle on which the semiconductor device shown in FIG. 1 is mounted. 図８に示す鉄道車両に設置されたインバータの内部構造の一例を示す平面図である。It is a top view which shows an example of the internal structure of the inverter installed in the rail vehicle shown in FIG. 図１に示す半導体装置が搭載された自動車の一例を示す斜視図である。It is a perspective view which shows an example of the motor vehicle carrying the semiconductor device shown in FIG.
　（実施の形態１） (Embodiment 1)
　図１は本発明の実施の形態１の半導体装置（パワーモジュール）の構造の一例を示す断面図、図２は本発明の実施の形態１の半導体装置に用いられる配線基板の構造の一例を示す平面図、図３は図１に示す半導体装置の焼結接合材によるチップ接合部の構造の一例を示す拡大部分断面図、図４は図３のＡ部に示す凸部の曲率半径を示す模式図である。 1 is a sectional view showing an example of the structure of a semiconductor device (power module) according to the first embodiment of the present invention. FIG. 2 shows an example of the structure of a wiring board used in the semiconductor device according to the first embodiment of the present invention. FIG. 3 is an enlarged partial cross-sectional view showing an example of the structure of the chip joint portion by the sintered joining material of the semiconductor device shown in FIG. 1, and FIG. 4 is a schematic diagram showing the curvature radius of the convex portion shown in part A of FIG. FIG.
　本実施の形態１の半導体装置は、例えば、鉄道の車両や自動車の車体等に搭載される半導体モジュール（パワーモジュール）である。したがって、複数のパワー系の半導体チップ（半導体素子）１を備えている半導体装置である。なお、半導体チップ１は、例えばＩＧＢＴ（Insulated Gate Bipolar Transistor ）やＭＯＳ(Metal Oxide Semiconductor) 、Ｄｉｏｄｅ等であるが、ただしこれらに限定されるものではない。 The semiconductor device according to the first embodiment is, for example, a semiconductor module (power module) mounted on a railway vehicle, an automobile body, or the like. Therefore, the semiconductor device includes a plurality of power semiconductor chips (semiconductor elements) 1. The semiconductor chip 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOS (Metal Oxide Semiconductor), a diode, or the like, but is not limited thereto.
　図１に示すパワーモジュール（半導体装置）２０の構成について説明する。パワーモジュール２０は、半導体チップ１を有しており、上記半導体チップ１は、上面１ａとその反対側の面である裏面（第１接合面）１ｂとを備えている。そして、半導体チップ１は、焼結接合材２を介してセラミック基板（配線基板）３と接合されている。すなわち、半導体チップ１の裏面１ｂは、焼結接合材２と接合している。 The configuration of the power module (semiconductor device) 20 shown in FIG. 1 will be described. The power module 20 includes a semiconductor chip 1, and the semiconductor chip 1 includes an upper surface 1 a and a back surface (first bonding surface) 1 b that is the opposite surface. The semiconductor chip 1 is bonded to a ceramic substrate (wiring substrate) 3 via a sintered bonding material 2. That is, the back surface 1 b of the semiconductor chip 1 is bonded to the sintered bonding material 2.
　なお、半導体チップ１は、１７５℃以上の高温で動作可能なＳｉＣもしくはＧａＮからなることが好ましいが、例えばシリコンからなるものであってもよい。 The semiconductor chip 1 is preferably made of SiC or GaN that can operate at a high temperature of 175 ° C. or higher, but may be made of, for example, silicon.
　また、パワーモジュール２０は、半導体チップ１の上面１ａに設けられた電極１ｄと、セラミック基板３の上面（第２接合面）３ａの配線３ｃｃ（３ｃ）とを電気的に接続する導電性のワイヤ６と、セラミック基板３の配線３ｃｃと電気的に接続し、かつ外部に引き出される端子７とを有している。 Further, the power module 20 is a conductive wire that electrically connects the electrode 1d provided on the upper surface 1a of the semiconductor chip 1 and the wiring 3cc (3c) of the upper surface (second bonding surface) 3a of the ceramic substrate 3. 6 and a terminal 7 which is electrically connected to the wiring 3cc of the ceramic substrate 3 and is drawn to the outside.
　本実施の形態１のパワーモジュール２０では、図２に示すように、１枚のセラミック基板３上に、複数（例えば、３つ）の半導体チップ１が搭載されている。具体的には、セラミック基板３の上面３ａに設けられた配線３ｃｂ上に複数の半導体チップ１が搭載されている。 In the power module 20 of the first embodiment, as shown in FIG. 2, a plurality of (for example, three) semiconductor chips 1 are mounted on one ceramic substrate 3. Specifically, a plurality of semiconductor chips 1 are mounted on the wiring 3 cb provided on the upper surface 3 a of the ceramic substrate 3.
　また、図１に示すように、セラミック基板３の上面３ａの配線３ｃｃには、パワーモジュール２０の外部端子である複数の端子７が接続されている。 Further, as shown in FIG. 1, a plurality of terminals 7 that are external terminals of the power module 20 are connected to the wiring 3 cc on the upper surface 3 a of the ceramic substrate 3.
　そして、複数の半導体チップ１および複数の端子７が搭載されたセラミック基板３は、接合材（他の接合材であり、例えば、はんだ合金など）５を介してベース板（金属板）４に搭載されている。すなわち、ベース板４は、接合材５を介してセラミック基板３を支持している。 The ceramic substrate 3 on which the plurality of semiconductor chips 1 and the plurality of terminals 7 are mounted is mounted on a base plate (metal plate) 4 via a bonding material (another bonding material such as a solder alloy) 5. Has been. That is, the base plate 4 supports the ceramic substrate 3 via the bonding material 5.
　ここで、セラミック基板３は、その上面３ａに複数の配線（導体膜）３ｃが形成されている。図２に示すセラミック基板３では、上面３ａの中央部に導体膜である配線３ｃｂが配置され、また、配線３ｃｂの両側に、図１に示すワイヤ６が接続される配線（導体膜）３ｃａおよび配線（導体膜）３ｃｃが形成されており、一方、下面３ｂにも配線３ｃｄが形成されている。これらの配線３ｃａ、３ｃｂ、３ｃｃ、３ｃｄは、例えば、Ｃｕ（銅）やＡｌ（アルミニウム）などからなり、セラミック基板３は、窒化珪素やアルミナ、窒化アルミニウムなどからなる。そして、セラミック基板３の下面３ｂに形成された配線３ｃｄは、接合材５によってベース板４に接合されている。 Here, the ceramic substrate 3 has a plurality of wirings (conductor films) 3c formed on the upper surface 3a thereof. In the ceramic substrate 3 shown in FIG. 2, a wiring 3cb, which is a conductor film, is arranged at the center of the upper surface 3a, and the wiring (conductor film) 3ca to which the wires 6 shown in FIG. A wiring (conductor film) 3cc is formed, while a wiring 3cd is also formed on the lower surface 3b. These wirings 3ca, 3cb, 3cc, 3cd are made of, for example, Cu (copper) or Al (aluminum), and the ceramic substrate 3 is made of silicon nitride, alumina, aluminum nitride, or the like. The wiring 3 cd formed on the lower surface 3 b of the ceramic substrate 3 is bonded to the base plate 4 by the bonding material 5.
　また、図１に示すように、半導体チップ１の上面１ａには、例えばゲート用の電極１ｃが形成されており、セラミック基板３の配線３ｃａとワイヤ６を介して電気的に接続されている。さらに、半導体チップ１の上面１ａに形成された別の電極１ｄは、セラミック基板３の配線３ｃｃとワイヤ６を介して電気的に接続されている。 Further, as shown in FIG. 1, for example, a gate electrode 1 c is formed on the upper surface 1 a of the semiconductor chip 1 and is electrically connected to the wiring 3 ca of the ceramic substrate 3 via the wire 6. Furthermore, another electrode 1 d formed on the upper surface 1 a of the semiconductor chip 1 is electrically connected to the wiring 3 cc of the ceramic substrate 3 via the wire 6.
　また、外部端子である端子７は、その一端が、セラミック基板３の配線３ｃｃに接合されており、さらに他端がケース８の外部に引き出されている。また、ベース板４は、放熱用の金属板である。また、放熱板でもあるベース板４には、複数の半導体チップ１、複数のワイヤ６およびセラミック基板３を覆うケース８が設けられており、そのケース８内には封止用の樹脂１１が充填されている。つまり、複数の半導体チップ１、複数のワイヤ６およびセラミック基板３は、上記封止用の樹脂１１によって封止されている。樹脂１１としては、例えばゲル状の樹脂材を用いることが好ましい。 Further, one end of the terminal 7 which is an external terminal is joined to the wiring 3 cc of the ceramic substrate 3, and the other end is drawn out of the case 8. The base plate 4 is a metal plate for heat dissipation. The base plate 4 that is also a heat sink is provided with a case 8 that covers the plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3. The case 8 is filled with a sealing resin 11. Has been. That is, the plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3 are sealed with the sealing resin 11. As the resin 11, for example, a gel-like resin material is preferably used.
　また、複数のワイヤ６のそれぞれは、例えばＡｌ線またはＣｕ線などの金属線である。 Further, each of the plurality of wires 6 is a metal wire such as an Al wire or a Cu wire, for example.
　そして、本実施の形態１のパワーモジュール２０では、セラミック基板３の上面３ａに形成された配線３ｃａ、３ｃｂ、３ｃｃは、それぞれ電極として用いられる。また、焼結接合材２は、半導体チップ１とセラミック基板３との間に配置されて、半導体チップ１とセラミック基板３とを接合する部材であり、焼結接合を基本とする接合材料であることが望ましい。一方、接合材５は、セラミック基板３とベース板４との間に配置されて、セラミック基板３とベース板４とを接合する部材である。接合材５は、好ましくは、Ｓｎを主成分とするはんだ合金もしくはＰｂを主成分とするはんだ合金であり、例えば、Ｐｂ－Ｓｎ、Ｓｎ－Ｃｕ、Ｓｎ－Ｃｕ－Ｓｎ、Ｓｎ－Ｓｂ、Ｓｎ－Ａｇ－Ｃｕなどのはんだ合金である。ただし、Ｚｎ－Ａｌ、Ａｕ－Ｇｅ、Ａｕ－Ｓｉ、焼結Ａｇ、焼結Ｃｕなどの接合材であってもよい。ベース板４は、Ｃｕ、Ａｌ、あるいはＡｌ合金、Ｃｕ合金、ＡｌとＳｉＣの複合材、もしくはＭｇ（マグネシウム）とＳｉＣの複合材などであってもよい。
　次に、本実施の形態１のパワーモジュール２０の特徴部分について説明する。 And in the power module 20 of this Embodiment 1, wiring 3ca, 3cb, 3cc formed in the upper surface 3a of the ceramic substrate 3 is each used as an electrode. The sintered bonding material 2 is a member that is disposed between the semiconductor chip 1 and the ceramic substrate 3 and bonds the semiconductor chip 1 and the ceramic substrate 3 and is a bonding material based on sintered bonding. It is desirable. On the other hand, the bonding material 5 is a member that is disposed between the ceramic substrate 3 and the base plate 4 and bonds the ceramic substrate 3 and the base plate 4. The bonding material 5 is preferably a solder alloy containing Sn as a main component or a solder alloy containing Pb as a main component. For example, Pb—Sn, Sn—Cu, Sn—Cu—Sn, Sn—Sb, Sn— It is a solder alloy such as Ag-Cu. However, a bonding material such as Zn—Al, Au—Ge, Au—Si, sintered Ag, and sintered Cu may be used. The base plate 4 may be Cu, Al, Al alloy, Cu alloy, a composite material of Al and SiC, or a composite material of Mg (magnesium) and SiC.
Next, the characteristic part of the power module 20 of this Embodiment 1 is demonstrated.
　本実施の形態１のパワーモジュール２０に搭載された半導体チップ１は、高耐熱性のＳｉＣやＧａＮなどの材料からなるものであることが好ましく、半導体チップ１がＳｉＣやＧａＮなどの材料からなることにより、更なる動作温度の高温化にも対応することができる。 The semiconductor chip 1 mounted on the power module 20 of the first embodiment is preferably made of a material such as high heat-resistant SiC or GaN, and the semiconductor chip 1 is made of a material such as SiC or GaN. Therefore, it is possible to cope with further increase in operating temperature.
　また、本実施の形態１のパワーモジュール２０では、図３に示すように、半導体チップ１の焼結接合材２と接合する裏面（第１接合面）１ｂに、それぞれが球面状を成す複数の凸部９ａ（９）が形成されている。さらに、セラミック基板３の焼結接合材２と接合する上面（第２接合面）３ａの配線３ｃｂの表面に、同じくそれぞれ球面状の複数の凸部９ｂ（９）が形成されている。 Further, in the power module 20 of the first embodiment, as shown in FIG. 3, a plurality of spherical surfaces are formed on the back surface (first bonding surface) 1 b bonded to the sintered bonding material 2 of the semiconductor chip 1. Convex part 9a (9) is formed. Further, a plurality of spherical convex portions 9b (9) are formed on the surface of the wiring 3cb of the upper surface (second bonding surface) 3a to be bonded to the sintered bonding material 2 of the ceramic substrate 3, respectively.
　なお、複数の球面状の凸部９は、半導体チップ１の裏面１ｂもしくはセラミック基板３の上面３ａの配線３ｃｂのうちの少なくとも何れか一方に形成されていればよい。ただし、半導体チップ１の裏面１ｂとセラミック基板３の上面３ａの配線３ｃｂとの両者に設けられている方が効果が大きいため、本実施の形態１では、半導体チップ１の裏面１ｂとセラミック基板３の上面３ａの配線３ｃｂのそれぞれに、球面状の複数の凸部９が形成されている場合を説明する。 The plurality of spherical convex portions 9 only need to be formed on at least one of the back surface 1b of the semiconductor chip 1 or the wiring 3cb on the top surface 3a of the ceramic substrate 3. However, since it is more effective to be provided on both the back surface 1b of the semiconductor chip 1 and the wiring 3cb on the top surface 3a of the ceramic substrate 3, in the first embodiment, the back surface 1b of the semiconductor chip 1 and the ceramic substrate 3 A case where a plurality of spherical convex portions 9 are formed on each of the wirings 3cb on the upper surface 3a will be described.
　また、複数の球面状の凸部９のそれぞれは、図３および図４に示すように、略半球状に形成されている。 Further, each of the plurality of spherical convex portions 9 is formed in a substantially hemispherical shape as shown in FIGS.
　これにより、焼結接合材２における半導体チップ１やセラミック基板３との接合界面付近の焼結密度を高めて焼結接合材２による接合信頼性を高めることができる。 Thereby, the sintering density of the sintered bonding material 2 in the vicinity of the bonding interface with the semiconductor chip 1 and the ceramic substrate 3 can be increased, and the bonding reliability of the sintered bonding material 2 can be increased.
　なお、図３に示すような複数の球面状の凸部９が形成された構造を表現する場合、複数の凹凸部が形成されていると言う表現を用いてもよいことは言うまでもない。すなわち、それぞれ球面状の複数の凸部９が設けられている場合には、隣接する凸部９間に隙間が形成されるため、この隙間を凹部と見立てることで、複数の凸部９を複数の凹凸部と表現することも可能である。 In addition, when expressing the structure in which the some spherical convex part 9 as shown in FIG. 3 was formed, it cannot be overemphasized that the expression said that the several uneven | corrugated part may be used. That is, when a plurality of spherical convex portions 9 are provided, a gap is formed between the adjacent convex portions 9, and the plurality of convex portions 9 can be formed by regarding the gap as a concave portion. It can also be expressed as an uneven portion.
　したがって、図３に示す構造に対しては、半導体チップ１の裏面１ｂおよびセラミック基板３の上面３ａの配線３ｃｂに、それぞれ複数の球面状の凹凸部（凸部９のこと）が形成されていると言うように表現してもよい。 Therefore, for the structure shown in FIG. 3, a plurality of spherical irregularities (protrusions 9) are formed on the back surface 1b of the semiconductor chip 1 and the wiring 3cb on the top surface 3a of the ceramic substrate 3, respectively. It may be expressed as
　ここで、本発明の課題を図５を用いて説明する。図５は比較例の焼結接合材によるチップ接合部の構造を示す拡大部分断面図である。 Here, the problem of the present invention will be described with reference to FIG. FIG. 5 is an enlarged partial cross-sectional view showing a structure of a chip joint portion made of a sintered joining material of a comparative example.
　焼結接合では、一般的にナノメートルオーダーの金属微粒子を使用するが、接合時にはナノメートルオーダーの微粒子がそのまま焼結するのではなく、まず微粒子同士で焼結が進むため、接合後には様々なサイズの粒子で接合部および接合界面は構成されている。その中で本発明者が図５に示すような焼結接合材２によるチップ接合構造を検討した結果、接合後の焼結接合材２には、直径１μｍ～１０μｍの粒子が多数を占めることを見出した。 In sintering joining, metal particles of nanometer order are generally used, but at the time of joining, nanometer order fine particles are not sintered as they are. The joint and the joint interface are composed of the size particles. Among them, as a result of studying the chip joint structure by the sintered joining material 2 as shown in FIG. 5, the present inventor has found that the sintered joining material 2 after joining has a large number of particles having a diameter of 1 μm to 10 μm. I found it.
　なお、接合後の形状は粒子の表面積が小さくなるほうがエネルギー的に安定なため、球体が結合したような形状となる。 In addition, since the shape after joining is more stable in terms of energy as the particle surface area becomes smaller, it becomes a shape in which spheres are combined.
　図５の比較例に示すように、焼結接合材２による半導体チップ１とセラミック基板３との接合において、セラミック基板３の上面３ａの全面が平坦なモジュール構造の場合、半導体チップ１の接合時に、直径１μｍ～１０μｍの粒子が形成されるため半導体チップ１やセラミック基板３との接合界面では粒子の焼結密度が低くなる。すると、焼結密度が低い接合界面部分は他の部分と比較して強度が低くなるため脆性的に破壊されてしまい、焼結接合材２と半導体チップ１との間の接合界面や焼結接合材２とセラミック基板３との間の接合界面で剥離が発生し、この剥離によって半導体装置の信頼性が低下するという課題が発生する。 As shown in the comparative example of FIG. 5, when the semiconductor chip 1 and the ceramic substrate 3 are bonded with the sintered bonding material 2, when the entire upper surface 3 a of the ceramic substrate 3 has a flat module structure, Since particles having a diameter of 1 μm to 10 μm are formed, the sintered density of the particles becomes low at the bonding interface with the semiconductor chip 1 and the ceramic substrate 3. As a result, the joint interface portion having a low sintered density is brittlely broken because the strength is lower than the other portions, and the joint interface between the sintered joint material 2 and the semiconductor chip 1 or the sintered joint is destroyed. Peeling occurs at the bonding interface between the material 2 and the ceramic substrate 3, and this peeling causes a problem that the reliability of the semiconductor device decreases.
　そこで、本発明者は、半導体装置の組立てプロセスを増加させることなく、焼結接合材２の接合界面の高信頼化を実現可能なパワーモジュールの構造について検討した。その結果、図３に示すように、半導体チップ１の裏面１ｂやセラミック基板３の上面３ａの配線３ｃｂに、それぞれ球面状を成す複数の凸部９を設けることで、焼結接合材２の接合界面近傍の焼結密度を高められることを見出した。すなわち、焼結接合材２の接合界面近傍の焼結密度を高めることで、焼結接合材２の接合界面での剥離の発生を低減して、接合界面における接合信頼性を向上できることを見出した。 Therefore, the present inventor examined the structure of the power module that can realize the high reliability of the bonding interface of the sintered bonding material 2 without increasing the assembly process of the semiconductor device. As a result, as shown in FIG. 3, a plurality of convex portions 9 each having a spherical shape are provided on the back surface 1 b of the semiconductor chip 1 and the wiring 3 cb on the upper surface 3 a of the ceramic substrate 3. It has been found that the sintered density in the vicinity of the interface can be increased. That is, it has been found that by increasing the sintering density in the vicinity of the bonding interface of the sintered bonding material 2, it is possible to reduce the occurrence of peeling at the bonding interface of the sintered bonding material 2 and to improve the bonding reliability at the bonding interface. .
　詳細には、図３に示すように、半導体チップ１の裏面１ｂやセラミック基板３の上面３ａの配線３ｃｂに、それぞれ球面状を成す複数の凸部９を設けることにより、隣接する球面状の凸部９間の隙間に焼結接合材２の一部（粒子）を入り込ませることができる。これにより、焼結接合材２の半導体チップ１との接合境界部２ａを含む第１接合部２ｂ、および焼結接合材２のセラミック基板３との接合境界部２ｃを含む第２接合部２ｄのそれぞれの焼結密度を、焼結接合材２における第１接合部２ｂおよび第２接合部２ｄを除く部分、すなわち焼結接合材２の厚さ方向における中央部２ｅ付近の焼結密度より大きく（高く）することができる。つまり、焼結接合材２の厚さ方向（半導体チップ１の厚さ方向と同方向）に沿って切断した断面視において、第１接合部２ｂおよび第２接合部２ｄのそれぞれの焼結密度を、第１接合部２ｂと第２接合部２ｄの間に位置する中央部２ｅの焼結密度より大きく（高く）することができる。 Specifically, as shown in FIG. 3, a plurality of spherical convex portions 9 are respectively provided on the back surface 1 b of the semiconductor chip 1 and the wiring 3 cb on the upper surface 3 a of the ceramic substrate 3, so that adjacent spherical convex portions are provided. Part (particles) of the sintered bonding material 2 can be inserted into the gap between the portions 9. Accordingly, the first bonding portion 2b including the bonding boundary portion 2a of the sintered bonding material 2 with the semiconductor chip 1 and the second bonding portion 2d including the bonding boundary portion 2c of the sintered bonding material 2 with the ceramic substrate 3 are obtained. Each sintered density is larger than the sintered density in the sintered joint material 2 excluding the first joint portion 2b and the second joint portion 2d, that is, in the vicinity of the central portion 2e in the thickness direction of the sintered joint material 2 ( Can be high). That is, in the cross-sectional view cut along the thickness direction of the sintered bonding material 2 (the same direction as the thickness direction of the semiconductor chip 1), the sintering density of each of the first bonding portion 2b and the second bonding portion 2d is determined. The sintering density of the central portion 2e located between the first joint portion 2b and the second joint portion 2d can be made larger (higher).
　このように焼結接合材２における半導体チップ１やセラミック基板３との接合界面近傍の焼結密度を大きくする（高める）ことができるため、接合界面で破壊することなく高い信頼性を得ることができる。言い換えれば、焼結接合材２における半導体チップ１やセラミック基板３との接合界面で発生する剥離を抑制または防止することができる。 As described above, since the sintered density in the vicinity of the bonding interface between the semiconductor chip 1 and the ceramic substrate 3 in the sintered bonding material 2 can be increased (increased), high reliability can be obtained without breaking at the bonding interface. it can. In other words, it is possible to suppress or prevent the peeling that occurs at the bonding interface between the sintered bonding material 2 and the semiconductor chip 1 or the ceramic substrate 3.
　また、応力が集中し易い箇所となる焼結接合材２の接合界面近傍に複数の球面形状の凸部９を設けたことにより、低高温の温度変化などによって接合界面近傍に付与される応力を分散させることができ、焼結接合材２による接合部の接合信頼性をさらに高めることができる。 Further, by providing a plurality of spherical convex portions 9 in the vicinity of the bonding interface of the sintered bonding material 2 where stress is likely to concentrate, the stress applied to the vicinity of the bonding interface due to temperature changes at low and high temperatures, etc. It is possible to disperse, and it is possible to further increase the bonding reliability of the bonded portion by the sintered bonding material 2.
　これにより、焼結接合材２によって半導体チップ１やセラミック基板３が接合されたパワーモジュール（半導体装置）２０の信頼性を高めることができる。また、高耐熱性を有するパワーモジュール（半導体装置）２０の構造を実現することができる。 Thereby, the reliability of the power module (semiconductor device) 20 in which the semiconductor chip 1 and the ceramic substrate 3 are joined by the sintered joining material 2 can be improved. Moreover, the structure of the power module (semiconductor device) 20 having high heat resistance can be realized.
　また、焼結接合材２を用いた接合部の接合信頼性が高められることで、低温と高温の環境が繰り返される温度サイクルなどの温度負荷に対しても大きな耐性を有することができる。 In addition, since the bonding reliability of the bonded portion using the sintered bonding material 2 is enhanced, it can have a great resistance against a temperature load such as a temperature cycle in which a low temperature environment and a high temperature environment are repeated.
　なお、複数の球面状の凸部９それぞれの球面の大きさは、図４に示すように、その曲率半径Ｒが０．５μｍ～５μｍであり、好ましくは３μｍ程度である。すなわち、形成される焼結接合材２の粒子の直径は、約６μｍ程度であるため、この接合後の粒子の大きさと同程度の曲率半径Ｒが３μｍ程度の球面が好ましく、種々のばらつきを考慮すると、曲率半径Ｒが０．５μｍ～５μｍ程度の球面の凸部９が複数設けられていることが好適である。複数の凸部９それぞれの球面の曲率半径Ｒを０．５μｍ～５μｍにすることで、接合後の焼結接合材２の一部（粒子）を、隣接する凸部９間の隙間に入り込ませることができ、焼結接合材２の接合界面近傍の密度を高めることができる。 As shown in FIG. 4, the spherical radius of each of the plurality of spherical convex portions 9 has a radius of curvature R of 0.5 μm to 5 μm, preferably about 3 μm. That is, since the diameter of the particles of the sintered joining material 2 to be formed is about 6 μm, a spherical surface having a radius of curvature R of about 3 μm, which is the same as the size of the particles after joining, is preferable, and various variations are considered. Then, it is preferable that a plurality of spherical convex portions 9 having a radius of curvature R of about 0.5 μm to 5 μm are provided. By setting the radius of curvature R of the spherical surface of each of the plurality of convex portions 9 to 0.5 μm to 5 μm, a part (particle) of the sintered bonding material 2 after joining can enter the gap between the adjacent convex portions 9. It is possible to increase the density in the vicinity of the bonding interface of the sintered bonding material 2.
　また、焼結接合材２は、ＣｕもしくはＡｇを主成分とする材料からなることが好ましい。そして、セラミック基板３の表裏面に形成された導体膜である配線３ｃは、銅箔から形成されていることが好適である。 Further, the sintered bonding material 2 is preferably made of a material mainly composed of Cu or Ag. And it is suitable for the wiring 3c which is a conductor film formed in the front and back of the ceramic substrate 3 to be formed from copper foil.
　なお、半導体チップ１の裏面１ｂに形成された複数の凸部９ａ（９）は、例えば無電解めっきによって形成することが可能である。一方、セラミック基板３の上面３ａの配線３ｃｂに形成された複数の凸部９ｂ（９）は、同じく無電解めっきによって形成することが可能であり、あるいは図示しない金型を用いてこの金型を押し付けてセラミック基板３の上面３ａの配線３ｃｂに転写する方法でも形成することが可能である。 In addition, the some convex part 9a (9) formed in the back surface 1b of the semiconductor chip 1 can be formed by electroless plating, for example. On the other hand, the plurality of convex portions 9b (9) formed on the wiring 3cb on the upper surface 3a of the ceramic substrate 3 can be similarly formed by electroless plating, or the mold can be formed using a mold (not shown). It can also be formed by a method of pressing and transferring to the wiring 3cb on the upper surface 3a of the ceramic substrate 3.
　また、複数の凸部９は、焼結接合材２がＣｕからなる場合には、ＣｕもしくはＮｉによって形成されることが好ましい。一方、焼結接合材２がＡｇからなる場合には、複数の凸部９は、Ａｇ、ＡｕもしくはＰｄによって形成されることが好ましい。
　次に、本実施の形態１のパワーモジュール２０の組立てについて説明する。 Moreover, when the sintered joining material 2 consists of Cu, it is preferable that the some convex part 9 is formed of Cu or Ni. On the other hand, when the sintered bonding material 2 is made of Ag, the plurality of convex portions 9 are preferably formed of Ag, Au, or Pd.
Next, assembly of the power module 20 of the first embodiment will be described.
　まず、図３に示すように、裏面１ｂに複数の球面状の凸部９ａ（９）が形成された半導体チップ１を準備し、さらに、上面３ａの配線３ｃｂに複数の球面状の凸部９ｂ（９）が形成されたセラミック基板３を準備する。 First, as shown in FIG. 3, a semiconductor chip 1 having a plurality of spherical convex portions 9a (9) formed on the back surface 1b is prepared, and a plurality of spherical convex portions 9b are formed on the wiring 3cb on the upper surface 3a. A ceramic substrate 3 on which (9) is formed is prepared.
　次に、セラミック基板３の上面３ａの配線３ｃｂに、微小な金属粉末を溶剤でペースト化した焼結接合用のペースト材を塗布する。塗布後、上記ペースト材を介して半導体チップ１を搭載して、２００～４００℃に加熱することで上記溶剤を揮発させ、同時に加圧することにより、焼結が進行して接合が達成される。すなわち、半導体チップ１とセラミック基板３とが焼結接合材２によって接合される。接合後は、金属粒子は、バルク金属へと変化すると同時に、接合界面では金属結合により接合が行われるため、焼結接合材２の接合部は非常に高い耐熱性と信頼性を有する。 Next, a paste material for sintering joining obtained by pasting a minute metal powder with a solvent is applied to the wiring 3cb on the upper surface 3a of the ceramic substrate 3. After the application, the semiconductor chip 1 is mounted via the paste material, and the solvent is volatilized by heating to 200 to 400 ° C., and simultaneously pressurizing, whereby the sintering progresses to achieve bonding. That is, the semiconductor chip 1 and the ceramic substrate 3 are joined by the sintered joining material 2. After the joining, the metal particles change into a bulk metal, and at the same time, joining is performed by metal bonding at the joining interface. Therefore, the joined portion of the sintered joining material 2 has very high heat resistance and reliability.
　次に、ベース板４上に、はんだ合金からなる接合材（他の接合材）５を介してセラミック基板３を配置し、接合材５を加熱溶融してセラミック基板３とベース板（金属板）４とを接合する。ベース板４は放熱用の板材である。 Next, the ceramic substrate 3 is disposed on the base plate 4 via a bonding material (other bonding material) 5 made of a solder alloy, the bonding material 5 is heated and melted, and the ceramic substrate 3 and the base plate (metal plate). 4 is joined. The base plate 4 is a plate material for heat dissipation.
　この時、例えば、リフロー炉などで加圧を行うとともに３００℃以上の加熱を加えることで、接合材５を溶融してセラミック基板３とベース板４とを接合する。これにより、図１に示すモジュール構造におけるセラミック基板３とベース板４とのはんだ接合を完了する。このように接合材５として、はんだ合金を採用することにより、リフロー炉を用いて容易にセラミック基板３とベース板４の接合を行うことができる。 At this time, for example, by applying pressure in a reflow furnace or the like and heating at 300 ° C. or higher, the bonding material 5 is melted and the ceramic substrate 3 and the base plate 4 are bonded. Thereby, the solder joint between the ceramic substrate 3 and the base plate 4 in the module structure shown in FIG. 1 is completed. Thus, by using a solder alloy as the bonding material 5, the ceramic substrate 3 and the base plate 4 can be easily bonded using a reflow furnace.
　次に、図１に示すように、半導体チップ１の電極１ｃとセラミック基板３の配線３ｃａとをワイヤ６によって電気的に接続する。さらに、半導体チップ１の電極１ｄとセラミック基板３の配線３ｃｃとをワイヤ６によって電気的に接続する。また、外部端子となる端子７をセラミック基板３の配線３ｃｃに接続する。 Next, as shown in FIG. 1, the electrode 1 c of the semiconductor chip 1 and the wiring 3 ca of the ceramic substrate 3 are electrically connected by a wire 6. Further, the electrode 1 d of the semiconductor chip 1 and the wiring 3 cc of the ceramic substrate 3 are electrically connected by the wire 6. Further, the terminal 7 serving as an external terminal is connected to the wiring 3 cc of the ceramic substrate 3.
　次に、端子７の一部が露出するように、かつセラミック基板３や半導体チップ１および複数のワイヤ６を覆うように、ベース板４にケース８を取り付ける。 Next, the case 8 is attached to the base plate 4 so that a part of the terminal 7 is exposed and the ceramic substrate 3, the semiconductor chip 1, and the plurality of wires 6 are covered.
　次に、ケース８内の空間に封止用の樹脂１１を充填し、この樹脂１１を硬化させてパワーモジュール２０の組立てを完了する。 Next, the resin 11 for sealing is filled in the space in the case 8 and the resin 11 is cured to complete the assembly of the power module 20.
　以上のように、本実施の形態１のパワーモジュール２０によれば、パワーモジュール２０の組立てプロセスを増加させることなく、焼結接合材２の接合界面の信頼性を向上させることができる。
　（実施の形態２） As described above, according to the power module 20 of the first embodiment, the reliability of the bonding interface of the sintered bonding material 2 can be improved without increasing the assembly process of the power module 20.
(Embodiment 2)
　図６は本発明の実施の形態２の半導体装置（パワーモジュール）の焼結接合材によるチップ接合部の構造の一例を示す拡大部分断面図である。本実施の形態２は、半導体チップ１の裏面（第１接合面）１ｂもしくはセラミック基板３の上面（第２接合面）３ａの配線３ｃｂのうちの少なくとも何れか一方に、複数の球面状の凸部９に加えて、さらに複数の球面状の凹部１０が形成されている構造を説明するものである。本実施の形態２ではその一例として、半導体チップ１の裏面１ｂとセラミック基板３の上面３ａの配線３ｃｂの両方に複数の球面状の凸部９と凹部１０が形成されている場合を説明する。 FIG. 6 is an enlarged partial cross-sectional view showing an example of the structure of a chip joint portion made of a sintered joint material of the semiconductor device (power module) according to the second embodiment of the present invention. In the second embodiment, a plurality of spherical protrusions are formed on at least one of the back surface (first bonding surface) 1b of the semiconductor chip 1 and the wiring 3cb of the upper surface (second bonding surface) 3a of the ceramic substrate 3. A structure in which a plurality of spherical recesses 10 are formed in addition to the portion 9 will be described. In the second embodiment, as an example, a case where a plurality of spherical convex portions 9 and concave portions 10 are formed on both the back surface 1b of the semiconductor chip 1 and the wiring 3cb on the top surface 3a of the ceramic substrate 3 will be described.
　すなわち、半導体チップ１の裏面１ｂに、複数の球面状の凸部９ａと複数の球面状の凹部１０ａとが、それぞれ隣り合う配列で形成されている。一方、セラミック基板３の上面３ａの配線３ｃｂにも複数の球面状の凸部９ｂと複数の球面状の凹部１０ｂとが、それぞれ隣り合う配列で形成されている。 That is, a plurality of spherical convex portions 9a and a plurality of spherical concave portions 10a are formed on the back surface 1b of the semiconductor chip 1 in an adjacent arrangement. On the other hand, a plurality of spherical convex portions 9b and a plurality of spherical concave portions 10b are formed in the wiring 3cb on the upper surface 3a of the ceramic substrate 3 in an adjacent arrangement.
　別の表現で言えば、半導体チップ１の裏面１ｂとセラミック基板３の上面３ａの配線３ｃｂのそれぞれに、球面状を成す複数の凹凸部（凹部１０と凸部９）が形成されている。そして、上記複数の球面状の凹凸部の球面の大きさは、実施の形態１と同様に、球面の曲率半径Ｒが０．５μｍ～５μｍであり、好ましくは３μｍ程度である。 In other words, a plurality of concave and convex portions (concave portions 10 and convex portions 9) having a spherical shape are formed on the back surface 1b of the semiconductor chip 1 and the wiring 3cb on the top surface 3a of the ceramic substrate 3, respectively. As for the size of the spherical surface of the plurality of spherical irregularities, the radius of curvature R of the spherical surface is 0.5 μm to 5 μm, preferably about 3 μm, as in the first embodiment.
　さらに、上記凹凸部は、実施の形態１と同様の材料によって形成されることが好ましい。すなわち、複数の上記凹凸部は、焼結接合材２がＣｕからなる場合には、ＣｕもしくはＮｉによって形成されることが好ましい。一方、焼結接合材２がＡｇからなる場合には、上記複数の凹凸部は、Ａｇ、ＡｕもしくはＰｄによって形成されることが好ましい。なお、上記複数の凹凸部についての形成方法は、半導体チップ１の裏面１ｂに形成する場合、裏面１ｂにＣｕなどの導体膜を形成した後、エッチングによって凹凸部を形成することが好ましい。一方、セラミック基板３の上面３ａの配線３ｃｂに上記複数の凹凸部を形成する場合には、セラミック基板３の上面３ａにＣｕなどの導体膜を形成した後、エッチングによって凹凸部を形成してもよいし、上面３ａにＣｕなどの導体膜を形成した後、図示しない金型を押し付けて表面に転写して上記複数の凹凸部を形成してもよい。 Furthermore, the concavo-convex part is preferably formed of the same material as in the first embodiment. That is, when the sintered joining material 2 is made of Cu, the plurality of uneven portions are preferably formed of Cu or Ni. On the other hand, when the sintered joining material 2 is made of Ag, the plurality of uneven portions is preferably formed of Ag, Au, or Pd. In addition, when forming on the back surface 1b of the semiconductor chip 1, it is preferable to form the uneven portions by etching after forming a conductor film such as Cu on the back surface 1b. On the other hand, when the plurality of uneven portions are formed on the wiring 3cb on the upper surface 3a of the ceramic substrate 3, the uneven portions may be formed by etching after forming a conductor film such as Cu on the upper surface 3a of the ceramic substrate 3. Alternatively, after forming a conductor film such as Cu on the upper surface 3a, a mold (not shown) may be pressed and transferred to the surface to form the plurality of uneven portions.
　以上のように、半導体チップ１の裏面１ｂとセラミック基板３の上面３ａの配線３ｃｂのそれぞれに、球面状を成す複数の凹凸部（凹部１０と凸部９）が形成されていることにより、焼結接合材２の接合界面近傍の焼結密度をさらに高めることができる。 As described above, a plurality of spherical concave and convex portions (the concave portions 10 and the convex portions 9) are formed on each of the back surface 1b of the semiconductor chip 1 and the wiring 3cb on the top surface 3a of the ceramic substrate 3, so that The sintered density in the vicinity of the bonding interface of the bonding material 2 can be further increased.
　その際、凹部１０による凹曲面と凸部９による凸曲面があることにより、接合時に加圧を行っても、焼結用のペースト材の保持力を向上させることができ、ペースト材の流れ出しを防止することができる。その結果、実施の形態１の構造と比べてさらに加圧の値を大きくすることができ、焼結接合材２の全体的な焼結密度を大きくする（高める）ことができる。したがって、実施の形態１の構造に比べてさらに信頼性が高いパワーモジュール２０（図１参照）の構造を実現することができる。
　（実施の形態３） At that time, the concave curved surface by the concave portion 10 and the convex curved surface by the convex portion 9 can improve the holding power of the paste material for sintering even when pressure is applied at the time of joining. Can be prevented. As a result, the value of pressurization can be further increased as compared with the structure of the first embodiment, and the overall sintered density of the sintered bonding material 2 can be increased (increased). Therefore, the structure of the power module 20 (see FIG. 1) having higher reliability than the structure of the first embodiment can be realized.
(Embodiment 3)
　図７は本発明の実施の形態３の半導体装置（パワーモジュール）の焼結接合材によるチップ接合部の構造の一例を示す拡大部分断面図である。 FIG. 7 is an enlarged partial cross-sectional view showing an example of the structure of a chip joint portion made of a sintered joint material of the semiconductor device (power module) according to the third embodiment of the present invention.
　本実施の形態３は、半導体チップ１の裏面（第１接合面）１ｂに複数の球面状の凸部９ａ（９）が形成され、かつセラミック基板３の上面（第２接合面）３ａの配線３ｃｂには、複数の球面状の凸部９と複数の球面状の凹部１０が形成されている構造を説明するものである。 In the third embodiment, a plurality of spherical convex portions 9a (9) are formed on the back surface (first bonding surface) 1b of the semiconductor chip 1, and wiring on the upper surface (second bonding surface) 3a of the ceramic substrate 3 is performed. 3cb describes a structure in which a plurality of spherical convex portions 9 and a plurality of spherical concave portions 10 are formed.
　すなわち、半導体チップ１の裏面１ｂに、複数の球面状の凸部９ａが形成され、一方、セラミック基板３の上面３ａの配線３ｃｂには、複数の球面状の凸部９ｂと複数の球面状の凹部１０ｂとが、それぞれ隣り合う配列で形成されている。つまり、セラミック基板３の上面３ａの配線３ｃｂには、球面状を成す複数の凹凸部（凹部１０と凸部９）が形成されている。 That is, a plurality of spherical projections 9a are formed on the back surface 1b of the semiconductor chip 1, while a plurality of spherical projections 9b and a plurality of spherical projections are formed on the wiring 3cb on the upper surface 3a of the ceramic substrate 3. The recesses 10b are formed in an array adjacent to each other. That is, the wiring 3cb on the upper surface 3a of the ceramic substrate 3 is formed with a plurality of concave and convex portions (concave portions 10 and convex portions 9) having a spherical shape.
　このように半導体チップ１の裏面１ｂに凸部９による凸曲面があり、セラミック基板３の上面３ａの配線３ｃｂに凹部１０による凹曲面と凸部９による凸曲面とがある構造においても、実施の形態１および２と同様の効果を得ることができる。なお、実施の形態３の凸部９や凹部１０における材料や形成方法についても、実施の形態２と同様であり、金型を押し付けて表面に転写する、もしくはめっきで形成するなどの任意の方法で形成することが可能である。
　＜適用例＞ Thus, even in a structure in which the back surface 1b of the semiconductor chip 1 has a convex curved surface by the convex portion 9, and the wiring 3cb of the upper surface 3a of the ceramic substrate 3 has a concave curved surface by the concave portion 10 and a convex curved surface by the convex portion 9. The same effects as those of Embodiments 1 and 2 can be obtained. Note that the material and the forming method of the convex portion 9 and the concave portion 10 of the third embodiment are the same as those of the second embodiment, and any method such as pressing a mold and transferring it to the surface or forming by plating. It is possible to form with.
<Application example>
　図８は図１に示す半導体装置が搭載された鉄道車両の一例を示す部分側面図、図９は図８に示す鉄道車両に設置されたインバータの内部構造の一例を示す平面図である。 8 is a partial side view showing an example of a railway vehicle on which the semiconductor device shown in FIG. 1 is mounted, and FIG. 9 is a plan view showing an example of an internal structure of an inverter installed in the railway vehicle shown in FIG.
　本適用例では、上記実施の形態１～３のパワーモジュール２０を搭載した鉄道車両について説明する。図８に示す鉄道車両２１は、例えば、図１に示すパワーモジュール２０が搭載されたものであり、車両本体２６と、パワーモジュール２０と、パワーモジュール２０を支持する実装部材と、集電装置であるパンタグラフ２２と、インバータ２３とを備えている。そして、パワーモジュール２０は、車両本体２６の下部に設置されたインバータ２３に搭載されている。 In this application example, a railway vehicle equipped with the power module 20 of the first to third embodiments will be described. A railway vehicle 21 shown in FIG. 8 is mounted with, for example, the power module 20 shown in FIG. 1, and includes a vehicle main body 26, a power module 20, a mounting member that supports the power module 20, and a current collector. A pantograph 22 and an inverter 23 are provided. The power module 20 is mounted on an inverter 23 installed at the lower part of the vehicle body 26.
　図９に示すように、インバータ２３の内部では、プリント基板（実装部材）２５上に複数のパワーモジュール２０が搭載され、さらにこれらのパワーモジュール２０を冷却する冷却装置２４が搭載されている。図１に示す本実施の形態のパワーモジュール２０では、半導体チップ１からの発熱量が多い。したがって、複数のパワーモジュール２０を冷却してインバータ２３の内部を冷却可能なように冷却装置２４が取り付けられている。 As shown in FIG. 9, inside the inverter 23, a plurality of power modules 20 are mounted on a printed circuit board (mounting member) 25, and a cooling device 24 for cooling these power modules 20 is mounted. In the power module 20 of the present embodiment shown in FIG. 1, the amount of heat generated from the semiconductor chip 1 is large. Therefore, the cooling device 24 is attached so that the plurality of power modules 20 can be cooled to cool the inside of the inverter 23.
　これにより、鉄道車両２１において、図１に示すモジュールの接合構造が用いられた複数のパワーモジュール２０を搭載したインバータ２３が設けられていることにより、インバータ２３内が高温環境となった場合であっても、インバータ２３およびそれが設けられた鉄道車両２１の信頼性を高めることができる。すなわち、高温環境下での動作安定性と高電流負荷にも耐え得るパワーモジュール２０およびこれを用いたインバータシステムを実現することができる。 As a result, in the railway vehicle 21, the inverter 23 equipped with the plurality of power modules 20 using the module joining structure shown in FIG. Even so, the reliability of the inverter 23 and the railway vehicle 21 provided with the inverter 23 can be improved. That is, it is possible to realize a power module 20 that can withstand operation stability under a high temperature environment and a high current load, and an inverter system using the same.
　本適用例（パワーモジュール２０を鉄道車両２１に適用した例）によれば、パワーモジュール２０においてチップ接合に焼結接合材２を用い、かつ半導体チップ１の裏面１ｂやセラミック基板３の上面３ａの配線３ｃｂに、複数の球面状の凸部９または凹凸部が形成されたことにより、焼結接合材２による接合部の接合信頼性を高めることができる。 According to this application example (an example in which the power module 20 is applied to the railway vehicle 21), the sintered bonding material 2 is used for chip bonding in the power module 20, and the back surface 1 b of the semiconductor chip 1 and the upper surface 3 a of the ceramic substrate 3 are used. By forming the plurality of spherical convex portions 9 or the concave and convex portions on the wiring 3cb, the bonding reliability of the bonding portion by the sintered bonding material 2 can be enhanced.
　これにより、高温環境に対する耐性が高くなるため、インバータ２３に対する冷却機能を弱めることができる。したがって、図９に示す冷却装置２４の小型化を図ることが可能になり、インバータ２３の小型化を図ることも可能になる。 As a result, the resistance to the high temperature environment is increased, so that the cooling function for the inverter 23 can be weakened. Therefore, the cooling device 24 shown in FIG. 9 can be downsized, and the inverter 23 can be downsized.
　さらに、鉄道車両２１に適用されたパワーモジュール２０において、高温、低温の環境に対する耐性が高められ、温度サイクルなどの温度負荷に対するパワーモジュール２０の耐性を高めることができる。 Furthermore, in the power module 20 applied to the railway vehicle 21, resistance to high temperature and low temperature environments can be enhanced, and resistance of the power module 20 to a temperature load such as a temperature cycle can be increased.
　次に、上記実施の形態のパワーモジュール２０を搭載した自動車について説明する。図１０は図１に示す半導体装置が搭載された自動車の一例を示す斜視図である。 Next, an automobile equipped with the power module 20 of the above embodiment will be described. FIG. 10 is a perspective view showing an example of an automobile on which the semiconductor device shown in FIG. 1 is mounted.
　図１０に示す自動車２７は、例えば、図１に示すパワーモジュール２０が搭載されたものであり、車体２８と、タイヤ２９と、パワーモジュール２０と、パワーモジュール２０を支持する実装部材である実装ユニット３０と、を備えている。 10 includes, for example, the power module 20 illustrated in FIG. 1, and includes a vehicle body 28, a tire 29, the power module 20, and a mounting unit that is a mounting member that supports the power module 20. 30.
　自動車２７では、パワーモジュール２０は、実装ユニット３０に含まれるインバータに搭載されているが、実装ユニット３０は、例えば、エンジン制御ユニット等であり、その場合、実装ユニット３０はエンジンの近傍に配置されている。この場合には、実装ユニット３０は、高温環境下での使用となり、これにより、パワーモジュール２０も高温状態となる。 In the automobile 27, the power module 20 is mounted on an inverter included in the mounting unit 30. The mounting unit 30 is, for example, an engine control unit, and in this case, the mounting unit 30 is disposed in the vicinity of the engine. ing. In this case, the mounting unit 30 is used in a high temperature environment, and the power module 20 is also in a high temperature state.
　しかしながら、自動車２７において、図１に示すモジュールの接合構造が用いられた複数のパワーモジュール２０を搭載したインバータが設けられていることにより、実装ユニット３０が高温環境となった場合であっても、自動車２７の信頼性を高めることができる。つまり自動車２７においても、高温環境下での動作安定性と高電流負荷にも耐え得るパワーモジュール２０およびこれを用いたインバータシステムを実現することができる。 However, even if the mounting unit 30 is in a high temperature environment by providing an inverter in which a plurality of power modules 20 using the module joining structure shown in FIG. The reliability of the automobile 27 can be improved. That is, in the automobile 27 as well, it is possible to realize the power module 20 that can withstand operation stability under a high temperature environment and a high current load, and an inverter system using the same.
　また、本適用例（パワーモジュール２０を自動車２７に適用した例）によれば、鉄道車両２１への適用例と同様に、パワーモジュール２０においてチップ接合に焼結接合材２を用い、かつ半導体チップ１の裏面１ｂやセラミック基板３の上面３ａに、複数の球面状の凸部９または凹凸部が形成されたことにより、焼結接合材２による接合部の接合信頼性を高めることができる。 Further, according to the present application example (example in which the power module 20 is applied to the automobile 27), the sintered bonding material 2 is used for chip bonding in the power module 20, as in the application example to the railcar 21, and the semiconductor chip. Since the plurality of spherical convex portions 9 or the concave and convex portions are formed on the back surface 1b of 1 and the upper surface 3a of the ceramic substrate 3, the bonding reliability of the bonding portion by the sintered bonding material 2 can be improved.
　また、自動車２７に適用されたパワーモジュール２０においても、高温、低温の環境に対する耐性が高められ、温度サイクルなどの温度負荷に対するパワーモジュール２０の耐性を高めることができる。 Also in the power module 20 applied to the automobile 27, resistance to high and low temperature environments can be increased, and the resistance of the power module 20 to temperature loads such as temperature cycles can be increased.
　以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.
　なお、本発明は上記した実施の形態に限定されるものではなく、様々な変形例が含まれる。例えば、上記した実施の形態は本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。 Note that the present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described.
　また、ある実施の形態の構成の一部を他の実施の形態の構成に置き換えることが可能であり、また、ある実施の形態の構成に他の実施の形態の構成を加えることも可能である。また、各実施の形態の構成の一部について、他の構成の追加、削除、置換をすることが可能である。なお、図面に記載した各部材や相対的なサイズは、本発明を分かりやすく説明するため簡素化・理想化しており、実装上はより複雑な形状となる。 Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment. In addition, each member and relative size which were described in drawing are simplified and idealized in order to demonstrate this invention clearly, and it becomes a more complicated shape on mounting.
　　１　半導体チップ
　１ａ　上面
　１ｂ　裏面（第１接合面）
　１ｃ、１ｄ　電極
　　２　焼結接合材
　２ａ　接合境界部
　２ｂ　第１接合部
　２ｃ　接合境界部
　２ｄ　第２接合部
　２ｅ　中央部
　３　セラミック基板（配線基板）
　３ａ　上面（第２接合面）
　３ｂ　下面
３ｃ、３ｃａ、３ｃｂ、３ｃｃ、 ３ｃｄ　配線（導体膜）
　　４　ベース板（金属板）
　　５　接合材（他の接合材）
　　６　ワイヤ
　　７　端子
　　８　ケース
　　９、９ａ、９ｂ　凸部
　１０、１０ａ、１０ｂ　凹部
　１１　樹脂
　２０　パワーモジュール（半導体装置）
　２１　鉄道車両
　２２　パンタグラフ
　２３　インバータ
　２４　冷却装置
　２５　プリント基板
　２６　車両本体
　２７　自動車
　２８　車体
　２９　タイヤ
　３０　実装ユニット DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a Upper surface 1b Back surface (1st junction surface)
1c, 1d electrode 2 sintered joint material 2a joint boundary 2b first joint 2c joint boundary 2d second joint 2e central part 3 ceramic substrate (wiring substrate)
3a Upper surface (second bonding surface)
3b Lower surface 3c, 3ca, 3cb, 3cc, 3cd Wiring (conductor film)
4 Base plate (metal plate)
5 Bonding materials (other bonding materials)
6 Wire 7 Terminal 8 Case 9, 9a, 9b Convex 10, 10a, 10b Concave 11 Resin 20 Power module (semiconductor device)
DESCRIPTION OF SYMBOLS 21 Rail vehicle 22 Pantograph 23 Inverter 24 Cooling device 25 Printed circuit board 26 Vehicle main body 27 Car 28 Car body 29 Tire 30 Mounting unit

Claims (15)

  1. 　半導体チップと、
    　前記半導体チップを支持し、前記半導体チップと電気的に接続された配線基板と、
    　前記半導体チップと前記配線基板との間に配置され、前記半導体チップと前記配線基板とを接合する焼結接合材と、
    　を有し、
    　前記半導体チップの前記焼結接合材と接合する第１接合面もしくは前記配線基板の前記焼結接合材と接合する第２接合面のうちの少なくとも何れか一方に、複数の球面状の凸部が形成されている、半導体装置。     A semiconductor chip;
    A wiring board that supports the semiconductor chip and is electrically connected to the semiconductor chip;
    A sintered bonding material that is disposed between the semiconductor chip and the wiring board and bonds the semiconductor chip and the wiring board;
    Have
    A plurality of spherical convex portions are provided on at least one of the first joint surface to be joined to the sintered joint material of the semiconductor chip or the second joint surface to be joined to the sintered joint material of the wiring board. A semiconductor device is formed.
  2. 　請求項１記載の半導体装置において、
    　前記焼結接合材は、その厚さ方向において、前記焼結接合材の前記半導体チップとの接合境界部を含む第１接合部、前記焼結接合材の前記配線基板との接合境界部を含む第２接合部、前記第１接合部と前記第２接合部の間に位置する中央部を有し、
    　前記厚さ方向に沿って切断した断面視において、前記第１および第２接合部のそれぞれの焼結密度は、前記中央部の焼結密度より大きい、半導体装置。     The semiconductor device according to claim 1,
    The sintered bonding material includes, in the thickness direction, a first bonding portion including a bonding boundary portion between the sintered bonding material and the semiconductor chip, and a bonding boundary portion between the sintered bonding material and the wiring substrate. A second joint, having a central portion located between the first joint and the second joint;
    In a cross-sectional view cut along the thickness direction, each of the first and second joint portions has a sintered density higher than that of the central portion.
  3. 　請求項２記載の半導体装置において、
    　前記複数の球面状の凸部それぞれの球面の曲率半径は、０．５μｍ～５μｍである、半導体装置。     The semiconductor device according to claim 2,
    A semiconductor device, wherein a radius of curvature of a spherical surface of each of the plurality of spherical convex portions is 0.5 μm to 5 μm.
  4. 　請求項１記載の半導体装置において、
    　前記半導体チップの前記第１接合面もしくは前記配線基板の前記第２接合面のうちの少なくとも何れか一方に、複数の球面状の凹部が形成されている、半導体装置。     The semiconductor device according to claim 1,
    A semiconductor device, wherein a plurality of spherical recesses are formed on at least one of the first bonding surface of the semiconductor chip and the second bonding surface of the wiring board.
  5. 　請求項１記載の半導体装置において、
    　前記焼結接合材は、ＣｕもしくはＡｇを主成分とする材料からなる、半導体装置。     The semiconductor device according to claim 1,
    The sintered bonding material is a semiconductor device made of a material mainly composed of Cu or Ag.
  6. 　請求項１記載の半導体装置において、
    　前記半導体チップは、ＳｉＣもしくはＧａＮからなる、半導体装置。     The semiconductor device according to claim 1,
    The semiconductor chip is a semiconductor device made of SiC or GaN.
  7. 　請求項１記載の半導体装置において、
    　鉄道の車両に設けられたインバータに搭載されている、半導体装置。     The semiconductor device according to claim 1,
    A semiconductor device mounted on an inverter provided in a railway vehicle.
  8. 　請求項１記載の半導体装置において、
    　自動車の車体に設けられたインバータに搭載されている、半導体装置。     The semiconductor device according to claim 1,
    A semiconductor device mounted on an inverter provided in the body of an automobile.
  9. 　半導体チップと、
    　前記半導体チップを支持し、前記半導体チップと電気的に接続され、表裏両面に導体膜が形成された配線基板と、
    　前記半導体チップと前記配線基板との間に配置され、前記半導体チップと前記配線基板とを接合する焼結接合材と、
    　前記半導体チップおよび前記配線基板が搭載された金属板と、
    　前記配線基板と前記金属板との間に配置され、前記配線基板と前記金属板とを接合する他の接合材と、
    　を有し、
    　前記半導体チップの前記焼結接合材と接合する第１接合面および前記導体膜の前記焼結接合材と接合する第２接合面に、複数の球面状の凹凸部が形成されている、半導体装置。     A semiconductor chip;
    A wiring board that supports the semiconductor chip, is electrically connected to the semiconductor chip, and has a conductor film formed on both front and back surfaces;
    A sintered bonding material that is disposed between the semiconductor chip and the wiring board and bonds the semiconductor chip and the wiring board;
    A metal plate on which the semiconductor chip and the wiring board are mounted;
    Another bonding material that is disposed between the wiring board and the metal plate and bonds the wiring board and the metal plate;
    Have
    A plurality of spherical concave and convex portions are formed on a first joint surface of the semiconductor chip joined to the sintered joint material and a second joint surface of the conductor film joined to the sintered joint material. .
  10. 　請求項９記載の半導体装置において、
    　前記焼結接合材は、その厚さ方向において、前記焼結接合材の前記半導体チップとの接合境界部を含む第１接合部、前記焼結接合材の前記配線基板との接合境界部を含む第２接合部、前記第１接合部と前記第２接合部の間に位置する中央部を有し、
    　前記厚さ方向に沿って切断した断面視において、前記第１および第２接合部のそれぞれの焼結密度は、前記中央部の焼結密度より大きい、半導体装置。     The semiconductor device according to claim 9.
    The sintered bonding material includes, in the thickness direction, a first bonding portion including a bonding boundary portion between the sintered bonding material and the semiconductor chip, and a bonding boundary portion between the sintered bonding material and the wiring substrate. A second joint, having a central portion located between the first joint and the second joint;
    In a cross-sectional view cut along the thickness direction, each of the first and second joint portions has a sintered density higher than that of the central portion.
  11. 　請求項１０記載の半導体装置において、
    　前記複数の球面状の凹凸部それぞれの球面の曲率半径は、０．５μｍ～５μｍである、半導体装置。     The semiconductor device according to claim 10.
    A semiconductor device, wherein a radius of curvature of a spherical surface of each of the plurality of spherical irregularities is 0.5 μm to 5 μm.
  12. 　請求項９記載の半導体装置において、
    　前記他の接合材は、はんだ合金からなる、半導体装置。     The semiconductor device according to claim 9.
    The other joining material is a semiconductor device made of a solder alloy.
  13. 　請求項９記載の半導体装置において、
    　前記焼結接合材は、ＣｕもしくはＡｇを主成分とする材料からなる、半導体装置。     The semiconductor device according to claim 9.
    The sintered bonding material is a semiconductor device made of a material mainly composed of Cu or Ag.
  14. 　請求項９記載の半導体装置において、
    　鉄道の車両に設けられたインバータに搭載されている、半導体装置。     The semiconductor device according to claim 9.
    A semiconductor device mounted on an inverter provided in a railway vehicle.
  15. 　請求項９記載の半導体装置において、
    　自動車の車体に設けられたインバータに搭載されている、半導体装置。     The semiconductor device according to claim 9.
    A semiconductor device mounted on an inverter provided in the body of an automobile.
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