WO2018166538A1

WO2018166538A1 - Continuous time δ-σ analogue-to-digital converter and coefficient calibration method therefor, and storage medium

Info

Publication number: WO2018166538A1
Application number: PCT/CN2018/079809
Authority: WO
Inventors: 郑雷; 李超; 严喻冬
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2017-03-17
Filing date: 2018-03-21
Publication date: 2018-09-20
Also published as: CN108631785A; CN108631785B

Abstract

Disclosed are a continuous time analogue-to-digital converter and a coefficient calibration method therefor, and a storage medium. A continuous time Δ-Σ analogue-to-digital converter at least comprises: a voltage comparator and a digital controller. The method comprises: in a pre-set calibration mode, a voltage comparator comparing a pre-acquired first calibration signal with a pre-set reference signal; and according to a comparison result of the first calibration signal and the reference signal, and a pre-set calibration parameter, a digital controller calibrating all pre-set coefficients, which are to be calibrated, in a continuous time Δ-Σ analogue-to-digital converter, wherein the comparison result comprises a high-level signal or a low-level signal.

Description

Continuous time Δ-Σ analog-to-digital converter and coefficient calibration method thereof, storage medium

Cross-reference to related applications

The present application is based on a Chinese patent application filed on Jan. 17, 2017, the entire disclosure of which is hereby incorporated by reference.

Technical field

The present application relates to the field of integrated circuit design technology, and in particular, to a continuous time delta-sigma analog-to-digital converter, a coefficient calibration method thereof, and a storage medium.

Background technique

In many electronic applications, analog input signals are converted to digital output signals. For example, in a precision measurement system, an electronic device is provided with one or more sensors for measurement, and these sensors can generate an analog signal that is then provided to an input of an analog to digital converter (ADC) to produce a digital The signal is output for further processing.

In wireless communication applications, the delta-sigma analog-to-digital converter includes a continuous-time delta-sigma analog-to-digital converter and a discrete-time delta-sigma analog-to-digital converter. Compared to discrete-time delta-sigma analog-to-digital converters, continuous-time delta-sigma analog-to-digital converters can digitize their input analog signals with lower sampling resolution and higher sampling rates. Specifically, the circuit structure of the continuous-time delta-sigma analog-to-digital converter is composed of an analog circuit and a digital circuit, wherein the analog circuit portion is a delta-sigma modulator, which is much larger than the sampling rate of the Nyquist frequency. The analog signal is sampled and quantized; the digital circuit is a digital filter that filters out most of the quantization noise after shaping by the delta-sigma modulator to achieve low-pass filtering and reduced sampling. The continuous-time delta-sigma analog-to-digital converter has anti-aliasing characteristics and is insensitive to process variations, which is beneficial for RF receiver applications. Compared to discrete-time delta-sigma analog-to-digital converters, continuous-time delta-sigma analog-to-digital converters reduce the bandwidth requirements of op amps and have a prominent performance in the measurement of DC and low-frequency signals.

Calibration of the coefficients is essential during the application of continuous-time delta-sigma analog-to-digital converters. This is because, during the application of the continuous-time Δ-Σ analog-to-digital converter, there are cases where the process deviation and the operating conditions change. At this time, the coefficient of the continuous-time Δ-Σ analog-to-digital converter will be deviated, and the coefficient will be deviated. This will result in inaccuracies in the transfer function and noise function in the continuous-time delta-sigma analog-to-digital converter, which not only affects the conversion effect and stability of the continuous-time delta-sigma analog-to-digital converter, but also reduces the continuous time Δ- Conversion accuracy of the Σ analog-to-digital converter.

The coefficient calibration methods in the existing continuous-time delta-sigma analog-to-digital converter mainly include the following two types:

First, use a separate calibration circuit to calibrate the resistor-capacitor product of the continuous-time Δ-Σ analog-to-digital converter and the current of the feedback digital-to-analog converter (DAC) in the continuous-time Δ-Σ analog-to-digital converter. The resistance or capacitance calibration control word controls the main circuit in the continuous-time delta-sigma analog-to-digital converter, and finally supplies the calibrated current to the feedback digital-to-analog converter in the continuous-time delta-sigma analog-to-digital converter; Second, use an independent circuit to monitor the output signal of the continuous-time delta-sigma analog-to-digital converter, and adjust the coefficients of the continuous-time delta-sigma analog-to-digital converter according to the frequency response.

In the process of implementing the present application, the inventors found that at least the following problems exist in the prior art:

The current coefficient calibration method for continuous-time delta-sigma analog-to-digital converters requires a calibration circuit independent of the continuous-time delta-sigma analog-to-digital converter, and the deviation and continuous-time Δ-Σ analog-to-digital conversion of the devices in the calibration circuit The main circuit of the device is not completely consistent, which not only makes the calibration accuracy of the coefficients of the continuous-time delta-sigma analog-to-digital converter difficult to guarantee, but also increases the production cost of the continuous-time delta-sigma analog-to-digital converter.

Summary of the invention

In order to solve the existing technical problems, the embodiments of the present application are expected to provide a continuous time Δ-Σ analog-to-digital converter and a coefficient calibration method thereof, which can not only improve the calibration precision of the coefficients of the continuous-time Δ-Σ analog-to-digital converter, Moreover, the production cost of the continuous-time delta-sigma analog-to-digital converter can be saved.

To achieve the above objective, the technical solution of the embodiment of the present application is implemented as follows:

The embodiment of the present application provides a coefficient calibration method for a continuous time delta-sigma analog-to-digital converter, the continuous time delta-sigma analog-to-digital converter including at least: a voltage comparator and a digital controller; the method includes:

The voltage comparator compares the pre-acquired first calibration signal with the reference signal when in a preset calibration mode;

The digital controller calibrates all the to-be-calibrated coefficients preset in the continuous-time delta-sigma analog-to-digital converter according to a comparison result of the first calibration signal and the reference signal and a preset calibration parameter; The comparison result includes: a high level signal or a low level signal.

In the above embodiment, the continuous time delta-sigma analog-to-digital converter further includes: a digital-to-analog converter and a current integrator connected in series with the digital-to-analog converter; the voltage comparator is pre-acquired Before the calibration signal is compared with the reference signal, the method further includes:

The current integrator receives a pre-generated second calibration signal through the digital to analog converter, and converts the second calibration signal into the first calibration signal;

The current integrator transmits the first calibration signal to the voltage comparator through the digital to analog converter.

In the above embodiment, the digital controller selects all the presets in the continuous time Δ-Σ analog-to-digital converter according to the comparison result of the first calibration signal and the reference signal and the preset calibration parameter. The calibration coefficients to be calibrated include:

The digital controller determines a target comparison result according to a comparison result of the first calibration signal and the reference signal;

The digital controller determines, according to the target comparison result and the calibration parameter, a calibration control word corresponding to all the to-be-calibrated coefficients; wherein the calibration parameters include: an initial calibration control word and an adjustment step;

The digital controller calibrates all of the coefficients to be calibrated based on the target comparison result and the calibration control word.

In the above embodiment, the digital controller determines the target comparison result according to the comparison result of the first calibration signal and the reference signal, and includes:

When the comparison result of the first calibration signal and the reference signal is plural, the digital controller counts the number of occurrences of the high level signal and the low level signal in all comparison results;

Determining that the high level signal is the target comparison result when the number of occurrences of the high level signal is greater than the number of occurrences of the low level signal;

When the number of occurrences of the high level signal is less than the number of occurrences of the low level signal, the low level signal is determined to be the target comparison result.

In the above embodiment, the digital controller determines, according to the target comparison result and the calibration parameter, a calibration control word corresponding to all the to-be-calibrated coefficients, including:

When the target comparison result is the high level signal, the digital controller reduces the initial calibration control word by the adjustment step size;

The digital controller increases the initial calibration control word by the adjustment step size when the target comparison result is the low level signal.

In the above embodiment, the digital controller calibrates all the coefficients to be calibrated according to the target comparison result and the calibration control word, including:

When the target comparison result is the high level signal, the digital controller reduces all the calibration coefficients to the calibration control word;

When the target comparison result is the low level signal, the digital controller increases all the calibration coefficients to the calibration control word.

The embodiment of the present application further provides a continuous time delta-sigma analog-to-digital converter, where the continuous-time delta-sigma analog-to-digital converter includes at least: a voltage comparator and a digital controller;

The voltage comparator is configured to compare the pre-acquired first calibration signal with the reference signal when in a preset calibration mode;

The digital controller is configured to compare all the to-be-calibrated coefficients preset in the continuous-time Δ-Σ analog-to-digital converter according to a comparison result of the first calibration signal and the reference signal and a preset calibration parameter Performing calibration; wherein the comparison result includes: a high level signal or a low level signal.

In the above embodiment, the continuous-time delta-sigma analog-to-digital converter further includes: a digital-to-analog converter and a current integrator connected in series with the digital-to-analog converter; wherein

The current integrator configured to receive a pre-generated second calibration signal by the digital to analog converter, to convert the second calibration signal to the first calibration signal; to pass the digital to analog converter A first calibration signal is sent to the voltage comparator.

In the above embodiment, the digital controller includes: a determining unit and a calibration unit; wherein

The determining unit is configured to determine a target comparison result according to the comparison result of the first calibration signal and the reference signal; the digital controller determines, according to the target comparison result and the calibration parameter, all the to-be-calibrated coefficients Calibrating a control word; wherein the calibration parameters include: an initial calibration control word and an adjustment step size;

The calibration unit is configured to calibrate all of the coefficients to be calibrated based on the target comparison result and the calibration control word.

In the above embodiment, the determining unit includes: a statistical subunit and a determining subunit; wherein

The statistical subunit is configured to count, when the comparison result of the first calibration signal and the reference signal is multiple, the number of occurrences of the high level signal and the low level signal in all comparison results;

The determining subunit is configured to determine that the high level signal is the target comparison result when the number of occurrences of the high level signal is greater than the number of occurrences of the low level signal; When the number of occurrences of the signal is less than the number of occurrences of the low level signal, the low level signal is determined to be the target comparison result.

In the above embodiment, the determining unit is configured to reduce the initial calibration control word by the adjustment step when the target comparison result is the high level signal; when the target comparison result is The initial calibration control word is increased by the adjustment step size when the low level signal is present.

In the above embodiment, the calibration unit is configured to reduce all the to-be-calibrated coefficients by the calibration control word when the target comparison result is the high-level signal; when the target comparison result is the When the signal is low, all the coefficients to be calibrated are increased by the calibration control word.

Embodiments of the present application provide a computer storage medium storing a computer program configured to perform a coefficient calibration method of the continuous time delta-sigma analog-to-digital converter.

It can be seen that, in the technical solution of the present application, the continuous-time delta-sigma analog-to-digital converter includes at least: a voltage comparator and a digital controller; in a preset calibration mode, the voltage comparator first obtains the first obtained in advance The calibration signal is compared with the reference signal, and then the digital controller calibrates all the to-be-calibrated coefficients preset in the continuous-time delta-sigma analog-to-digital converter according to the comparison result of the first calibration signal and the reference signal and the preset calibration parameters. . That is to say, in the technical solution of the present application, all the presets to be set in the continuous-time delta-sigma analog-to-digital converter can be realized by the voltage comparator and the digital controller in the continuous-time delta-sigma analog-to-digital converter. The coefficients are calibrated. In the prior art, a calibration circuit independent of the continuous-time delta-sigma analog-to-digital converter is required to calibrate all the parameters to be calibrated preset in the continuous-time delta-sigma analog-to-digital converter. Therefore, compared with the prior art, the continuous-time delta-sigma analog-to-digital converter provided by the embodiments of the present application can not only improve the calibration precision of the coefficients of the continuous-time delta-sigma analog-to-digital converter, but also save the continuous time Δ- The production cost of the modulo analog-to-digital converter; and the technical solution of the embodiment of the present application is simple, convenient, popular, and applicable.

DRAWINGS

1 is a schematic diagram showing an implementation flow of a coefficient calibration method for a continuous time delta-sigma analog-to-digital converter according to an embodiment of the present application;

2 is a schematic structural diagram of a circuit of a continuous time delta-sigma analog-to-digital converter according to an embodiment of the present application;

3 is a schematic structural diagram of a circuit of a bias circuit according to an embodiment of the present application;

4 is a schematic flow chart of a method for implementing calibration of all coefficients to be calibrated by a digital controller according to an embodiment of the present application;

5 is a schematic diagram of a first component structure of a continuous time delta-sigma analog-to-digital converter according to an embodiment of the present application;

FIG. 6 is a schematic diagram showing a second composition structure of a continuous time delta-sigma analog-to-digital converter according to an embodiment of the present application.

detailed description

The technical solutions in the embodiments of the present application will be clearly and completely described in the following with reference to the accompanying drawings in the embodiments.

FIG. 1 is a schematic flow chart showing the implementation of a coefficient calibration method for a continuous time delta-sigma analog-to-digital converter according to an embodiment of the present application. As shown in FIG. 1, the coefficient calibration method of the continuous time delta-sigma analog-to-digital converter may include the following steps:

Step 101: When in a preset calibration mode, the voltage comparator compares the pre-acquired first calibration signal with the reference signal.

In a particular embodiment of the present application, the continuous time delta-sigma analog-to-digital converter can be in two preset operating modes: a calibration mode and a non-calibration mode. Specifically, when the continuous-time delta-sigma analog-to-digital converter is in the calibration mode, the continuous-time delta-sigma analog-to-digital converter can be implemented in the continuous-time delta-sigma analog-to-digital converter by the voltage comparator and the digital controller. Set all the parameters to be calibrated for calibration; when the continuous time Δ-Σ analog-to-digital converter is in non-calibration mode, the continuous-time Δ-Σ analog-to-digital converter can pass through the digital-to-analog converter, voltage comparator and digital-to-analog The current integrator connected in series with the converter implements analog-to-digital conversion of the analog signal of the input continuous-time delta-sigma analog-to-digital converter.

2 is a schematic diagram showing the circuit structure of a continuous-time delta-sigma analog-to-digital converter in an embodiment of the present application. As shown in FIG. 2, the continuous-time delta-sigma analog-to-digital converter may include: a digital-to-analog converter DAC1, a digital-to-analog converter DAC2, a digital-to-analog converter DAC3, a voltage comparator, a digital controller, and a digital-to-analog converter, respectively. The DAC1 and the digital-to-analog converter DAC2 are connected in series with a current integrator AMP1 and a current integrator AMP2. When the continuous-time delta-sigma analog-to-digital converter is in the calibration mode, the digital-to-analog converter DAC2, the voltage comparator, the digital controller, and the current integrator AMP2 are in operation, and the digital-to-analog converter DAC1, the digital-to-analog converter DAC3, and Current integrator AMP1 is inactive; digital-to-analog converter DAC1, digital-to-analog converter DAC2, digital-to-analog converter DAC3, voltage comparator, current integrator when continuous-time delta-sigma analog-to-digital converter is in non-calibration mode Both AMP1 and current integrator AMP2 are in operation.

In a specific embodiment of the present application, the coefficient calibration principle of the continuous time delta-sigma analog-to-digital converter is consistent with the coefficient calibration principle of the existing continuous-time delta-sigma analog-to-digital converter, that is, when the continuous time Δ-Σ modulus When the converter is in the preset calibration mode, the continuous-time Δ-Σ analog-to-digital converter ensures that the product of the resistance and capacitance of each current integrator is constant, and the product of the current and resistance of each digital-to-analog converter is also guaranteed. constant.

Specifically, in the specific embodiment of the present application, when the continuous time delta-sigma analog-to-digital converter is in a preset calibration mode, the enable signal ccal_enb can control the digital-to-analog converter DAC1 and the current integrator AMP1 to be in an inoperative state. When the continuous time delta-sigma analog-to-digital converter is in the preset non-calibration mode, the enable signal ccal_enb can control the digital-to-analog converter DAC1 and the current integrator AMP1 to be in an active state. Specifically, the enable signal ccal_enb can control the switch S1 and the switch S2 between the current integrator AMP1 and the current integrator AMP2 to be turned on or off. When the enable signal ccal_enb is low, the enable signal ccal_enb controls the switch S1 and the switch S2 to be turned on; when the enable signal ccal_enb is high, the enable signal ccal_enb controls the switch S1 and the switch S2 to be turned off. Therefore, when the continuous-time delta-sigma analog-to-digital converter is in the preset calibration mode, the digital-to-analog converter DAC1 and the current integrator AMP1 are in an inoperative state; when the continuous-time delta-sigma analog-to-digital converter is in a preset non-position In the calibration mode, the digital-to-analog converter DAC1 and the current integrator AMP1 are in operation.

Specifically, in a specific embodiment of the present application, when the continuous time delta-sigma analog-to-digital converter is in a preset calibration mode, the enable signal dac2_en can control the digital-to-analog converter DAC2 to be in an active state; when continuous time Δ- When the Σ-analog converter is in the preset non-calibration mode, the enable signal dac2_en can control the digital-to-analog converter DAC2 to be inactive. When the enable signal dac2_en is high, the enable signal dac2_en controls the digital-to-analog converter DAC2 to be in an active state; when the enable signal dac2_en is low, the enable signal dac2_en controls the digital-to-analog converter DAC2 to be in an inoperative state. Therefore, when the continuous-time delta-sigma analog-to-digital converter is in the preset calibration mode, the digital-to-analog converter DAC2 is in an active state; when the continuous-time delta-sigma analog-to-digital converter is in a preset non-calibration mode, the digital-analog Converter DAC2 is in an inactive state.

Specifically, in a specific embodiment of the present application, when the continuous time delta-sigma analog-to-digital converter is in a preset calibration mode, the enable signal dac3_en can control the digital-to-analog converter DAC3 to be in an inoperative state; when the continuous time Δ - When the Σ-analog converter is in the pre-set non-calibration mode, the enable signal dac2_en can control the digital-to-analog converter DAC3 to be in operation. When the enable signal dac3_en is low, the enable signal dac3_en controls the digital-to-analog converter DAC3 to be inactive; when the enable signal dac3_en is high, the enable signal dac3_en controls the digital-to-analog converter DAC3 to be in an active state. Therefore, when the continuous-time delta-sigma analog-to-digital converter is in the preset calibration mode, the digital-to-analog converter DAC3 is in an inactive state; when the continuous-time delta-sigma analog-to-digital converter is in the preset non-calibration mode, the number The analog converter DAC3 is in operation.

In addition, in a specific embodiment of the present application, when the continuous time delta-sigma analog-to-digital converter is in a preset calibration mode, the enable signal ccal_enb can also control the positive output of the current integrator AMP2 and the positive of the voltage comparator. The input terminal is in a connected state; when the continuous time delta-sigma analog-to-digital converter is in a preset non-calibration mode, the enable signal ccal_enb can also control the negative output terminal of the current integrator AMP2 to be disconnected from the positive input terminal of the voltage comparator. Open state. Specifically, the enable signal ccal-enb can control the switch S5 between the negative output of the current integrator AMP2 and the positive input of the voltage comparator to be turned on or off. When the enable signal ccal_enb is low, the enable signal ccal_enb controls the switch S5 to be turned on; when the enable signal ccal_enb is high, the enable signal ccal_enb controls the switch S5 to be turned off. Therefore, when the continuous-time delta-sigma analog-to-digital converter is in a preset calibration mode, the negative output of the current integrator AMP2 is in communication with the positive input of the voltage comparator; when the continuous-time delta-sigma analog-to-digital converter When in the pre-set non-calibration mode, the negative output of the current integrator AMP2 is disconnected from the positive input of the voltage comparator.

Specifically, in a specific embodiment of the present application, when the continuous time delta-sigma analog-to-digital converter is in a preset calibration mode, the enable signal ccal_en can control the positive output of the current integrator AMP2 and the negative of the voltage comparator. The input terminal is in a connected state, and the reference voltage Vref is connected to the positive input terminal of the voltage comparator; when the continuous time delta-sigma analog-to-digital converter is in a preset non-calibration mode, the enable signal ccal_en can control the current integrator AMP2 The positive input is disconnected from the negative input of the voltage comparator, and the reference voltage Vref is not connected to the positive input of the voltage comparator. Specifically, the enable signal ccal_en can control whether the switch S3 between the positive output terminal of the current integrator AMP2 and the negative input terminal of the voltage comparator is turned on or off, and the enable signal ccal_en can control whether the reference voltage Vref is connected to the voltage comparator. Positive input. When the continuous time delta-sigma analog-to-digital converter is in the preset calibration mode, the enable signal ccal_en is high, the enable signal ccal_en controls the switch S3 to be turned off, and the enable signal ccal_en controls the switch S4 to be turned off; when the continuous time Δ- When the Σ-analog converter is in the preset non-calibration mode, the enable signal ccal_en is low, the enable signal ccal_en controls the switch S3 to be turned on, and the enable signal ccal_en controls the switch S4 to be turned on. Therefore, when the continuous-time delta-sigma analog-to-digital converter is in a preset calibration mode, the positive output terminal of the current integrator AMP2 is in communication with the negative input terminal of the voltage comparator, and the reference voltage Vref is connected to the voltage comparator. Positive input terminal; when the continuous time Δ-Σ analog-to-digital converter is in the preset non-calibration mode, the positive input terminal of the current integrator AMP2 is disconnected from the negative input terminal of the voltage comparator, and the reference voltage Vref is not connected. Enter the positive input of the voltage comparator.

Specifically, in a specific embodiment of the present application, when the continuous time delta-sigma analog-to-digital converter is in a preset calibration mode, the enable signal ccal_enb and the clock signal CLK can control the digital-to-analog converter DAC2 and the current integrator AMP2. In the connected state or the disconnected state; when the continuous time delta-sigma analog-to-digital converter is in the preset non-calibration mode, the enable signal ccal_enb can control the digital-to-analog converter DAC2 and the current integrator AMP2 to be in a continuous state. Specifically, the enable signal ccal-enb and the clock signal CLK can control the switches S10 and S11 between the digital-to-analog converter DAC2 and the current integrator AMP2 to be turned on or off. When the enable signal ccal_enb is low and the clock signal CLK is high, the enable signal ccal_enb and the clock signal CLK control the switches S10 and S11 are turned off, when the enable signal ccal_enb is low and the clock signal CLK is low The enable signal ccal_enb and the clock signal CLK control the switches S10 and S11 to be turned on; when the enable signal ccal_enb is at the high level, the enable signal ccal_enb controls the switches S10 and S11 to be turned off. Therefore, when the continuous-time delta-sigma analog-to-digital converter is in the preset calibration mode, the digital-to-analog converter DAC2 and the current integrator AMP2 are in a connected state or an off state; when the continuous-time delta-sigma analog-to-digital converter is in advance When the non-calibration mode is set, the digital-to-analog converter DAC2 and the current integrator AMP2 are always in communication.

Specifically, in a specific embodiment of the present application, after the current integrator AMP2 receives the pre-generated second calibration signal Iref_ccal through the digital-to-analog converter DAC2, the current integrator AMP2 can output the converted value at time T/2. The first calibration signal Voutp_amp2 to the voltage comparator, that is, the current integrator AMP2 is output after the T/2 duration is the first calibration signal Voutp_amp2. Specifically, in a specific embodiment of the present application, the expression of the first calibration signal Voutp_amp2 may be:

Voutp_amp2=(Iref_ccal×T)/(2×C2)+V _cm

Wherein Iref_ccal is the second calibration signal; T is the period of the clock signal CLK; C2 is the capacitance corresponding to the current integrator AMP2; and Vcm is the common mode voltage generated when the second calibration signal is generated.

Preferably, in a specific embodiment of the present application, the continuous-time delta-sigma analog-to-digital converter may further include: a bias circuit and a current mirror circuit; wherein the bias circuit may generate a current signal Iref in advance and input to The current mirror circuit outputs a second calibration signal Iref_ccal to the digital-to-analog converter DAC2 after mirroring the current signal Iref.

FIG. 3 is a schematic structural diagram of a circuit of a bias circuit according to an embodiment of the present application. As shown in FIG. 3, the bias circuit is composed of the following three parts: a current integrator, a field effect transistor, and a voltage dividing resistor string. For example, the bias circuit may include a current integrator AMP3, field effect transistors PM0, PM1, PM2, PM3, and a voltage dividing resistor string composed of R4, R5, and R6. In the above bias circuit, if the input terminal of the current integrator AMP3 is connected to the reference voltage source Vbg, the common mode voltage is between the resistors R4 and R5 in the bias circuit, and the reference voltage between the resistors R5 and R6 is The expression for generating the current signal Iref on the effect tube PM0 can be:

Iref_ccal=Vbg/(R4+R5+R6)

Wherein, Vbg is a preset reference voltage source; R4, R5 and R6 are three preset resistors; according to the above equation analysis, since the reference voltage source Vbg is a fixed value, the current signal Iref and the resistors R4, R5, and R6 The product of the sum is also a fixed value. When all the resistors in the continuous-time delta-sigma analog-to-digital converter are of the same type as the resistors R4, R5, and R6, it is possible to ensure the deviation of all resistors in the continuous-time delta-sigma analog-to-digital converter due to process and temperature. Consistent.

In a specific embodiment of the present application, the current mirror circuit can obtain the current signal Iref through the bias circuit, and then the current mirror circuit mirrors the current signal Iref, and outputs the second calibration signal Iref-_ccal expression:

Iref_ccal=(m×Vbg)/(R4+R5+R6)

Where m is the amplification factor of the current Iref preset in the current mirror circuit; Vbg is a reference voltage source preset in the bias circuit; and R4, R5, and R6 are three resistors preset in the bias circuit. Since the reference voltage source Vbg in the bias circuit is a preset value, the product of the current Iref in the bias circuit and the sum of the resistors R4, R5, and R6 is a constant value, that is, the current Iref is a function of the resistors R4, R5, and R6. And the same ratio is reversely changed. Therefore, the second calibration signal Iref_ccal after the current Iref is amplified by m times by the current mirror circuit also changes inversely with the sum of the resistors R4, R5, and R6, that is, the second calibration signal Iref_ccal is located therewith. The resistance of the circuit changes inversely in proportion. The current mirror circuit supplies the second calibration signal Iref_ccal to the digital-to-analog converter DAC1, the digital-to-analog converter DAC2, and the digital-to-analog converter DAC3 to ensure the current corresponding to each digital-to-analog converter in the continuous-time Δ-Σ analog-to-digital converter. The product of the resistance does not change.

According to the above analysis, when the continuous time Δ-Σ analog-to-digital converter is in the preset calibration mode, the current integrator AMP2 can receive the second calibration signal Iref_ccal generated by the bias circuit and the current mirror circuit through the digital-to-analog converter DAC2. After the T/2 duration, the first calibration signal Voutp_amp is output to the voltage comparator.

In a specific embodiment of the present application, the voltage comparator can compare the output signal of the current integrator with a preset reference signal that is input to the positive input of the voltage comparator when receiving the output signal of the current integrator, and Output the output comparison result to the digital controller.

In a specific embodiment of the present application, the voltage comparator may be on the falling edge of the preset clock signal CLK for the first calibration signal Voutp_amp2 output from the reference voltage Vref input from the negative input terminal and the current integrator AMP2 input from the positive input terminal. Compare at the moment and output the comparison result. When the first calibration signal Voutp_amp2 output by the current integrator AMP2 is smaller than the reference voltage Vref, the output of the voltage comparator can output a high level signal; when the first calibration signal Voutp_amp2 output by the current integrator AMP2 is greater than the reference voltage Vref, The output of the voltage comparator can output a low level signal.

Preferably, in the specific embodiment of the present application, when the voltage comparator compares the first calibration signal Voutp_amp2 outputted by the current integrator AMP2 with the reference voltage Vref, the preset reset clock signal CLKN can control the current integrator. AMP2 is active or not working. Specifically, the reset clock signal CLKN can control the switches S6, S7, S8, and S9 connected to the current integrator AMP2 to be turned on or off. When the reset clock signal CLKN is at a high level, the reset clock signal CLKN controls the switches S6, S7, S8, and S9 to be turned off; when the reset clock signal CLKN is at a low level, the reset clock signal CLKN controls the switches S6, S7, S8, and S9 to be turned on. Therefore, when the reset clock signal CLKN is at a high level, the reset clock signal CLK controls the current integrator AMP2 to be in an inoperative state; when the reset clock signal CLKN is at a low level, the reset clock signal CLK controls the current integrator AMP2 to be in an active state. The reset clock signal CLKN and the clock signal CLK do not overlap in phase, and the period of the reset clock signal CLKN and the clock signal CLK are the same.

Step 102: The digital controller calibrates all the to-be-calibrated coefficients preset in the continuous-time Δ-Σ analog-to-digital converter according to the comparison result of the first calibration signal and the reference signal and the preset calibration parameter; wherein the comparison result includes : High level signal or low level signal.

In a specific embodiment of the present application, after the voltage comparator outputs the comparison result of the first calibration signal Voutp_amp2 and the reference voltage Vref, the digital controller may calibrate all the coefficients to be calibrated according to the comparison result of the voltage comparator output. FIG. 4 is a schematic flow chart of a method for implementing calibration of all coefficients to be calibrated by a digital controller according to an embodiment of the present application. As shown in FIG. 4, the method for the digital controller to calibrate all the coefficients to be calibrated may include the following steps:

Step 102a: The digital controller determines a target comparison result according to a comparison result of the first calibration signal and the reference signal.

In a specific embodiment of the present application, after the digital controller acquires the comparison result of the first calibration signal and the reference signal, the digital controller may first determine the target comparison result according to the comparison result of the first calibration signal and the reference signal. Preferably, the voltage comparator compares the first calibration signal Voutp_amp2 and the reference signal Vref at each falling edge of the clock signal CLK and outputs a plurality of comparison results. Therefore, the digital controller can determine the target comparison result based on the plurality of comparison results. Specifically, in a specific embodiment of the present application, when the comparison result of the first calibration signal Voutp_amp2 and the reference signal Vref is one, the digital controller may determine the calibration signal as the target calibration signal; when the first calibration signal Voutp_amp2 and When the comparison result of the reference signal Vref is plural, the digital controller may first count the number of occurrences of the high level signal and the low level signal in all the comparison results, when the number of occurrences of the high level signal is greater than the number of occurrences of the low level signal The digital controller determines that the high level signal is the target comparison result; when the number of occurrences of the high level signal is less than the number of occurrences of the low level signal, the digital controller determines that the low level signal is the target comparison result.

Preferably, in a specific embodiment of the present application, when the comparison result of the first calibration signal Voutp_amp2 and the reference voltage Vref is plural, the digital controller may first select a partial comparison result among all the comparison results, and then according to the selected Part of the comparison results determine the target comparison results. Specifically, the digital controller can select the comparison result of the intermediate position among all the comparison results to determine the target comparison result, which can ensure that the calibration control word output by the digital controller is more accurate. For example, the voltage comparator continuously outputs nine comparison results, and the digital controller may first select the third to seventh comparison results among the nine comparison results; and then determine the target comparison result based on the five comparison results.

Step 102b: The digital controller determines, according to the target comparison result and the calibration parameter, a calibration control word corresponding to all the coefficients to be calibrated.

In a specific embodiment of the present application, the calibration parameters preset in the digital controller are an initial calibration control word and an adjustment step size, and the digital controller according to the obtained target comparison result and a preset initial calibration control word and an adjustment step size It is possible to determine the output of the calibration control word.

Specifically, in a specific embodiment of the present application, the target comparison result determined by the digital controller includes: a high level signal or a low level signal. When the digital controller calculates the calibration control word for the first time, when the target comparison result is a high level signal, the digital controller reduces the initial calibration control word by a preset adjustment step; when the target comparison result is a low level signal The digital controller increases the initial calibration control word by a preset adjustment step size. When the digital controller calculates the calibration control word for the Kth time, when the target comparison result is a high level signal, the digital controller reduces the K-1 calculated calibration control word by a preset adjustment step; when the target compares When the result is a low level signal, the digital controller increases the calibration control word after the K-1th calculation by a preset adjustment step size.

Preferably, in a specific embodiment of the present application, the reference voltage Vref can also be connected to the negative input terminal of the voltage comparator through an adjustment circuit, and the first calibration signal Voutp_amp2 is connected to the positive input terminal of the voltage comparator. When the digital controller calculates the calibration control word for the first time, when the target comparison result is a high level signal, the digital controller increases the initial calibration control word by a preset adjustment step; when the target comparison result is a low level signal The digital controller reduces the initial calibration control word by a preset adjustment step size. When the digital controller calculates the calibration control word for the Kth time, when the target comparison result is a high level signal, the digital controller increases the K-1 calculated calibration control word by a preset adjustment step; when the target compares When the result is a low level signal, the digital controller reduces the calibration control word after the K-1th calculation by a preset adjustment step size; wherein K is a natural number greater than or equal to 2.

Specifically, in a specific embodiment of the present application, the calibration parameter may include: an initial calibration control word and an adjustment step; in addition, the target comparison result may be a high level signal, or the target comparison result may also be a low level signal. Wherein, when the target comparison result is a high level signal, the digital controller can reduce the initial calibration control word by an adjustment step size; when the target comparison result is a low level signal, the digital controller can increase the initial calibration control word Great adjustment step size. For example, assume that the initial calibration control word in the calibration parameters is: 10; the adjustment step size in the calibration parameters is: 2. When the target comparison result is a high level signal, the digital controller may reduce the initial calibration control word 10 by the adjustment step size 2, and obtain a calibration control word corresponding to all the coefficients to be calibrated to be 8; when the target comparison result is a low level signal When the digital controller can increase the initial calibration control word 10 by the adjustment step size 2, the calibration control word corresponding to all the coefficients to be calibrated is 12.

Preferably, in a specific embodiment of the present application, the reference voltage Vref can also be connected to the negative input terminal of the voltage comparator through an adjustment circuit, and the first calibration signal Voutp_amp2 is connected to the positive input terminal of the voltage comparator. When the target comparison result is a low level signal, the digital controller may reduce the initial calibration control word by an adjustment step; when the target comparison result is a high level signal, the digital controller may increase the initial calibration control word by an adjustment step. long.

Step 102c: The digital controller calibrates all the coefficients to be calibrated according to the target comparison result and the calibration control word.

In a specific embodiment of the present application, after the digital controller acquires the target comparison result and the calibration control word, the digital controller can calibrate all the coefficients to be calibrated according to the target comparison result and the calibration control word.

Specifically, in a specific embodiment of the present application, the calibration parameter may include: an initial calibration control word and an adjustment step; in addition, the target comparison result may be a high level signal, or the target comparison result may also be a low level signal. When the target comparison result is a low level signal, the digital controller can increase the capacitance C1 and C2 in the continuous time Δ-Σ analog-to-digital converter by the calibration control word; when the target comparison result is a high level signal, the digital control The capacitors C1 and C2 in the continuous-time delta-sigma analog-to-digital converter can be reduced by the calibration control word. For example, assume that the calibration control word obtained by step 102b is: 10. When the target comparison result is a high level signal, the digital controller can reduce the values of the capacitors C1 and C2 in the continuous-time delta-sigma analog-to-digital converter by 10, and when the target comparison result is a low-level signal, the digital control The value of capacitors C1 and C2 in the continuous-time delta-sigma analog-to-digital converter can be increased by 10. Among them, the capacitors C1 and C2 are adjustable capacitors, and the size of the capacitors C1 and C2 can be adjusted by turning on or off part of the switches of the capacitors C1 and C2 capacitor arrays.

Preferably, in a specific embodiment of the present application, the reference voltage Vref can also be connected to the negative input terminal of the voltage comparator through an adjustment circuit, and the first calibration signal Voutp_amp2 is connected to the positive input terminal of the voltage comparator. When the target comparison result is a high level signal, the digital controller can increase the capacitance C1 and C2 in the continuous time Δ-Σ analog-to-digital converter by the calibration control word; when the target comparison result is a low level signal, the digital controller The capacitors C1 and C2 in the continuous time delta-sigma analog-to-digital converter can be reduced by the calibration control word.

Preferably, in a specific embodiment of the present application, the calibration of the capacitors C1 and C2 ends when the current target comparison result is compared with the previous target comparison result. Wherein, the current target comparison result is changed compared with the previous target result, including the following two cases: the previous target comparison result is a high level signal, the current target comparison result is a low level signal; or, the previous target comparison result For the low level signal, the current target comparison result is a high level signal.

In a specific embodiment of the present application, when the calibration of the capacitors C1 and C2 ends, the first calibration signal Voutp_amp2 output by the current integrator AMP2 and the reference voltage Vref are infinitely close, and the first calibration signal Voutp_amp2 and the reference output by the current integrator AMP2 are determined. The voltages Vref are equal.

Preferably, in a specific embodiment of the present application, the expression that the reference voltage Vref can be obtained according to the bias circuit can be:

Vref=V _cm +(R5)/(R4+R5+R6)

Preferably, the expression of the calibration current Iref_ccal in step 101 is substituted into the expression of the first calibration signal Voutp_amp2, and the expression of the first calibration signal Voutp_amp2 after the substitution may be:

Voutp_amp2=(m×Vbg×T)/(2×C2×(R4+R5+R6))+V _cm

When the values of the first calibration signal and the reference signal are equal, it is obtained:

R5×C2=(m×Vbg×T)/2

According to the above formula, the first calibration signal Voutp_amp2 after calibration and the reference voltage Vref are equal, and the above formula is actually established. Since the amplification factor m, the reference voltage Vbg, and the period T of the clock signal CLK in the above equation are all set values in advance, it is ensured that the product of the resistor R5 and the capacitor C2 is a constant value. In the same continuous-time Δ-Σ analog-to-digital converter, the same type of resistance changes with the external factors such as process and temperature. If the product of resistor R5 and capacitor C2 is guaranteed to be constant, the resistor R2 can be guaranteed. The product of the capacitor C2 is constant, and the product of the capacitor C1 and the resistor R1 adjusted according to the same calibration control word is also ensured, thereby realizing the guarantee of each current integrator in the coefficient calibration of the continuous time Δ-Σ analog-to-digital converter. The corresponding resistance and capacitance products are unchanged for this purpose.

Through the above steps 101-103, when the continuous-time delta-sigma analog-to-digital converter is in the preset calibration mode, the continuous-time delta-sigma analog-to-digital converter can calibrate its own coefficients through its own related device without independent The calibration circuit calibrates its own coefficients. Therefore, the deviation of the calibration result caused by the inconsistency of the independent calibration circuit and the main circuit process or the working environment is avoided, not only the coefficient calibration of the continuous time delta-sigma analog-to-digital converter is realized, but also the calibration precision is improved, and the production is saved. cost.

A coefficient calibration method for a continuous-time delta-sigma analog-to-digital converter provided by an embodiment of the present application, the continuous-time delta-sigma analog-to-digital converter includes at least: a digital-to-analog converter, a voltage comparator, a digital controller, and a digital-to-analog converter a current integrator connected in series; in a preset calibration mode, the voltage comparator compares the pre-acquired first calibration signal with a preset reference signal, and then the digital controller according to the first calibration signal and the reference signal The comparison result and the preset calibration parameters calibrate all the parameters to be calibrated set in advance in the continuous time delta-sigma analog-to-digital converter. That is to say, the coefficient calibration method of the continuous-time delta-sigma analog-to-digital converter of the present application can realize the continuous time Δ-Σ by the voltage comparator and the digital controller in the continuous-time delta-sigma analog-to-digital converter. All the parameters to be calibrated preset in the analog-to-digital converter are calibrated. In the prior art, a calibration circuit independent of the continuous-time delta-sigma analog-to-digital converter is required to calibrate all the parameters to be calibrated preset in the continuous-time delta-sigma analog-to-digital converter. Therefore, compared with the prior art, the coefficient calibration method of the continuous time Δ-Σ analog-to-digital converter provided by the embodiment of the present application can not only improve the calibration precision of the coefficients of the continuous-time Δ-Σ analog-to-digital converter, but also saves The production cost of the continuous-time Δ-Σ analog-to-digital converter; and the technical solution of the embodiment of the present application is simple, convenient, popular, and applicable.

FIG. 5 is a schematic diagram of a first component structure of a continuous time delta-sigma analog-to-digital converter according to an embodiment of the present application. As shown in FIG. 5, the continuous time delta-sigma analog-to-digital converter includes at least: a voltage comparator 501 and a digital controller 502;

The voltage comparator 501 is configured to compare the pre-acquired first calibration signal with the reference signal when the calibration mode is set in advance;

The digital controller 502 is configured to: all presets to be set in the continuous time delta-sigma analog-to-digital converter according to a comparison result of the first calibration signal and the reference signal and a preset calibration parameter The coefficients are calibrated; wherein the comparison results include: a high level signal or a low level signal.

In an embodiment, the continuous-time delta-sigma analog-to-digital converter further includes: a digital-to-analog converter 503 and a current integrator 504 connected in series with the digital-to-analog converter 503;

The current integrator 504 is configured to receive a second calibration signal generated in advance by the digital-to-analog converter 503, convert the second calibration signal into the first calibration signal, and use the digital-to-analog conversion The 503 sends the first calibration signal to the voltage comparison 501.

FIG. 6 is a schematic diagram showing a second composition structure of a continuous time delta-sigma analog-to-digital converter according to an embodiment of the present application. As shown in FIG. 6, the digital controller 502 includes: a determining unit 5021 and a calibration unit 5022; wherein

The determining unit 5021 is configured to determine a target comparison result according to the first calibration signal and the reference signal comparison result, and to determine calibration control corresponding to all to-be-calibrated coefficients according to the target comparison result and the calibration parameter. a word; wherein the calibration parameters include: an initial calibration control word and an adjustment step size;

The calibration unit 5022 is configured to calibrate all of the coefficients to be calibrated based on the target comparison result and the calibration control word.

In an embodiment, the determining unit 5021 includes: a statistical subunit (not shown in the figure) and a determining subunit (not shown); wherein

The statistical subunit is configured to count the number of occurrences of the high level signal and the low level signal in all comparison result statistics when the comparison result of the first calibration signal and the reference signal is multiple ;

In an embodiment, the determining unit 5021 is configured to reduce the initial calibration control word by the adjustment step when the target comparison result is the high level signal; when the target comparison result When the low level signal is the low calibration signal, the initial calibration control word is increased by the adjustment step size.

In an embodiment, the calibration unit 5022 is configured to reduce all the to-be-calibrated coefficients by the calibration control word when the target comparison result is the high-level signal; when the target comparison result is When a low level signal is described, all of the coefficients to be calibrated are increased by the calibration control word.

The continuous time delta-sigma analog-to-digital converter provided by the embodiment of the present application includes at least: a voltage comparator and a digital controller; in a preset calibration mode, the voltage comparator will pre-acquire the first calibration signal and preset The reference signals are compared, and then the digital controller calibrates all the to-be-calibrated coefficients preset in the continuous-time delta-sigma analog-to-digital converter according to the comparison result of the first calibration signal and the reference signal and the preset calibration parameters. That is to say, the continuous-time delta-sigma analog-to-digital converter of the present application can realize the continuous-time delta-sigma analog-to-digital converter by the voltage comparator and the digital controller in the continuous-time delta-sigma analog-to-digital converter. All the calibration coefficients to be set in advance are calibrated. In the prior art, a calibration circuit independent of the continuous-time delta-sigma analog-to-digital converter is required to calibrate all the parameters to be calibrated preset in the continuous-time delta-sigma analog-to-digital converter. Therefore, compared with the prior art, the continuous-time delta-sigma analog-to-digital converter provided by the embodiments of the present application can not only improve the calibration precision of the coefficients of the continuous-time delta-sigma analog-to-digital converter, but also save the continuous time Δ- The production cost of the modulo analog-to-digital converter; and the technical solution of the embodiment of the present application is simple, convenient, popular, and applicable.

Those skilled in the art will appreciate that embodiments of the present application can be provided as a method, system, or computer program product. Accordingly, the application can take the form of a hardware embodiment, a software embodiment, or an embodiment in combination with software and hardware. Moreover, the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the present application. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

Accordingly, embodiments of the present invention also provide a storage medium in which a computer program is stored, the computer program being configured to perform a coefficient calibration method of a continuous time delta-sigma analog-to-digital converter of an embodiment of the present invention.

The above is only the preferred embodiment of the present application and is not intended to limit the scope of the present application.

Industrial applicability

In the technical solution of the present application, the continuous-time delta-sigma analog-to-digital converter includes at least: a voltage comparator and a digital controller; in a preset calibration mode, the voltage comparator first obtains the pre-acquired first calibration signal and reference The signals are compared, and then the digital controller calibrates all of the to-be-calibrated coefficients preset in the continuous-time delta-sigma analog-to-digital converter according to the comparison result of the first calibration signal and the reference signal and the preset calibration parameters. That is to say, in the technical solution of the present application, all the presets to be set in the continuous-time delta-sigma analog-to-digital converter can be realized by the voltage comparator and the digital controller in the continuous-time delta-sigma analog-to-digital converter. The coefficients are calibrated. In the prior art, a calibration circuit independent of the continuous-time delta-sigma analog-to-digital converter is required to calibrate all the parameters to be calibrated preset in the continuous-time delta-sigma analog-to-digital converter. Therefore, compared with the prior art, the continuous-time delta-sigma analog-to-digital converter provided by the embodiments of the present application can not only improve the calibration precision of the coefficients of the continuous-time delta-sigma analog-to-digital converter, but also save the continuous time Δ- The production cost of the modulo analog-to-digital converter; and the technical solution of the embodiment of the present application is simple, convenient, popular, and applicable.

Claims

A coefficient calibration method for a continuous time delta-sigma analog-to-digital converter, the continuous-time delta-sigma analog-to-digital converter comprising at least: a voltage comparator and a digital controller; the method comprising:

The voltage comparator compares the pre-acquired first calibration signal with the reference signal when in a preset calibration mode;

The digital controller calibrates all the to-be-calibrated coefficients preset in the continuous-time delta-sigma analog-to-digital converter according to a comparison result of the first calibration signal and the reference signal and a preset calibration parameter; The comparison result includes: a high level signal or a low level signal.
The method of claim 1 wherein said continuous time delta-sigma analog to digital converter further comprises: a digital to analog converter and a current integrator coupled in series with said digital to analog converter; said voltage comparison Before comparing the pre-acquired calibration signal with the reference signal, the method further includes:

The current integrator receives a pre-generated second calibration signal through the digital to analog converter, and converts the second calibration signal into the first calibration signal;

The current integrator transmits the first calibration signal to the voltage comparator through the digital to analog converter.
The method according to claim 1, wherein said digital controller pairs said continuous time Δ-Σ analog-to-digital converter according to a comparison result of said first calibration signal and said reference signal and a preset calibration parameter All the calibration coefficients to be set in advance are calibrated, including:

The digital controller determines a target comparison result according to a comparison result of the first calibration signal and the reference signal;

The digital controller determines, according to the target comparison result and the calibration parameter, a calibration control word corresponding to all the to-be-calibrated coefficients; wherein the calibration parameters include: an initial calibration control word and an adjustment step;

The digital controller calibrates all of the coefficients to be calibrated based on the target comparison result and the calibration control word.
The method of claim 3, wherein the digital controller determines a target comparison result based on a comparison result of the first calibration signal and the reference signal, comprising:

When the comparison result of the first calibration signal and the reference signal is plural, the digital controller counts the number of occurrences of the high level signal and the low level signal in all comparison results;

Determining that the high level signal is the target comparison result when the number of occurrences of the high level signal is greater than the number of occurrences of the low level signal;

When the number of occurrences of the high level signal is less than the number of occurrences of the low level signal, the low level signal is determined to be the target comparison result.
The method according to claim 3, wherein the digital controller determines a calibration control word corresponding to all the coefficients to be calibrated based on the target comparison result and the calibration parameter, including:

When the target comparison result is the high level signal, the digital controller reduces the initial calibration control word by the adjustment step size;

The digital controller increases the initial calibration control word by the adjustment step size when the target comparison result is the low level signal.
The method of claim 3 wherein said digital controller calibrates all of the coefficients to be calibrated based on said target comparison result and said calibration control word, comprising:

When the target comparison result is the high level signal, the digital controller reduces all the calibration coefficients to the calibration control word;

When the target comparison result is the low level signal, the digital controller increases all the calibration coefficients to the calibration control word.
A continuous time delta-sigma analog-to-digital converter comprising: a voltage comparator and a digital controller; wherein

The voltage comparator is configured to compare the pre-acquired first calibration signal with the reference signal when in a preset calibration mode;

The digital controller is configured to compare all the to-be-calibrated coefficients preset in the continuous-time Δ-Σ analog-to-digital converter according to a comparison result of the first calibration signal and the reference signal and a preset calibration parameter Performing calibration; wherein the comparison result includes: a high level signal or a low level signal.
The continuous time delta-sigma analog-to-digital converter of claim 7 wherein said continuous time delta-sigma analog-to-digital converter further comprises: a digital to analog converter and a current coupled in series with said digital to analog converter Integrator; among them,

The current integrator configured to receive a pre-generated second calibration signal by the digital to analog converter, to convert the second calibration signal to the first calibration signal; to pass the digital to analog converter A first calibration signal is sent to the voltage comparator.
The continuous time delta-sigma analog-to-digital converter according to claim 7, wherein said digital controller comprises: a determining unit and a calibration unit; wherein

The determining unit is configured to determine a target comparison result according to the comparison result of the first calibration signal and the reference signal; the digital controller determines, according to the target comparison result and the calibration parameter, all the to-be-calibrated coefficients Calibrating a control word; wherein the calibration parameters include: an initial calibration control word and an adjustment step size;

The calibration unit is configured to calibrate all of the coefficients to be calibrated based on the target comparison result and the calibration control word.
The continuous time delta-sigma analog-to-digital converter according to claim 9, wherein the determining unit comprises: a statistical subunit and a determining subunit; wherein

The statistical subunit is configured to count, when the comparison result of the first calibration signal and the reference signal is multiple, the number of occurrences of the high level signal and the low level signal in all comparison results;

The determining subunit is configured to determine that the high level signal is the target comparison result when the number of occurrences of the high level signal is greater than the number of occurrences of the low level signal; When the number of occurrences of the signal is less than the number of occurrences of the low level signal, the low level signal is determined to be the target comparison result.
The continuous time delta-sigma analog-to-digital converter according to claim 9, wherein said determining unit is configured to reduce said initial calibration control word when said target comparison result is said high level signal The adjustment step size; when the target comparison result is the low level signal, increasing the initial calibration control word by the adjustment step size.
The continuous time delta-sigma analog-to-digital converter according to claim 9, wherein said calibration unit is configured to reduce all coefficients to be calibrated when said target comparison result is said high level signal Calibrating the control word; when the target comparison result is the low level signal, increasing all the coefficients to be calibrated to the calibration control word.
A storage medium having stored therein computer executable instructions configured to perform a coefficient calibration method of the continuous time delta-sigma analog to digital converter of any of claims 1-6.