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WO2018151052A1 - Non-voltage-dropping power supply circuit and application circuit - Google Patents

Non-voltage-dropping power supply circuit and application circuit Download PDF

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Publication number
WO2018151052A1
WO2018151052A1 PCT/JP2018/004694 JP2018004694W WO2018151052A1 WO 2018151052 A1 WO2018151052 A1 WO 2018151052A1 JP 2018004694 W JP2018004694 W JP 2018004694W WO 2018151052 A1 WO2018151052 A1 WO 2018151052A1
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WO
WIPO (PCT)
Prior art keywords
voltage
power supply
type power
voltage drop
mosfet
Prior art date
Application number
PCT/JP2018/004694
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French (fr)
Japanese (ja)
Inventor
一穂 松本
Original Assignee
一穂 松本
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Priority claimed from JP2017024516A external-priority patent/JP6137723B1/en
Priority claimed from JP2017109590A external-priority patent/JP6191040B1/en
Application filed by 一穂 松本 filed Critical 一穂 松本
Publication of WO2018151052A1 publication Critical patent/WO2018151052A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/08Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/02Conversion of AC power input into DC power output without possibility of reversal
    • H02M7/04Conversion of AC power input into DC power output without possibility of reversal by static converters
    • H02M7/12Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • JPA-2003348750 DC power supply circuit and standby power circuit using the power supply WO2200332105 Standby power circuit JPA_200959308 DC power switch JPA_2012506693 JPA_2013255425 System and method for imitating ideal diode of power control device JPB_6137723 Non-voltage drop type power supply circuit and its application circuit JPB_6147402 DC power distribution system JPB_6191040 Ideal diode using complex voltage drop type power supply circuit
  • Patent Documents 1 and 2 Patent Documents 1 and 2
  • an “ideal diode” that can reduce the forward voltage of the rectifying diode using a power MOSFET or the like.
  • Patent Document 4 Non-Patent Documents 1 and 2
  • an “ideal diode” is configured using a power MOSFET or the like, since it is a so-called synchronous rectification method that requires a separate power source for the control circuit, it has a circuit configuration that cannot be made into two terminals. Even if there is a power MOSFET having a withstand voltage of several thousand volts, it cannot be used for commercial AC rectification because the withstand voltage of the control integrated circuit is insufficient.
  • DC distribution is considered to be efficient because it can reduce unnecessary AC / DC conversion, but it cannot be expected to stop spontaneously once discharge has started, so a means to stop discharge is secured. It is necessary to keep it.
  • a method of intermittently repeating intermittently is conceivable.
  • the voltage is too high to rectify commercial 100V to 220V and use it as a power source for the control circuit, and the standby power is reduced to 0. There was a drawback that could not be made.
  • FIG. 1A shows a non-voltage drop type power supply (80) having a first basic circuit configuration.
  • a voltage dividing resistor at the source (S) of the depletion type FET (85d) (a circuit configuration using an Nch MOSFET, which can also be constituted by a Pch MOSFET or a junction type FET with reversed polarity).
  • (89, R1, R2) and the capacitor (C1) are connected in parallel, the voltage (V1) of the AC power supply (2) is applied to the drain (D) through the diode (82) for reverse voltage protection, and the gate ( G) is connected to the midpoint of the voltage dividing resistor (89, R1, R2).
  • the capacitance (86p, Cg) is between the gate (G) and the source (S) of the depletion type FET (85d). Since it exists, it operates under the influence of its time constant ⁇ (the product of the parallel combined resistance value of the voltage dividing resistors R1 and R2 and the capacitance (86p, Cg) between the gate (G) and the source (S)). Since a delay occurs, the capacitor (C1) is charged to a voltage higher than the charging voltage (Vc chg ).
  • FIG. 1B shows an operation waveform. Charging is performed when the voltage (V1) of the AC power supply (2) rises, and after charging to a voltage higher than the charging voltage (Vc chg ), the voltage (V G ) rises with a delay, and the depletion type FET The gate threshold voltage (V Gth ) of ( 85d ) is reached and a cut-off state is entered, and charging is completed.
  • the depletion type FET (85d) conducts when the voltage (V1) of the AC power supply (2) is low, there is little power loss during charging, and if the depletion type FET (85d) continues to be cut off after charging, Furthermore, even if the power supply voltage (V1) rises, the current (I1) does not flow, so that the power consumption due to the voltage drop is small.
  • the voltage (V2) across the capacitor (C1) varies depending on the characteristics of the depletion type FET (85d) used, a direct current of several volts to several tens of volts can be obtained.
  • Rg high-resistance
  • the series resistance (Rf), the voltage dividing resistance (89, R1, R2), the parallel capacitance (Cs), and the like indicate elements that impede pulsed charging of the non-voltage drop type power supply (80).
  • the operation waveform (V2) as shown in FIG. 2B is obtained, and the charging current (I1) collapses from the pulse shape, and the current (I1) continues to flow even when the power supply voltage (V1) rises.
  • a Zener diode (82z) and a resistor (Rz) indicate a method for reducing an excessive voltage.
  • a junction type FET is used as the depletion type FET (85d)
  • the influence of the leakage current of the gate (G) must be considered.
  • FIG. 3A shows a complex voltage drop type power supply (80j) having a second basic circuit configuration.
  • This is a method of rectifying the AC power supply (2) by using a capacitor (C0) with a capacitor (C0) and securing the power for the control circuit, and is a circuit configuration method that is generally widely used.
  • a complex voltage drop is performed by the capacitor (C0), and the voltage is rectified by the diodes (D1, D2) to obtain DC power in the capacitors (C1, C2). Since the complex voltage drop due to the capacitor (C0) is used, no power consumption is involved.
  • the voltage (V2 +, V2-) of the capacitors (C1, C2) increases every cycle of the AC power supply (2).
  • the voltage reaches a maximum of 1.42 times the effective voltage of the AC power supply (2).
  • a Zener diode (82z) or the like In order to stably obtain a voltage of several volts to several tens of volts, it is necessary to make a constant voltage by consuming surplus power with a Zener diode (82z) or the like.
  • Non-voltage drop type power supply (80) (a) Basic circuit 1, (b) Operation waveform Operation inhibiting element (a) Adjustment element, (b) Operation waveform 1, (c) Operation waveform 2 Complex voltage drop type power supply (80j) (a) Basic circuit 2, (b) Operation waveform Ideal diode (82i, non-falling type) (a) circuit configuration, (b) operation waveform, (c) symbol notation, (d) external component, (e) bridge rectifier circuit, (f) full wave rectification waveform Ideal diode (82j, complex type) (a) circuit configuration, (b) operation waveform (ideal diode), (c) operation waveform (power supply unit), (d) rectified waveform (ideal diode), (e) rectified waveform ( Power supply part) Ideal diode (82j, complex type) (a) Symbol (NchMOSFET), (b) Symbol (PchMOSFET), (c) Bridge rectifier circuit, (d) Operation waveform Duplex ideal di
  • the power is supplied from the non-voltage drop type power supply (80) to the operational amplifier (83), and the voltage between the source (S) and drain (D) of the enhancement type power MOSFET (85e-1) is changed to the resistance (Rs).
  • a polarity detector (83D) is configured. Only when the direction of the current (I2) is negative (the conduction direction of the ideal diode (82i)), a positive voltage (V4) is applied to the gate (G), and the gate of the enhancement type power MOSFET (85e-1) (G ) To drive the enhancement-type power MOSFET (85e-1) to reduce the voltage drop.
  • FIG. 4B shows operation waveforms of the circuit (a).
  • the upper stage shows the flow of current (I2) flowing from the drain (D) to the source (S) of the enhancement type power MOSFET (85e-1), and the lower stage shows the input voltage (V3, chain line) of the operational amplifier (83) and the operational amplifier (83).
  • 83) (V4, solid line: voltage applied to the gate).
  • the current (I2) flowing through the enhancement type power MOSFET (85e-1) flows in the conduction direction of the parasitic diode (82p) (in the direction opposite to the arrow of I2), and is therefore expressed as negative.
  • the operational amplifier (83) performs inversion amplification, and a positive voltage (V4) is applied to the gate (G).
  • the voltage (V4) of the gate (G) is quickly lowered to 0V and the enhancement type power MOSFET (85e-1) is shut off. To do.
  • an operational amplifier (83) that operates with a single power supply is used, but the fact that the direction of the current flowing through the on-resistance of several milliohms is reversed is detected by comparison in the negative voltage region of several millivolts.
  • a high resistance (Rh) is connected to the inverting input terminal ( ⁇ ) of the operational amplifier 83, and a minute positive voltage is applied by the resistance voltage divider (Radj), so that the inverting input terminal The voltage of (-) is shifted to the positive voltage side.
  • the enhancement type power MOSFET When the voltage (V3) is negative, if the internal resistance of the enhancement type power MOSFET (85e-1) decreases, the input voltage (V3) of the operational amplifier also decreases, so that negative feedback is provided, so the enhancement type power MOSFET The operation is performed so that the voltage between the drain (D) and the source (S) of (85e-1) maintains a constant value. Further, since the on-resistance of the enhancement type power MOSFET (85e-1) increases when the current (I2) decreases, it is possible to obtain a condition that makes it easy to detect the direction change of the current because of the negative feedback. it can. In order to increase the current capacity, a plurality of enhancement type power MOSFETs can be connected in parallel. Different voltage-dividing resistors are passed through the gates (G), for example, so that the voltages to be turned on are different, the loop gain is lowered, and the current direction change can be easily detected. (Suppresses excessive gain by adding FET.)
  • the ideal diode (82i) using the non-voltage drop type power supply (80) can handle the entire circuit as a two-terminal ideal diode (82i).
  • FIG. 4C is a symbolized representation of an ideal diode (82i) using a non-voltage drop type power supply (80).
  • An arrow extending from the cathode (K) (in the case of an Nch MOSFET) is a symbol of an ideal diode (82i) indicating that power is supplied to the internal circuit.
  • FIG. 4D is also a representation of the ideal diode 82i symbolized, but clearly shows that the capacitor C1 of the non-voltage drop type power supply 80 is externally attached. (There is no change that it can be handled as two terminals.)
  • FIG. 4 (e) represents a bridge rectifier circuit (24) constituted by an ideal diode (82i) using the symbols shown in FIG. 4 (d). Since the diodes (Dc) and (Dd) connect the anodes (A), both the common lines (80c) have the same potential. Therefore, the non-voltage drop type power supply (80) can be shared with each other. it can. (Effective when configuring a module.)
  • the common line (80c) is not at the same potential, and the built-in non-voltage drop type power supply circuit (80) is provided. It cannot be shared.
  • an ideal diode (82i, including a non-voltage drop type power supply (80)) is configured using an enhancement type power MOSFET of Pch, since the cathodes become a common line (80c), the diode (Da) It is possible to share the non-voltage drop type power supply (80) of (Db) with each other.
  • the operational amplifier (83) to be used is an operational amplifier that can operate with a single power source that operates normally even when the common-mode input voltage of the input terminals (+,-) becomes a voltage near the positive power supply voltage. It is necessary to use it.
  • the ideal diodes (82i) configured using Nch and Pch enhancement type power MOSFETs (85e-1) are respectively diodes (Da, Dc)
  • the terminals connected to the AC power supply 2 are connected to the common line (80c). Therefore, since both a positive power source and a negative power source can be used in the internal circuit, the dual power source can be used for the operational amplifier (83).
  • the capacitor (C1) is externally attached. However, if the current consumption of the operational amplifier used is small, the capacity of the capacitor (C1) can be reduced. Is also possible.
  • the voltage of the smoothing capacitor (C2) is applied, so that the conduction angle of the current flowing in the forward direction is reduced, but the reverse voltage is applied to the ideal diode (82i) at the non-conduction angle. Therefore, power for driving the circuit can be obtained by the non-voltage drop type power supply (80).
  • the ideal diode (82i) of the application circuit 1 is limited to a use such as a rectifier circuit to which a reverse voltage is repeatedly applied.
  • FIG. 5A shows an ideal diode (82j) configured using a complex voltage drop type power supply (80j) and an Nch enhancement type power MOSFET (85e-1), which are the second basic circuit configuration.
  • the common line (80c) of the complex voltage drop type power supply (80j) is connected to the source (S) of the enhancement type power MOSFET (85e-1) to become the anode (A) of the ideal diode (82i) and the drain (D) Becomes the cathode (K).
  • a polarity detector (83D) is configured in addition to the inverting input ( ⁇ ) and the non-inverting input (+) of the operational amplifier (83).
  • the diode (82, D3) is for protecting an overvoltage of the operational amplifier (83).
  • FIG. 5B shows the waveform of the rectification operation of the ideal diode (82j).
  • the upper stage shows the flow of the current (I2) flowing from the drain (D) to the source (S) of the enhancement type power MOSFET (85e-1), and the lower stage shows the voltage (V3) of the inverting input terminal ( ⁇ ) of the operational amplifier (83).
  • the voltage (V3) of the inverting input terminal ( ⁇ ) of the operational amplifier (83) is negative
  • the voltage (V3) of the gate (G) decreases when the internal resistance of the enhancement type power MOSFET (85e-1) decreases. Therefore, since negative feedback occurs, the operation is performed so that the voltage between the drain (D) and the source (S) of the enhancement type power MOSFET (85e-1) maintains a constant value.
  • the negative feedback is provided, the on-resistance of the enhancement type power MOSFET (85e-1) increases when the current (I2) decreases, but it is possible to obtain a condition for easily detecting the direction change of the current. it can.
  • the loop gain is adjusted to set the operating range of the ideal diode (82j) according to the application.
  • the inverting output (V4) is directed to the potential below the common line (80c), so that the enhancement type power MOSFET (85e-1 ) Goes to the shut-off state.
  • the Pch enhancement type power MOSFET (85e-1) is used, the conduction direction is reversed, so that the display of the anode (A) and the cathode (K) in FIG. It is necessary to connect (Radj) to the positive voltage side and apply a positive voltage of several millivolts to the non-inverting input terminal (+).
  • the ideal diode (82j) using the complex voltage drop type power supply (80j) can handle the entire circuit as a two-terminal ideal diode (82j).
  • FIG. 6B is a symbolized representation of an ideal diode (82j) using a Pch enhancement type power MOSFET (85e-1).
  • the anode (A) and the cathode (K) are interchanged, and the arrow changes to an arrow extending from the anode (A).
  • FIG. 6C shows the bridge rectifier circuit 24 using the symbols in FIG. 6A
  • FIG. 6D shows its operation waveform. Since the voltage of the smoothing capacitor (C3) is applied, the conduction angle of the forward current (I2) is reduced. At the non-conduction angle, a reverse voltage is applied to each ideal diode (82j), so that power for driving the circuit can be obtained from the complex voltage drop type power supply (80j).
  • the ideal diode (82j) is limited to applications where a voltage in the reverse direction is repeatedly applied, such as a rectifier circuit of the AC power supply (2).
  • the breakdown voltage and capacity of the capacitor (C0) are selected according to the voltage range applied in the reverse direction.
  • an example using a complex voltage drop type power supply (80j) having both positive and negative power supply configurations is shown.
  • a capacitor (C1) and a Zener diode (Dz1) or a capacitor (C2) and a Zener diode (Dz2) are shown.
  • a complex voltage drop type power supply circuit (80j) of a single power source of only positive or only negative can be configured.
  • the non-inverting input (+) of the operational amplifier (83) is connected to the common line (80c), and a resistor is connected to the inverting input ( ⁇ ). It is necessary to apply a voltage of several millivolts.
  • the Zener diode (82z) that consumes surplus power can be used as a light source such as an indication of the operating state or a power indicator of a device incorporating the ideal diode (82j). .
  • the MOSFET (85e-3) is cut off and the operational amplifier (83) Since the inverting input ( ⁇ ) becomes 0 V, the output is inverted to cut off the two enhancement type power MOSFETs (85e-1, 85e-2).
  • the voltage to be inverted can be adjusted by adding a voltage dividing resistor (89) to the gate (G) of the MOSFET (85e-3).
  • FIG. 7 (b) shows the solar diode panel (11) connected in parallel using the symbol of the ideal diode (82ii) (the bar structure of the diode symbol is outlined because the internal configuration is different).
  • a connection example is shown.
  • solar panels (11) of a plurality of systems are connected in parallel and the power conditioner (13) is operating at the optimum input voltage, a voltage increase of about 5% when one system is shut down (system When the voltage is 400 V, about 20 V) is expected, and driving power can be obtained by performing a short interruption of about several tens of milliseconds for each system.
  • the common line (80c) cannot be shared with an external circuit.
  • FIG. 8A shows a first basic circuit configuration, a non-voltage drop type power supply (80) and two enhancement type power MOSFETs (85e-1 and 85e-2), which are turned on and off according to illuminance.
  • FIG. 8B shows an operation waveform. (The broken line is an operation waveform when the illuminance is large.)
  • the voltage of the non-voltage drop type power supply (80) is not exceeded by the diode (82-2) through the diode (82-1) and the resistor (88, Rs). Restricted to Further, the voltage (V3) is applied to the non-inverting input terminal (+) of the operational amplifier (83) through the voltage dividing resistors (89, R3, R4). A voltage (V2) divided by the optical sensor (84s, CDS) and the resistor (88, Rh) is applied to the inverting input terminal ( ⁇ ) of the operational amplifier (83). When the illuminance is high, the resistance value of the optical sensor (84s, CDS) decreases, and the voltage (V2) of the inverting input terminal ( ⁇ ) increases.
  • the electronic switch (84) in the operating state cuts off the current (I2) and charges the non-voltage drop type power supply (80).
  • the output pulse width (t) of the one-shot pulse generator (84p) is set slightly shorter than the cycle (T) of the AC power supply (2) so as not to hinder the charging of the non-voltage drop type power supply (80).
  • Has hysteresis In order to provide positive feedback to the non-inverting input terminal (+) of the operational amplifier (83) by the diode (82-3), the capacitor (C3) and the resistor (88, Rf), and to ensure the on-off transition, Has hysteresis.
  • FIG. 9B shows operation waveforms.
  • the voltage (V1) is the voltage of the power supply (1)
  • the voltage (V4) is the voltage between the gate (G) and the source (S)
  • the current (I1) is the charge of the non-voltage drop type power supply (80). Current is shown.
  • the periodic pulse generator (84P) conducts the enhancement type power MOSFET (85e-1) for a certain period of time, and supplies power to the load (R L ).
  • the enhancement type power MOSFET (85e-1) is cut off, the current (I1) flows, and driving power is obtained in the capacitor (C1), and this is repeated. Since an intermittent direct current is output to the output terminal (80O) of FIG. 9A, the output of the application circuit 5 is a power supply (12) whose voltage changes.
  • FIG. 9C is a symbolized representation of the electronic switch (84) driven by the periodic pulse generator (84P).
  • the periodic pulse generator (80P) When the periodic pulse generator (80P) is not built in, it is necessary to connect and use the power supply (12) whose voltage changes. When the voltage of the output terminal (80O) does not decrease, such as a capacitive load, driving power may not be obtained. Due to the influence of the parasitic diode (82p), the direction of the voltage applied to the electronic switch (84) is limited.
  • FIG. 10A shows a first non-voltage drop type power supply (80) and an N-ch enhancement type power MOSFET (85e-1), a P-ch MOSFET (85x), and a first basic circuit configuration. Equipped with an overcurrent detector (84I) and safety electrode current detector (84g) that operate with power from a non-voltage drop type power supply (80), or other sensors (earthquake, fire) not shown in the figure.
  • FIG. 10B shows an operation waveform.
  • the voltage (V1) is the voltage of the power supply (1)
  • the voltage (V4) is the voltage between the gate (G) and the source (S)
  • the current (I1) is the charge of the non-voltage drop type power supply (80).
  • the current (I3) indicates the current of the Pch MOSFET (85x).
  • the enhancement type power MOSFET (85e-1) is turned on for a certain period of time to supply power to the load.
  • the enhancement type power MOSFET (85e-1) is cut off, if the load (R L ) is capacitive, the voltage across the load is maintained, so there is a possibility that sufficient current (I1) does not flow. is there.
  • the Pch MOSFET (85x) is pulse-driven to short-circuit the load (R L ) to obtain currents (I1, I3) for driving. It is the structure which ensures the electric power of. Since driving of the Pch MOSFET (85x) requires a negative voltage, a negative pulse voltage is applied to the gate (G) by capacitive coupling (Cc, R4). At the same time, a reverse voltage is applied to the ideal diodes (82i, 82j, 82ii) used on the load side by using the voltage accumulated in the capacitor (C6) to secure driving power. (Although not shown in the figure, when the enhancement type power MOSFET (85e-2) is provided, the enhancement type power MOSFET (85e-2) is turned on simultaneously with the Pch MOSFET (85x).)
  • the current (I1) can be obtained with certainty, but even when there is no load, it is not shown in the figure because it continues to operate with power for driving.
  • the on-resistance was increased by forming a negative feedback path and controlling the voltage drop of the enhancement type power MOSFET (85e-1) to be a constant value around 10 millivolts. Even in the situation, if the voltage drop is several millivolts or less, it can be reliably detected that there is no load.
  • FIG. 10C represents a safety breaker (31) for direct current distribution that interrupts power using the symbol of the electronic switch (84).
  • FIG. 11 shows a “DC power distribution system” that intermittently supplies power using an electronic switch (84) including a non-voltage drop type power supply (80) that is a first basic circuit configuration.
  • the DC power distribution system supplies intermittent power at different times from the power distribution board (3) through two lines of wiring, and combines them with ideal diodes (82i, 82j, 82ii) on the electrical equipment (6) side. It has a configuration that can receive no DC power. (In the case of the low-power electric device (6), it is operated by supplying one system. Similar to the single-phase three-wire wiring of the commercial AC power supply, it is applied to the high-power electric device (6). Reference 6)
  • the electric device (6) that operates with the intermittent direct current (12) can be designed to operate with the non-smooth direct current (12) obtained by full-wave rectification of the commercial AC power supply (2).
  • a conversion plug and conversion outlet with a built-in bridge rectifier (24) of ideal diodes (82i, 82j, 82ii) electrical equipment (6) operating on DC can be connected to commercial AC power supply (2) is there.
  • the present application can provide a practical ideal diode or electronic switch by efficiently and easily obtaining a minute DC power, and driving a power MOSFET or the like using the power to provide a practical ideal diode or electronic switch.
  • a rectifier circuit, a DC power distribution system, or the like can be configured.

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Abstract

[Problem] In order to form an electronic switch for intermittently switching a commercial power supply using a power MOSFET, a drive power, although very small, is required and therefore a conventional circuit configuration has had the disadvantage of, for example, consuming power even during no-load time. Although a highly efficient rectification scheme using the power MOSFET exists, the scheme separately requires drive power and therefore cannot be treated as a two terminal diode. Accordingly, a simple method for obtaining a very small power for controlling ten and several volts has been desired. [Solution] Provided are a non-voltage-dropping power supply circuit, an electronic switch using a power MOSFET, and an ideal diode capable of being treated as a two terminal. The non-voltage-dropping power supply circuit can obtain a very small power without causing a voltage drop in such a way that: a resistor having a high resistance is connected to the gate of a depletion-type FET to cause an operation delay; and instantaneous charging is performed when the power supply voltage reaches a required voltage.

Description

電圧非降下型電源回路及びその応用回路Non-voltage drop type power supply circuit and its application circuit
 本発明は、電圧が変化する電源から、電力消費を伴う電圧降下を避けて、微小な直流電力を得る電子回路の構成方法とその応用回路に関するものである。 The present invention relates to a method of configuring an electronic circuit and its application circuit that obtains a minute DC power by avoiding a voltage drop accompanying power consumption from a power source that changes in voltage.
 商用電源を電気的に制御しようとすると、微小な電力が必要になるが、一般に使用されている電源回路の構成では、部品数が多くなり、電力効率が低く、待機電力を完全に0とすることが出来なかった。
 整流用のショットキーバリアダイオードは、0.3~数ボルトの順方向の電圧降下があるから、取り扱う電力の1%前後が熱となってしまっていた。
 順方向電圧を減少し、整流効率を改善する「理想ダイオード」と称する、パワーMOSFETなどを用いて順方向電圧を10分の1から100分の1に減少させる回路の構成方法が存在するが、いわゆる「同期整流方式」であり、駆動用の電源を別に必要とし、2端子として取り扱うことができない回路構成であった。
When a commercial power source is to be electrically controlled, a very small amount of power is required. However, in the configuration of a generally used power supply circuit, the number of parts increases, power efficiency is low, and standby power is completely zero. I couldn't.
Since the rectifying Schottky barrier diode has a forward voltage drop of 0.3 to several volts, about 1% of the power handled is heat.
There is a circuit configuration method for reducing the forward voltage from 1/10 to 1/100 using a power MOSFET or the like, called an “ideal diode” that reduces the forward voltage and improves rectification efficiency. This is a so-called “synchronous rectification method”, which requires a separate driving power supply and cannot be handled as two terminals.
JPA_2003348750 直流電源回路およびその電源を用いた待機電力回路JPA-2003348750 DC power supply circuit and standby power circuit using the power supply WO2003032105 待機電力回路WO2200332105 Standby power circuit JPA_2009159308 直流電源スイッチJPA_200959308 DC power switch JPA_2012506693 JPA_2013255425 電力制御装置の理想ダイオードを模倣するシステム及びその方法JPA_2012506693 JPA_2013255425 System and method for imitating ideal diode of power control device JPB_6137723 電圧非降下型電源回路及びその応用回路JPB_6137723 Non-voltage drop type power supply circuit and its application circuit JPB_6147402 直流配電システムJPB_6147402 DC power distribution system JPB_6191040 複素電圧降下型電源回路を用いた理想ダイオードJPB_6191040 Ideal diode using complex voltage drop type power supply circuit
・パワーMOSFETなどを用いて商用交流電源を電気的に開閉しようとすると、制御回路のための直流数ボルトから十数ボルトの微小な電力が必要となるが、商用交流電源を整流して得た電圧では高過ぎる。
 一般的な直流電源回路を組み込むと、パワーMOSFETなどを制御するのに要するよりもかなり大きな電力を消費することになり、部品数が多くなるとともに、無負荷時においても電力を消費してしまう欠点があった。(特許文献3)
・ When a commercial AC power supply is electrically opened and closed using a power MOSFET or the like, a minute power of several volt to several tens of volts is required for the control circuit. The voltage is too high.
Incorporation of a general DC power supply circuit consumes much more power than is necessary to control a power MOSFET, etc., and the number of parts increases and power is consumed even when there is no load. was there. (Patent Document 3)
・FETを使用して電圧を降下させる回路など、簡易な回路構成の直流電源が使用されることもあるが、電力効率が低く、負荷が無いときの待機電力を完全に0とすることが出来ないなどの欠点があった。(特許文献1、2) -DC power supply with a simple circuit configuration, such as a circuit that uses an FET to lower the voltage, may be used, but power efficiency is low, and standby power when there is no load can be completely zero There were disadvantages such as not. (Patent Documents 1 and 2)
・また、パワーMOSFETなどを用いて整流用ダイオードの順方向電圧を減少することができる「理想ダイオード」と称する回路構成が存在する。(特許文献4、非特許文献1、2)
 パワーMOSFETなどを用いて「理想ダイオード」を構成しているが、制御回路用の電源が別に必要な、いわゆる同期整流方式であるため、2端子化することが出来ない回路構成であった。
 数千ボルトの耐圧のパワーMOSFETがあっても、制御用の集積回路の耐圧が不足するため、商用交流の整流にも使用することが出来なかった。
There is also a circuit configuration called an “ideal diode” that can reduce the forward voltage of the rectifying diode using a power MOSFET or the like. (Patent Document 4, Non-Patent Documents 1 and 2)
Although an “ideal diode” is configured using a power MOSFET or the like, since it is a so-called synchronous rectification method that requires a separate power source for the control circuit, it has a circuit configuration that cannot be made into two terminals.
Even if there is a power MOSFET having a withstand voltage of several thousand volts, it cannot be used for commercial AC rectification because the withstand voltage of the control integrated circuit is insufficient.
 さらに、直流配電は、無駄な交流・直流変換を少なくすることができるから、効率が良いとされるが、一旦放電が始まると自然に停止することが期待できないため、放電を停止させる手段を確保しておく必要がある。
 その1つの方法として、間欠的に断続を繰り返す方法などが考えられるが、前述のとおり商用の100V~220Vを整流して制御回路用の電源として利用するには電圧が高過ぎ、待機電力を0にすることができない欠点があった。
Furthermore, DC distribution is considered to be efficient because it can reduce unnecessary AC / DC conversion, but it cannot be expected to stop spontaneously once discharge has started, so a means to stop discharge is secured. It is necessary to keep it.
As one of the methods, a method of intermittently repeating intermittently is conceivable. However, as described above, the voltage is too high to rectify commercial 100V to 220V and use it as a power source for the control circuit, and the standby power is reduced to 0. There was a drawback that could not be made.
 簡単な回路構成で、微小な直流電力を得る簡便な方法が求められていた。
 
There has been a demand for a simple method for obtaining minute DC power with a simple circuit configuration.
 図1(a)は、第1の基本回路構成の電圧非降下型電源(80)である。
 ディプレッション型FET(85d)(NchのMOSFETを使用した回路構成である。極性が逆になったPchのMOSFET、あるいはジャンクション型のFETでも構成可能である。)のソース(S)に分圧抵抗器(89、R1、R2)とコンデンサー(C1)とを並列に接続し、逆電圧保護のダイオード(82)をとおしてドレイン(D)に交流電源(2)の電圧(V1)を加え、ゲート(G)を分圧抵抗器(89、R1、R2)の中点に接続している。
FIG. 1A shows a non-voltage drop type power supply (80) having a first basic circuit configuration.
A voltage dividing resistor at the source (S) of the depletion type FET (85d) (a circuit configuration using an Nch MOSFET, which can also be constituted by a Pch MOSFET or a junction type FET with reversed polarity). (89, R1, R2) and the capacitor (C1) are connected in parallel, the voltage (V1) of the AC power supply (2) is applied to the drain (D) through the diode (82) for reverse voltage protection, and the gate ( G) is connected to the midpoint of the voltage dividing resistor (89, R1, R2).
 ディプレッション型FET(85d)であるから、ゲート(G)とソース(S)との間の電圧が0Vであっても、ドレイン(D)とソース(S)との間に電流(I1)が流れるので、交流電源(2)の電圧が正のときは、電流(I1)によって、コンデンサー(C1)に充電される。
 分圧抵抗器(89、R1、R2)によって分圧された電圧がゲート(G)に加わり、ゲートしきい値電圧(VGth)に達すると、ドレイン(D)とソース(S)との間が遮断され、充電が停止する。
 分圧抵抗器(89、R1、R2)の比により、コンデンサー(C1)の充電電圧(Vcchg)を調整できる。
  Vcchg = VGth × R1/(R1+R2)
Since it is a depletion type FET (85d), even if the voltage between the gate (G) and the source (S) is 0V, the current (I1) flows between the drain (D) and the source (S). Therefore, when the voltage of the AC power supply (2) is positive, the capacitor (C1) is charged by the current (I1).
When the voltage divided by the voltage dividing resistors (89, R1, R2) is applied to the gate (G) and reaches the gate threshold voltage (V Gth ), it is between the drain (D) and the source (S). Is cut off and charging stops.
The charging voltage (Vc chg ) of the capacitor (C1) can be adjusted by the ratio of the voltage dividing resistors (89, R1, R2).
Vc chg = V Gth x R1 / (R1 + R2)
 ここで、分圧抵抗器(89、R1、R2)の抵抗値を高く設定すると、ディプレッション型FET(85d)のゲート(G)-ソース(S)間には静電容量(86p、Cg)が存在するから、その時定数τ(分圧抵抗器R1、R2の並列合成抵抗値とゲート(G)-ソース(S)間の静電容量(86p、Cg)との積)の影響を受けて動作遅れを生じるので、コンデンサー(C1)に充電電圧(Vcchg)より高い電圧まで充電されることになる。
  τ=Cg×R1×R2/(R1+R2)
 負荷(R)によって消費されてコンデンサー(C1)の電圧(V2)が下がり、分圧した電圧がゲートしきい値電圧(VGth)以下になるまで、次の充電は行われない。
Here, when the resistance value of the voltage dividing resistor (89, R1, R2) is set high, the capacitance (86p, Cg) is between the gate (G) and the source (S) of the depletion type FET (85d). Since it exists, it operates under the influence of its time constant τ (the product of the parallel combined resistance value of the voltage dividing resistors R1 and R2 and the capacitance (86p, Cg) between the gate (G) and the source (S)). Since a delay occurs, the capacitor (C1) is charged to a voltage higher than the charging voltage (Vc chg ).
τ = Cg × R1 × R2 / (R1 + R2)
The next charge is not performed until the voltage (V2) of the capacitor (C1) is consumed by the load (R L ) and the divided voltage becomes equal to or lower than the gate threshold voltage (V Gth ).
 図1(b)は、動作波形である。
 交流電源(2)の電圧(V1)が上昇するときに充電が行われ、充電電圧(Vcchg)より高い電圧まで充電された後に、遅延して電圧(V)が上昇し、ディプレッション型FET(85d)のゲートしきい値電圧(VGth)に達して遮断状態になり、充電が終了する。
 交流電源(2)の電圧(V1)が低いときにディプレッション型FET(85d)が導通するから、充電の際の電力損失が少なく、充電終了後ディプレッション型FET(85d)の遮断状態が続けば、さらに電源電圧(V1)が上昇しても電流(I1)が流れないから電圧降下による電力消費が少ない。
 コンデンサー(C1)の両端の電圧(V2)は、使用するディプレッション型FET(85d)の特性などによって異なるが、数ボルトから十数ボルトの直流を得ることができる。
FIG. 1B shows an operation waveform.
Charging is performed when the voltage (V1) of the AC power supply (2) rises, and after charging to a voltage higher than the charging voltage (Vc chg ), the voltage (V G ) rises with a delay, and the depletion type FET The gate threshold voltage (V Gth ) of ( 85d ) is reached and a cut-off state is entered, and charging is completed.
Since the depletion type FET (85d) conducts when the voltage (V1) of the AC power supply (2) is low, there is little power loss during charging, and if the depletion type FET (85d) continues to be cut off after charging, Furthermore, even if the power supply voltage (V1) rises, the current (I1) does not flow, so that the power consumption due to the voltage drop is small.
Although the voltage (V2) across the capacitor (C1) varies depending on the characteristics of the depletion type FET (85d) used, a direct current of several volts to several tens of volts can be obtained.
 図2(a)に示すように、ゲート(G)とソース(S)間にコンデンサー(86p、C)を、ゲート(G)に直列に高抵抗(Rg)を追加して時定数を調整することもできる。(分圧抵抗器89のR1、R2で分圧しない構成の場合は、高抵抗Rgが必須である。)
 直列の抵抗(Rf)、分圧抵抗(89、R1、R2)、並列の容量(Cs)などは、電圧非降下型電源(80)のパルス状の充電を阻害する要素であることを示す。
 図2(b)のような動作波形(V2)となり、充電電流(I1)はパルス状から崩れ、電源電圧(V1)が上昇したときも、電流(I1)が流れ続ける状態となる。
As shown in FIG. 2 (a), a condenser gate (G) and between the source (S) (86p, C g ) to adjust the time constant by adding a high-resistance (Rg) in series to the gate (G) You can also (In the case where the voltage dividing resistor 89 is not divided by R1 and R2, a high resistance Rg is essential.)
The series resistance (Rf), the voltage dividing resistance (89, R1, R2), the parallel capacitance (Cs), and the like indicate elements that impede pulsed charging of the non-voltage drop type power supply (80).
The operation waveform (V2) as shown in FIG. 2B is obtained, and the charging current (I1) collapses from the pulse shape, and the current (I1) continues to flow even when the power supply voltage (V1) rises.
 時定数の設定によっては、図2(c)の電圧(V2)の動作波形のように、一時的に過剰な充電が行われ、毎サイクルの安定した充電が行われないことも生じる。
 ツェナーダイオード(82z)、抵抗(Rz)は、過剰な電圧を低減する方法を示している。
 ディプレッション型FET(85d)に、ジャンクション型のFETを用いる場合は、ゲート(G)の漏れ電流の影響を考慮しなければならない。
 
Depending on the setting of the time constant, excessive charging is temporarily performed as shown in the operation waveform of the voltage (V2) in FIG. 2C, and stable charging in each cycle may not be performed.
A Zener diode (82z) and a resistor (Rz) indicate a method for reducing an excessive voltage.
When a junction type FET is used as the depletion type FET (85d), the influence of the leakage current of the gate (G) must be considered.
 図3(a)は、第2の基本回路構成の複素電圧降下型電源(80j)である。
 交流電源(2)にコンデンサー(C0)を使用して複素電圧降下させた上で整流し、制御回路用の電力を確保する方法であり、一般に広く利用されている回路構成方法である。
 コンデンサー(C0)により複素電圧降下させて、ダイオード(D1,D2)により整流し、コンデンサー(C1、C2)に直流電力を得る。
 コンデンサー(C0)による複素電圧降下を利用するから、電力消費を伴わない。
FIG. 3A shows a complex voltage drop type power supply (80j) having a second basic circuit configuration.
This is a method of rectifying the AC power supply (2) by using a capacitor (C0) with a capacitor (C0) and securing the power for the control circuit, and is a circuit configuration method that is generally widely used.
A complex voltage drop is performed by the capacitor (C0), and the voltage is rectified by the diodes (D1, D2) to obtain DC power in the capacitors (C1, C2).
Since the complex voltage drop due to the capacitor (C0) is used, no power consumption is involved.
 複素電圧降下型電源(80j)の出力電圧は、消費されなければ、交流電源(2)のサイクルごとにコンデンサー(C1、C2)の電圧(V2+、V2-)が増大し、この回路構成では、交流電源(2)の実効電圧の最大1.42倍の電圧に達する。
 数ボルト~十数ボルトの電圧を安定に得るためには、ツェナーダイオード(82z)等により、余剰電力を消費させて定電圧化する必要がある。
 
If the output voltage of the complex voltage drop type power supply (80j) is not consumed, the voltage (V2 +, V2-) of the capacitors (C1, C2) increases every cycle of the AC power supply (2). The voltage reaches a maximum of 1.42 times the effective voltage of the AC power supply (2).
In order to stably obtain a voltage of several volts to several tens of volts, it is necessary to make a constant voltage by consuming surplus power with a Zener diode (82z) or the like.
 少数の部品で、電圧降下を避けて微小な直流電力を簡便な方法で得ることができる。
 高い電力効率で微小な直流電力を得ることができ、多くの応用回路を提供できる。
 完全な2端子化が可能な理想のダイオード及び直流配電等に必要な電子スイッチを提供できる。
With a small number of parts, a minute DC power can be obtained by a simple method while avoiding a voltage drop.
Micro DC power can be obtained with high power efficiency, and many application circuits can be provided.
It is possible to provide an ideal diode that can be completely made into two terminals and an electronic switch necessary for direct current distribution.
電圧非降下型電源(80)(a)基本回路1、(b)動作波形Non-voltage drop type power supply (80) (a) Basic circuit 1, (b) Operation waveform 動作阻害要素(a)調整要素、(b)動作波形1、(c)動作波形2Operation inhibiting element (a) Adjustment element, (b) Operation waveform 1, (c) Operation waveform 2 複素電圧降下型電源(80j)(a)基本回路2、(b)動作波形Complex voltage drop type power supply (80j) (a) Basic circuit 2, (b) Operation waveform 理想ダイオード(82i、非降下型)(a)回路構成、(b)動作波形、(c)記号表記、(d)外付け部品、(e)ブリッジ整流回路、(f)全波整流波形Ideal diode (82i, non-falling type) (a) circuit configuration, (b) operation waveform, (c) symbol notation, (d) external component, (e) bridge rectifier circuit, (f) full wave rectification waveform 理想ダイオード(82j、複素型)(a)回路構成、(b)動作波形(理想ダイオード)、(c)動作波形(電源部)、(d)整流波形(理想ダイオード)、(e)整流波形(電源部)Ideal diode (82j, complex type) (a) circuit configuration, (b) operation waveform (ideal diode), (c) operation waveform (power supply unit), (d) rectified waveform (ideal diode), (e) rectified waveform ( Power supply part) 理想ダイオード(82j、複素型)(a)記号(NchMOSFET)、(b)記号(PchMOSFET)、(c)ブリッジ整流回路、(d)動作波形Ideal diode (82j, complex type) (a) Symbol (NchMOSFET), (b) Symbol (PchMOSFET), (c) Bridge rectifier circuit, (d) Operation waveform 二重化した理想ダイオード(82ii)(a)回路構成、(b)太陽電池の並列接続Duplex ideal diode (82ii) (a) Circuit configuration, (b) Parallel connection of solar cells 二重化した電子スイッチ(84)(a)回路構成、(b)動作波形Redundant electronic switch (84) (a) Circuit configuration, (b) Operating waveform 自律動作する電子スイッチ(84)(a)回路構成、(b)動作波形、(c)記号表記Electronic switch that operates autonomously (84) (a) Circuit configuration, (b) Operation waveform, (c) Symbol notation 短絡路付き電子スイッチ(84)(a)回路構成、(b)動作波形、(c)記号表記Electronic switch with short circuit (84) (a) Circuit configuration, (b) Operation waveform, (c) Symbol notation 直流配電システムへの応用例Application example to DC distribution system
<応用回路1>
 図4(a)は、第1の基本回路構成である電圧非降下型電源(80)を用いた、理想ダイオード(82i)である。
 エンハンスメント型のパワーMOSFET(85e-1)を理想ダイオード(82i)として用いるので、その寄生ダイオード(82p)の導通方向(アノード(A)からカソード(K))が理想ダイオード(82i)の導通方向となるように構成する。
 電圧非降下型電源(80)の共通線(80c)をエンハンスメント型のパワーMOSFET(85e-1)のソース(S)に接続し、理想ダイオード(82i)のアノード(A)とする。
<Application circuit 1>
FIG. 4A shows an ideal diode (82i) using a non-voltage drop type power supply (80) which is the first basic circuit configuration.
Since the enhancement type power MOSFET (85e-1) is used as the ideal diode (82i), the conduction direction of the parasitic diode (82p) (the anode (A) to the cathode (K)) is the conduction direction of the ideal diode (82i). Configure to be
The common line (80c) of the non-voltage drop type power supply (80) is connected to the source (S) of the enhancement type power MOSFET (85e-1) to be the anode (A) of the ideal diode (82i).
 電圧非降下型電源(80)からオペアンプ(83)に電源を供給し、エンハンスメント型のパワーMOSFET(85e-1)のソース(S)とドレイン(D)との間の電圧を、抵抗(Rs)を通してオペアンプ(83)に加えて、極性検出器(83D)を構成している。
 電流(I2)の方向が負(理想ダイオード(82i)の導通方向)であるときのみゲート(G)に正の電圧(V4)を加えてエンハンスメント型のパワーMOSFET(85e-1)のゲート(G)を駆動し、エンハンスメント型のパワーMOSFET(85e-1)を導通させて、電圧降下を減少させている。
The power is supplied from the non-voltage drop type power supply (80) to the operational amplifier (83), and the voltage between the source (S) and drain (D) of the enhancement type power MOSFET (85e-1) is changed to the resistance (Rs). In addition to the operational amplifier (83), a polarity detector (83D) is configured.
Only when the direction of the current (I2) is negative (the conduction direction of the ideal diode (82i)), a positive voltage (V4) is applied to the gate (G), and the gate of the enhancement type power MOSFET (85e-1) (G ) To drive the enhancement-type power MOSFET (85e-1) to reduce the voltage drop.
 図4(b)は、回路(a)の動作波形である。
 上段はエンハンスメント型のパワーMOSFET(85e-1)のドレイン(D)からソース(S)に流れる電流(I2)の流れを、下段はオペアンプ(83)の入力の電圧(V3、鎖線)とオペアンプ(83)の出力電圧(V4、実線:ゲートに加わる電圧でもある。)を表している。
 エンハンスメント型のパワーMOSFET(85e-1)に流れる電流(I2)は、寄生ダイオード(82p)の導通方向に流れている(I2の矢印と逆方向)ので、負で表されている。
 電圧(V3)が負になったときは、オペアンプ(83)により反転増幅を行って、ゲート(G)に正の電圧(V4)を加える。
 電流(I2)の方向が反転し、電圧(V3)が正となったときに、素早くゲート(G)の電圧(V4)を0Vに下げて、エンハンスメント型のパワーMOSFET(85e-1)を遮断する。
FIG. 4B shows operation waveforms of the circuit (a).
The upper stage shows the flow of current (I2) flowing from the drain (D) to the source (S) of the enhancement type power MOSFET (85e-1), and the lower stage shows the input voltage (V3, chain line) of the operational amplifier (83) and the operational amplifier (83). 83) (V4, solid line: voltage applied to the gate).
The current (I2) flowing through the enhancement type power MOSFET (85e-1) flows in the conduction direction of the parasitic diode (82p) (in the direction opposite to the arrow of I2), and is therefore expressed as negative.
When the voltage (V3) becomes negative, the operational amplifier (83) performs inversion amplification, and a positive voltage (V4) is applied to the gate (G).
When the direction of the current (I2) is reversed and the voltage (V3) becomes positive, the voltage (V4) of the gate (G) is quickly lowered to 0V and the enhancement type power MOSFET (85e-1) is shut off. To do.
 この例では、単一電源で動作するオペアンプ(83)を用いているが、数ミリオームのオン抵抗に流れる電流の向きが反転したことを、数ミリボルトの負電圧の領域で比較を行って検出する必要がある。このため、図4(а)に示すように、オペアンプ83の反転入力端子(-)に高抵抗(Rh)を接続し、抵抗分圧器(Radj)により微小な正電圧を加えて、反転入力端子(-)の電圧を正電圧側にシフトしている。
オペアンプ(83)の反転入力(-)の電圧(V3)が正のときは、出力の電圧(V4)が接地電位に向かうので、エンハンスメント型のパワーMOSFET(85e-1)の内部抵抗が上昇する。その結果さらに比較入力電圧が上昇して正帰還となるから、エンハンスメント型のパワーMOSFET(85e-1)が遮断状態に向かう。
In this example, an operational amplifier (83) that operates with a single power supply is used, but the fact that the direction of the current flowing through the on-resistance of several milliohms is reversed is detected by comparison in the negative voltage region of several millivolts. There is a need. For this reason, as shown in FIG. 4A, a high resistance (Rh) is connected to the inverting input terminal (−) of the operational amplifier 83, and a minute positive voltage is applied by the resistance voltage divider (Radj), so that the inverting input terminal The voltage of (-) is shifted to the positive voltage side.
When the voltage (V3) of the inverting input (−) of the operational amplifier (83) is positive, the output voltage (V4) goes to the ground potential, so that the internal resistance of the enhancement type power MOSFET (85e-1) increases. . As a result, the comparison input voltage further rises to provide positive feedback, so that the enhancement type power MOSFET (85e-1) goes to the cutoff state.
電圧(V3)が負のときは、エンハンスメント型のパワーMOSFET(85e-1)の内部抵抗が減少すると、オペアンプの入力電圧(V3)も減少するので、負帰還となるから、エンハンスメント型のパワーMOSFET(85e-1)のドレイン(D)-ソース(S)間の電圧が一定値を保つように動作をする。
また、負帰還となっているから、電流(I2)が減少したときにエンハンスメント型のパワーMOSFET(85e-1)のオン抵抗が上昇するので、電流の方向転換を検出し易い条件を得ることができる。
電流容量を増すために複数のエンハンスメント型のパワーMOSFETを並列接続することができる。ゲート(G)にそれぞれ異なる分圧抵抗器を通すなどして、ONとなる電圧が異なるように接続し、ループゲインを下げ、電流の方向転換を容易に検出できるようにする。(FETを加えることによる過剰なゲインを抑制する。)
When the voltage (V3) is negative, if the internal resistance of the enhancement type power MOSFET (85e-1) decreases, the input voltage (V3) of the operational amplifier also decreases, so that negative feedback is provided, so the enhancement type power MOSFET The operation is performed so that the voltage between the drain (D) and the source (S) of (85e-1) maintains a constant value.
Further, since the on-resistance of the enhancement type power MOSFET (85e-1) increases when the current (I2) decreases, it is possible to obtain a condition that makes it easy to detect the direction change of the current because of the negative feedback. it can.
In order to increase the current capacity, a plurality of enhancement type power MOSFETs can be connected in parallel. Different voltage-dividing resistors are passed through the gates (G), for example, so that the voltages to be turned on are different, the loop gain is lowered, and the current direction change can be easily detected. (Suppresses excessive gain by adding FET.)
電圧非降下型電源(80)を用いた理想ダイオード(82i)は、回路全体を2端子の理想ダイオード(82i)として取り扱うことができる。
図4(c)は、電圧非降下型電源(80)を用いた理想ダイオード(82i)を記号化して表現したものである。
カソード(K)から延びる矢印(NchMOSFETの場合。)で、内部回路に電源を供給していることを示す、理想ダイオード(82i)の記号である。
The ideal diode (82i) using the non-voltage drop type power supply (80) can handle the entire circuit as a two-terminal ideal diode (82i).
FIG. 4C is a symbolized representation of an ideal diode (82i) using a non-voltage drop type power supply (80).
An arrow extending from the cathode (K) (in the case of an Nch MOSFET) is a symbol of an ideal diode (82i) indicating that power is supplied to the internal circuit.
図4(d)は、同じく理想ダイオード(82i)を記号化して表現したものであるが、電圧非降下型電源(80)のコンデンサー(C1)を外付けにすることを明示している。(2端子として取り扱い可能なことに変わりはない。)
図4(e)は、図4(d)に示す記号を使用して、理想ダイオード(82i)で構成したブリッジ整流回路(24)を表現している。
ダイオード(Dc)と(Dd)は、アノード(A)同志を接続しているから、双方の共通線(80c)が同電位であるので、互いに電圧非降下型電源(80)を共有することができる。(モジュールを構成する場合などに有効である。)
FIG. 4D is also a representation of the ideal diode 82i symbolized, but clearly shows that the capacitor C1 of the non-voltage drop type power supply 80 is externally attached. (There is no change that it can be handled as two terminals.)
FIG. 4 (e) represents a bridge rectifier circuit (24) constituted by an ideal diode (82i) using the symbols shown in FIG. 4 (d).
Since the diodes (Dc) and (Dd) connect the anodes (A), both the common lines (80c) have the same potential. Therefore, the non-voltage drop type power supply (80) can be shared with each other. it can. (Effective when configuring a module.)
ダイオード(Da)と(Db)は、電源を供給する矢印の線がカソード(K)側であるから、共通線(80c)が同電位でなく、内蔵する電圧非降下型電源回路(80)を共有することはできない。
Pchのエハンスメント型のパワーMOSFETを用いて理想ダイオード(82i、電圧非降下型電源(80)を含む。)を構成した場合は、カソード同志が共通線(80c)となるので、ダイオード(Da)と(Db)の電圧非降下型電源(80)を互いに共有させることが可能である。
この場合、使用するオペアンプ(83)は、入力端子(+、-)の同相入力電圧が正の電源電圧付近の電圧となった場合においても、正常に動作する単一電源で動作可能なオペアンプを用いる必要がある。
In the diodes (Da) and (Db), since the arrow line for supplying power is on the cathode (K) side, the common line (80c) is not at the same potential, and the built-in non-voltage drop type power supply circuit (80) is provided. It cannot be shared.
When an ideal diode (82i, including a non-voltage drop type power supply (80)) is configured using an enhancement type power MOSFET of Pch, since the cathodes become a common line (80c), the diode (Da) It is possible to share the non-voltage drop type power supply (80) of (Db) with each other.
In this case, the operational amplifier (83) to be used is an operational amplifier that can operate with a single power source that operates normally even when the common-mode input voltage of the input terminals (+,-) becomes a voltage near the positive power supply voltage. It is necessary to use it.
NchとPchのエハンスメント型のパワーMOSFET(85e-1)を用いて構成した理想ダイオード(82i)を、それぞれダイオード(Da、Dc)とすると、交流電源2に接続する端子が共通線(80c)となるので、内部回路には正電源と負電源の両方が使用可能となるから、オペアンプ(83)に両電源用を使用することができる。(ダイオードDb、Ddの組合せでも同様である。)
コンデンサー(C1)を外付けとする記号について説明したが、使用するオペアンプの消費電流が小さい場合は、コンデンサー(C1)の容量も小さくできるので、全てを1つの集積回路にして完全な2端子化も可能と考えられる。
When the ideal diodes (82i) configured using Nch and Pch enhancement type power MOSFETs (85e-1) are respectively diodes (Da, Dc), the terminals connected to the AC power supply 2 are connected to the common line (80c). Therefore, since both a positive power source and a negative power source can be used in the internal circuit, the dual power source can be used for the operational amplifier (83). (The same applies to the combination of the diodes Db and Dd.)
We have explained the symbol that the capacitor (C1) is externally attached. However, if the current consumption of the operational amplifier used is small, the capacity of the capacitor (C1) can be reduced. Is also possible.
直流を得るための整流回路では、平滑用コンデンサー(C2)の電圧が加わるから、順方向に流れる電流の導通角が小さくなるが、非導通角では理想ダイオード(82i)に逆方向の電圧が加わるので、電圧非降下型電源(80)により、回路を駆動するための電力を得ることができる。
本応用回路1の理想ダイオード(82i)は、整流回路など、繰返し逆方向の電圧が加えられる用途に限られる。
 
In the rectifier circuit for obtaining direct current, the voltage of the smoothing capacitor (C2) is applied, so that the conduction angle of the current flowing in the forward direction is reduced, but the reverse voltage is applied to the ideal diode (82i) at the non-conduction angle. Therefore, power for driving the circuit can be obtained by the non-voltage drop type power supply (80).
The ideal diode (82i) of the application circuit 1 is limited to a use such as a rectifier circuit to which a reverse voltage is repeatedly applied.
<応用回路2>
 図5(a)は、第2の基本回路構成である複素電圧降下型電源(80j)とNchのエンハンスメント型のパワーMOSFET(85e-1)を用いて構成した、理想ダイオード(82j)である。
 複素電圧降下型電源(80j)の共通線(80c)をエンハンスメント型のパワーMOSFET(85e-1)のソース(S)に接続し、理想ダイオード(82i)のアノード(A)となり、ドレイン(D)がカソード(K)となる。
<Application circuit 2>
FIG. 5A shows an ideal diode (82j) configured using a complex voltage drop type power supply (80j) and an Nch enhancement type power MOSFET (85e-1), which are the second basic circuit configuration.
The common line (80c) of the complex voltage drop type power supply (80j) is connected to the source (S) of the enhancement type power MOSFET (85e-1) to become the anode (A) of the ideal diode (82i) and the drain (D) Becomes the cathode (K).
 複素電圧降下型電源(80j)からオペアンプ(83)に電源を供給し、エンハンスメント型のパワーMOSFET(85e-1)のドレイン(D)とソース(S)との間の電圧を、抵抗(Rs)を通してオペアンプ(83)の反転入力(-)と非反転入力(+)に加えて、極性検出器(83D)を構成している。
 ダイオード(82、D3)は、オペアンプ(83)の過大電圧の保護用である。
Power is supplied from the complex voltage drop type power supply (80j) to the operational amplifier (83), and the voltage between the drain (D) and the source (S) of the enhancement type power MOSFET (85e-1) is changed to the resistance (Rs). In addition to the inverting input (−) and the non-inverting input (+) of the operational amplifier (83), a polarity detector (83D) is configured.
The diode (82, D3) is for protecting an overvoltage of the operational amplifier (83).
 図5(b)は、理想ダイオード(82j)の整流動作の波形である。上段はエンハンスメント型のパワーMOSFET(85e-1)のドレイン(D)からソース(S)に流れる電流(I2)の流れを、下段はオペアンプ(83)の反転入力端子(-)の電圧(V3:鎖線)とオペアンプ(83)の出力電圧(V4:実線、ゲートGに加わる電圧でもある。)を表している。
 実際の電流(I2)は、寄生ダイオード(82p)の導通方向に流れるので、負で表されている。
FIG. 5B shows the waveform of the rectification operation of the ideal diode (82j). The upper stage shows the flow of the current (I2) flowing from the drain (D) to the source (S) of the enhancement type power MOSFET (85e-1), and the lower stage shows the voltage (V3) of the inverting input terminal (−) of the operational amplifier (83). (Chain line) and the output voltage of the operational amplifier (83) (V4: solid line, also applied to the gate G).
Since the actual current (I2) flows in the conduction direction of the parasitic diode (82p), it is expressed as negative.
 図5(c)に示すように、オペアンプ(83)の反転入力端子(-)の電圧(V3)が負になったとき(電流(I2)の向きが寄生ダイオード(82p)の導通方向であるとき。)は、オペアンプ(83)により反転増幅を行い、ゲート(G)に正の電圧(V4)を加えてエンハンスメント型のパワーMOSFET(85e-1)を導通状態にする。
 電流(I2)の方向が反転し、電圧(V3)が正となったときに素早くゲート(G)に加える電圧(V4)を0V以下に下げてパワーMOSFET(85e-1)を遮断する。
 負荷(R)が純抵抗である場合は、図5(c)に示すとおり、コンデンサー(C0)に交流電源(2)の正の半サイクルのみが加わり、この間にコンデンサー(C0)に往復両方向に電流(I1)が流れる。
 交流電源(2)の正の半サイクルの間に、コンデンサー(C1、C2)が順に充電される。
As shown in FIG. 5C, when the voltage (V3) of the inverting input terminal (−) of the operational amplifier (83) becomes negative (the direction of the current (I2) is the conduction direction of the parasitic diode (82p). ) Is inverted and amplified by the operational amplifier (83), and a positive voltage (V4) is applied to the gate (G) to make the enhancement type power MOSFET (85e-1) conductive.
When the direction of the current (I2) is reversed and the voltage (V3) becomes positive, the voltage (V4) applied to the gate (G) is quickly lowered to 0 V or less to cut off the power MOSFET (85e-1).
When the load (R L ) is a pure resistance, as shown in FIG. 5C, only the positive half cycle of the AC power source (2) is applied to the capacitor (C0), and during this time, the capacitor (C0) is reciprocated in both directions. A current (I1) flows through.
During the positive half cycle of the AC power supply (2), the capacitors (C1, C2) are charged in sequence.
 理想ダイオード(82j)の負荷に平滑用コンデンサー(C3)が加わると、図5(d)に示すとおり、理想ダイオード(82j)の導通角が狭くなるから、複素電圧降下型電源(80j)の共通線(80c)の電位(V0)を基準として、理想ダイオード(82j)に加わる電圧(V1)は、図5(e)に示すように、交流電源(2)の電圧に整流電圧が加わるから、正方向にシフトした電圧波形となる。 When a smoothing capacitor (C3) is added to the load of the ideal diode (82j), the conduction angle of the ideal diode (82j) becomes narrow as shown in FIG. With reference to the potential (V0) of the line (80c), the voltage (V1) applied to the ideal diode (82j) is, as shown in FIG. The voltage waveform is shifted in the positive direction.
 コンデンサー(C0)に流れる電流(I1)は、交流電源(2)の電圧に比例する。
 従って、交流1000V用に最適化した理想ダイオード(82j)は、交流100Vで使用すると駆動用の電力が不足する可能性があるから、使用電圧の範囲ごとに理想ダイオード(82j)を設計する必要がある。
 また、整流方式や交流電源(2)の周波数(50Hz、60Hzなど)によってもコンデンサー(C0)に流れる電流(I1)が異なるので、用途に合わせた設計をする必要がある。
The current (I1) flowing through the capacitor (C0) is proportional to the voltage of the AC power supply (2).
Therefore, since the ideal diode (82j) optimized for AC 1000V may be insufficient for driving when used at AC 100V, it is necessary to design the ideal diode (82j) for each range of operating voltage. is there.
In addition, the current (I1) flowing through the capacitor (C0) varies depending on the rectification method and the frequency (50 Hz, 60 Hz, etc.) of the AC power supply (2), so it is necessary to design for the application.
 図5(a)の回路では、AC100V、60Hzの電源に接続し、コンデンサー(C0)を0.1μFとしたとき、消費電流が0.5mA程度のオペアンプ(83)を駆動できる。
 消費電流が0.1mA程度のオペアンプ(83)を使用した場合、コンデンサー(C0)を0.02μFと小さくすることができる。
In the circuit of FIG. 5A, when connected to a power supply of AC 100V, 60 Hz and the capacitor (C0) is 0.1 μF, the operational amplifier (83) with a current consumption of about 0.5 mA can be driven.
When the operational amplifier (83) having a current consumption of about 0.1 mA is used, the capacitor (C0) can be reduced to 0.02 μF.
 正負両電源が使用できるので、使用するオペアンプ(83)の仕様を限定する必要が無い。
エンハンスメント型のパワーMOSFET(85e-1)のオン抵抗に流れる電流(I2)の向きを、負電圧の領域で直接比較することができるので、オペアンプ(83)の正入力端子(+)に抵抗分圧器(Radj)により数ミリボルトの負電圧を加える構成としている。
 
Since both positive and negative power supplies can be used, it is not necessary to limit the specifications of the operational amplifier (83) to be used.
Since the direction of the current (I2) flowing through the on-resistance of the enhancement type power MOSFET (85e-1) can be directly compared in the negative voltage region, the resistance component is connected to the positive input terminal (+) of the operational amplifier (83). A negative voltage of several millivolts is applied by a pressure device (Radj).
 オペアンプ(83)の反転入力端子(-)の電圧(V3)が負のときは、エンハンスメント型のパワーMOSFET(85e-1)の内部抵抗が減少すると、ゲート(G)の電圧(V3)も減少するので、負帰還となるから、エンハンスメント型のパワーMOSFET(85e-1)のドレイン(D)-ソース(S)間の電圧が一定値を保つように動作をする。
 また、負帰還となっているから、電流(I2)が減少したときにエンハンスメント型のパワーMOSFET(85e-1)のオン抵抗が上昇するが、電流の方向転換を検出し易い条件を得ることができる。
 ループゲインを調整して、理想ダイオード(82j)の動作範囲を用途に応じた設定にする。
When the voltage (V3) of the inverting input terminal (−) of the operational amplifier (83) is negative, the voltage (V3) of the gate (G) decreases when the internal resistance of the enhancement type power MOSFET (85e-1) decreases. Therefore, since negative feedback occurs, the operation is performed so that the voltage between the drain (D) and the source (S) of the enhancement type power MOSFET (85e-1) maintains a constant value.
In addition, since the negative feedback is provided, the on-resistance of the enhancement type power MOSFET (85e-1) increases when the current (I2) decreases, but it is possible to obtain a condition for easily detecting the direction change of the current. it can.
The loop gain is adjusted to set the operating range of the ideal diode (82j) according to the application.
 オペアンプ(83)の反転入力端子(-)の電圧(V3)が正のときは、その反転出力(V4)が共通線(80c)以下の電位に向かうので、エンハンスメント型のパワーMOSFET(85e-1)が遮断状態に向かう。
Pchのエンハンスメント型のパワーMOSFET(85e-1)を使用する場合は、導通方向が逆になるから、図5(a)のアノード(A)とカソード(K)の表示が逆となり、抵抗分圧器(Radj)を正電圧側に接続し、非反転入力端子(+)に数ミリボルトの正電圧を加える構成にする必要がある。
複素電圧降下型電源(80j)を用いた理想ダイオード(82j)は、回路全体を2端子の理想ダイオード(82j)として取り扱うことができる。
When the voltage (V3) of the inverting input terminal (−) of the operational amplifier (83) is positive, the inverting output (V4) is directed to the potential below the common line (80c), so that the enhancement type power MOSFET (85e-1 ) Goes to the shut-off state.
When the Pch enhancement type power MOSFET (85e-1) is used, the conduction direction is reversed, so that the display of the anode (A) and the cathode (K) in FIG. It is necessary to connect (Radj) to the positive voltage side and apply a positive voltage of several millivolts to the non-inverting input terminal (+).
The ideal diode (82j) using the complex voltage drop type power supply (80j) can handle the entire circuit as a two-terminal ideal diode (82j).
図6(a)は、Nchのエンハンスメント型のパワーMOSFET(85e-1)と複素電圧降下型電源(80j)を用いた理想ダイオード(82j)を記号化して表現したものである。
 記号は、カソード(K)から延びるコンデンサーの記号が付いた矢印で、内部回路に電源を供給していることを表している。
FIG. 6A is a symbolic representation of an ideal diode (82j) using an Nch enhancement type power MOSFET (85e-1) and a complex voltage drop type power supply (80j).
The symbol is an arrow with a capacitor symbol extending from the cathode (K), indicating that power is being supplied to the internal circuit.
図6(b)は、Pchのエンハンスメント型のパワーMOSFET(85e-1)を用いた理想ダイオード(82j)を記号化して表現したものである。
 Nchと比較すると、アノード(A)とカソード(K)が入れ替わり、矢印がアノード(A)から延びる矢印に変わる。
 図6(c)は、図6(a)の記号を使用して、ブリッジ整流回路(24)を構成したもので、図6(d)は、その動作波形を示す。
 平滑用コンデンサー(C3)の電圧が加わるから、順方向の電流(I2)の導通角が小さくなる。
 非導通角では、それぞれの理想ダイオード(82j)に逆方向の電圧が加わるので、複素電圧降下型電源(80j)により、回路を駆動するための電力を得ることができる。
FIG. 6B is a symbolized representation of an ideal diode (82j) using a Pch enhancement type power MOSFET (85e-1).
Compared with Nch, the anode (A) and the cathode (K) are interchanged, and the arrow changes to an arrow extending from the anode (A).
FIG. 6C shows the bridge rectifier circuit 24 using the symbols in FIG. 6A, and FIG. 6D shows its operation waveform.
Since the voltage of the smoothing capacitor (C3) is applied, the conduction angle of the forward current (I2) is reduced.
At the non-conduction angle, a reverse voltage is applied to each ideal diode (82j), so that power for driving the circuit can be obtained from the complex voltage drop type power supply (80j).
 理想ダイオード(82j)は、交流電源(2)の整流回路など、繰返し逆方向の電圧が加えられる用途に限られる。
 逆方向に加わる電圧範囲により、コンデンサー(C0)の耐圧と容量を選定する。
 図には、正と負の両電源構成の複素電圧降下型電源(80j)を用いた例を示したが、コンデンサー(C1)及びツェナーダイオード(Dz1)または、コンデンサー(C2)及びツェナーダイオード(Dz2)の何れか一方を省略して短絡する回路構成とすることで、正のみまたは負のみの単電源の複素電圧降下型電源回路(80j)を構成することができる。
The ideal diode (82j) is limited to applications where a voltage in the reverse direction is repeatedly applied, such as a rectifier circuit of the AC power supply (2).
The breakdown voltage and capacity of the capacitor (C0) are selected according to the voltage range applied in the reverse direction.
In the figure, an example using a complex voltage drop type power supply (80j) having both positive and negative power supply configurations is shown. However, a capacitor (C1) and a Zener diode (Dz1) or a capacitor (C2) and a Zener diode (Dz2) are shown. By omitting any one of () and making a short circuit, a complex voltage drop type power supply circuit (80j) of a single power source of only positive or only negative can be configured.
 若干の部品数削減を行うことが出来るが、単一電源とする場合、オペアンプ(83)の非反転入力(+)を共通線(80c)に接続し、反転入力(-)に抵抗器を介して数ミリボルトの電圧を加える構成にする必要がある。
 余剰電力を消費するツェナーダイオード(82z)の全部または一部をLEDに置き換えることにより、動作状態の表示、あるいは、理想ダイオード(82j)を組み込んだ機器の電源インジケータ等の光源に利用することができる。
 
Although the number of parts can be reduced slightly, in the case of a single power supply, the non-inverting input (+) of the operational amplifier (83) is connected to the common line (80c), and a resistor is connected to the inverting input (−). It is necessary to apply a voltage of several millivolts.
By replacing all or part of the Zener diode (82z) that consumes surplus power with LEDs, it can be used as a light source such as an indication of the operating state or a power indicator of a device incorporating the ideal diode (82j). .
<応用回路3>
 図7(a)は、第1の基本回路である電圧非降下型電源(80)、及び、2つのエンハンスメント型のパワーMOSFET(85e-1)を用いて構成した理想ダイオード(82ii)である。
 応用回路1では、複数の系統の太陽電池を並列に接続するために用いる逆流防止ダイオードでは、常時順方向の電流が流れ続けるため、駆動用の電力を得ることができない。 
図7(a)の理想ダイオード(82ii)は、エンハンスメント型のパワーMOSFET(85e-1)を一時的に遮断して、電圧非降下型電源(80)により駆動用の電力を得る構成である。
<Application circuit 3>
FIG. 7A shows an ideal diode (82ii) configured by using a non-voltage drop type power supply (80) which is a first basic circuit and two enhancement type power MOSFETs (85e-1).
In the application circuit 1, in the backflow prevention diode used for connecting the solar cells of a plurality of systems in parallel, a forward current always flows, and thus driving power cannot be obtained.
The ideal diode (82ii) in FIG. 7A has a configuration in which the enhancement type power MOSFET (85e-1) is temporarily cut off and driving power is obtained from the voltage non-drop-type power supply (80).
 2つのエンハンスメント型のパワーMOSFET(85e-1、85e-2)を使用し、逆方向に電圧が加えられた場合でも耐えることができ、順方向では電圧非降下型電源(80)を通して駆動用の電力を得た後、ゲート(G)に電圧を加えて、2つのエンハンスメント型のパワーMOSFET(85e-1、85e-2)を導通させている。
 オペアンプ(83)の差動入力端子の極性が応用回路1とは逆になっており、電流の方向に応じて、2つのエンハンスメント型のパワーMOSFET(85e-1、85e-2)を同時に導通と遮断を行うので、電流(I2)の方向が理想ダイオード(82ii)の順方向である。
Two enhancement type power MOSFETs (85e-1, 85e-2) can be used, and can withstand even when a voltage is applied in the reverse direction. After obtaining power, a voltage is applied to the gate (G) to make the two enhancement type power MOSFETs (85e-1, 85e-2) conductive.
The polarity of the differential input terminal of the operational amplifier (83) is opposite to that of the application circuit 1, and the two enhancement type power MOSFETs (85e-1, 85e-2) are simultaneously turned on according to the direction of the current. Since the interruption is performed, the direction of the current (I2) is the forward direction of the ideal diode (82ii).
 電圧非降下型電源(80)の電圧(V2)が、MOSFET(85e-3)のゲート閾値電圧(VGth-3)まで低下したとき、MOSFET(85e-3)が遮断し、オペアンプ(83)の反転入力(-)が0Vとなるから、出力を反転させて、2つのエンハンスメント型のパワーMOSFET(85e-1、85e-2)を遮断する。
 図に示していないが、MOSFET(85e-3)のゲート(G)に分圧抵抗器(89)を加えることで、反転する電圧を調整することができる。
When the voltage (V2) of the non-voltage drop type power supply (80) drops to the gate threshold voltage (V Gth-3 ) of the MOSFET (85e-3), the MOSFET (85e-3) is cut off and the operational amplifier (83) Since the inverting input (−) becomes 0 V, the output is inverted to cut off the two enhancement type power MOSFETs (85e-1, 85e-2).
Although not shown in the figure, the voltage to be inverted can be adjusted by adding a voltage dividing resistor (89) to the gate (G) of the MOSFET (85e-3).
 MOSFET(85e-3)のゲート(G)に接続されている高抵抗(88、Rg)と、ゲート(G)-ソース(S)間の静電容量(86p、Cg)との時定数τにより動作遅れを生じるので、コンデンサー(C1)に余分に充電を行うことができる。(電圧非降下型電源(80)の時定数τと競合するので、同程度に設定する。)
 遮断時にエンハンスメント型のパワーMOSFET(85e-1)のドレイン(D)-ソース(S)間の電圧が上昇するが、MOSFET(85e-3)により遮断されているので、オペアンプ(83)に影響は及ばない。
Due to the time constant τ between the high resistance (88, Rg) connected to the gate (G) of the MOSFET (85e-3) and the capacitance (86p, Cg) between the gate (G) and the source (S). Since an operation delay occurs, the capacitor (C1) can be charged excessively. (Since it competes with the time constant τ of the non-voltage drop type power supply (80), set it to the same level.)
The voltage between the drain (D) and the source (S) of the enhancement type power MOSFET (85e-1) rises at the time of interruption, but since it is cut off by the MOSFET (85e-3), the operational amplifier (83) is not affected. It doesn't reach.
 応用回路3の場合、電圧非降下型電源(80)のディプレッション型FET(85d)と分圧抵抗器(89、R1、R2)を省略して設計することも可能である。
この場合、ダイオード(82)のカソード(K)とコンデンサー(C1、+端子)を直結する。
ただし、図中のスイッチ(87、SW)を切断することで、太陽電池の系統を切り離すスイッチとして使用することが出来るが、系統の全ての電圧が掛かることを想定しなければならないから、ディプレッション型FET(85d)等を省略することができない。(スイッチ(87、SW)の挿入個所を変えれば、省略できる。)
In the case of the application circuit 3, it is possible to design by omitting the depletion type FET (85d) and the voltage dividing resistors (89, R1, R2) of the non-voltage drop type power supply (80).
In this case, the cathode (K) of the diode (82) and the capacitor (C1, + terminal) are directly connected.
However, it can be used as a switch to disconnect the solar cell system by disconnecting the switch (87, SW) in the figure, but it must be assumed that all voltages of the system are applied. The FET (85d) or the like cannot be omitted. (It can be omitted by changing the insertion point of the switch (87, SW).)
 図7(b)は、理想ダイオード(82ii)の記号(内部構成が異なるので、ダイオード記号の棒状の部分を白抜きにしている。)を使用して、太陽電池パネル(11)を並列接続した場合の接続例を示している。
 複数の系統の太陽電池パネル(11)が並列接続され、パワーコンディショナー(13)が最適条件の入力電圧で動作していた場合、1つの系統を遮断したときに5%程度の電圧上昇(系統の電圧が400Vの場合、約20V)が見込まれるから、系統毎に数十m秒程度の短時間の遮断を行なうことで駆動用の電力を得ることができる。
 2つのエンハンスメント型のパワーMOSFET(85e-1、85e-2)を使用する回路構成の場合、共通線(80c)を外部回路と共有することが出来ない。
 
FIG. 7 (b) shows the solar diode panel (11) connected in parallel using the symbol of the ideal diode (82ii) (the bar structure of the diode symbol is outlined because the internal configuration is different). A connection example is shown.
When solar panels (11) of a plurality of systems are connected in parallel and the power conditioner (13) is operating at the optimum input voltage, a voltage increase of about 5% when one system is shut down (system When the voltage is 400 V, about 20 V) is expected, and driving power can be obtained by performing a short interruption of about several tens of milliseconds for each system.
In the case of a circuit configuration using two enhancement type power MOSFETs (85e-1, 85e-2), the common line (80c) cannot be shared with an external circuit.
<応用回路4>
図8(a)は、第1の基本回路構成である電圧非降下型電源(80)と2つのエンハンスメント型のパワーMOSFET(85e-1、85e-2)で構成した、照度によりon-offする交流商用電源(2)に使用する電子スイッチ(84)である。
図8(b)は、動作波形である。(破線は、照度が大きいときの動作波形である。)
<Application circuit 4>
FIG. 8A shows a first basic circuit configuration, a non-voltage drop type power supply (80) and two enhancement type power MOSFETs (85e-1 and 85e-2), which are turned on and off according to illuminance. An electronic switch (84) used for the AC commercial power supply (2).
FIG. 8B shows an operation waveform. (The broken line is an operation waveform when the illuminance is large.)
 交流電源(2)の電圧が正のとき、ダイオード(82-1)、抵抗器(88、Rs)を通して、ダイオード(82-2)により、電圧非降下型電源(80)の電圧を超えないように制限している。さらに、分圧抵抗器(89、R3、R4)を通して、電圧(V3)がオペアンプ(83)の非反転入力端子(+)に加えられる。
 オペアンプ(83)の反転入力端子(-)には、光センサー(84s、CDS)と、抵抗器(88、Rh)とで分圧した電圧(V2)が加えられる。照度が大きいときは、光センサー(84s、CDS)の抵抗値が下がるので、反転入力端子(-)の電圧(V2)が上昇する。
 照度が大きいときに非反転入力端子(+)の電圧が、反転入力端子(-)の電圧(V2)を超えることが無いように分圧抵抗器(89、R3、R4)を設定しているから、オペアンプ(83)の出力端子は、0ボルトである。
When the voltage of the AC power supply (2) is positive, the voltage of the non-voltage drop type power supply (80) is not exceeded by the diode (82-2) through the diode (82-1) and the resistor (88, Rs). Restricted to Further, the voltage (V3) is applied to the non-inverting input terminal (+) of the operational amplifier (83) through the voltage dividing resistors (89, R3, R4).
A voltage (V2) divided by the optical sensor (84s, CDS) and the resistor (88, Rh) is applied to the inverting input terminal (−) of the operational amplifier (83). When the illuminance is high, the resistance value of the optical sensor (84s, CDS) decreases, and the voltage (V2) of the inverting input terminal (−) increases.
The voltage divider resistors (89, R3, R4) are set so that the voltage at the non-inverting input terminal (+) does not exceed the voltage (V2) at the inverting input terminal (−) when the illuminance is high. Therefore, the output terminal of the operational amplifier (83) is 0 volts.
 照度が下がり、反転入力端子(-)の電圧(V2)が下がると、非反転入力端子(+)の電圧(V3)が上回るから、交流電源(2)の電圧変化に応じて、オペアンプ(83)の出力が上昇し、ワンショットパルス発生器(84p)を駆動する。
ワンショットパルス発生器(84p)は、2つのエンハンスメント型のパワーMOSFET(85e-1、85e-2)のゲート(G)を駆動し、一定時間(t)導通させる。
When the illuminance decreases and the voltage (V2) of the inverting input terminal (−) decreases, the voltage (V3) of the non-inverting input terminal (+) increases, so that the operational amplifier (83 ) Rises to drive the one-shot pulse generator (84p).
The one-shot pulse generator (84p) drives the gates (G) of the two enhancement type power MOSFETs (85e-1 and 85e-2) and conducts them for a certain time (t).
図8(b)の動作波形のとおり、動作状態の電子スイッチ(84)は、電流(I2)を遮断して、電圧非降下型電源(80)の充電を行っている。
電圧非降下型電源(80)の充電に支障を来さないように、ワンショットパルス発生器(84p)の出力パルス幅(t)を交流電源(2)の周期(T)より若干短く設定する。
ダイオード(82-3)、コンデンサー(C3)及び抵抗器(88、Rf)により、オペアンプ(83)の非反転入力端子(+)に正帰還を与え、on-offの遷移を確実にするため、ヒステリシスを持たせている。
 
As shown in the operation waveform of FIG. 8B, the electronic switch (84) in the operating state cuts off the current (I2) and charges the non-voltage drop type power supply (80).
The output pulse width (t) of the one-shot pulse generator (84p) is set slightly shorter than the cycle (T) of the AC power supply (2) so as not to hinder the charging of the non-voltage drop type power supply (80). .
In order to provide positive feedback to the non-inverting input terminal (+) of the operational amplifier (83) by the diode (82-3), the capacitor (C3) and the resistor (88, Rf), and to ensure the on-off transition, Has hysteresis.
<応用回路5>
 図9(a)は、第1の基本回路構成である電圧非降下型電源(80)とエンハンスメント型のパワーMOSFET(85e-1)で構成した電子スイッチ(84)である。
 直流電力を安全に配電するため、配電区間内で発生した放電を、確実に消弧出来ることが求められる。
 周期パルス発生器(84P)を内蔵し、エンハンスメント型のパワーMOSFET(85e-1)の断続を繰り返すとともに、遮断した瞬間に、電流(I1)が電圧非降下型電源(80)に流れ、駆動用の電力をコンデンサー(C1)に得る構成としている。
 無負荷時には、電圧非降下型電源(80)が完全に停止するので、無駄な電力を消費しない。
<Application circuit 5>
FIG. 9A shows an electronic switch (84) composed of a first non-voltage drop type power supply (80) and an enhancement type power MOSFET (85e-1) as the first basic circuit configuration.
In order to distribute DC power safely, it is required that the discharge generated in the distribution section can be extinguished reliably.
The periodic pulse generator (84P) is built in, and the enhancement type power MOSFET (85e-1) is repeatedly turned on and off, and at the moment of interruption, the current (I1) flows to the non-voltage drop type power supply (80) to drive Power is obtained in the capacitor (C1).
When there is no load, the non-voltage drop type power supply (80) is completely stopped, so that useless power is not consumed.
 図9(b)は、動作波形である。
 電圧(V1)は、電源(1)の電圧を、電圧(V4)は、ゲート(G)-ソース(S)間の電圧を、電流(I1)は、電圧非降下型電源(80)の充電電流を示している。
 電源(1)と負荷(R)が接続されたときに、電流(I1)が流れ、駆動用の電力をコンデンサー(C1)に得る。
 次に、周期パルス発生器(84P)は、エンハンスメント型のパワーMOSFET(85e-1)を一定時間導通させ、負荷(R)に電力を供給する。
 エンハンスメント型のパワーMOSFET(85e-1)を遮断したときに、電流(I1)が流れ、コンデンサー(C1)に駆動用の電力を得て、これを繰り返す。
 図9(a)の出力端子(80O)には、断続する直流が出力されるから、応用回路5の出力は、電圧が変化する電源(12)である。
FIG. 9B shows operation waveforms.
The voltage (V1) is the voltage of the power supply (1), the voltage (V4) is the voltage between the gate (G) and the source (S), and the current (I1) is the charge of the non-voltage drop type power supply (80). Current is shown.
When the power source (1) and the load (R L ) are connected, a current (I1) flows, and driving power is obtained in the capacitor (C1).
Next, the periodic pulse generator (84P) conducts the enhancement type power MOSFET (85e-1) for a certain period of time, and supplies power to the load (R L ).
When the enhancement type power MOSFET (85e-1) is cut off, the current (I1) flows, and driving power is obtained in the capacitor (C1), and this is repeated.
Since an intermittent direct current is output to the output terminal (80O) of FIG. 9A, the output of the application circuit 5 is a power supply (12) whose voltage changes.
 図9(c)は、周期パルス発生器(84P)により駆動する電子スイッチ(84)を記号化して表現したものである。
 周期パルス発生器(80P)を内蔵しない場合は、その電圧が変化する電源(12)に接続して使用する必要がある。
 容量性の負荷など、出力端子(80O)の電圧が下がらない場合は、駆動電力が得られないことがある。
 寄生ダイオード(82p)の影響があるので、電子スイッチ(84)に加える電圧の向きが制限される。
 
FIG. 9C is a symbolized representation of the electronic switch (84) driven by the periodic pulse generator (84P).
When the periodic pulse generator (80P) is not built in, it is necessary to connect and use the power supply (12) whose voltage changes.
When the voltage of the output terminal (80O) does not decrease, such as a capacitive load, driving power may not be obtained.
Due to the influence of the parasitic diode (82p), the direction of the voltage applied to the electronic switch (84) is limited.
<応用回路6>
 図10(a)は、第1の基本回路構成である電圧非降下型電源(80)とN-chのエンハンスメント型のパワーMOSFET(85e-1)、P-chのMOSFET(85x)、並びに、電圧非降下型電源(80)からの電力で動作する過電流検出器(84I)、保安電極電流検出器(84g)を備え、あるいは図には示していないが、その他のセンサー(地震、火災)の信号などにより多彩な動作ができる電子スイッチ(84)である。
<Application circuit 6>
FIG. 10A shows a first non-voltage drop type power supply (80) and an N-ch enhancement type power MOSFET (85e-1), a P-ch MOSFET (85x), and a first basic circuit configuration. Equipped with an overcurrent detector (84I) and safety electrode current detector (84g) that operate with power from a non-voltage drop type power supply (80), or other sensors (earthquake, fire) not shown in the figure This is an electronic switch (84) that can be operated in various ways according to the above signal.
 図10(b)は、動作波形である。
 電圧(V1)は、電源(1)の電圧を、電圧(V4)は、ゲート(G)-ソース(S)間の電圧を、電流(I1)は、電圧非降下型電源(80)の充電電流を、電流(I3)は、PchのMOSFET(85x)の電流を示している。
 電源(1)と負荷(R)が接続されたときに、電流(I1)が流れ、駆動用の電力をコンデンサー(C1)に得る。
 エンハンスメント型のパワーMOSFET(85e-1)を一定時間導通させ、負荷に電力を供給する。
 エンハンスメント型のパワーMOSFET(85e-1)を遮断したときに、負荷(R)が容量性である場合は、負荷両端の電圧を維持するから、十分な電流(I1)が流れない可能性がある。
FIG. 10B shows an operation waveform.
The voltage (V1) is the voltage of the power supply (1), the voltage (V4) is the voltage between the gate (G) and the source (S), and the current (I1) is the charge of the non-voltage drop type power supply (80). The current (I3) indicates the current of the Pch MOSFET (85x).
When the power source (1) and the load (R L ) are connected, a current (I1) flows, and driving power is obtained in the capacitor (C1).
The enhancement type power MOSFET (85e-1) is turned on for a certain period of time to supply power to the load.
When the enhancement type power MOSFET (85e-1) is cut off, if the load (R L ) is capacitive, the voltage across the load is maintained, so there is a possibility that sufficient current (I1) does not flow. is there.
 そこで、エンハンスメント型のパワーMOSFET(85e-1)を遮断した直後に、PchのMOSFET(85x)をパルス駆動して、負荷(R)を短絡し、電流(I1、I3)得て、駆動用の電力を確保する構成である。
 PchのMOSFET(85x)の駆動は、負の電圧が必要であるから、容量結合(Cc、R4)により、負のパルス状の電圧をゲート(G)に加えている。
 同時に、負荷側に使用されている理想ダイオード(82i、82j、82ii)にコンデンサー(C6)に蓄積した電圧を利用して逆方向の電圧を与え、駆動用の電力を確保する構成である。(図には示していないが、エンハンスメント型のパワーMOSFET(85e-2)を有する場合は、PchのMOSFET(85x)と同時に導通させる。)
Therefore, immediately after the enhancement type power MOSFET (85e-1) is cut off, the Pch MOSFET (85x) is pulse-driven to short-circuit the load (R L ) to obtain currents (I1, I3) for driving. It is the structure which ensures the electric power of.
Since driving of the Pch MOSFET (85x) requires a negative voltage, a negative pulse voltage is applied to the gate (G) by capacitive coupling (Cc, R4).
At the same time, a reverse voltage is applied to the ideal diodes (82i, 82j, 82ii) used on the load side by using the voltage accumulated in the capacitor (C6) to secure driving power. (Although not shown in the figure, when the enhancement type power MOSFET (85e-2) is provided, the enhancement type power MOSFET (85e-2) is turned on simultaneously with the Pch MOSFET (85x).)
 容量性の負荷(R)であっても確実に電流(I1)を得ることができるが、無負荷時においても、駆動用の電力を得て動作を継続するから、図には示していないが、負荷(R)への供給電流(I2)を監視し、無負荷の場合は動作を停止するように構成することが望ましい。
 少ない電流を確実に検出するために、エンハンスメント型のパワーMOSFET(85e-1)の電圧降下が十ミリボルト前後の一定値となるよう負帰還路を形成して制御することで、オン抵抗を増加した状況においても、電圧降下が数ミリボルト以下なら無負荷であると確実に検出することができる。
Even if it is a capacitive load (R L ), the current (I1) can be obtained with certainty, but even when there is no load, it is not shown in the figure because it continues to operate with power for driving. However, it is desirable to monitor the supply current (I2) to the load (R L ) and stop the operation when there is no load.
In order to reliably detect a small current, the on-resistance was increased by forming a negative feedback path and controlling the voltage drop of the enhancement type power MOSFET (85e-1) to be a constant value around 10 millivolts. Even in the situation, if the voltage drop is several millivolts or less, it can be reliably detected that there is no load.
 図10(c)は、電子スイッチ(84)の記号を用いて、電力を断続する直流配電用の安全ブレーカー(31)を表現したものである。
 
FIG. 10C represents a safety breaker (31) for direct current distribution that interrupts power using the symbol of the electronic switch (84).
<応用回路7>
 図11は、第1の基本回路構成である電圧非降下型電源(80)を含む電子スイッチ(84)を用いた電力を断続する「直流配電システム」である。
 直流配電システムは、配電盤(3)から異なる時刻に断続する直流電力を2系統の配線により供給し、電気機器(6)側の理想ダイオード(82i、82j、82ii)で合成することで、断続の無い直流電力を受け取ることができる構成を採っている。(小電力の電気機器(6)にあっては、1系統の供給で動作させる。商用交流電源の単相3線式の配線と同様に、大電力の電気機器(6)に適用する。特許文献6)
<Application circuit 7>
FIG. 11 shows a “DC power distribution system” that intermittently supplies power using an electronic switch (84) including a non-voltage drop type power supply (80) that is a first basic circuit configuration.
The DC power distribution system supplies intermittent power at different times from the power distribution board (3) through two lines of wiring, and combines them with ideal diodes (82i, 82j, 82ii) on the electrical equipment (6) side. It has a configuration that can receive no DC power. (In the case of the low-power electric device (6), it is operated by supplying one system. Similar to the single-phase three-wire wiring of the commercial AC power supply, it is applied to the high-power electric device (6). Reference 6)
 2つの系統を、交互に断続するためには、相互に同期させなければならない。
図11に示すようにNchのエンハンスメント型のパワーMOSFETを使用した電子スイッチ(84、Sa、Sb)を直流電源(1)の正極側に配置して回路の断続をしようとすると、2つの電子スイッチ(84、Sa、Sb)の共通線(80c、図には示していない。)が共通でないため、同期のための回路を直接接続することができない。
In order to alternately interrupt the two systems, they must be synchronized with each other.
As shown in FIG. 11, when an electronic switch (84, Sa, Sb) using an Nch enhancement type power MOSFET is arranged on the positive electrode side of the DC power supply (1) to try to interrupt the circuit, two electronic switches Since the common line (80c, not shown in the drawing) of (84, Sa, Sb) is not common, a circuit for synchronization cannot be directly connected.
 図に示していないが、Pchのエンハンスメント型のパワーMOSFETを用いると、直流電源の正極側が共通線(80c、2つのパワーMOSFETを使用する場合を除く。)となるので、同期のための回路などを容易に接続することができる。
 なお、図11に示すように、フォトカプラー(84c)などを使用すれば、電位の異なる回路間においても簡単に接続することが出来るから、電子スイッチ(84、Sa、Sb)の開閉の他、図11に示すように商用交流電源(2)と周期パルス発生器(84P)の同期も容易である。
Although not shown in the figure, when a Pch enhancement type power MOSFET is used, the positive side of the DC power supply becomes a common line (except when 80c and two power MOSFETs are used). Can be easily connected.
As shown in FIG. 11, if a photocoupler (84c) or the like is used, it is possible to easily connect between circuits having different potentials. Therefore, in addition to opening / closing of the electronic switches (84, Sa, Sb), As shown in FIG. 11, the commercial AC power source (2) and the periodic pulse generator (84P) can be easily synchronized.
 広く利用されている商用交流電源(2)が支配的な環境において、直流配電システムを導入するには、互換性を確保することが必須である。
 断続する直流(12)で動作する電気機器(6)は、商用交流電源(2)を全波整流した平滑しない直流(12)で動作するように設計することができる。
 理想ダイオード(82i、82j、82ii)のブリッジ整流器(24)を内蔵した変換プラグ、変換コンセントを使用して、直流で動作する電気機器(6)は、商用交流電源(2)にも接続可能である。
 
In order to introduce a DC power distribution system in an environment where a commercial AC power source (2) that is widely used is dominant, it is essential to ensure compatibility.
The electric device (6) that operates with the intermittent direct current (12) can be designed to operate with the non-smooth direct current (12) obtained by full-wave rectification of the commercial AC power supply (2).
Using a conversion plug and conversion outlet with a built-in bridge rectifier (24) of ideal diodes (82i, 82j, 82ii), electrical equipment (6) operating on DC can be connected to commercial AC power supply (2) is there.
 商用電源に電子スイッチなどを使用する場合、駆動するための微小な直流電源が必要である。
 本願は、微小な直流電力を効率的にかつ簡便に得る方法と、その電力を使用してパワーMOSFET等を駆動して、実用的な理想ダイオードや電子スイッチを提供することができ、効率のよい整流回路、直流配電システムなどを構成することができる。
 
When an electronic switch or the like is used for a commercial power supply, a minute DC power supply for driving is necessary.
The present application can provide a practical ideal diode or electronic switch by efficiently and easily obtaining a minute DC power, and driving a power MOSFET or the like using the power to provide a practical ideal diode or electronic switch. A rectifier circuit, a DC power distribution system, or the like can be configured.
1 直流電源 11 太陽電池 12 半波・両波整流(非平滑)、断続する直流 
  (変換器)13 パワーコンディショナー(直流交流変換器)
2 交流電源 
  (整流器)24 両波整流器(ブリッジ整流器)
3 配線盤  30 メインブレーカー 31 安全ブレーカー 3f フィルター
4 コンセント 5 プラグ 6 電気機器 69 内部回路
8 部品 80 電圧非降下型電源 80j 複素電圧降下型電源
     80c 共通線 80o 電源出力端子 80O 出力端子(応用回路の出力端子)
     81 電源入力端子
     82 ダイオード(D1、D2) 82p 寄生ダイオード 
     82i、82j、82ii 理想ダイオード(Da~Dd) 
     82b ブリッジ整流器
     82z ツェナーダイオード(Dz1、Dz2)
     83 オペアンプ(単一電源用) 83D 極性検出器 
     84 電子スイッチ(S、Sp、Sa、Sb、Spa~Spb)
     84c フォトカップラー 84d FETドライバ 
     84g 保安電極電流検出器 84I 過電流検出器
     84P 周期パルス発生器 84p ワンショットパルス発生器
     84s 各種センサー(人感センサー・照度センサー等)
     85d ディプレッション型FET(Nch)
     85e 85e-1~3 エンハンスメント型のパワーMOSFET(Nch)
     85x エンハンスメント型のMOSFET(Pch)
     86 コンデンサー(C0、C0a~C0d、C1、C1a~C1d、C2、C3、C4、C6、Cc、Ci) 
     86p 静電容量(Cg、C
     87 スイッチ(SW)
     88 抵抗器(Rf,Rg、R、R、Rs、Rz)
     89 分圧抵抗器(R1、R2、R3、R4、Radj
9 その他  90 接地(大地) 91 筐体
I 電流(I1、I2)
V 電圧(V1~V4、V0:電圧の基準、共通線80c)
 
1 DC power supply 11 Solar cell 12 Half-wave / double-wave rectification (non-smooth), intermittent DC
(Converter) 13 Power conditioner (DC / AC converter)
2 AC power supply
(Rectifier) 24 double-wave rectifier (bridge rectifier)
3 Wiring board 30 Main breaker 31 Safety breaker 3f Filter 4 Outlet 5 Plug 6 Electrical equipment 69 Internal circuit 8 Parts 80 Non-voltage drop type power supply 80j Complex voltage drop type power supply 80c Common line 80o Power supply output terminal 80O Output terminal (Output of application circuit) Terminal)
81 Power input terminal 82 Diode (D1, D2) 82p Parasitic diode
82i, 82j, 82ii Ideal diode (Da to Dd)
82b Bridge rectifier 82z Zener diode (Dz1, Dz2)
83 operational amplifier (for single power supply) 83D polarity detector
84 Electronic switch (S, Sp, Sa, Sb, Spa-Spb)
84c Photocoupler 84d FET driver
84g Safety electrode current detector 84I Overcurrent detector 84P Periodic pulse generator 84p One shot pulse generator 84s Various sensors (human sensor, illuminance sensor, etc.)
85d Depletion type FET (Nch)
85e 85e-1 to 3 enhancement type power MOSFET (Nch)
85x enhancement type MOSFET (Pch)
86 Capacitors (C0, C0a to C0d, C1, C1a to C1d, C2, C3, C4, C6, Cc, Ci)
86p Capacitance (Cg, C G )
87 Switch (SW)
88 resistors (Rf, Rg, R h , R L , Rs, Rz)
89 Voltage divider resistors (R1, R2, R3, R4, R adj )
9 Others 90 Grounding (ground) 91 Case I Current (I1, I2)
V voltage (V1 to V4, V0: voltage reference, common line 80c)

Claims (7)

  1.  ディプレッション型FET(85d、Nch及びPchのMOS型及びジャンクション型の電界効果トランジスタ。以下同じ。)、コンデンサー(86、C1)、並びに、ダイオード(82)を備え、
     前記ディプレッション型FET(85d)の
      ドレイン(D)を、前記ダイオード(82)を通して電源入力端子(81)に、
      ゲート(G)を、分圧抵抗器(89、R1、R2)に、抵抗器(88)を通してあるいは直接に、
      ソース(S)を、前記分圧抵抗器(89、R1)の1つ、前記コンデンサー(86、C1)及び出力端子(80o)に、
     前記コンデンサ(86、C1、他の端子)と前記分圧抵抗器(89、R2)の他の1つを共通線(80c)に、それぞれ接続し、
     前記共通線(80c)と前記出力端子(80o)を出力とする回路を構成し、
     前記電源入力端子(81)の電圧が、必要とする電圧前後の電圧となるときに、
     前記ディプレッション型FET(85d)のゲート(G)-ソース(S)間の静電容量(86p、Cg、C)とゲート(G)に直列に入る抵抗(前記抵抗器88および前記分圧抵抗器89の合成抵抗値)との時定数τによる動作遅延により、前記ディプレッション型FET(85d)を通して、前記コンデンサー(86、C1)に前記分圧抵抗器(89、R1、R2)の分圧比により決まる電圧より高い電圧まで充電を行うことで、電力損失を伴う電圧降下を避けて直流電力を得ることを特徴とする電圧非降下型電源(80)。
     
    A depletion type FET (85d, Nch and Pch MOS type and junction type field effect transistors; the same applies hereinafter), a capacitor (86, C1), and a diode (82),
    The drain (D) of the depletion type FET (85d) is connected to the power input terminal (81) through the diode (82).
    The gate (G) is connected to the voltage dividing resistor (89, R1, R2) through the resistor (88) or directly.
    A source (S) is connected to one of the voltage dividing resistors (89, R1), the capacitor (86, C1) and the output terminal (80o).
    Connecting the capacitor (86, C1, other terminal) and the other one of the voltage dividing resistors (89, R2) to a common line (80c), respectively;
    Configure a circuit that outputs the common line (80c) and the output terminal (80o),
    When the voltage of the power input terminal (81) becomes a voltage around the required voltage,
    Capacitance (86p, Cg, C G ) between the gate (G) and the source (S) of the depletion type FET (85d) and a resistor (the resistor 88 and the voltage dividing resistor) in series with the gate (G) Due to the operation delay due to the time constant τ with respect to the combined resistance value of the capacitor 89, through the depletion type FET (85d), the voltage dividing ratio of the voltage dividing resistor (89, R1, R2) to the capacitor (86, C1) A non-voltage drop type power supply (80) characterized in that a DC power is obtained by avoiding a voltage drop accompanied by power loss by charging to a voltage higher than a determined voltage.
  2.  電圧非降下型電源(80)及びエンハンスメント型のパワーMOSFET(85e、Nch及びPchのMOS型電界効果トランジスタ。電流容量を増すために同じ型の複数のFETを並列接続したものを含む。以下同じ。)を備え、
     ドレイン(D)を前記電圧非降下型電源(80)及び電源入力端子(81)に、
     ソース(S)を共通線(80c)と出力端子(80O)に、それぞれ接続し、
     前記電圧非降下型電源(80)で得た電力により、前記エンハンスメント型のパワーMOSFET(85e-1)のソース(S)とゲート(G)との間に電圧を加えて制御する電子スイッチ(84)を構成することを特徴とする請求項1に記載の電圧非降下型電源(80)の応用回路。
     
    Non-voltage drop type power supply (80) and enhancement type power MOSFET (85e, Nch and Pch MOS field effect transistors, including a plurality of FETs of the same type connected in parallel to increase current capacity, and so on. )
    The drain (D) is connected to the non-voltage drop type power supply (80) and the power supply input terminal (81).
    The source (S) is connected to the common line (80c) and the output terminal (80O), respectively.
    An electronic switch (84) controlled by applying a voltage between the source (S) and the gate (G) of the enhancement type power MOSFET (85e-1) by the electric power obtained from the non-voltage drop type power source (80). The application circuit of the non-voltage drop type power supply (80) according to claim 1, wherein
  3.  電圧非降下型電源(80)及びエンハンスメント型のパワーMOSFET(85e、Nch及びPchのMOS型電界効果トランジスタ。電流容量を増すために同じ型の複数のFETを並列接続したものを含む。以下同じ。)を2個(複数のFETを並列接続したものである場合は、2組)を備え、
     前記2個(2組)の前記エンハンスメント型のパワーMOSFET(85e-1、85e-2)のソース(S)同志及びゲート(G)同志を接続して、直列接続したものであって、
     一方(85e-1)のドレイン(D)を前記電圧非降下型電源(80)及び電源入力端子(81)に、
     他方(85e-2)のドレイン(D)を出力端子(80O)に
     双方(85e-1、85e-2)のソース(S)を共通線(80c)に、それぞれ接続し、
     前記電圧非降下型電源(80)で得た電力により、前記エンハンスメント型のパワーMOSFET(85e-1、85e-2)のソース(S)とゲート(G)との間に電圧を加えて制御する双方向の電圧に対処できる電子スイッチ(84)を構成することを特徴とする請求項1に記載の電圧非降下型電源(80)の応用回路。
     
    Non-voltage drop type power supply (80) and enhancement type power MOSFET (85e, Nch and Pch MOS field effect transistors, including a plurality of FETs of the same type connected in parallel to increase current capacity, and so on. ) 2 (2 sets if a plurality of FETs are connected in parallel),
    The source (S) and gate (G) of the two (two sets) enhancement type power MOSFETs (85e-1, 85e-2) are connected and connected in series,
    On the other hand, the drain (D) of (85e-1) is connected to the non-voltage drop type power supply (80) and the power input terminal (81).
    Connect the drain (D) of the other (85e-2) to the output terminal (80O) and the sources (S) of both (85e-1, 85e-2) to the common line (80c),
    Control is performed by applying a voltage between the source (S) and the gate (G) of the enhancement type power MOSFETs (85e-1, 85e-2) by the electric power obtained from the non-voltage drop type power supply (80). The application circuit of the non-voltage drop power supply (80) according to claim 1, characterized in that it constitutes an electronic switch (84) capable of dealing with bidirectional voltages.
  4.  電圧非降下型電源(80)及びエンハンスメント型のパワーMOSFET(85e、Nch及びPchのMOS型電界効果トランジスタ。並列接続したもの及び直列接続したもの並びに両方を行ったものを含む。以下同じ。)を備え、
     前記電圧非降下型電源(80)に必要以上の電圧が加えられない環境(加えられる電圧が内部回路の部品の耐圧よりも低い、あるいは、必要な電圧の電力を蓄積した後、前記電圧非降下型電源(80)と並列に接続された前記エンハンスメント型のパワーMOSFET(85e-1、85e-2)を導通させ、必要以上の電圧が加えられることがない環境。)で使用する場合において、前記電圧非降下型電源(80)を構成するディプレッション型FET(85d)を省略(ゲート(G)に接続された抵抗器(88)、分圧抵抗器(89)を含めて取り除き、除去したディプレッション型FET(85d)のドレイン(D)とソース(S)への配線を直結する。)したことを特徴とする、
     請求項1から3のいずれか1項に記載の電圧非降下型電源(80)の応用回路。
     
    Non-voltage drop type power supply (80) and enhancement type power MOSFET (85e, Nch and Pch MOS type field effect transistors. Including those connected in parallel and those connected in series, and the same). Prepared,
    An environment in which an unnecessarily high voltage is not applied to the non-voltage drop type power supply (80) (the applied voltage is lower than the withstand voltage of the components of the internal circuit, or after storing the necessary voltage power, the voltage non-drop In an environment where the enhancement type power MOSFETs (85e-1, 85e-2) connected in parallel with the type power supply (80) are made conductive and an excessive voltage is not applied). The depletion type FET (85d) constituting the non-voltage drop type power supply (80) is omitted (the depletion type removed by removing the resistor (88) and the voltage dividing resistor (89) connected to the gate (G)). The wiring to the drain (D) and the source (S) of the FET (85d) is directly connected.)
    The application circuit of the non-voltage drop type power supply (80) according to any one of claims 1 to 3.
  5.  電圧非降下型電源(80)、エンハンスメント型のパワーMOSFET(85e、Nch及びPchのMOS型電界効果トランジスタ。同じ型のFETを並列接続したもの及び直列接続したもの並びに両方を行ったものを含む。以下同じ。)、及び、エンハンスメント型のMOSFET(85x、Pch及びNchのMOS型電界効果トランジスタであって、前記エンハンスメント型のパワーMOSFET(85e-1)と異なるチャンネル型のMOSFET)を備え、
     前記電圧非降下型電源(80)と前記エンハンスメント型のパワーMOSFET(85e-1)を並列接続して、電源と負荷(R)との間に直列に接続、及び、
     前記エンハンスメント型のMOSFET(85x)を負荷(R)に対して並列に接続した構成とし、
    前記エンハンスメント型のパワーMOSFET(85e、85e-1)を遮断するとともに、
     前記エンハンスメント型のMOSFET(85x)のドレイン(D)とソース(S)間を導通することにより、負荷(R)に関わらず、前記電圧非降下型電源(80)に電力を得ることを特徴とする、
     請求項1から4のいずれか1項に記載の電圧非降下型電源(80)の応用回路。
     
    Non-voltage drop type power supply (80), enhancement type power MOSFET (85e, Nch and Pch MOS field effect transistors. Including those in which FETs of the same type are connected in parallel and in series, and both. The same shall apply hereinafter), and an enhancement type MOSFET (85x, Pch and Nch MOS field effect transistors, which are different from the enhancement type power MOSFET (85e-1)).
    The non-voltage drop type power supply (80) and the enhancement type power MOSFET (85e-1) are connected in parallel, and connected in series between the power supply and a load (R L ), and
    The enhancement type MOSFET (85x) is connected in parallel to the load (R L ),
    Shuts off the enhancement type power MOSFETs (85e, 85e-1);
    By conducting between the drain (D) and the source (S) of the enhancement type MOSFET (85x), power is obtained from the non-voltage drop type power supply (80) regardless of the load (R L ). And
    The application circuit of the non-voltage drop type power supply (80) according to any one of claims 1 to 4.
  6.  電圧非降下型電源(80)及びエンハンスメント型のパワーMOSFET(85e、Nch及びPchのMOS型電界効果トランジスタを並列接続したもの及び直列接続したもの並びに両方を行ったものを含む。以下同じ。)並びに、
     電流方向検出器(83D、オペアンプ83等により構成するものを含む。以下同じ。)を備え、
     電源と負荷(R)との間に直列接続した前記電圧非降下型電源(80)に電圧が加えられた時に、駆動に必要な電圧の電力を蓄積し、
     前記電流方向検出器(83D)により電流の方向を検出し、出力端子(80O)に接続された前記エンハンスメント型のパワーMOSFET(85e-1、85e-2)の寄生ダイオード(82p)の導通方向に電流が流れるときのみ、ソース(S)とゲート(G)間に電圧を加えて、ドレイン(D)とソース(S)間を導通させる、
     2端子として取り扱うことができる理想ダイオード(82i、82ii)を構成することを特徴とする、
     請求項1から4のいずれか1項に記載の電圧非降下型電源(80)の応用回路。
     
    Non-voltage drop type power supply (80) and enhancement type power MOSFET (including those in which 85e, Nch and Pch MOS field effect transistors are connected in parallel and connected in series, and both are applied. The same applies hereinafter) and ,
    A current direction detector (including those composed of 83D, operational amplifier 83, etc., the same shall apply hereinafter)
    When voltage is applied to the non-voltage drop type power source (80) connected in series between the power source and the load (R L ), the power of the voltage necessary for driving is accumulated,
    The direction of current is detected by the current direction detector (83D), and the conduction direction of the parasitic diode (82p) of the enhancement type power MOSFET (85e-1, 85e-2) connected to the output terminal (80O) is detected. Only when a current flows, a voltage is applied between the source (S) and the gate (G) to make the drain (D) and the source (S) conductive.
    An ideal diode (82i, 82ii) that can be handled as two terminals is configured.
    The application circuit of the non-voltage drop type power supply (80) according to any one of claims 1 to 4.
  7.  コンデンサー(C0、C1、C2)、ダイオード(D1、D2)、及び、ツェナーダイオード(Dz1、Dz2)を備え、
     直列に接続した前記ダイオード(D1、D2)の中点に前記コンデンサー(C0)を介して電源入力端子(81)に接続し、前記ダイオード(D1、D2)の他端に、一端を共通線(80c)に接続したコンデンサー(C1、C2)及びツェナーダイオード(82z、Dz1、Dz2)を接続し、正と負の直流電力を出力する両電源型の複素電圧降下型電源回路(80j)、並びに、
     当該複素電圧降下型電源回路(80j)の
      コンデンサー(C1)及びツェナーダイオード(82z、Dz1)または
      コンデンサー(C2)及びツェナーダイオード(82z、Dz2)の何れか一方を省略して、共通線(80c)に接続し、正のみまたは負のみの直流電力を出力する単一電源型の複素電圧降下型電源回路(80j)としたものを含み、
     前記の何れかの複素電圧降下型電源回路(80j)、オペアンプ(83)等を用いて構成した極性検出器(83D)、及び、エンハンスメント型のパワーMOSFET(85e:Nch及びPchのMOSFET。同じ型のMOSFETを並列接続したものを含む。以下同じ。)を備え、
     前記エンハンスメント型のパワーMOSFET(85e-1)のドレイン(D)とソース(S)をそれぞれ電源入力(81)と共通線(80c)に接続し、
     ドレイン(D)とソース(S)間の電圧を、過大電圧保護等の回路(Rs、D3、Radj)を介して前記極性検出器(83D)を構成するオペアンプ(83)の反転入力(-)と非反転入力(+)にそれぞれ接続し、
     前記エンハンスメント型のパワーMOSFET(85e-1)に流れる電流(電圧)の向きを前記極性検出器(83D)により検出してゲート(G)に加える電圧を制御し、寄生ダイオード(82p)の導通方向に電流が流れるときのみ、ソース(S)とゲート(G)間に電圧を加えて、ドレイン(D)とソース(S)導通させる、2端子として取り扱うことができることを特徴とする理想ダイオード(82j)。
     
    A capacitor (C0, C1, C2), a diode (D1, D2), and a Zener diode (Dz1, Dz2);
    The midpoint of the diodes (D1, D2) connected in series is connected to the power input terminal (81) via the capacitor (C0), and one end is connected to the other end of the diode (D1, D2) with a common line ( 80c) is connected to the capacitors (C1, C2) and the Zener diodes (82z, Dz1, Dz2), and outputs a positive and negative DC power, a dual power supply type complex voltage drop power supply circuit (80j), and
    Either the capacitor (C1) and the zener diode (82z, Dz1) or the capacitor (C2) and the zener diode (82z, Dz2) of the complex voltage drop type power supply circuit (80j) is omitted, and the common line (80c) And a single power supply type complex voltage drop type power supply circuit (80j) that outputs positive-only or negative-only DC power,
    A polarity detector (83D) configured using any of the complex voltage drop type power supply circuit (80j), the operational amplifier (83), and the like, and an enhancement type power MOSFET (85e: Nch and Pch MOSFETs, the same type). Including MOSFETs connected in parallel. The same shall apply hereinafter.)
    The drain (D) and source (S) of the enhancement type power MOSFET (85e-1) are connected to the power input (81) and the common line (80c), respectively.
    The voltage between the drain (D) and the source (S) is applied to the inverting input (−) of the operational amplifier (83) constituting the polarity detector (83D) through a circuit (Rs, D3, Radj) such as overvoltage protection. And non-inverting input (+) respectively,
    The direction of the current (voltage) flowing through the enhancement type power MOSFET (85e-1) is detected by the polarity detector (83D), and the voltage applied to the gate (G) is controlled to control the conduction direction of the parasitic diode (82p). An ideal diode (82j) that can be treated as a two-terminal device that conducts a drain (D) and a source (S) by applying a voltage between the source (S) and the gate (G) only when a current flows through ).
PCT/JP2018/004694 2017-02-14 2018-02-09 Non-voltage-dropping power supply circuit and application circuit WO2018151052A1 (en)

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JP2017-024516 2017-02-14
JP2017024516A JP6137723B1 (en) 2017-02-14 2017-02-14 Non-voltage drop type power supply circuit and its application circuit
JP2017109590A JP6191040B1 (en) 2017-06-01 2017-06-01 Ideal diode using complex voltage drop type power supply circuit
JP2017-109590 2017-06-01

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001224179A (en) * 2000-02-08 2001-08-17 Ntt Data Corp Rectifier and rectifying device
US20040046532A1 (en) * 2002-09-09 2004-03-11 Paolo Menegoli Low dropout voltage regulator using a depletion pass transistor
JP2005518010A (en) * 2002-02-18 2005-06-16 フリースケール セミコンダクター インコーポレイテッド Low dropout voltage regulator
JP2013255425A (en) * 2013-09-11 2013-12-19 Leach International Corp System and method for emulating ideal diode in power control device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001224179A (en) * 2000-02-08 2001-08-17 Ntt Data Corp Rectifier and rectifying device
JP2005518010A (en) * 2002-02-18 2005-06-16 フリースケール セミコンダクター インコーポレイテッド Low dropout voltage regulator
US20040046532A1 (en) * 2002-09-09 2004-03-11 Paolo Menegoli Low dropout voltage regulator using a depletion pass transistor
JP2013255425A (en) * 2013-09-11 2013-12-19 Leach International Corp System and method for emulating ideal diode in power control device

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