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WO2018146843A1 - Dispositif d'alimentation électrique - Google Patents

Dispositif d'alimentation électrique Download PDF

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Publication number
WO2018146843A1
WO2018146843A1 PCT/JP2017/031627 JP2017031627W WO2018146843A1 WO 2018146843 A1 WO2018146843 A1 WO 2018146843A1 JP 2017031627 W JP2017031627 W JP 2017031627W WO 2018146843 A1 WO2018146843 A1 WO 2018146843A1
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WIPO (PCT)
Prior art keywords
clock
power supply
output voltage
control signal
delay
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PCT/JP2017/031627
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English (en)
Japanese (ja)
Inventor
鳴 劉
純之 荒田
隆介 佐原
山脇　大造
豪一 小野
Original Assignee
日立オートモティブシステムズ株式会社
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Application filed by 日立オートモティブシステムズ株式会社 filed Critical 日立オートモティブシステムズ株式会社
Publication of WO2018146843A1 publication Critical patent/WO2018146843A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the present invention relates to a power supply device, and more particularly to a technique effective for controlling power by a power supply device that supplies power to an ECU (Electronic Control Unit) mounted on a vehicle.
  • ECU Electronic Control Unit
  • the operating voltage of in-vehicle ECUs tends to be lowered.
  • the operating voltage of a microcomputer used in an in-vehicle ECU is about 5V or 3.3V, but is about 1V or less.
  • the power supply device that supplies power to the ECU is also required to have a low voltage.
  • a switching power supply device is widely used.
  • the power supply voltage supplied from the battery is stepped down to generate a low voltage of about 1 V or less.
  • a switching power supply apparatus having a two-stage configuration in which two switching power supply circuits are connected in series is widely used, and the power supply voltage of the battery is sequentially stepped down by these two switching power supply circuits and supplied to the ECU. A power supply is generated.
  • the switching duty ratio is determined by the input / output voltage ratio. For example, when the input voltage is about 40V and the output voltage is about 1V, the switching duty ratio is 2.5%.
  • the switching frequency is increased, a switching circuit that can apply a duty ratio of 2.5% can be made.
  • the switching frequency is generally required to be 500 KHz or more depending on the specification of the power supply voltage fluctuation of the microcomputer in the ECU, and it is difficult to create a switching circuit that can apply a duty ratio of 2.5%.
  • the output voltage of the first switching power supply circuit in the two-stage configuration is generally used as a power supply voltage for other loads mounted on the ECU board, such as an A / D (Analog / Digital) converter. Since the performance of the A / D converter depends on the performance of the power supply voltage, that is, the accuracy of the power supply voltage, the output voltage ripple requirement of the first switching power supply circuit is higher.
  • a / D Analog / Digital
  • switching power supply circuit As for this type of switching power supply circuit, there is a switching power supply circuit having an appropriate number of cascade connection stages according to, for example, a voltage ratio between an input voltage and an output voltage (see, for example, Patent Document 1).
  • the switching frequency of the next-stage switching power supply circuit is set high in order to suppress the ripple of the output voltage of the first-stage switching power supply circuit. Need arises.
  • An object of the present invention is to provide a technique capable of generating a highly accurate power supply voltage with low loss without increasing a switching frequency in a switching power supply circuit.
  • a typical power supply device includes a first switching power supply circuit, a second switching power supply circuit, a first control circuit, a second control circuit, and a delay generation unit.
  • the first switching power supply circuit generates a first output voltage from an externally input voltage.
  • the second switching power supply circuit generates a second output voltage from the first output voltage.
  • the first control circuit controls the first output voltage generated by the first switching power supply circuit based on the first clock.
  • the second control circuit controls the second output voltage generated by the second switching power supply circuit based on the second clock.
  • the delay generation unit adjusts the frequency of the first clock and the frequency of the second clock to an integer multiple to reduce the delay between the first clock and the second clock and the ripple of the first output voltage. To control.
  • the first switching power supply circuit has a first switching unit
  • the second switching power supply circuit has a second switching unit.
  • the first switching unit switches the input voltage.
  • the second switching unit switches the first output voltage.
  • the first control circuit generates a first control signal for controlling the first switching unit from the first clock, and the second control circuit controls the second switching unit from the second clock.
  • a second control signal is generated.
  • the delay generation unit controls the phases of the first control signal and the second control signal to control the delays of the first clock and the second clock.
  • a typical power supply device has an edge detector.
  • the edge detector detects a signal rising edge or a signal falling edge between the first control signal and the second control signal.
  • the delay generation unit controls the delays of the first clock and the second clock so that the signal rising edges or signal falling edges of the first control signal and the second control signal are aligned.
  • FIG. 3 is an explanatory diagram illustrating an example of a configuration of a power supply device according to Embodiment 1.
  • FIG. It is explanatory drawing which shows an example of the phase relationship of the control signal which the control circuit of FIG. 1 produces
  • FIG. 10 is an explanatory diagram illustrating an example of a configuration of a power supply device according to a second embodiment. It is a timing chart which shows an example of each signal in the power supply device of FIG. 6 is a timing chart showing another example of each signal in the power supply device of FIG. 5.
  • FIG. 10 is an explanatory diagram illustrating an example of a configuration of a power supply device according to a second embodiment. It is a timing chart which shows an example of each signal in the power supply device of FIG. 6 is a timing
  • FIG. 10 is an explanatory diagram illustrating an example of a configuration of a power supply device according to a third embodiment. It is a timing chart which shows an example of each signal in the control part in the power supply device of FIG. It is explanatory drawing which shows an example of a structure of the power supply device in the comparison technique with respect to embodiment. It is explanatory drawing which shows an example of operation
  • FIG. 11 is an explanatory diagram illustrating an example of a cause of the worst case of output voltage ripple when the control signal generated by the control circuit of FIG. 10 has a phase difference. It is explanatory drawing which showed the example which reduces the ripple of the output voltage at the time of the worst case shown in FIG.
  • FIG. 10 is an explanatory diagram showing an example of the configuration of the power supply device in the comparison technique with respect to the present embodiment.
  • the power supply device has a configuration including a switching power supply circuit 30 and a switching power supply circuit 31, and the switching power supply circuits 30 and 31 are connected in series.
  • the first switching power supply circuit 30 generates the output voltage Vo1 from the input voltage Batt.
  • the input voltage Batt is a power supply voltage of a battery (not shown).
  • the output voltage Vo1 is a voltage lower than the battery voltage Batt.
  • the second switching power supply circuit 31 generates the output voltage Vo2 from the output voltage Vo1.
  • the output voltage Vo2 is a voltage lower than the output voltage Vo1.
  • the output voltage Vo1 is a first output voltage
  • the output voltage Vo2 is a second output voltage.
  • the load 49 connected to the power supply device is a load using the output voltage Vo1 as an operation power supply, and is an analog circuit such as an A / D converter, for example.
  • the load 50 connected to the power supply device is a load that uses the output voltage Vo2 as an operation power supply, and is, for example, a microcomputer.
  • the switching power supply circuit 30 includes a switching operation unit 1 and a control unit 3.
  • the switching power supply circuit 30 inputs a feedback voltage from the output voltage Vo1 to the control unit 3 and inputs a control signal Ctrl1 generated by the control unit 3 to the switching operation unit 1 to generate a desired output voltage value.
  • the control signal Ctrl1 is a first control signal.
  • the switching operation unit 1 includes a switching element 7, a switching element 8, an inductor 9, a smoothing output capacitor 10, and a driver 11.
  • the load 49 and the load 50 are driven while energy is stored in the inductor 9.
  • the switching element 7 is turned off and the switching element 8 is turned on, the energy accumulated in the inductor 9 is released, and the load 49 and the load 50 are driven.
  • the smoothing output capacitor 10 is a capacitor and suppresses the voltage ripple of the output voltage Vo1 of the switching power supply circuit 30.
  • the driver 11 is a drive circuit that drives the switching element 7 and the switching element 8 with a control signal Ctrl1 output from the control unit 3 to perform a switching operation.
  • the switching element 7 is composed of, for example, an N channel MOS (Metal Oxide Semiconductor) transistor, and the switching element 8 is composed of a P channel MOS transistor or the like.
  • the switching element 7 is turned on when the signal output from the driver 11 is a high signal, and the switching element 8 is turned on when the signal output from the driver 11 is a low signal.
  • the frequency divider 21 is a circuit that generates a clock that determines the on / off operation frequency of the switching element 7 and the switching element 8 of the switching power supply circuit 30 based on the reference clock from the clock generation circuit 4.
  • the control circuit 12 which is the first control circuit, is a circuit that generates the control signal Ctrl1 based on the feedback voltage at the output voltage Vo1 and the clock output from the frequency divider 21.
  • the frequency of the control signal Ctrl1 is determined by the frequency of the clock output from the frequency divider 21.
  • the control circuit 20 as the second control circuit generates the control signal Ctrl2 based on the feedback voltage in the output voltage Vo2 and the clock generated by the frequency divider 22.
  • the frequency of the control signal Ctrl2 is determined by the frequency of the clock generated by the frequency divider 22.
  • FIG. 11 is an explanatory diagram showing an example of the operation of the power supply device of FIG.
  • FIG. 11 shows the signal timing of the control signal Ctrl1 output from the control circuit 12 in the upper part, and the signal timing of the control signal Ctrl2 output from the control circuit 20 in the lower part.
  • a current IL that is an inductor current is an input current of the smoothing output capacitor 10
  • a current Io is an output current of the smoothing output capacitor 10.
  • control signals Ctrl1 and Ctrl2 are generated by the control circuits 12 and 20, respectively. Therefore, the phase relationship between the control signal Ctrl1 and the control signal Ctrl2 is not controlled. In other words, it is not fixed.
  • FIG. 12 illustrates an example of the cause of the worst case of the ripple in the output voltage Vo1 of the switching power supply circuit 30 when there is a phase difference between the control signal Ctrl1 and the control signal Ctrl2 generated by the control circuit of FIG. FIG.
  • the ripple of the output voltage Vo1 increases as the difference in charge amount between the input and output of the smoothing output capacitor 10, that is, the region indicated by hatching in FIG.
  • the input current of the smoothing output capacitor 10, that is, the current IL is a current like a triangular wave generated from the on / off operation of the switching element 7 and the switching element 8 by the control signal Ctrl1.
  • the output current of the smoothing output capacitor 10, that is, the current Io is a current like a rectangular wave generated from the on / off operation of the switching element 14 and the switching element 15 by the control signal Ctrl2.
  • the phase relationship between the control signal Ctrl1 and the control signal Ctrl2 causes a period in which the difference between the current IL and the current Io is the largest, and the difference between the input and output charge amounts (shown by hatching). As a result, the worst case in which the ripple of the output voltage Vo1 is maximized occurs.
  • FIG. 13 is an explanatory diagram showing an example of reducing the ripple of the output voltage Vo1 in the worst case shown in FIG.
  • the difference in the charge amount between the input and output of the smoothing output capacitor 10 (area of the area indicated by hatching) can be reduced. it can. That is, the frequency of the control signal Ctrl2 is set higher than the frequency of the control signal Ctrl1.
  • FIG. 1 is an explanatory diagram showing an example of the configuration of the power supply device according to the first embodiment.
  • the same components as those in FIG. 10 described above are denoted by the same reference numerals.
  • control signal Ctrl1 and the control signal Ctrl2 generated by the control unit 5 are respectively input to the switching operation units 1 and 2 to generate desired output voltage values, thereby supplying operating power to the loads 49 and 50.
  • the switching operation unit 1 is a first switching power supply circuit
  • the switching operation unit 2 is a second switching power supply circuit.
  • the control unit 5 includes a control circuit 12, a control circuit 20, a frequency divider 24, a clock generation circuit 26, a voltage detection comparison unit 56, and a phase control unit 6.
  • the switching operation unit 1, the switching operation unit 2, the loads 49 and 50, the control circuit 12, and the control circuit 20 in FIG. 1 are the same as those in FIG.
  • the clock generation circuit 26 generates a reference clock for the control unit 5.
  • the frequency divider 24 generates a clock CLOCK1 and a clock CLOCK2_1 based on the reference clock generated by the clock generation circuit 26, respectively.
  • the clock CLOCK1 becomes the first clock.
  • the voltage comparator 55 compares the input voltage Batt detected by the input voltage detector 53 with the output voltage Vo1 detected by the output voltage detector 54 to generate a signal Slope.
  • the edge detector 28 detects the phase difference between the control signal Ctrl1 and the control signal Ctrl2.
  • the edge detector 28 detects high / low of the control signal Ctrl2 at the timing of the falling edge of the control signal Ctrl1.
  • the control signal Ctrl2 is high, the pulse signal H_out is generated and output.
  • the control signal Ctrl2 is low, the pulse signal L_out is generated and output.
  • a frequency divider 24 for generating the control signals Ctrl1 and Ctrl2 whose frequencies are integer multiples is provided.
  • a case where the frequencies of the control signals Ctrl1 and Ctrl2 are the same will be described as an example.
  • FIG. 2 is an explanatory diagram showing an example of the phase relationship between the control signals Ctrl1 and Ctrl2 generated by the control circuit of FIG.
  • FIG. 2A shows a case where the slope of increase of current IL is larger than the slope of decrease of current IL
  • FIG. 2B shows the slope of rise of current IL as the slope of decrease of current IL. The smaller case is shown.
  • the timing for adjusting the phase between the control signal Ctrl1 and the control signal Ctrl2 differs depending on the rise and fall slopes of the current IL.
  • the slope of increase and decrease in current IL can be obtained from the following equation.
  • FIG. 3 is a timing chart showing an example of each signal in the control unit 5 included in the power supply device 32 of FIG.
  • FIG. 4 is a timing chart showing another example of each signal in the control unit 5 included in the power supply device 32 of FIG.
  • FIG. 3 shows an example of signal timing when the falling edge of the control signal Ctrl1 and the falling edge of the control signal Ctrl2 shown in FIG.
  • FIG. 4 shows an example of signal timing when the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 shown in FIG.
  • the frequency divider 24 generates a clock CLOCK1 and a clock CLOCK2_1 whose frequencies are integer multiples from the reference clock from the clock generation circuit 26, respectively.
  • the control circuit 12 generates the control signal Ctrl1 based on the feedback voltage from the output voltage Vo1 and the clock CLOCK1.
  • the delay setting time of the unit delay generator 27 is td.
  • the unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period td.
  • the control circuit 20 generates the control signal Ctrl2 based on the feedback voltage from the output voltage Vo2 and the clock CLOCK2_2.
  • the edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out.
  • the delay set in the unit delay generator 27 is increased by one unit from td, and the delay time becomes td + x.
  • Second period Due to the change in the input voltage Batt, the duty ratio of the control signal Ctrl1 generated from the control circuit 12 increases.
  • the unit delay generator 27 generates a clock CLOCK2_2 obtained by delaying the clock CLOCK2_1 by a period of td + x.
  • the edge detector 28 detects that the control signal Ctrl2 is low at the falling edge timing of the control signal Ctrl1, and outputs a pulse signal L_out.
  • the delay amount set in the unit delay generator 27 is increased by one unit from td + x and becomes td + 2x.
  • the unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 2x and generates the clock CLOCK2_2.
  • the edge detector 28 detects that the control signal Ctrl2 is low at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal L_out.
  • the delay set in the unit delay generator 27 is increased by one unit from td + 2x to become td + 3x.
  • the unit delay generator 27 delays the clock CLOCK2_1 by the period of td + 4x and generates the clock CLOCK2_2.
  • the edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out.
  • the delay set in the unit delay generator 27 is decreased by 1 unit from td + 4x to become td + 3x.
  • the delay amount set in the unit delay generator 27 by the pulse signals H_out and L_out is set to repeat td + 3x and td + 4x for each period.
  • the frequency divider 24 generates clocks CLOCK1 and CLOCK2_1 whose frequencies are integer multiples from the reference clock from the clock generation circuit 26, respectively.
  • the control circuit 12 generates the control signal Ctrl1 based on the feedback voltage from the output voltage Vo1 and the clock CLOCK1.
  • the delay setting time of the unit delay generator 27 is td + 4x.
  • the unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 4x and outputs it as the clock CLOCK2_2.
  • the control circuit 20 generates the control signal Ctrl2 based on the feedback voltage from the output voltage Vo2 and the clock CLOCK2_2.
  • the edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out. At this time, since the difference between the input voltage Batt and the output voltage Vo1 is smaller than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is smaller than the falling slope, and the signal Slope1 is high.
  • Second period Due to the change in the input voltage Batt, the duty ratio of the control signal Ctrl1 generated from the control circuit 12 decreases.
  • the unit delay generator 27 delays the clock CLOCK2_1 by the period of td + 3x and outputs it as the clock CLOCK2_2.
  • the delay set in the unit delay generator 27 is decreased by 1 unit from td + 3x to become td + 2x.
  • the unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 2x and outputs it as the clock CLOCK2_2.
  • the edge detector 28 detects that the control signal Ctrl2 is low at the timing of the falling edge of the control signal Ctrl1, and outputs the pulse signal L_out. At this time, since the difference between the input voltage Batt and the output voltage Vo1 is larger than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is larger than the falling slope, and the signal Slope1 is continuously low.
  • the delay amount set in the unit delay generator 27 is decreased by 1 unit from td + 2x to become td + x.
  • the unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period td.
  • the edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out.
  • the load 49 using the output voltage Vo1 as an operation power supply is an analog circuit such as an A / D converter as described above. Therefore, the accuracy of analog / digital conversion of the A / D converter can be improved by reducing the ripple of the output voltage Vo1.
  • the power supply device 41 includes a switching operation unit 1, a switching operation unit 2, and a control unit 19, as shown in FIG.
  • the power supply device 41 inputs the feedback voltage from the output voltages Vo 1 and Vo 2 to the control unit 19.
  • the control signals Ctrl1 and Ctrl2 generated by the control unit 19 are input to the switching operation units 1 and 2, and desired output voltages Vo1 and Vo2 are generated by the switching operation and supplied as the operation voltages of the load 50 and the load 49. To do.
  • the switching operation unit 1 includes a switching element 7, a switching element 8, an inductor 9, a smoothing output capacitor 10, a driver 11, and a current detector 57. Since the switching element 7, the switching element 8, the inductor 9, the smoothing output capacitor 10, and the driver 11 are the same as those in FIG.
  • the current detector 57 changes the current IL flowing through the inductor 9 into a voltage value and outputs it.
  • the control unit 19 includes a controller 33, a controller 34, a frequency divider 24, a current detection comparison unit 60, and a clock generation circuit 26.
  • the current detection comparison unit 60 includes a current detection ADC 58 and a current gradient comparator 59.
  • the current detection / comparison unit 60 generates a signal Slope 2 indicating the relationship between the magnitude of the increase and decrease in the current IL flowing through the inductor 9.
  • the current detection ADC 58 converts the voltage value obtained by converting the current IL by the current detector 57 into a digital voltage value.
  • the current slope comparator 59 outputs a signal Slope2 indicating the magnitude of the slope of the rise of the current IL flowing through the inductor 9 and the fall of the current IL from the current detection ADC 58 during one cycle when the switching elements 7 and 8 are switched. Generated based on the output digital voltage value.
  • the signal Slope2 becomes low.
  • the slope of increase of the current IL flowing through the inductor 9 is smaller than the slope of decrease of the current IL, the signal Slope2 becomes high.
  • the current slope comparator 59 is a circuit that compares the rise and fall slopes of the current IL during one cycle, the result of the signal Slope2 is the comparison result between the rise and fall slopes of the current IL one cycle before. It is.
  • the controller 33 includes an AD converter 37, a PID controller 36, and a DPWM generator 35.
  • the controller 33 converts the feedback voltage from the output voltage Vo1 into a digital feedback pressure value by the AD converter 37, and the PID controller 36 generates a digital control value Digital_in.
  • the DPWM generator 35 generates the control signal Ctrl1 based on the clock CLOCK1 generated by the frequency divider 24 and the digital control value Digital_in generated by the PID controller 36.
  • the digital control value Digital_in represents the high time of the control signal Ctrl1.
  • the AD converter 37 is an analog-digital conversion circuit that converts a feedback voltage from the output voltage Vo1 into a digital feedback voltage value.
  • the PID controller 36 performs a proportional-integral-differential (Proportional-Integral-Differential) operation using the digital feedback voltage value converted by the AD converter 37 so that the switching operation unit 1 can generate a desired output voltage.
  • a digital control value Digital_in is generated.
  • the DPWM generator 35 is a so-called digital PWM (Pulse Width Modulation) circuit that uses the digital control value Digital_in from the PID controller 36 to generate the control signal Ctrl1 by the clock CLOCK1 output from the frequency divider 24.
  • digital PWM Pulse Width Modulation
  • the controller 34 includes an AD converter 40, a PID controller 39, a DPWM generator 38, and a variable delay device 42.
  • the controller 34 is a digital controller such as a microcomputer.
  • the feedback voltage from the output voltage Vo2 is converted into a digital feedback pressure value by the AD converter 40.
  • the digital control value Digital_in_2 is generated by the PID controller 39.
  • the clock CLOCK2_2 is generated by the digital control value Digital_in_2, the digital control value Digital_in generated by the PID controller 36, and the clock CLOCK2_1 output from the frequency divider 24.
  • the control signal Ctrl2 is generated from the DPWM generator 38 based on the digital control value Digital_in_2 from the PID controller 39 and the clock CLOCK2_2.
  • the digital control value Digital_in_2 represents the high time of the control signal Ctrl2.
  • the AD converter 40 is an analog-digital conversion circuit that converts a feedback voltage from the output voltage Vo2 into a digital feedback voltage value.
  • the PID controller 39 uses the digital feedback voltage value converted by the AD converter 40 to perform a proportional-integral-differential (Proportional-Integral-Differential) operation so that the switching operation unit 2 can generate a desired output voltage.
  • the digital control value Digital_in_2 is generated.
  • the DPWM generator 38 is a digital PWM (Pulse Width Modulation) circuit that generates the control signal Ctrl2 by the clock CLOCK2_2 using the digital control value Digital_in_2 generated by the PID controller 39.
  • PWM Pulse Width Modulation
  • the variable delay unit 42 sets the delay time by the digital control value Digital_in generated by the PID controller 36, the digital control value Digital_in_2 generated by the PID controller 39, and the signal Slope2 output from the current slope comparator 59, A clock CLOCK2_2 obtained by delaying the clock CLOCK2_1 output from the frequency divider 24 by a set delay time is generated.
  • the delay time is the difference between the high time of the control signal Ctrl1 and the high time of the control signal Ctrl2.
  • the delay time is the high time of the control signal Ctrl1.
  • FIG. 6 is a timing chart showing an example of each signal in the power supply device 41 of FIG.
  • FIG. 7 is a timing chart showing another example of each signal in the power supply device 41 of FIG.
  • FIG. 6 shows an example of signal timing when the power supply device 41 shown in FIG. 5 matches the falling edge of the control signal Ctrl1 and the falling edge of the control signal Ctrl2 shown in FIG. is there.
  • FIG. 7 shows an example of signal timing when the power supply device 41 shown in FIG. 5 matches the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 shown in FIG. .
  • the frequency divider 24 generates clocks CLOCK1 and CLOCK2_1 whose frequencies are integer multiples from the reference clock output from the clock generation circuit 26, respectively.
  • the controller 33 generates a digital control value Digital_in representing a high time t1 of the control signal Ctrl1 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t1.
  • variable delay device 42 sets the delay setting time to t1 by the digital control value Digital_in representing the time t1.
  • the variable delay device 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period t1.
  • control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the rising edge of the control signal Ctrl2.
  • the duty ratio of the control signal Ctrl1 generated by the controller 33 increases from t1 / Ts1 to t2 / Ts2.
  • the controller 33 generates a digital control value Digital_in representing the time t2 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t2.
  • variable delay device 42 sets the delay setting time to t2 by the digital control value Digital_in representing the time t2.
  • variable delay device 42 delays the clock CLOCK2_1 by the period t2, and generates the clock CLOCK2_2 as the clock CLOCK2_2. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the rising edge of the control signal Ctrl2.
  • variable delay device 42 sets the delay setting time to t2-t3 by the digital control value Digital_in representing the time t2 and the digital control value Digital_in_2 representing the time t3.
  • the variable delay device 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period t2-t3. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the falling edge of the control signal Ctrl2.
  • the frequency divider 24 generates clocks CLOCK1 and CLOCK2_1 whose frequencies are integer multiples from the reference clock output from the clock generation circuit 26.
  • the controller 33 generates a digital control value Digital_in representing a high time t2 of the control signal Ctrl1 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t2.
  • variable delay device 42 sets the delay setting time to t2-t3 by the digital control value Digital_in representing the time t2 and the digital control value Digital_in_2 representing the time t3.
  • the variable delay device 42 generates a clock CLOCK2_2 obtained by delaying the clock CLOCK2_1 by a period of t2-t3. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the falling edge of the control signal Ctrl2.
  • the duty ratio of the control signal Ctrl1 generated by the controller 33 decreases from t2 / Ts1 to t1 / Ts2.
  • the controller 33 generates a digital control value Digital_in representing time t2 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t1.
  • variable delay device 42 sets the delay setting time to t1 ⁇ t3 by the digital control value Digital_in representing the time t2 and the digital control value Digital_in_2 representing the time t3.
  • the variable delay device 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period t2-t3. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the falling edge of the control signal Ctrl2.
  • variable delay device 42 sets the delay setting time to t1 by the digital control value Digital_in representing the time t1.
  • the variable delay device 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period t1. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the rising edge of the control signal Ctrl2.
  • the tracking time of the delay time of the control signal Ctrl2 can be shortened, so that the ripple of the output voltage Vo1 during the tracking period is suppressed. can do.
  • control signal Ctrl1 and the control signal Ctrl2 are not adjusted by the feedback control of the phase relationship between the control signal Ctrl1 and the control signal Ctrl2, but the control signal Ctrl1 is controlled by the ripple feedback control of the output voltage Vo1.
  • a technique for adjusting the delay of Ctrl1 and Ctrl2 will be described.
  • FIG. 8 is an explanatory diagram showing an example of the configuration of the power supply device 43 according to the third embodiment.
  • FIG. 8 parts having the same configuration as those in FIGS. 1 and 5 are denoted by the same reference numerals.
  • the generator 38 and the unit delay generator 27 are the same as those in FIG. 1 and FIG.
  • the power supply device 43 includes a switching operation unit 1, a switching operation unit 2, and a control unit 51.
  • the power supply device 43 inputs the feedback voltage from the output voltages Vo1 and Vo2 to the control unit 51, inputs the control signals Ctrl1 and Ctrl2 generated by the control unit 51 to the switching operation units 1 and 2, and outputs a desired output voltage value. Is generated.
  • the control unit 51 includes a controller 25, a controller 44, a frequency divider 24, a clock generation circuit 26, and a delay adjustment circuit 47.
  • the controller 44 includes an AD converter 45, a PID controller 36, and a DPWM generator 35.
  • the controller 44 is a digital controller such as a microcomputer, for example, and generates a control signal Ctrl1 to be input to the switching operation unit 1. Specifically, the feedback voltage from the output voltage Vo1 is converted into a digital feedback pressure value by the AD converter 45, and a digital control value is generated by the PID controller 36.
  • control signal Ctrl1 is generated from the DPWM generator 35 based on the clock CLOCK1 output from the frequency divider 24 and the digital control value generated by the PID controller 36.
  • the AD converter 45 is an analog-digital conversion circuit that converts a feedback voltage from the output voltage Vo1 into a digital feedback voltage value.
  • the digital feedback voltage converted by the AD converter 45 has two uses.
  • One is input to the PID controller 36 as in the second embodiment.
  • the other is to measure the magnitude of the ripple of the output voltage Vo1 every one cycle before the control signal Ctrl1.
  • the difference between the AD converter 45 and the AD converter 37 of FIG. 5 of the second embodiment is the sampling frequency.
  • the sampling frequency of the AD converter 37 is the same as the frequency of the control signal Ctrl1.
  • the sampling frequency of the AD converter 45 is set to a frequency that is, for example, twice or more higher than the frequency of the control signal Ctrl1. There is a need.
  • the delay adjustment circuit 47 includes a ripple comparator 52, a sample hold circuit 48, a ripple comparator 46, and a unit delay generator 27.
  • the delay adjustment circuit 47 adjusts the phase relationship between the control signal Ctrl1 and the control signal Ctrl2.
  • the ripple comparator 52 and the sample hold circuit 48 constitute a detector.
  • the ripple comparator 52 obtains the ripple value of the output voltage Vo1 in one cycle of the control signal Ctrl1 using the digital feedback voltage value of the output voltage Vo1 converted by the AD converter 45.
  • the sample hold circuit 48 stores the ripple value of the output voltage Vo1 one cycle before the control signal Ctrl1.
  • the ripple comparator 46 compares the ripple value of the output voltage Vo1 before and after one cycle of the control signal Ctrl1, and outputs the comparison results as pulse signals H_out and L_out.
  • the pulse signal H_out is generated.
  • the pulse signal L_out is generated.
  • the unit delay generator 27 delays the clock CLOCK2_1 from the frequency divider 24 by a desired delay time based on the pulse signals H_out and L_out detected from the ripple comparator 46, and generates the clock CLOCK2_2.
  • the ripple comparator 46 when the ripple comparator 46 generates the pulse signal L_out, the clock CLOCK2_2 obtained by delaying the clock CLOCK2_1 from the frequency divider 24 by reducing the delay time by one unit is output.
  • the controller 25 includes an AD converter 40, a PID controller 39, and a DPWM generator 38.
  • the controller 25 is a digital controller such as a microcomputer, for example, and generates a control signal Ctrl2.
  • a feedback voltage from the output voltage Vo2 is converted into a digital feedback pressure value by the AD converter 40, a digital control value is generated by the PID controller 39, and a clock output from the unit delay generator 27 is generated.
  • the DPWM generator 38 generates the control signal Ctrl2 based on the digital control value output from the CLOCK2_2 and the PID controller 39.
  • FIG. 9 is a timing chart showing an example of each signal in the control unit 51 in the power supply device 43 of FIG.
  • the frequency divider 24 generates clocks CLOCK 1 and CLOCK 2 _ 1 whose frequency is an integer multiple from the reference clock of the clock generation circuit 26.
  • the controller 44 generates a control signal Ctrl1 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1.
  • the initial delay setting time of the unit delay generator 27 is td.
  • the unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period td.
  • the controller 25 generates a control signal Ctrl2_2 from the feedback voltage from the output voltage Vo2 and the clock CLOCK2_2.
  • the ripple comparator 46 detects that the ripple value of the output voltage Vo1 one cycle before the control signal Ctrl1 is larger than one cycle later, and outputs the pulse signal H_out. As a result, the delay set in the unit delay generator 27 becomes td + x which is increased by one unit from the initial td.
  • Second period The output voltage Vo1 changes depending on the input voltage Batt or the operating state of the loads 49 and 50, and the duty ratio of the control signal Ctrl1 generated from the controller 44 increases.
  • the unit delay generator 27 delays the clock CLOCK2_1 by a period of td + x and generates the clock CLOCK2_2.
  • the ripple comparator 46 detects that the ripple value of the output voltage (Vo1) before one cycle of the control signal Ctrl1 is larger than after one cycle, and outputs the pulse signal H_out.
  • the delay set in the unit delay generator 27 is increased by 1 unit from the initial td, and becomes td + 2x.
  • the unit delay generator 27 delays the clock CLOCK2_1 by the period of td + 2x, and generates the clock CLOCK2_2.
  • the ripple comparator 46 detects that the ripple value of the output voltage Vo1 before one cycle of the control signal Ctrl1 is smaller than after one cycle, and outputs the pulse signal L_out. As a result, the delay set in the unit delay generator 27 is decreased by one unit from td + 2x to become td + x.
  • the delay set in the unit delay generator 27 by the pulse signal H_out or the pulse signal L_out is set repeatedly between td + 2x and td + x for each period.
  • a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. .
  • each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit.
  • Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor.
  • Information such as programs, tables, and files for realizing each function can be stored in a recording device such as a memory, a hard disk, an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.
  • control lines and information lines indicate what is considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. Actually, it may be considered that almost all the components are connected to each other.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

La présente invention génère une tension d'alimentation électrique très précise avec une faible perte sans augmenter la fréquence de commutation d'un circuit d'alimentation électrique à découpage. Un dispositif d'alimentation électrique (32) comprend une unité d'opération de commutation (1), une autre unité d'opération de commutation (2), un circuit de commande (12), un autre circuit de commande (20) et une unité de commande de phase (6). L'unité d'opération de commutation (1) génère une tension de sortie (Vo1) à partir d'une nappe de tension d'entrée à entrée externe. L'unité d'opération de commutation (2) génère une tension de sortie (Vo2) à partir de la tension de sortie (Vo1). Le circuit de commande (12) commande la tension de sortie (Vo1) sur la base d'une horloge (CLOCK1). Le circuit de commande (20) commande la tension de sortie (Vo2) sur la base d'une horloge (CLOCK2_2). L'unité de commande de phase (6) règle la fréquence de l'horloge (CLOCK1) et la fréquence de l'horloge (CLOCK2_2) de manière à représenter un multiple entier et commande les retards des horloges (CLOCK1, CLOCK2_2) de sorte que l'ondulation de la tension de sortie (Vo1) est réduite.
PCT/JP2017/031627 2017-02-10 2017-09-01 Dispositif d'alimentation électrique WO2018146843A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119315820A (zh) * 2024-12-16 2025-01-14 大连科技学院 一种直流微电网的功率转换系统及方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01255469A (ja) * 1988-04-01 1989-10-12 Matsushita Electric Works Ltd 電源装置
JPH10225108A (ja) * 1996-12-03 1998-08-21 Fujitsu Ltd 昇降圧ｄｃ／ｄｃコンバータ
JP2006141183A (ja) * 2004-11-15 2006-06-01 Matsushita Electric Ind Co Ltd 昇降圧コンバータ
JP2009081988A (ja) * 2007-09-07 2009-04-16 Panasonic Corp バックブーストスイッチングレギュレータ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01255469A (ja) * 1988-04-01 1989-10-12 Matsushita Electric Works Ltd 電源装置
JPH10225108A (ja) * 1996-12-03 1998-08-21 Fujitsu Ltd 昇降圧ｄｃ／ｄｃコンバータ
JP2006141183A (ja) * 2004-11-15 2006-06-01 Matsushita Electric Ind Co Ltd 昇降圧コンバータ
JP2009081988A (ja) * 2007-09-07 2009-04-16 Panasonic Corp バックブーストスイッチングレギュレータ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119315820A (zh) * 2024-12-16 2025-01-14 大连科技学院 一种直流微电网的功率转换系统及方法

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