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WO2018146843A1 - Power supply device - Google Patents

Power supply device Download PDF

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Publication number
WO2018146843A1
WO2018146843A1 PCT/JP2017/031627 JP2017031627W WO2018146843A1 WO 2018146843 A1 WO2018146843 A1 WO 2018146843A1 JP 2017031627 W JP2017031627 W JP 2017031627W WO 2018146843 A1 WO2018146843 A1 WO 2018146843A1
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WO
WIPO (PCT)
Prior art keywords
clock
power supply
output voltage
control signal
delay
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PCT/JP2017/031627
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French (fr)
Japanese (ja)
Inventor
鳴 劉
純之 荒田
隆介 佐原
山脇　大造
豪一 小野
Original Assignee
日立オートモティブシステムズ株式会社
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Application filed by 日立オートモティブシステムズ株式会社 filed Critical 日立オートモティブシステムズ株式会社
Publication of WO2018146843A1 publication Critical patent/WO2018146843A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the present invention relates to a power supply device, and more particularly to a technique effective for controlling power by a power supply device that supplies power to an ECU (Electronic Control Unit) mounted on a vehicle.
  • ECU Electronic Control Unit
  • the operating voltage of in-vehicle ECUs tends to be lowered.
  • the operating voltage of a microcomputer used in an in-vehicle ECU is about 5V or 3.3V, but is about 1V or less.
  • the power supply device that supplies power to the ECU is also required to have a low voltage.
  • a switching power supply device is widely used.
  • the power supply voltage supplied from the battery is stepped down to generate a low voltage of about 1 V or less.
  • a switching power supply apparatus having a two-stage configuration in which two switching power supply circuits are connected in series is widely used, and the power supply voltage of the battery is sequentially stepped down by these two switching power supply circuits and supplied to the ECU. A power supply is generated.
  • the switching duty ratio is determined by the input / output voltage ratio. For example, when the input voltage is about 40V and the output voltage is about 1V, the switching duty ratio is 2.5%.
  • the switching frequency is increased, a switching circuit that can apply a duty ratio of 2.5% can be made.
  • the switching frequency is generally required to be 500 KHz or more depending on the specification of the power supply voltage fluctuation of the microcomputer in the ECU, and it is difficult to create a switching circuit that can apply a duty ratio of 2.5%.
  • the output voltage of the first switching power supply circuit in the two-stage configuration is generally used as a power supply voltage for other loads mounted on the ECU board, such as an A / D (Analog / Digital) converter. Since the performance of the A / D converter depends on the performance of the power supply voltage, that is, the accuracy of the power supply voltage, the output voltage ripple requirement of the first switching power supply circuit is higher.
  • a / D Analog / Digital
  • switching power supply circuit As for this type of switching power supply circuit, there is a switching power supply circuit having an appropriate number of cascade connection stages according to, for example, a voltage ratio between an input voltage and an output voltage (see, for example, Patent Document 1).
  • the switching frequency of the next-stage switching power supply circuit is set high in order to suppress the ripple of the output voltage of the first-stage switching power supply circuit. Need arises.
  • An object of the present invention is to provide a technique capable of generating a highly accurate power supply voltage with low loss without increasing a switching frequency in a switching power supply circuit.
  • a typical power supply device includes a first switching power supply circuit, a second switching power supply circuit, a first control circuit, a second control circuit, and a delay generation unit.
  • the first switching power supply circuit generates a first output voltage from an externally input voltage.
  • the second switching power supply circuit generates a second output voltage from the first output voltage.
  • the first control circuit controls the first output voltage generated by the first switching power supply circuit based on the first clock.
  • the second control circuit controls the second output voltage generated by the second switching power supply circuit based on the second clock.
  • the delay generation unit adjusts the frequency of the first clock and the frequency of the second clock to an integer multiple to reduce the delay between the first clock and the second clock and the ripple of the first output voltage. To control.
  • the first switching power supply circuit has a first switching unit
  • the second switching power supply circuit has a second switching unit.
  • the first switching unit switches the input voltage.
  • the second switching unit switches the first output voltage.
  • the first control circuit generates a first control signal for controlling the first switching unit from the first clock, and the second control circuit controls the second switching unit from the second clock.
  • a second control signal is generated.
  • the delay generation unit controls the phases of the first control signal and the second control signal to control the delays of the first clock and the second clock.
  • a typical power supply device has an edge detector.
  • the edge detector detects a signal rising edge or a signal falling edge between the first control signal and the second control signal.
  • the delay generation unit controls the delays of the first clock and the second clock so that the signal rising edges or signal falling edges of the first control signal and the second control signal are aligned.
  • FIG. 3 is an explanatory diagram illustrating an example of a configuration of a power supply device according to Embodiment 1.
  • FIG. It is explanatory drawing which shows an example of the phase relationship of the control signal which the control circuit of FIG. 1 produces
  • FIG. 10 is an explanatory diagram illustrating an example of a configuration of a power supply device according to a second embodiment. It is a timing chart which shows an example of each signal in the power supply device of FIG. 6 is a timing chart showing another example of each signal in the power supply device of FIG. 5.
  • FIG. 10 is an explanatory diagram illustrating an example of a configuration of a power supply device according to a second embodiment. It is a timing chart which shows an example of each signal in the power supply device of FIG. 6 is a timing
  • FIG. 10 is an explanatory diagram illustrating an example of a configuration of a power supply device according to a third embodiment. It is a timing chart which shows an example of each signal in the control part in the power supply device of FIG. It is explanatory drawing which shows an example of a structure of the power supply device in the comparison technique with respect to embodiment. It is explanatory drawing which shows an example of operation
  • FIG. 11 is an explanatory diagram illustrating an example of a cause of the worst case of output voltage ripple when the control signal generated by the control circuit of FIG. 10 has a phase difference. It is explanatory drawing which showed the example which reduces the ripple of the output voltage at the time of the worst case shown in FIG.
  • FIG. 10 is an explanatory diagram showing an example of the configuration of the power supply device in the comparison technique with respect to the present embodiment.
  • the power supply device has a configuration including a switching power supply circuit 30 and a switching power supply circuit 31, and the switching power supply circuits 30 and 31 are connected in series.
  • the first switching power supply circuit 30 generates the output voltage Vo1 from the input voltage Batt.
  • the input voltage Batt is a power supply voltage of a battery (not shown).
  • the output voltage Vo1 is a voltage lower than the battery voltage Batt.
  • the second switching power supply circuit 31 generates the output voltage Vo2 from the output voltage Vo1.
  • the output voltage Vo2 is a voltage lower than the output voltage Vo1.
  • the output voltage Vo1 is a first output voltage
  • the output voltage Vo2 is a second output voltage.
  • the load 49 connected to the power supply device is a load using the output voltage Vo1 as an operation power supply, and is an analog circuit such as an A / D converter, for example.
  • the load 50 connected to the power supply device is a load that uses the output voltage Vo2 as an operation power supply, and is, for example, a microcomputer.
  • the switching power supply circuit 30 includes a switching operation unit 1 and a control unit 3.
  • the switching power supply circuit 30 inputs a feedback voltage from the output voltage Vo1 to the control unit 3 and inputs a control signal Ctrl1 generated by the control unit 3 to the switching operation unit 1 to generate a desired output voltage value.
  • the control signal Ctrl1 is a first control signal.
  • the switching operation unit 1 includes a switching element 7, a switching element 8, an inductor 9, a smoothing output capacitor 10, and a driver 11.
  • the load 49 and the load 50 are driven while energy is stored in the inductor 9.
  • the switching element 7 is turned off and the switching element 8 is turned on, the energy accumulated in the inductor 9 is released, and the load 49 and the load 50 are driven.
  • the smoothing output capacitor 10 is a capacitor and suppresses the voltage ripple of the output voltage Vo1 of the switching power supply circuit 30.
  • the driver 11 is a drive circuit that drives the switching element 7 and the switching element 8 with a control signal Ctrl1 output from the control unit 3 to perform a switching operation.
  • the switching element 7 is composed of, for example, an N channel MOS (Metal Oxide Semiconductor) transistor, and the switching element 8 is composed of a P channel MOS transistor or the like.
  • the switching element 7 is turned on when the signal output from the driver 11 is a high signal, and the switching element 8 is turned on when the signal output from the driver 11 is a low signal.
  • the frequency divider 21 is a circuit that generates a clock that determines the on / off operation frequency of the switching element 7 and the switching element 8 of the switching power supply circuit 30 based on the reference clock from the clock generation circuit 4.
  • the control circuit 12 which is the first control circuit, is a circuit that generates the control signal Ctrl1 based on the feedback voltage at the output voltage Vo1 and the clock output from the frequency divider 21.
  • the frequency of the control signal Ctrl1 is determined by the frequency of the clock output from the frequency divider 21.
  • the control circuit 20 as the second control circuit generates the control signal Ctrl2 based on the feedback voltage in the output voltage Vo2 and the clock generated by the frequency divider 22.
  • the frequency of the control signal Ctrl2 is determined by the frequency of the clock generated by the frequency divider 22.
  • FIG. 11 is an explanatory diagram showing an example of the operation of the power supply device of FIG.
  • FIG. 11 shows the signal timing of the control signal Ctrl1 output from the control circuit 12 in the upper part, and the signal timing of the control signal Ctrl2 output from the control circuit 20 in the lower part.
  • a current IL that is an inductor current is an input current of the smoothing output capacitor 10
  • a current Io is an output current of the smoothing output capacitor 10.
  • control signals Ctrl1 and Ctrl2 are generated by the control circuits 12 and 20, respectively. Therefore, the phase relationship between the control signal Ctrl1 and the control signal Ctrl2 is not controlled. In other words, it is not fixed.
  • FIG. 12 illustrates an example of the cause of the worst case of the ripple in the output voltage Vo1 of the switching power supply circuit 30 when there is a phase difference between the control signal Ctrl1 and the control signal Ctrl2 generated by the control circuit of FIG. FIG.
  • the ripple of the output voltage Vo1 increases as the difference in charge amount between the input and output of the smoothing output capacitor 10, that is, the region indicated by hatching in FIG.
  • the input current of the smoothing output capacitor 10, that is, the current IL is a current like a triangular wave generated from the on / off operation of the switching element 7 and the switching element 8 by the control signal Ctrl1.
  • the output current of the smoothing output capacitor 10, that is, the current Io is a current like a rectangular wave generated from the on / off operation of the switching element 14 and the switching element 15 by the control signal Ctrl2.
  • the phase relationship between the control signal Ctrl1 and the control signal Ctrl2 causes a period in which the difference between the current IL and the current Io is the largest, and the difference between the input and output charge amounts (shown by hatching). As a result, the worst case in which the ripple of the output voltage Vo1 is maximized occurs.
  • FIG. 13 is an explanatory diagram showing an example of reducing the ripple of the output voltage Vo1 in the worst case shown in FIG.
  • the difference in the charge amount between the input and output of the smoothing output capacitor 10 (area of the area indicated by hatching) can be reduced. it can. That is, the frequency of the control signal Ctrl2 is set higher than the frequency of the control signal Ctrl1.
  • FIG. 1 is an explanatory diagram showing an example of the configuration of the power supply device according to the first embodiment.
  • the same components as those in FIG. 10 described above are denoted by the same reference numerals.
  • control signal Ctrl1 and the control signal Ctrl2 generated by the control unit 5 are respectively input to the switching operation units 1 and 2 to generate desired output voltage values, thereby supplying operating power to the loads 49 and 50.
  • the switching operation unit 1 is a first switching power supply circuit
  • the switching operation unit 2 is a second switching power supply circuit.
  • the control unit 5 includes a control circuit 12, a control circuit 20, a frequency divider 24, a clock generation circuit 26, a voltage detection comparison unit 56, and a phase control unit 6.
  • the switching operation unit 1, the switching operation unit 2, the loads 49 and 50, the control circuit 12, and the control circuit 20 in FIG. 1 are the same as those in FIG.
  • the clock generation circuit 26 generates a reference clock for the control unit 5.
  • the frequency divider 24 generates a clock CLOCK1 and a clock CLOCK2_1 based on the reference clock generated by the clock generation circuit 26, respectively.
  • the clock CLOCK1 becomes the first clock.
  • the voltage comparator 55 compares the input voltage Batt detected by the input voltage detector 53 with the output voltage Vo1 detected by the output voltage detector 54 to generate a signal Slope.
  • the edge detector 28 detects the phase difference between the control signal Ctrl1 and the control signal Ctrl2.
  • the edge detector 28 detects high / low of the control signal Ctrl2 at the timing of the falling edge of the control signal Ctrl1.
  • the control signal Ctrl2 is high, the pulse signal H_out is generated and output.
  • the control signal Ctrl2 is low, the pulse signal L_out is generated and output.
  • a frequency divider 24 for generating the control signals Ctrl1 and Ctrl2 whose frequencies are integer multiples is provided.
  • a case where the frequencies of the control signals Ctrl1 and Ctrl2 are the same will be described as an example.
  • FIG. 2 is an explanatory diagram showing an example of the phase relationship between the control signals Ctrl1 and Ctrl2 generated by the control circuit of FIG.
  • FIG. 2A shows a case where the slope of increase of current IL is larger than the slope of decrease of current IL
  • FIG. 2B shows the slope of rise of current IL as the slope of decrease of current IL. The smaller case is shown.
  • the timing for adjusting the phase between the control signal Ctrl1 and the control signal Ctrl2 differs depending on the rise and fall slopes of the current IL.
  • the slope of increase and decrease in current IL can be obtained from the following equation.
  • FIG. 3 is a timing chart showing an example of each signal in the control unit 5 included in the power supply device 32 of FIG.
  • FIG. 4 is a timing chart showing another example of each signal in the control unit 5 included in the power supply device 32 of FIG.
  • FIG. 3 shows an example of signal timing when the falling edge of the control signal Ctrl1 and the falling edge of the control signal Ctrl2 shown in FIG.
  • FIG. 4 shows an example of signal timing when the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 shown in FIG.
  • the frequency divider 24 generates a clock CLOCK1 and a clock CLOCK2_1 whose frequencies are integer multiples from the reference clock from the clock generation circuit 26, respectively.
  • the control circuit 12 generates the control signal Ctrl1 based on the feedback voltage from the output voltage Vo1 and the clock CLOCK1.
  • the delay setting time of the unit delay generator 27 is td.
  • the unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period td.
  • the control circuit 20 generates the control signal Ctrl2 based on the feedback voltage from the output voltage Vo2 and the clock CLOCK2_2.
  • the edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out.
  • the delay set in the unit delay generator 27 is increased by one unit from td, and the delay time becomes td + x.
  • Second period Due to the change in the input voltage Batt, the duty ratio of the control signal Ctrl1 generated from the control circuit 12 increases.
  • the unit delay generator 27 generates a clock CLOCK2_2 obtained by delaying the clock CLOCK2_1 by a period of td + x.
  • the edge detector 28 detects that the control signal Ctrl2 is low at the falling edge timing of the control signal Ctrl1, and outputs a pulse signal L_out.
  • the delay amount set in the unit delay generator 27 is increased by one unit from td + x and becomes td + 2x.
  • the unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 2x and generates the clock CLOCK2_2.
  • the edge detector 28 detects that the control signal Ctrl2 is low at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal L_out.
  • the delay set in the unit delay generator 27 is increased by one unit from td + 2x to become td + 3x.
  • the unit delay generator 27 delays the clock CLOCK2_1 by the period of td + 4x and generates the clock CLOCK2_2.
  • the edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out.
  • the delay set in the unit delay generator 27 is decreased by 1 unit from td + 4x to become td + 3x.
  • the delay amount set in the unit delay generator 27 by the pulse signals H_out and L_out is set to repeat td + 3x and td + 4x for each period.
  • the frequency divider 24 generates clocks CLOCK1 and CLOCK2_1 whose frequencies are integer multiples from the reference clock from the clock generation circuit 26, respectively.
  • the control circuit 12 generates the control signal Ctrl1 based on the feedback voltage from the output voltage Vo1 and the clock CLOCK1.
  • the delay setting time of the unit delay generator 27 is td + 4x.
  • the unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 4x and outputs it as the clock CLOCK2_2.
  • the control circuit 20 generates the control signal Ctrl2 based on the feedback voltage from the output voltage Vo2 and the clock CLOCK2_2.
  • the edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out. At this time, since the difference between the input voltage Batt and the output voltage Vo1 is smaller than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is smaller than the falling slope, and the signal Slope1 is high.
  • Second period Due to the change in the input voltage Batt, the duty ratio of the control signal Ctrl1 generated from the control circuit 12 decreases.
  • the unit delay generator 27 delays the clock CLOCK2_1 by the period of td + 3x and outputs it as the clock CLOCK2_2.
  • the delay set in the unit delay generator 27 is decreased by 1 unit from td + 3x to become td + 2x.
  • the unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 2x and outputs it as the clock CLOCK2_2.
  • the edge detector 28 detects that the control signal Ctrl2 is low at the timing of the falling edge of the control signal Ctrl1, and outputs the pulse signal L_out. At this time, since the difference between the input voltage Batt and the output voltage Vo1 is larger than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is larger than the falling slope, and the signal Slope1 is continuously low.
  • the delay amount set in the unit delay generator 27 is decreased by 1 unit from td + 2x to become td + x.
  • the unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period td.
  • the edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out.
  • the load 49 using the output voltage Vo1 as an operation power supply is an analog circuit such as an A / D converter as described above. Therefore, the accuracy of analog / digital conversion of the A / D converter can be improved by reducing the ripple of the output voltage Vo1.
  • the power supply device 41 includes a switching operation unit 1, a switching operation unit 2, and a control unit 19, as shown in FIG.
  • the power supply device 41 inputs the feedback voltage from the output voltages Vo 1 and Vo 2 to the control unit 19.
  • the control signals Ctrl1 and Ctrl2 generated by the control unit 19 are input to the switching operation units 1 and 2, and desired output voltages Vo1 and Vo2 are generated by the switching operation and supplied as the operation voltages of the load 50 and the load 49. To do.
  • the switching operation unit 1 includes a switching element 7, a switching element 8, an inductor 9, a smoothing output capacitor 10, a driver 11, and a current detector 57. Since the switching element 7, the switching element 8, the inductor 9, the smoothing output capacitor 10, and the driver 11 are the same as those in FIG.
  • the current detector 57 changes the current IL flowing through the inductor 9 into a voltage value and outputs it.
  • the control unit 19 includes a controller 33, a controller 34, a frequency divider 24, a current detection comparison unit 60, and a clock generation circuit 26.
  • the current detection comparison unit 60 includes a current detection ADC 58 and a current gradient comparator 59.
  • the current detection / comparison unit 60 generates a signal Slope 2 indicating the relationship between the magnitude of the increase and decrease in the current IL flowing through the inductor 9.
  • the current detection ADC 58 converts the voltage value obtained by converting the current IL by the current detector 57 into a digital voltage value.
  • the current slope comparator 59 outputs a signal Slope2 indicating the magnitude of the slope of the rise of the current IL flowing through the inductor 9 and the fall of the current IL from the current detection ADC 58 during one cycle when the switching elements 7 and 8 are switched. Generated based on the output digital voltage value.
  • the signal Slope2 becomes low.
  • the slope of increase of the current IL flowing through the inductor 9 is smaller than the slope of decrease of the current IL, the signal Slope2 becomes high.
  • the current slope comparator 59 is a circuit that compares the rise and fall slopes of the current IL during one cycle, the result of the signal Slope2 is the comparison result between the rise and fall slopes of the current IL one cycle before. It is.
  • the controller 33 includes an AD converter 37, a PID controller 36, and a DPWM generator 35.
  • the controller 33 converts the feedback voltage from the output voltage Vo1 into a digital feedback pressure value by the AD converter 37, and the PID controller 36 generates a digital control value Digital_in.
  • the DPWM generator 35 generates the control signal Ctrl1 based on the clock CLOCK1 generated by the frequency divider 24 and the digital control value Digital_in generated by the PID controller 36.
  • the digital control value Digital_in represents the high time of the control signal Ctrl1.
  • the AD converter 37 is an analog-digital conversion circuit that converts a feedback voltage from the output voltage Vo1 into a digital feedback voltage value.
  • the PID controller 36 performs a proportional-integral-differential (Proportional-Integral-Differential) operation using the digital feedback voltage value converted by the AD converter 37 so that the switching operation unit 1 can generate a desired output voltage.
  • a digital control value Digital_in is generated.
  • the DPWM generator 35 is a so-called digital PWM (Pulse Width Modulation) circuit that uses the digital control value Digital_in from the PID controller 36 to generate the control signal Ctrl1 by the clock CLOCK1 output from the frequency divider 24.
  • digital PWM Pulse Width Modulation
  • the controller 34 includes an AD converter 40, a PID controller 39, a DPWM generator 38, and a variable delay device 42.
  • the controller 34 is a digital controller such as a microcomputer.
  • the feedback voltage from the output voltage Vo2 is converted into a digital feedback pressure value by the AD converter 40.
  • the digital control value Digital_in_2 is generated by the PID controller 39.
  • the clock CLOCK2_2 is generated by the digital control value Digital_in_2, the digital control value Digital_in generated by the PID controller 36, and the clock CLOCK2_1 output from the frequency divider 24.
  • the control signal Ctrl2 is generated from the DPWM generator 38 based on the digital control value Digital_in_2 from the PID controller 39 and the clock CLOCK2_2.
  • the digital control value Digital_in_2 represents the high time of the control signal Ctrl2.
  • the AD converter 40 is an analog-digital conversion circuit that converts a feedback voltage from the output voltage Vo2 into a digital feedback voltage value.
  • the PID controller 39 uses the digital feedback voltage value converted by the AD converter 40 to perform a proportional-integral-differential (Proportional-Integral-Differential) operation so that the switching operation unit 2 can generate a desired output voltage.
  • the digital control value Digital_in_2 is generated.
  • the DPWM generator 38 is a digital PWM (Pulse Width Modulation) circuit that generates the control signal Ctrl2 by the clock CLOCK2_2 using the digital control value Digital_in_2 generated by the PID controller 39.
  • PWM Pulse Width Modulation
  • the variable delay unit 42 sets the delay time by the digital control value Digital_in generated by the PID controller 36, the digital control value Digital_in_2 generated by the PID controller 39, and the signal Slope2 output from the current slope comparator 59, A clock CLOCK2_2 obtained by delaying the clock CLOCK2_1 output from the frequency divider 24 by a set delay time is generated.
  • the delay time is the difference between the high time of the control signal Ctrl1 and the high time of the control signal Ctrl2.
  • the delay time is the high time of the control signal Ctrl1.
  • FIG. 6 is a timing chart showing an example of each signal in the power supply device 41 of FIG.
  • FIG. 7 is a timing chart showing another example of each signal in the power supply device 41 of FIG.
  • FIG. 6 shows an example of signal timing when the power supply device 41 shown in FIG. 5 matches the falling edge of the control signal Ctrl1 and the falling edge of the control signal Ctrl2 shown in FIG. is there.
  • FIG. 7 shows an example of signal timing when the power supply device 41 shown in FIG. 5 matches the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 shown in FIG. .
  • the frequency divider 24 generates clocks CLOCK1 and CLOCK2_1 whose frequencies are integer multiples from the reference clock output from the clock generation circuit 26, respectively.
  • the controller 33 generates a digital control value Digital_in representing a high time t1 of the control signal Ctrl1 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t1.
  • variable delay device 42 sets the delay setting time to t1 by the digital control value Digital_in representing the time t1.
  • the variable delay device 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period t1.
  • control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the rising edge of the control signal Ctrl2.
  • the duty ratio of the control signal Ctrl1 generated by the controller 33 increases from t1 / Ts1 to t2 / Ts2.
  • the controller 33 generates a digital control value Digital_in representing the time t2 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t2.
  • variable delay device 42 sets the delay setting time to t2 by the digital control value Digital_in representing the time t2.
  • variable delay device 42 delays the clock CLOCK2_1 by the period t2, and generates the clock CLOCK2_2 as the clock CLOCK2_2. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the rising edge of the control signal Ctrl2.
  • variable delay device 42 sets the delay setting time to t2-t3 by the digital control value Digital_in representing the time t2 and the digital control value Digital_in_2 representing the time t3.
  • the variable delay device 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period t2-t3. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the falling edge of the control signal Ctrl2.
  • the frequency divider 24 generates clocks CLOCK1 and CLOCK2_1 whose frequencies are integer multiples from the reference clock output from the clock generation circuit 26.
  • the controller 33 generates a digital control value Digital_in representing a high time t2 of the control signal Ctrl1 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t2.
  • variable delay device 42 sets the delay setting time to t2-t3 by the digital control value Digital_in representing the time t2 and the digital control value Digital_in_2 representing the time t3.
  • the variable delay device 42 generates a clock CLOCK2_2 obtained by delaying the clock CLOCK2_1 by a period of t2-t3. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the falling edge of the control signal Ctrl2.
  • the duty ratio of the control signal Ctrl1 generated by the controller 33 decreases from t2 / Ts1 to t1 / Ts2.
  • the controller 33 generates a digital control value Digital_in representing time t2 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t1.
  • variable delay device 42 sets the delay setting time to t1 ⁇ t3 by the digital control value Digital_in representing the time t2 and the digital control value Digital_in_2 representing the time t3.
  • the variable delay device 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period t2-t3. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the falling edge of the control signal Ctrl2.
  • variable delay device 42 sets the delay setting time to t1 by the digital control value Digital_in representing the time t1.
  • the variable delay device 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period t1. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the rising edge of the control signal Ctrl2.
  • the tracking time of the delay time of the control signal Ctrl2 can be shortened, so that the ripple of the output voltage Vo1 during the tracking period is suppressed. can do.
  • control signal Ctrl1 and the control signal Ctrl2 are not adjusted by the feedback control of the phase relationship between the control signal Ctrl1 and the control signal Ctrl2, but the control signal Ctrl1 is controlled by the ripple feedback control of the output voltage Vo1.
  • a technique for adjusting the delay of Ctrl1 and Ctrl2 will be described.
  • FIG. 8 is an explanatory diagram showing an example of the configuration of the power supply device 43 according to the third embodiment.
  • FIG. 8 parts having the same configuration as those in FIGS. 1 and 5 are denoted by the same reference numerals.
  • the generator 38 and the unit delay generator 27 are the same as those in FIG. 1 and FIG.
  • the power supply device 43 includes a switching operation unit 1, a switching operation unit 2, and a control unit 51.
  • the power supply device 43 inputs the feedback voltage from the output voltages Vo1 and Vo2 to the control unit 51, inputs the control signals Ctrl1 and Ctrl2 generated by the control unit 51 to the switching operation units 1 and 2, and outputs a desired output voltage value. Is generated.
  • the control unit 51 includes a controller 25, a controller 44, a frequency divider 24, a clock generation circuit 26, and a delay adjustment circuit 47.
  • the controller 44 includes an AD converter 45, a PID controller 36, and a DPWM generator 35.
  • the controller 44 is a digital controller such as a microcomputer, for example, and generates a control signal Ctrl1 to be input to the switching operation unit 1. Specifically, the feedback voltage from the output voltage Vo1 is converted into a digital feedback pressure value by the AD converter 45, and a digital control value is generated by the PID controller 36.
  • control signal Ctrl1 is generated from the DPWM generator 35 based on the clock CLOCK1 output from the frequency divider 24 and the digital control value generated by the PID controller 36.
  • the AD converter 45 is an analog-digital conversion circuit that converts a feedback voltage from the output voltage Vo1 into a digital feedback voltage value.
  • the digital feedback voltage converted by the AD converter 45 has two uses.
  • One is input to the PID controller 36 as in the second embodiment.
  • the other is to measure the magnitude of the ripple of the output voltage Vo1 every one cycle before the control signal Ctrl1.
  • the difference between the AD converter 45 and the AD converter 37 of FIG. 5 of the second embodiment is the sampling frequency.
  • the sampling frequency of the AD converter 37 is the same as the frequency of the control signal Ctrl1.
  • the sampling frequency of the AD converter 45 is set to a frequency that is, for example, twice or more higher than the frequency of the control signal Ctrl1. There is a need.
  • the delay adjustment circuit 47 includes a ripple comparator 52, a sample hold circuit 48, a ripple comparator 46, and a unit delay generator 27.
  • the delay adjustment circuit 47 adjusts the phase relationship between the control signal Ctrl1 and the control signal Ctrl2.
  • the ripple comparator 52 and the sample hold circuit 48 constitute a detector.
  • the ripple comparator 52 obtains the ripple value of the output voltage Vo1 in one cycle of the control signal Ctrl1 using the digital feedback voltage value of the output voltage Vo1 converted by the AD converter 45.
  • the sample hold circuit 48 stores the ripple value of the output voltage Vo1 one cycle before the control signal Ctrl1.
  • the ripple comparator 46 compares the ripple value of the output voltage Vo1 before and after one cycle of the control signal Ctrl1, and outputs the comparison results as pulse signals H_out and L_out.
  • the pulse signal H_out is generated.
  • the pulse signal L_out is generated.
  • the unit delay generator 27 delays the clock CLOCK2_1 from the frequency divider 24 by a desired delay time based on the pulse signals H_out and L_out detected from the ripple comparator 46, and generates the clock CLOCK2_2.
  • the ripple comparator 46 when the ripple comparator 46 generates the pulse signal L_out, the clock CLOCK2_2 obtained by delaying the clock CLOCK2_1 from the frequency divider 24 by reducing the delay time by one unit is output.
  • the controller 25 includes an AD converter 40, a PID controller 39, and a DPWM generator 38.
  • the controller 25 is a digital controller such as a microcomputer, for example, and generates a control signal Ctrl2.
  • a feedback voltage from the output voltage Vo2 is converted into a digital feedback pressure value by the AD converter 40, a digital control value is generated by the PID controller 39, and a clock output from the unit delay generator 27 is generated.
  • the DPWM generator 38 generates the control signal Ctrl2 based on the digital control value output from the CLOCK2_2 and the PID controller 39.
  • FIG. 9 is a timing chart showing an example of each signal in the control unit 51 in the power supply device 43 of FIG.
  • the frequency divider 24 generates clocks CLOCK 1 and CLOCK 2 _ 1 whose frequency is an integer multiple from the reference clock of the clock generation circuit 26.
  • the controller 44 generates a control signal Ctrl1 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1.
  • the initial delay setting time of the unit delay generator 27 is td.
  • the unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period td.
  • the controller 25 generates a control signal Ctrl2_2 from the feedback voltage from the output voltage Vo2 and the clock CLOCK2_2.
  • the ripple comparator 46 detects that the ripple value of the output voltage Vo1 one cycle before the control signal Ctrl1 is larger than one cycle later, and outputs the pulse signal H_out. As a result, the delay set in the unit delay generator 27 becomes td + x which is increased by one unit from the initial td.
  • Second period The output voltage Vo1 changes depending on the input voltage Batt or the operating state of the loads 49 and 50, and the duty ratio of the control signal Ctrl1 generated from the controller 44 increases.
  • the unit delay generator 27 delays the clock CLOCK2_1 by a period of td + x and generates the clock CLOCK2_2.
  • the ripple comparator 46 detects that the ripple value of the output voltage (Vo1) before one cycle of the control signal Ctrl1 is larger than after one cycle, and outputs the pulse signal H_out.
  • the delay set in the unit delay generator 27 is increased by 1 unit from the initial td, and becomes td + 2x.
  • the unit delay generator 27 delays the clock CLOCK2_1 by the period of td + 2x, and generates the clock CLOCK2_2.
  • the ripple comparator 46 detects that the ripple value of the output voltage Vo1 before one cycle of the control signal Ctrl1 is smaller than after one cycle, and outputs the pulse signal L_out. As a result, the delay set in the unit delay generator 27 is decreased by one unit from td + 2x to become td + x.
  • the delay set in the unit delay generator 27 by the pulse signal H_out or the pulse signal L_out is set repeatedly between td + 2x and td + x for each period.
  • a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. .
  • each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit.
  • Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor.
  • Information such as programs, tables, and files for realizing each function can be stored in a recording device such as a memory, a hard disk, an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.
  • control lines and information lines indicate what is considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. Actually, it may be considered that almost all the components are connected to each other.

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Abstract

The present invention generates a highly accurate power supply voltage with low loss without increasing the switching frequency of a switching power supply circuit. A power supply device 32 has a switching operation unit 1, another switching operation unit 2, a control circuit 12, another control circuit 20, and a phase control unit 6. The switching operation unit 1 generates an output voltage Vo1 from an externally input input-voltage Batt. The switching operation unit 2 generates an output voltage Vo2 from the output voltage Vo1. The control circuit 12 controls output voltage Vo1 on the basis of a clock CLOCK1. The control circuit 20 controls the output voltage Vo2 on the basis of a clock CLOCK2_2. The phase control unit 6 adjusts the frequency of the clock CLOCK1 and the frequency of the clock CLOCK2_2 to be an integral multiple and controls the delays of the clocks CLOCK1, CLOCK2_2 so that the ripple of the output voltage Vo1 is reduced.

Description

電源装置Power supply
　本発明は、電源装置に関し、特に、車載に搭載されるＥＣＵ(Electronic Control Unit)に電源を供給する電源装置による電源の制御に有効な技術に関する。 The present invention relates to a power supply device, and more particularly to a technique effective for controlling power by a power supply device that supplies power to an ECU (Electronic Control Unit) mounted on a vehicle.
　近年、ＬＳＩ（Large Scale Integration）回路の低電圧化により、車載ＥＣＵについても動作電圧が低電圧化される傾向にある。例えば車載ＥＣＵに用いられるマイクロコンピュータの動作電圧は、５Ｖあるいは３．３Ｖ程度あったものが、１Ｖ程度あるいはそれ以下の電圧となっている。 In recent years, due to the lower voltage of LSI (Large Scale Integration) circuits, the operating voltage of in-vehicle ECUs tends to be lowered. For example, the operating voltage of a microcomputer used in an in-vehicle ECU is about 5V or 3.3V, but is about 1V or less.
　それに伴い、該ＥＣＵに電源を供給する電源装置についても、低電圧化が要求される。この種の電源装置は、例えばスイッチング電源装置が広く用いられており、バッテリから供給される電源電圧を降圧して１Ｖ程度あるいはそれ以下の低電圧を生成する。 Along with this, the power supply device that supplies power to the ECU is also required to have a low voltage. As this type of power supply device, for example, a switching power supply device is widely used. The power supply voltage supplied from the battery is stepped down to generate a low voltage of about 1 V or less.
　また、スイッチング電源装置は、２つのスイッチング電源回路を直列に接続する２段構成のものが広く用いられており、これら２つのスイッチング電源回路によってバッテリの電源電圧を順に降圧することによりＥＣＵに供給する電源装置が生成される。 In addition, a switching power supply apparatus having a two-stage configuration in which two switching power supply circuits are connected in series is widely used, and the power supply voltage of the battery is sequentially stepped down by these two switching power supply circuits and supplied to the ECU. A power supply is generated.
　ここで、２つのスイッチング回路を有する理由は、以下の通りである。 Here, the reason for having two switching circuits is as follows.
　スイッチング電源回路が１つの場合、スイッチングデューティ比は入出力電圧比によって決まる。例えば入力電圧が４０Ｖ程度であり、出力電圧が１Ｖ程度の時には、スイッチングデューティ比が２．５％となる。 When there is one switching power supply circuit, the switching duty ratio is determined by the input / output voltage ratio. For example, when the input voltage is about 40V and the output voltage is about 1V, the switching duty ratio is 2.5%.
　スイッチング周波数を長くすれば、２．５％のデューティ比を適用できるスイッチング回路を作ることができる。しかし、負荷急変時、ＥＣＵにおけるマイクロコンピュータの電源電圧変動の仕様によってスイッチング周波数が一般的に５００ＫＨｚ以上必要であり、２．５％のデューティ比を適用できるスイッチング回路を作成することは困難である。 If the switching frequency is increased, a switching circuit that can apply a duty ratio of 2.5% can be made. However, when the load suddenly changes, the switching frequency is generally required to be 500 KHz or more depending on the specification of the power supply voltage fluctuation of the microcomputer in the ECU, and it is difficult to create a switching circuit that can apply a duty ratio of 2.5%.
　また、２段構成中の１つ目のスイッチング電源回路の出力電圧は、一般的にＥＣＵボードに載せる他の負荷、例えばＡ／Ｄ（Analog/Digital）変換器などの電源電圧としても用いられる。Ａ／Ｄ変換器の性能は、電源電圧の性能、すなわち電源電圧の精度によって左右するため、１つ目のスイッチング電源回路の出力電圧のリップル要求がより高いものとなる。 Also, the output voltage of the first switching power supply circuit in the two-stage configuration is generally used as a power supply voltage for other loads mounted on the ECU board, such as an A / D (Analog / Digital) converter. Since the performance of the A / D converter depends on the performance of the power supply voltage, that is, the accuracy of the power supply voltage, the output voltage ripple requirement of the first switching power supply circuit is higher.
　以上の理由から２つのスイッチング電源回路を直列接続した電源装置が用いられている。 For the above reasons, a power supply device in which two switching power supply circuits are connected in series is used.
　なお、この種のスイッチング電源回路については、例えば入力電圧と出力電圧との電圧比に応じて、適切なる縦続接続段数を有するスイッチング電源回路がある（例えば特許文献１参照）。 As for this type of switching power supply circuit, there is a switching power supply circuit having an appropriate number of cascade connection stages according to, for example, a voltage ratio between an input voltage and an output voltage (see, for example, Patent Document 1).
特開２０１１－２１１７６９号公報JP 2011-111769 A
　上述した２つのスイッチング電源回路を直列に接続した構成の電源装置の場合には、初段のスイッチング電源回路の出力電圧のリップルを抑制するために、次段のスイッチング電源回路のスイッチング周波数を高く設定する必要が生じる。 In the case of the power supply device having the configuration in which the two switching power supply circuits described above are connected in series, the switching frequency of the next-stage switching power supply circuit is set high in order to suppress the ripple of the output voltage of the first-stage switching power supply circuit. Need arises.
　しかしながら、２つ目のスイッチング電源回路のスイッチング周波数が増加すると、該スイッチング周波数が増加するに伴い、スイッチング素子によるスイッチング損失および該スイッチング素子を駆動するドライバのドライブ損失が大きくなってしまうという問題がある。これにより、電源装置における効率が低下してしまう。 However, when the switching frequency of the second switching power supply circuit increases, there is a problem that the switching loss due to the switching element and the drive loss of the driver that drives the switching element increase as the switching frequency increases. . Thereby, the efficiency in a power supply device will fall.
　本発明の目的は、スイッチング電源回路におけるスイッチング周波数を増加させることなく、低損失にて高精度な電源電圧を生成することのできる技術を提供することにある。 An object of the present invention is to provide a technique capable of generating a highly accurate power supply voltage with low loss without increasing a switching frequency in a switching power supply circuit.
　本発明の前記ならびにその他の目的と新規な特徴については、本明細書の記述および添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
　本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
　すなわち、代表的な電源装置は、第１のスイッチング電源回路、第２のスイッチング電源回路、第１の制御回路、第２の制御回路、および遅延生成部を有する。 That is, a typical power supply device includes a first switching power supply circuit, a second switching power supply circuit, a first control circuit, a second control circuit, and a delay generation unit.
　第１のスイッチング電源回路は、外部から入力される入力電圧から第１の出力電圧を生成する。第２のスイッチング電源回路は、第１の出力電圧から第２の出力電圧を生成する。 The first switching power supply circuit generates a first output voltage from an externally input voltage. The second switching power supply circuit generates a second output voltage from the first output voltage.
　第１の制御回路は、第１のスイッチング電源回路が生成する第１の出力電圧を第１のクロックに基づいて制御する。第２の制御回路は、第２のスイッチング電源回路が生成する第２の出力電圧を第２のクロックに基づいて制御する。 The first control circuit controls the first output voltage generated by the first switching power supply circuit based on the first clock. The second control circuit controls the second output voltage generated by the second switching power supply circuit based on the second clock.
　遅延生成部は、第１のクロックの周波数と第２のクロックの周波数とを整数倍に調整して、第１のクロックと第２のクロックとの遅延を第１の出力電圧のリップルを低減するように制御する。 The delay generation unit adjusts the frequency of the first clock and the frequency of the second clock to an integer multiple to reduce the delay between the first clock and the second clock and the ripple of the first output voltage. To control.
　また、第１のスイッチング電源回路は、第１のスイッチング部を有し、第２のスイッチング電源回路は、第２のスイッチング部を有する。第１のスイッチング部は、入力電圧をスイッチングする。第２のスイッチング部は、第１の出力電圧をスイッチングする。 Also, the first switching power supply circuit has a first switching unit, and the second switching power supply circuit has a second switching unit. The first switching unit switches the input voltage. The second switching unit switches the first output voltage.
　そして、第１の制御回路は、第１のクロックから第１のスイッチング部を制御する第１の制御信号を生成し、第２の制御回路は、第２のクロックから第２のスイッチング部を制御する第２の制御信号を生成する。遅延生成部は、第１の制御信号と第２の制御信号との位相を制御して、第１のクロックおよび第２のクロックの遅延を制御する。 The first control circuit generates a first control signal for controlling the first switching unit from the first clock, and the second control circuit controls the second switching unit from the second clock. A second control signal is generated. The delay generation unit controls the phases of the first control signal and the second control signal to control the delays of the first clock and the second clock.
　さらに、代表的な電源装置は、エッジ検出器を有する。エッジ検出器は、第１の制御信号と第２の制御信号との信号立ち上がりエッジまたは信号立ち下がりエッジを検出する。 Furthermore, a typical power supply device has an edge detector. The edge detector detects a signal rising edge or a signal falling edge between the first control signal and the second control signal.
　遅延生成部は、第１の制御信号と第２の制御信号との信号立ち上がりエッジまたは信号立ち下がりエッジを揃えるように第１のクロックおよび第２のクロックの遅延を制御する。 The delay generation unit controls the delays of the first clock and the second clock so that the signal rising edges or signal falling edges of the first control signal and the second control signal are aligned.
　本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。 Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
　（１）電源装置における損失を低減することができる。 (1) Loss in the power supply device can be reduced.
　（２）精度の高い出力電圧を生成することができる。 (2) A highly accurate output voltage can be generated.
　（３）上記（１）、（２）により、信頼性の高い電源装置を実現することができる。 (3) According to the above (1) and (2), a highly reliable power supply device can be realized.
実施の形態１による電源装置による構成の一例を示す説明図である。3 is an explanatory diagram illustrating an example of a configuration of a power supply device according to Embodiment 1. FIG. 図１の制御回路が生成する制御信号の位相関係の一例を示す説明図である。It is explanatory drawing which shows an example of the phase relationship of the control signal which the control circuit of FIG. 1 produces | generates. 図１の電源装置が有する制御部における各信号の一例を示すタイミングチャートである。It is a timing chart which shows an example of each signal in the control part which the power supply device of FIG. 1 has. 図１の電源装置が有する制御部における各信号の他の例を示すタイミングチャートである。It is a timing chart which shows the other example of each signal in the control part which the power supply device of FIG. 1 has. 実施の形態２による電源装置における構成の一例を示す説明図である。FIG. 10 is an explanatory diagram illustrating an example of a configuration of a power supply device according to a second embodiment. 図５の電源装置における各信号の一例を示すタイミングチャートである。It is a timing chart which shows an example of each signal in the power supply device of FIG. 図５の電源装置における各信号の他の例を示すタイミングチャートである。6 is a timing chart showing another example of each signal in the power supply device of FIG. 5. 実施の形態３による電源装置における構成の一例を示す説明図である。FIG. 10 is an explanatory diagram illustrating an example of a configuration of a power supply device according to a third embodiment. 図８の電源装置における制御部における各信号の一例を示すタイミングチャートである。It is a timing chart which shows an example of each signal in the control part in the power supply device of FIG. 実施の形態に対する比較技術における電源装置の構成の一例を示す説明図である。It is explanatory drawing which shows an example of a structure of the power supply device in the comparison technique with respect to embodiment. 図１０の電源装置における動作の一例を示す説明図である。It is explanatory drawing which shows an example of operation | movement in the power supply device of FIG. 図１０の制御回路が生成する制御信号に位相差がある場合の出力電圧のリップルのワーストケースの発生原因の一例を示した説明図である。FIG. 11 is an explanatory diagram illustrating an example of a cause of the worst case of output voltage ripple when the control signal generated by the control circuit of FIG. 10 has a phase difference. 図１２に示したワーストケース時の出力電圧のリップルを低減する例を示した説明図である。It is explanatory drawing which showed the example which reduces the ripple of the output voltage at the time of the worst case shown in FIG.
 実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する。 In all the drawings for explaining the embodiments, the same members are, in principle, given the same reference numerals, and the repeated explanation thereof is omitted.
　（実施の形態１）
　〈実施の形態に対する比較技術〉　
　以下の実施の形態においては、本発明の特徴を分かり易くするために、本実施の形態に対する比較技術と比較して説明する。まず、本実施の形態に対する比較技術を説明する。 (Embodiment 1)
<Comparison technology to the embodiment>
In the following embodiment, in order to make the features of the present invention easier to understand, the description will be made in comparison with a comparative technique for the present embodiment. First, a comparison technique with respect to the present embodiment will be described.
　本実施の形態に対する比較技術における２段構成の電源装置について説明する。 A description will be given of a power supply device having a two-stage configuration in a comparison technique with respect to this embodiment.
　図１０は、本実施の形態に対する比較技術における電源装置の構成の一例を示す説明図である。 FIG. 10 is an explanatory diagram showing an example of the configuration of the power supply device in the comparison technique with respect to the present embodiment.
　この場合、電源装置は、図１０に示すように、スイッチング電源回路３０およびスイッチング電源回路３１を有する構成からなり、これらスイッチング電源回路３０，３１が直列に接続されている。 In this case, as shown in FIG. 10, the power supply device has a configuration including a switching power supply circuit 30 and a switching power supply circuit 31, and the switching power supply circuits 30 and 31 are connected in series.
　１個目のスイッチング電源回路３０は、入力電圧Ｂａｔｔから出力電圧Ｖｏ１を生成する。入力電圧Ｂａｔｔは、図示しないバッテリの電源電圧である。出力電圧Ｖｏ１は、バッテリ電圧Ｂａｔｔよりも低い電圧である。 The first switching power supply circuit 30 generates the output voltage Vo1 from the input voltage Batt. The input voltage Batt is a power supply voltage of a battery (not shown). The output voltage Vo1 is a voltage lower than the battery voltage Batt.
　２個目のスイッチング電源回路３１は、出力電圧Ｖｏ１から出力電圧Ｖｏ２を生成する。出力電圧Ｖｏ２は、出力電圧Ｖｏ１よりも低い電圧である。ここで、出力電圧Ｖｏ１は、第１の出力電圧であり、出力電圧Ｖｏ２は、第２の出力電圧である。 The second switching power supply circuit 31 generates the output voltage Vo2 from the output voltage Vo1. The output voltage Vo2 is a voltage lower than the output voltage Vo1. Here, the output voltage Vo1 is a first output voltage, and the output voltage Vo2 is a second output voltage.
　電源装置に接続される負荷４９は、出力電圧Ｖｏ１を動作電源とする負荷であり、例えばＡ／Ｄ変換器などのアナログ回路である。同様に、電源装置に接続される負荷５０は、出力電圧Ｖｏ２を動作電源とする負荷であり、例えばマイクロコンピュータなどである。 The load 49 connected to the power supply device is a load using the output voltage Vo1 as an operation power supply, and is an analog circuit such as an A / D converter, for example. Similarly, the load 50 connected to the power supply device is a load that uses the output voltage Vo2 as an operation power supply, and is, for example, a microcomputer.
　スイッチング電源回路３０は、スイッチング動作部１および制御部３を有する。このスイッチング電源回路３０は、出力電圧Ｖｏ１からの帰還電圧を制御部３に入力し、制御部３が生成した制御信号Ｃｔｒｌ１をスイッチング動作部１に入力して、所望の出力電圧値を生成する。制御信号Ｃｔｒｌ１は、第１の制御信号となる。 The switching power supply circuit 30 includes a switching operation unit 1 and a control unit 3. The switching power supply circuit 30 inputs a feedback voltage from the output voltage Vo1 to the control unit 3 and inputs a control signal Ctrl1 generated by the control unit 3 to the switching operation unit 1 to generate a desired output voltage value. The control signal Ctrl1 is a first control signal.
　スイッチング動作部１は、スイッチング素子７、スイッチング素子８、インダクタ９、平滑用出力容量１０、およびドライバ１１を有する。 The switching operation unit 1 includes a switching element 7, a switching element 8, an inductor 9, a smoothing output capacitor 10, and a driver 11.
　スイッチング素子７がオンして、第１のスイッチング部であるスイッチング素子８がオフすると、エネルギをインダクタ９に蓄積しながら、負荷４９と負荷５０を駆動する。一方、スイッチング素子７がオフし、スイッチング素子８がオンすると、インダクタ９に蓄積したエネルギを放出し、負荷４９と負荷５０を駆動する。 When the switching element 7 is turned on and the switching element 8 as the first switching unit is turned off, the load 49 and the load 50 are driven while energy is stored in the inductor 9. On the other hand, when the switching element 7 is turned off and the switching element 8 is turned on, the energy accumulated in the inductor 9 is released, and the load 49 and the load 50 are driven.
　平滑用出力容量１０は、コンデンサであり、スイッチング電源回路３０の出力電圧Ｖｏ１の電圧リップルを抑制する。ドライバ１１は、制御部３から出力される制御信号Ｃｔｒｌ１によってスイッチング素子７、スイッチング素子８をそれぞれ駆動してスイッチング動作させる駆動回路である。 The smoothing output capacitor 10 is a capacitor and suppresses the voltage ripple of the output voltage Vo1 of the switching power supply circuit 30. The driver 11 is a drive circuit that drives the switching element 7 and the switching element 8 with a control signal Ctrl1 output from the control unit 3 to perform a switching operation.
　スイッチング素子７は、例えばＮチャネルＭＯＳ（Metal Oxide Semiconductor）トランジスタなどからなり、スイッチング素子８は、ＰチャネルＭＯＳトランジスタなどからなる。スイッチング素子７は、ドライバ１１から出力される信号がハイ信号の際にオンし、スイッチング素子８は、ドライバ１１から出力される信号がロー信号の際にオンする。 The switching element 7 is composed of, for example, an N channel MOS (Metal Oxide Semiconductor) transistor, and the switching element 8 is composed of a P channel MOS transistor or the like. The switching element 7 is turned on when the signal output from the driver 11 is a high signal, and the switching element 8 is turned on when the signal output from the driver 11 is a low signal.
　制御部３は、制御回路１２、分周器２１、およびクロック生成回路４を有する。クロック生成回路４は、基準クロックを生成する、この基準クロックは、スイッチング電源回路３０の制御部３の基準クロックとなる。 The control unit 3 includes a control circuit 12, a frequency divider 21, and a clock generation circuit 4. The clock generation circuit 4 generates a reference clock, and this reference clock becomes a reference clock for the control unit 3 of the switching power supply circuit 30.
　分周器２１は、クロック生成回路４からの基準クロックによってスイッチング電源回路３０のスイッチング素子７、スイッチング素子８のオン／オフ動作の周波数を決めるクロックを生成する回路である。 The frequency divider 21 is a circuit that generates a clock that determines the on / off operation frequency of the switching element 7 and the switching element 8 of the switching power supply circuit 30 based on the reference clock from the clock generation circuit 4.
　第１の制御回路である制御回路１２は、出力電圧Ｖｏ１における帰還電圧と分周器２１から出力されるクロックに基づいて制御信号Ｃｔｒｌ１を生成する回路である。制御信号Ｃｔｒｌ１の周波数は、分周器２１から出力されるクロックの周波数によって決まる。 The control circuit 12, which is the first control circuit, is a circuit that generates the control signal Ctrl1 based on the feedback voltage at the output voltage Vo1 and the clock output from the frequency divider 21. The frequency of the control signal Ctrl1 is determined by the frequency of the clock output from the frequency divider 21.
　スイッチング電源回路３１は、スイッチング動作部２および制御部２９を有する。スイッチング電源回路３１は、出力電圧Ｖｏ２における帰還電圧が制御部２９に入力され、該制御部２９が生成した制御信号Ｃｔｒｌ２をスイッチング動作部２に入力することにより、所望の出力電圧値を生成する。制御信号Ｃｔｒｌ２は、第２の制御信号となる。 The switching power supply circuit 31 includes a switching operation unit 2 and a control unit 29. The switching power supply circuit 31 generates a desired output voltage value by inputting the feedback voltage at the output voltage Vo2 to the control unit 29 and inputting the control signal Ctrl2 generated by the control unit 29 to the switching operation unit 2. The control signal Ctrl2 is a second control signal.
　スイッチング動作部２は、スイッチング素子１４、スイッチング素子１５、インダクタ１６、平滑用出力容量１７、およびドライバ１８を有する。スイッチング素子１４，１５は、例えばＭＯＳトランジスタなどからなる。 The switching operation unit 2 includes a switching element 14, a switching element 15, an inductor 16, a smoothing output capacitor 17, and a driver 18. The switching elements 14 and 15 are made of MOS transistors, for example.
　スイッチング素子１４がオンして、第２のスイッチングであるスイッチング素子１５がオフすると、エネルギを第２のインダクタであるインダクタ１６に蓄積しながら、負荷５０を駆動する。一方、スイッチング素子１４がオフし、スイッチング素子１５がオンすると、インダクタ１６に蓄積したエネルギを放出し、負荷５０を駆動する。 When the switching element 14 is turned on and the switching element 15 that is the second switching is turned off, the load 50 is driven while accumulating energy in the inductor 16 that is the second inductor. On the other hand, when the switching element 14 is turned off and the switching element 15 is turned on, the energy accumulated in the inductor 16 is released and the load 50 is driven.
　平滑用出力容量１７は、平滑用出力容量１０と同様にコンデンサであり、スイッチング電源回路３１の出力電圧Ｖｏ２の電圧リップルを抑制する。 The smoothing output capacitor 17 is a capacitor similarly to the smoothing output capacitor 10, and suppresses voltage ripple of the output voltage Vo2 of the switching power supply circuit 31.
　ドライバ１８は、制御部２９の制御信号Ｃｔｒｌ２に基づいてスイッチング素子１４、スイッチング素子１５のスイッチング動作を制御する駆動回路である。 The driver 18 is a drive circuit that controls the switching operation of the switching element 14 and the switching element 15 based on the control signal Ctrl2 of the control unit 29.
　スイッチング素子１４は、例えばＮチャネルＭＯＳ（Metal Oxide Semiconductor）トランジスタなどからなり、スイッチング素子１５は、ＰチャネルＭＯＳトランジスタなどからなる。スイッチング素子１４は、ドライバ１８から出力される信号がハイ信号の際にオンし、スイッチング素子１５は、ドライバ１８から出力される信号がロー信号の際にオンする。 The switching element 14 is composed of, for example, an N channel MOS (Metal Oxide Semiconductor) transistor, and the switching element 15 is composed of a P channel MOS transistor or the like. The switching element 14 is turned on when the signal output from the driver 18 is a high signal, and the switching element 15 is turned on when the signal output from the driver 18 is a low signal.
　制御部２９は、制御回路２０、分周器２２、およびクロック生成回路２３を有する。クロック生成回路２３は、基準クロックを生成する。この基準クロックは、スイッチング電源回路３１の制御部２９の基準クロックとなる。 The control unit 29 includes a control circuit 20, a frequency divider 22, and a clock generation circuit 23. The clock generation circuit 23 generates a reference clock. This reference clock is a reference clock for the control unit 29 of the switching power supply circuit 31.
　分周器２２は、クロック生成回路２３が生成する基準クロックからスイッチング電源回路３１のスイッチング素子１４およびスイッチング素子１５のオン／オフ動作の周波数を決めるクロックを生成する。 The frequency divider 22 generates a clock that determines the on / off operation frequency of the switching element 14 and the switching element 15 of the switching power supply circuit 31 from the reference clock generated by the clock generation circuit 23.
　第２の制御回路である制御回路２０は、出力電圧Ｖｏ２における帰還電圧と分周器２２が生成するクロックに基づいて、制御信号Ｃｔｒｌ２を生成する。この制御信号Ｃｔｒｌ２の周波数は、分周器２２が生成するクロックの周波数によって決まる。 The control circuit 20 as the second control circuit generates the control signal Ctrl2 based on the feedback voltage in the output voltage Vo2 and the clock generated by the frequency divider 22. The frequency of the control signal Ctrl2 is determined by the frequency of the clock generated by the frequency divider 22.
　図１１は、図１０の電源装置における動作の一例を示す説明図である。 FIG. 11 is an explanatory diagram showing an example of the operation of the power supply device of FIG.
　図１１は、上方に制御回路１２から出力される制御信号Ｃｔｒｌ１の信号タイミングを示しており、その下方には、制御回路２０から出力される制御信号Ｃｔｒｌ２の信号タイミングを示している。 FIG. 11 shows the signal timing of the control signal Ctrl1 output from the control circuit 12 in the upper part, and the signal timing of the control signal Ctrl2 output from the control circuit 20 in the lower part.
　また、図１２および図１３は、上方から下方にかけて、制御回路１２から出力される制御信号Ｃｔｒｌ１、制御回路２０から出力される制御信号Ｃｔｒｌ２、電流Ｉｏ，ＩＬ、および出力電圧Ｖｏ１のリップルにおける信号タイミングをそれぞれ示している。インダクタ電流である電流ＩＬは、平滑用出力容量１０の入力電流であり、電流Ｉｏは、平滑用出力容量１０の出力電流である。 12 and 13 show signal timings in the ripples of the control signal Ctrl1 output from the control circuit 12, the control signal Ctrl2 output from the control circuit 20, the currents Io and IL, and the output voltage Vo1 from above to below. Respectively. A current IL that is an inductor current is an input current of the smoothing output capacitor 10, and a current Io is an output current of the smoothing output capacitor 10.
　図１０に示した電源装置では、制御信号Ｃｔｒｌ１、Ｃｔｒｌ２が制御回路１２，２０によってそれぞれ生成されている。そのため、制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２との位相関係は、制御されていない。言い換えれば固定ではない。 In the power supply device shown in FIG. 10, control signals Ctrl1 and Ctrl2 are generated by the control circuits 12 and 20, respectively. Therefore, the phase relationship between the control signal Ctrl1 and the control signal Ctrl2 is not controlled. In other words, it is not fixed.
　制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２との周波数に差があると、制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２との位相関係が少しずつ変わっていく。これによって、図１１に示すように、スイッチング電源回路３０の出力電圧Ｖｏ１のリップルが最大となるワーストケースが生じる。 If there is a difference in frequency between the control signal Ctrl1 and the control signal Ctrl2, the phase relationship between the control signal Ctrl1 and the control signal Ctrl2 changes little by little. As a result, as shown in FIG. 11, a worst case occurs in which the ripple of the output voltage Vo1 of the switching power supply circuit 30 becomes maximum.
　図１２は、図１０の制御回路が生成する制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２とに位相差がある場合に、スイッチング電源回路３０の出力電圧Ｖｏ１におけるリップルのワーストケースの発生原因の一例を示した説明図である。 FIG. 12 illustrates an example of the cause of the worst case of the ripple in the output voltage Vo1 of the switching power supply circuit 30 when there is a phase difference between the control signal Ctrl1 and the control signal Ctrl2 generated by the control circuit of FIG. FIG.
　平滑用出力容量１０の入出力の電荷量の差、図１２においてハッチングにて示す領域が大きいほど、出力電圧Ｖｏ１のリップルが大きくなる。平滑用出力容量１０の入出力の電荷量の差、すなわち図１２のハッチングにて示す領域の面積は、平滑用出力容量１０の入出力電流の差および入出力電流の差が生じる期間によって決まる。 The ripple of the output voltage Vo1 increases as the difference in charge amount between the input and output of the smoothing output capacitor 10, that is, the region indicated by hatching in FIG. The difference in charge amount between the input and output of the smoothing output capacitor 10, that is, the area of the region indicated by hatching in FIG.
　平滑用出力容量１０の入力電流、すなわち電流ＩＬは、制御信号Ｃｔｒｌ１によってスイッチング素子７、スイッチング素子８のオン／オフ動作から生成される三角波のような電流である。 The input current of the smoothing output capacitor 10, that is, the current IL is a current like a triangular wave generated from the on / off operation of the switching element 7 and the switching element 8 by the control signal Ctrl1.
　平滑用出力容量１０の出力電流、すなわち電流Ｉｏは、制御信号Ｃｔｒｌ２によってスイッチング素子１４、スイッチング素子１５のオン／オフ動作から生成される矩形波のような電流である。 The output current of the smoothing output capacitor 10, that is, the current Io is a current like a rectangular wave generated from the on / off operation of the switching element 14 and the switching element 15 by the control signal Ctrl2.
　図１２に示したように、制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２との位相関係によって、電流ＩＬと電流Ｉｏの間の差が最も大きい期間が生じて、入出力の電荷量の差（ハッチングにて示す領域の面積）が最大となるため、出力電圧Ｖｏ１のリップルが最大となるワーストケースが発生する。 As shown in FIG. 12, the phase relationship between the control signal Ctrl1 and the control signal Ctrl2 causes a period in which the difference between the current IL and the current Io is the largest, and the difference between the input and output charge amounts (shown by hatching). As a result, the worst case in which the ripple of the output voltage Vo1 is maximized occurs.
　図１３は、図１２に示したワーストケース時の出力電圧Ｖｏ１のリップルを低減する例を示した説明図である。 FIG. 13 is an explanatory diagram showing an example of reducing the ripple of the output voltage Vo1 in the worst case shown in FIG.
　この場合、電流ＩＬと電流Ｉｏとの間の差が最も大きい期間を短縮することで、平滑用出力容量１０の入出力の電荷量の差（ハッチングにて示す領域の面積）を低減することができる。すなわち、制御信号Ｃｔｒｌ２の周波数を制御信号Ｃｔｒｌ１の周波数より高く設定することである。 In this case, by shortening the period in which the difference between the current IL and the current Io is the largest, the difference in the charge amount between the input and output of the smoothing output capacitor 10 (area of the area indicated by hatching) can be reduced. it can. That is, the frequency of the control signal Ctrl2 is set higher than the frequency of the control signal Ctrl1.
　しかしながら、制御信号Ｃｔｒｌ２の周波数が増加すると、スイッチング素子１４およびスイッチング素子１５のスイッチング損失ならびにドライバ１８の駆動損失が増加してしまうことになる。そこで、本実施の形態では、上述した比較技術に存在する課題に対する工夫を施している。 However, when the frequency of the control signal Ctrl2 increases, the switching loss of the switching element 14 and the switching element 15 and the driving loss of the driver 18 increase. Therefore, in this embodiment, a device for the problems existing in the above-described comparison technique is devised.
　以下、実施の形態を詳細に説明する。 Hereinafter, embodiments will be described in detail.
　〈電源装置の構成例〉
　図１は、本実施の形態１による電源装置による構成の一例を示す説明図である。なお、図１においては、上述した図１０と同一の構成部分には同一の符号を付している。 <Configuration example of power supply device>
FIG. 1 is an explanatory diagram showing an example of the configuration of the power supply device according to the first embodiment. In FIG. 1, the same components as those in FIG. 10 described above are denoted by the same reference numerals.
　図１に示す電源装置３２は、スイッチング動作部１、スイッチング動作部２、および制御部５を有する。電源装置３２は、出力電圧Ｖｏ１および出力電圧Ｖｏ２からの帰還電圧を制御部５に入力する。 1 includes a switching operation unit 1, a switching operation unit 2, and a control unit 5. The power supply device 32 inputs the feedback voltage from the output voltage Vo1 and the output voltage Vo2 to the control unit 5.
　そして、制御部５が生成した制御信号Ｃｔｒｌ１および制御信号Ｃｔｒｌ２をスイッチング動作部１，２にそれぞれ入力し、所望の出力電圧値を生成することにより、負荷４９，５０に動作電源を供給する。スイッチング動作部１は、第１のスイッチング電源回路であり、スイッチング動作部２は、第２のスイッチング電源回路である。 Then, the control signal Ctrl1 and the control signal Ctrl2 generated by the control unit 5 are respectively input to the switching operation units 1 and 2 to generate desired output voltage values, thereby supplying operating power to the loads 49 and 50. The switching operation unit 1 is a first switching power supply circuit, and the switching operation unit 2 is a second switching power supply circuit.
　制御部５は、制御回路１２、制御回路２０、分周器２４、クロック生成回路２６、電圧検出比較部５６、および位相制御部６を有する。 The control unit 5 includes a control circuit 12, a control circuit 20, a frequency divider 24, a clock generation circuit 26, a voltage detection comparison unit 56, and a phase control unit 6.
　ここで、図１におけるスイッチング動作部１、スイッチング動作部２、負荷４９，５０、制御回路１２、および制御回路２０は、図１０と同様であるので説明を省略する。 Here, the switching operation unit 1, the switching operation unit 2, the loads 49 and 50, the control circuit 12, and the control circuit 20 in FIG. 1 are the same as those in FIG.
　クロック生成回路２６は、制御部５の基準クロックを生成する。分周器２４は、クロック生成回路２６が生成した基準クロックに基づいて、クロックＣＬＯＣＫ１およびクロックＣＬＯＣＫ２＿１をそれぞれ生成する。クロックＣＬＯＣＫ１は、第１のクロックとなる。 The clock generation circuit 26 generates a reference clock for the control unit 5. The frequency divider 24 generates a clock CLOCK1 and a clock CLOCK2_1 based on the reference clock generated by the clock generation circuit 26, respectively. The clock CLOCK1 becomes the first clock.
　クロックＣＬＯＣＫ１は、スイッチング動作部１のスイッチング素子７およびスイッチング素子８のオン／オフ動作の周波数１／Ｔｓ１を決めるクロックである。クロックＣＬＯＣＫ２＿１は、スイッチング動作部２のスイッチング素子１４およびスイッチング素子１５のオン／オフ動作の周波数１／Ｔｓ２を決めるクロックである。クロックＣＬＯＣＫ１とクロックＣＬＯＣＫ２＿１は、周波数が整数倍である。 The clock CLOCK 1 is a clock that determines the frequency 1 / Ts 1 of the on / off operation of the switching element 7 and the switching element 8 of the switching operation unit 1. The clock CLOCK2_1 is a clock that determines the frequency 1 / Ts2 of the on / off operation of the switching element 14 and the switching element 15 of the switching operation unit 2. The frequency of the clock CLOCK1 and the clock CLOCK2_1 is an integral multiple.
　電圧検出比較部５６は、入力電圧検出器５３、出力電圧検出器５４、および電圧比較器５５を有する。電圧検出比較部５６は、信号Ｓｌｏｐｅ１を生成する。この信号Ｓｌｏｐｅ１は、電源装置３２に入力され、入力電圧Ｂａｔｔと出力電圧Ｖｏ１の間の関係によってインダクタ９に流れる電流ＩＬの上昇と低下の傾きの大きさの関係を示す信号である。入力電圧Ｂａｔｔは、図示しない自動車に搭載されるバッテリから出力される。 The voltage detection comparator 56 includes an input voltage detector 53, an output voltage detector 54, and a voltage comparator 55. The voltage detection / comparison unit 56 generates the signal Slope1. This signal Slope1 is a signal that is input to the power supply device 32 and indicates the relationship between the magnitude of the rise and fall of the current IL flowing through the inductor 9 depending on the relationship between the input voltage Batt and the output voltage Vo1. The input voltage Batt is output from a battery mounted on an automobile (not shown).
　入力電圧検出器５３は、入力電圧Ｂａｔｔの電圧レベルを検出する。出力電圧検出器５４は、出力電圧Ｖｏ１の電圧レベルを検出する。これら入力電圧検出器５３および出力電圧検出器５４によって電圧検出部が構成される。 The input voltage detector 53 detects the voltage level of the input voltage Batt. The output voltage detector 54 detects the voltage level of the output voltage Vo1. These input voltage detector 53 and output voltage detector 54 constitute a voltage detector.
　電圧比較器５５は、入力電圧検出器５３が検出した入力電圧Ｂａｔｔと出力電圧検出器５４が検出した出力電圧Ｖｏ１とを比較して信号Ｓｌｏｐｅを生成する。 The voltage comparator 55 compares the input voltage Batt detected by the input voltage detector 53 with the output voltage Vo1 detected by the output voltage detector 54 to generate a signal Slope.
　入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より大きい場合、第１のインダクタであるインダクタ９に流れる電流ＩＬの上昇の傾きは、電流ＩＬの低下の傾きより大きく、信号Ｓｌｏｐｅ１がローになる。 When the difference between the input voltage Batt and the output voltage Vo1 is larger than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 as the first inductor is larger than the falling slope of the current IL, and the signal Slope1 is low. Become.
　入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より小さい場合、インダクタ９に流れる電流ＩＬの上昇の傾きは、電流ＩＬの低下の傾きより小さく、信号Ｓｌｏｐｅ１がハイになる。 When the difference between the input voltage Batt and the output voltage Vo1 is smaller than the output voltage Vo1, the increase slope of the current IL flowing through the inductor 9 is smaller than the decrease slope of the current IL, and the signal Slope1 becomes high.
　遅延生成部である位相制御部６は、エッジ検出器２８および単位遅延生成器２７を有する。この位相制御部６は、制御信号Ｃｔｒｌ１および制御信号Ｃｔｒｌ２の位相関係を制御する。 The phase control unit 6 that is a delay generation unit includes an edge detector 28 and a unit delay generator 27. The phase control unit 6 controls the phase relationship between the control signal Ctrl1 and the control signal Ctrl2.
　エッジ検出器２８は、制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２との位相差を検出する。エッジ検出器２８は、制御信号Ｃｔｒｌ１の立ち下がりエッジのタイミングにて制御信号Ｃｔｒｌ２のハイ／ローを検出する。制御信号Ｃｔｒｌ２がハイの場合は、パルス信号Ｈ＿ｏｕｔを生成して出力し、制御信号Ｃｔｒｌ２がローの場合には、パルス信号Ｌ＿ｏｕｔを生成して出力する。 The edge detector 28 detects the phase difference between the control signal Ctrl1 and the control signal Ctrl2. The edge detector 28 detects high / low of the control signal Ctrl2 at the timing of the falling edge of the control signal Ctrl1. When the control signal Ctrl2 is high, the pulse signal H_out is generated and output. When the control signal Ctrl2 is low, the pulse signal L_out is generated and output.
　単位遅延生成器２７は、エッジ検出器２８が検出したパルス信号Ｈ＿ｏｕｔ，Ｌ＿ｏｕｔと電圧検出比較部５６から出力される信号Ｓｌｏｐｅ１に基づいて、分周器２４からのクロックＣＬＯＣＫ２＿１を所望の遅延時間にて遅延させた第２のクロックとなるクロックＣＬＯＣＫ２＿２を生成する。 The unit delay generator 27 generates the clock CLOCK2_1 from the frequency divider 24 at a desired delay time based on the pulse signals H_out and L_out detected by the edge detector 28 and the signal Slope1 output from the voltage detection comparator 56. A clock CLOCK2_2 as a delayed second clock is generated.
　信号Ｓｌｏｐｅ１がローであり、エッジ検出器２８から出力されるパルス信号がパルス信号Ｈ＿ｏｕｔの場合には、分周器２４からのクロックＣＬＯＣＫ２＿１を１単位分増加するように遅延させて、クロックＣＬＯＣＫ２＿２として出力する。ここで、１単位とは、スイッチング素子７がオンすることのできる最少の時間、すなわちスイッチングタイムの最小時間である。 When the signal Slope1 is low and the pulse signal output from the edge detector 28 is the pulse signal H_out, the clock CLOCK2_1 from the frequency divider 24 is delayed so as to increase by one unit and output as the clock CLOCK2_2. To do. Here, one unit is the minimum time that the switching element 7 can be turned on, that is, the minimum time of the switching time.
　一方、信号Ｓｌｏｐｅ１がローであり、エッジ検出器２８から出力されるパルス信号がパルス信号Ｌ＿ｏｕｔの場合には、クロックＣＬＯＣＫ２＿１の遅延時間を１単位分減少するように遅延させたクロックをクロックＣＬＯＣＫ２＿２として出力する。 On the other hand, when the signal Slope1 is low and the pulse signal output from the edge detector 28 is the pulse signal L_out, a clock obtained by delaying the delay time of the clock CLOCK2_1 by one unit is output as the clock CLOCK2_2. To do.
　信号Ｓｌｏｐｅ１がハイであり、エッジ検出器２８の出力がパルス信号Ｈ＿ｏｕｔの場合には、クロック信号ＣＬＯＣＫ２＿１の遅延時間を１単位分減少するように遅延させたクロックをクロックＣＬＯＣＫ２＿２として出力する。 When the signal Slope1 is high and the output of the edge detector 28 is the pulse signal H_out, a clock obtained by delaying the delay time of the clock signal CLOCK2_1 by one unit is output as the clock CLOCK2_2.
　また、信号Ｓｌｏｐｅ１がハイであり、エッジ検出器２８の出力がパルス信号Ｌ＿ｏｕｔの場合には、クロックＣＬＯＣＫ２＿１の遅延時間を１単位分増加するように遅延させたクロックをクロックＣＬＯＣＫ２＿２として出力する。 Also, when the signal Slope1 is high and the output of the edge detector 28 is the pulse signal L_out, a clock obtained by delaying the delay time of the clock CLOCK2_1 by one unit is output as the clock CLOCK2_2.
　制御部５は、以下に示す工夫によって、制御信号Ｃｔｒｌ２の周波数を増加することなく、出力電圧Ｖｏ１のリップルを低減することができるものである。 The controller 5 can reduce the ripple of the output voltage Vo1 without increasing the frequency of the control signal Ctrl2 by the following device.
　（１）制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２との位相関係を固定するために、周波数が整数倍である制御信号Ｃｔｒｌ１，Ｃｔｒｌ２を生成する分周器２４を設ける。ここで、制御信号Ｃｔｒｌ１，Ｃｔｒｌ２の周波数が同じである時を一例として説明する。 (1) In order to fix the phase relationship between the control signal Ctrl1 and the control signal Ctrl2, a frequency divider 24 for generating the control signals Ctrl1 and Ctrl2 whose frequencies are integer multiples is provided. Here, a case where the frequencies of the control signals Ctrl1 and Ctrl2 are the same will be described as an example.
　（２）制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２間の位相関係を所望の位相関係になるように位相制御部６にて制御信号Ｃｔｒｌ２を遅延させる。制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２との間の所望の位相関係は、図１２に比べて、平滑用出力容量１０の入出力電流である電流ＩＬと電流Ｉｏと差が小さくなり、入出力の電荷量の差（図１２のハッチングにて示す領域の面積）が小さくなる関係である。 (2) The phase control unit 6 delays the control signal Ctrl2 so that the phase relationship between the control signal Ctrl1 and the control signal Ctrl2 becomes a desired phase relationship. The desired phase relationship between the control signal Ctrl1 and the control signal Ctrl2 has a smaller difference between the current IL and the current Io, which are the input / output currents of the smoothing output capacitor 10, compared to FIG. (The area of the region indicated by hatching in FIG. 12) is reduced.
　〈制御信号の位相について〉
　図２は、図１の制御回路が生成する制御信号Ｃｔｒｌ１，Ｃｔｒｌ２の位相関係の一例を示す説明図である。 <About the phase of the control signal>
FIG. 2 is an explanatory diagram showing an example of the phase relationship between the control signals Ctrl1 and Ctrl2 generated by the control circuit of FIG.
　図２（ａ）は、電流ＩＬの上昇の傾きが電流ＩＬの低下の傾きより大きい場合を示したものであり、図２（ｂ）は、電流ＩＬの上昇の傾きが電流ＩＬの低下の傾きより小さい場合を示したものである。 FIG. 2A shows a case where the slope of increase of current IL is larger than the slope of decrease of current IL, and FIG. 2B shows the slope of rise of current IL as the slope of decrease of current IL. The smaller case is shown.
　図２においては、上方から下方にかけて、制御信号Ｃｔｒｌ１、制御信号Ｃｔｒｌ２、電流ＩＬ，Ｉｏ、および出力電圧Ｖｏ１のリップルにおける信号タイミングをそれぞれ示している。 FIG. 2 shows signal timings in the ripples of the control signal Ctrl1, the control signal Ctrl2, the currents IL and Io, and the output voltage Vo1 from the top to the bottom.
　平滑用出力容量１０の出力電流である電流Ｉｏが流れる期間中、電流ＩＬの変化の傾きが小さいほど、入出力の電荷量の差、すなわち図２のハッチングにて示す領域の面積が小さくなる。このため、電流ＩＬの上昇と低下の傾きによって、制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２との間の位相を合わせるタイミングが異なる。 During the period in which the current Io, which is the output current of the smoothing output capacitor 10, flows, the difference in input / output charge amount, that is, the area of the region shown by hatching in FIG. For this reason, the timing for adjusting the phase between the control signal Ctrl1 and the control signal Ctrl2 differs depending on the rise and fall slopes of the current IL.
　電流ＩＬの上昇と低下の傾きは、以下の式から求められる。 The slope of increase and decrease in current IL can be obtained from the following equation.
　電流ＩＬの上昇の傾き：（Ｂａｔｔ－Ｖｏ１）／Ｌ１
　電流ＩＬの低下の傾き：－Ｖｏ１／Ｌ１
　電流ＩＬの上昇の傾きが電流ＩＬの低下の傾きより大きい場合には、制御信号Ｃｔｒｌ１の立ち下がりエッジと制御信号Ｃｔｒｌ２の立ち上がりエッジと合わせば、図２（ａ）に示すように、入出力の電荷量の差（ハッチングにて示す領域の面積グレーの面積）が小さくなり、上述した図１２に比べて、出力電圧Ｖｏ１のリップルを小さくすることができる。 Increasing slope of current IL: (Batt−Vo1) / L1
Slope of decrease in current IL: -Vo1 / L1
When the rising slope of the current IL is larger than the falling slope of the current IL, if the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 are combined, as shown in FIG. The difference in the amount of charge (the area of the gray area indicated by hatching) is reduced, and the ripple of the output voltage Vo1 can be reduced as compared with FIG.
　また、電流ＩＬの上昇の傾きが電流ＩＬの低下の傾きより小さい場合には、制御信号Ｃｔｒｌ１の立ち下がりエッジと制御信号Ｃｔｒｌ２の立ち下がりエッジとを合わせば、図２（ｂ）に示すように、入出力の電荷量の差（ハッチングにて示す領域の面積）が小さくなり、同様に出力電圧Ｖｏ１のリップルを小さくすることができる。 Further, when the rising slope of the current IL is smaller than the falling slope of the current IL, the falling edge of the control signal Ctrl1 and the falling edge of the control signal Ctrl2 are combined as shown in FIG. Thus, the difference in charge amount between input and output (area of the area indicated by hatching) is reduced, and the ripple of the output voltage Vo1 can be reduced similarly.
　〈電源装置の動作例〉
　制御部５が図４に示した波形を実現する際の電源装置３２の動作について、図３および図４を用いて説明する。 <Example of power supply operation>
The operation of the power supply device 32 when the control unit 5 realizes the waveform shown in FIG. 4 will be described with reference to FIGS.
　図３は、図１の電源装置３２が有する制御部５における各信号の一例を示すタイミングチャートである。図４は、図１の電源装置３２が有する制御部５における各信号の他の例を示すタイミングチャートである。 FIG. 3 is a timing chart showing an example of each signal in the control unit 5 included in the power supply device 32 of FIG. FIG. 4 is a timing chart showing another example of each signal in the control unit 5 included in the power supply device 32 of FIG.
　図３は、図２（ｂ）に示した制御信号Ｃｔｒｌ１の立ち下がりエッジと制御信号Ｃｔｒｌ２の立ち下がりエッジとを合わせる際の信号タイミングの例を示したものである。図４は、図２（ａ）に示した制御信号Ｃｔｒｌ１の立ち下がりエッジと制御信号Ｃｔｒｌ２の立ち上がりエッジとを合わせる際の信号タイミングの例を示したものである。 FIG. 3 shows an example of signal timing when the falling edge of the control signal Ctrl1 and the falling edge of the control signal Ctrl2 shown in FIG. FIG. 4 shows an example of signal timing when the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 shown in FIG.
　また、図３および図４においては、上方から下方にかけて、クロックＣＬＯＣＫ１、クロックＣＬＯＣＫ２＿１、クロックＣＬＯＣＫ２＿２、制御信号Ｃｔｒｌ１、制御信号Ｃｔｒｌ２、パルス信号Ｌ＿ｏｕｔ、パルス信号Ｈ＿ｏｕｔ、信号Ｓｌｏｐｅ１、および入力電圧Ｂａｔｔにおける信号タイミングをそれぞれ示している。 3 and 4, the signal timing in the clock CLOCK1, the clock CLOCK2_1, the clock CLOCK2_2, the control signal Ctrl1, the control signal Ctrl2, the pulse signal L_out, the pulse signal H_out, the signal Slope1, and the input voltage Batt from above to below. Respectively.
　まず、図３を用いて制御信号Ｃｔｒｌ１の立ち下がりエッジと制御信号Ｃｔｒｌ２の立ち下がりエッジとを合わせる際の動作について説明する。 First, the operation when the falling edge of the control signal Ctrl1 and the falling edge of the control signal Ctrl2 are matched will be described with reference to FIG.
　１周期目（安定期間）
　分周器２４は、クロック生成回路２６からの基準クロックから周波数が整数倍であるクロックＣＬＯＣＫ１およびクロックＣＬＯＣＫ２＿１をそれぞれ生成する。ここで、制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２との周波数が同じである時（Ｔｓ１＝Ｔｓ２）を一例として説明する。 1st cycle (stable period)
The frequency divider 24 generates a clock CLOCK1 and a clock CLOCK2_1 whose frequencies are integer multiples from the reference clock from the clock generation circuit 26, respectively. Here, a case where the frequencies of the control signal Ctrl1 and the control signal Ctrl2 are the same (Ts1 = Ts2) will be described as an example.
　制御回路１２は、出力電圧Ｖｏ１からの帰還電圧とクロックＣＬＯＣＫ１に基づいて、制御信号Ｃｔｒｌ１を生成する。単位遅延生成器２７の遅延設定時間は、ｔｄとなる。単位遅延生成器２７は、クロックＣＬＯＣＫ２＿１をｔｄ期間分遅延させて、クロックＣＬＯＣＫ２＿２として生成する。 The control circuit 12 generates the control signal Ctrl1 based on the feedback voltage from the output voltage Vo1 and the clock CLOCK1. The delay setting time of the unit delay generator 27 is td. The unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period td.
　制御回路２０は、出力電圧Ｖｏ２からの帰還電圧とクロックＣＬＯＣＫ２＿２に基づいて、制御信号Ｃｔｒｌ２を生成する。エッジ検出器２８が制御信号Ｃｔｒｌ１の立ち下がりエッジのタイミングにて制御信号Ｃｔｒｌ２がハイであることを検出し、パルス信号Ｈ＿ｏｕｔを出力する。 The control circuit 20 generates the control signal Ctrl2 based on the feedback voltage from the output voltage Vo2 and the clock CLOCK2_2. The edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out.
　この時、入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より大きいので、インダクタ９に流れる電流ＩＬの上昇の傾きは、低下の傾きより大きく、信号Ｓｌｏｐｅ１はローである。これによって、単位遅延生成器２７に設定された遅延分はｔｄから１単位を増加して、遅延時間はｔｄ＋ｘとなる。 At this time, since the difference between the input voltage Batt and the output voltage Vo1 is larger than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is larger than the falling slope, and the signal Slope1 is low. As a result, the delay set in the unit delay generator 27 is increased by one unit from td, and the delay time becomes td + x.
　２～５周期目（追従期間）
　２周期目：入力電圧Ｂａｔｔの変化によって、制御回路１２から生成した制御信号Ｃｔｒｌ１のｄｕｔｙ（デューティ）比が増加する。単位遅延生成器２７は、クロックＣＬＯＣＫ２＿１をｔｄ＋ｘ期間分遅延させたクロックＣＬＯＣＫ２＿２を生成する。エッジ検出器２８が制御信号Ｃｔｒｌ１の立ち下りエッジのタイミングにて制御信号Ｃｔｒｌ２がローであることを検出し、パルス信号Ｌ＿ｏｕｔを出力する。 2nd to 5th period (follow-up period)
Second period: Due to the change in the input voltage Batt, the duty ratio of the control signal Ctrl1 generated from the control circuit 12 increases. The unit delay generator 27 generates a clock CLOCK2_2 obtained by delaying the clock CLOCK2_1 by a period of td + x. The edge detector 28 detects that the control signal Ctrl2 is low at the falling edge timing of the control signal Ctrl1, and outputs a pulse signal L_out.
　この時、入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より小さいので、インダクタ９に流れる電流ＩＬの上昇の傾きは、低下の傾きより小さく、信号Ｓｌｏｐｅ１がハイになる。 At this time, since the difference between the input voltage Batt and the output voltage Vo1 is smaller than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is smaller than the falling slope, and the signal Slope1 becomes high.
　これによって、単位遅延生成器２７に設定された遅延分は、ｔｄ＋ｘから１単位を増加し、ｔｄ＋２ｘとなる。 Thus, the delay amount set in the unit delay generator 27 is increased by one unit from td + x and becomes td + 2x.
　３周期目：単位遅延生成器２７は、クロックＣＬＯＣＫ２＿１をｔｄ＋２ｘ期間分遅延させて、クロックＣＬＯＣＫ２＿２として生成する。エッジ検出器２８が制御信号Ｃｔｒｌ１の立ち下がりエッジのタイミングで制御信号Ｃｔｒｌ２がローであることを検出し、パルス信号Ｌ＿ｏｕｔを出力する。 Third period: The unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 2x and generates the clock CLOCK2_2. The edge detector 28 detects that the control signal Ctrl2 is low at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal L_out.
　この時、入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より小さいので、インダクタ９に流れる電流ＩＬの上昇の傾きは、低下の傾きより小さく、信号Ｓｌｏｐｅ１は引き続きハイである。これによって、単位遅延生成器２７に設定された遅延分は、ｔｄ＋２ｘから１単位を増加し、ｔｄ＋３ｘとなる。 At this time, since the difference between the input voltage Batt and the output voltage Vo1 is smaller than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is smaller than the falling slope, and the signal Slope1 continues to be high. As a result, the delay set in the unit delay generator 27 is increased by one unit from td + 2x to become td + 3x.
　４周期目：３周期目の周期と同様の動作を行い、単位遅延生成器２７に設定された遅延分は、ｔｄ＋４ｘとなる。 Fourth cycle: The same operation as the third cycle is performed, and the delay set in the unit delay generator 27 is td + 4x.
　５周期目：単位遅延生成器２７は、クロックＣＬＯＣＫ２＿１をｔｄ＋４ｘ期間分遅延させて、クロックＣＬＯＣＫ２＿２として生成する。エッジ検出器２８が制御信号Ｃｔｒｌ１の立ち下がりエッジのタイミングにて制御信号Ｃｔｒｌ２がハイであることを検出し、パルス信号Ｈ＿ｏｕｔを出力する。 5th cycle: The unit delay generator 27 delays the clock CLOCK2_1 by the period of td + 4x and generates the clock CLOCK2_2. The edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out.
　この時、入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差は、出力電圧Ｖｏ１より小さいので、インダクタ９に流れる電流ＩＬの上昇の傾きは低下の傾きより小さく、信号Ｓｌｏｐｅ１は、引き続きハイである。 At this time, since the difference between the input voltage Batt and the output voltage Vo1 is smaller than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is smaller than the falling slope, and the signal Slope1 continues to be high.
　これによって、単位遅延生成器２７に設定された遅延分は、ｔｄ＋４ｘから１単位を減少して、ｔｄ＋３ｘとなる。 Thus, the delay set in the unit delay generator 27 is decreased by 1 unit from td + 4x to become td + 3x.
　６周期目以後（安定期間）
　以上により、パルス信号Ｈ＿ｏｕｔ，　Ｌ＿ｏｕｔによって、単位遅延生成器２７に設定された遅延分は、周期毎にｔｄ＋３ｘとｔｄ＋４ｘとが繰り返して設定される。 After the 6th cycle (stable period)
As described above, the delay amount set in the unit delay generator 27 by the pulse signals H_out and L_out is set to repeat td + 3x and td + 4x for each period.
　続いて、図４を用いて、制御信号Ｃｔｒｌ１の立ち下がりエッジと制御信号Ｃｔｒｌ２の立ち上がりエッジとを合わせる際の動作について説明する。 Subsequently, an operation when the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 are matched will be described with reference to FIG.
　１周期目（安定期間）
　分周器２４は、クロック生成回路２６からの基準クロックから周波数が整数倍であるクロックＣＬＯＣＫ１，ＣＬＯＣＫ２＿１をそれぞれ生成する。ここで、制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２との周波数が同じである時（Ｔｓ１＝Ｔｓ２）を一例として説明する。 1st cycle (stable period)
The frequency divider 24 generates clocks CLOCK1 and CLOCK2_1 whose frequencies are integer multiples from the reference clock from the clock generation circuit 26, respectively. Here, a case where the frequencies of the control signal Ctrl1 and the control signal Ctrl2 are the same (Ts1 = Ts2) will be described as an example.
　制御回路１２は、出力電圧Ｖｏ１からの帰還電圧とクロックＣＬＯＣＫ１とに基づいて、制御信号Ｃｔｒｌ１を生成する。単位遅延生成器２７の遅延設定時間は、ｔｄ＋４ｘとなる。 The control circuit 12 generates the control signal Ctrl1 based on the feedback voltage from the output voltage Vo1 and the clock CLOCK1. The delay setting time of the unit delay generator 27 is td + 4x.
　単位遅延生成器２７は、クロックＣＬＯＣＫ２＿１をｔｄ＋４ｘ期間分遅延させて、クロックＣＬＯＣＫ２＿２として出力する。制御回路２０は、出力電圧Ｖｏ２からの帰還電圧とクロックＣＬＯＣＫ２＿２とに基づいて、制御信号Ｃｔｒｌ２を生成する。 The unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 4x and outputs it as the clock CLOCK2_2. The control circuit 20 generates the control signal Ctrl2 based on the feedback voltage from the output voltage Vo2 and the clock CLOCK2_2.
　エッジ検出器２８は、制御信号Ｃｔｒｌ１の立ち下がりエッジのタイミングにて制御信号Ｃｔｒｌ２がハイであることを検出し、パルス信号Ｈ＿ｏｕｔを出力する。この時、入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より小さいので、インダクタ９に流れる電流ＩＬの上昇の傾きは、低下の傾きより小さく、信号Ｓｌｏｐｅ１はハイである。 The edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out. At this time, since the difference between the input voltage Batt and the output voltage Vo1 is smaller than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is smaller than the falling slope, and the signal Slope1 is high.
　これによって、単位遅延生成器２７に設定された遅延分は、ｔｄ＋４ｘから１単位を減少して、ｔｄ＋３ｘとなる。 Thus, the delay set in the unit delay generator 27 is decreased by 1 unit from td + 4x to become td + 3x.
　２～５周期目（追従期間）
　２周期目：入力電圧Ｂａｔｔの変化によって、制御回路１２から生成した制御信号Ｃｔｒｌ１のｄｕｔｙ比が減少する。単位遅延生成器２７は、クロックＣＬＯＣＫ２＿１をｔｄ＋３ｘ期間分遅延させて、クロックＣＬＯＣＫ２＿２として出力する。 2nd to 5th period (follow-up period)
Second period: Due to the change in the input voltage Batt, the duty ratio of the control signal Ctrl1 generated from the control circuit 12 decreases. The unit delay generator 27 delays the clock CLOCK2_1 by the period of td + 3x and outputs it as the clock CLOCK2_2.
　エッジ検出器２８は、制御信号Ｃｔｒｌ１の立ち下がりエッジのタイミングにて制御信号Ｃｔｒｌ２がローであることを検出し、パルス信号Ｌ＿ｏｕｔを出力する。この時、入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より大きいので、インダクタ９に流れる電流ＩＬの上昇の傾きは、低下の傾きより大きく、信号Ｓｌｏｐｅ１がローになる。 The edge detector 28 detects that the control signal Ctrl2 is low at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal L_out. At this time, since the difference between the input voltage Batt and the output voltage Vo1 is larger than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is larger than the falling slope, and the signal Slope1 becomes low.
　これによって、単位遅延生成器２７に設定された遅延分は、ｔｄ＋３ｘから１単位を減少して、ｔｄ＋２ｘとなる。 Thus, the delay set in the unit delay generator 27 is decreased by 1 unit from td + 3x to become td + 2x.
　３周期目：単位遅延生成器２７は、クロックＣＬＯＣＫ２＿１をｔｄ＋２ｘ期間分遅延させて、クロックＣＬＯＣＫ２＿２として出力する。 Third period: The unit delay generator 27 delays the clock CLOCK2_1 by a period of td + 2x and outputs it as the clock CLOCK2_2.
　エッジ検出器２８は、制御信号Ｃｔｒｌ１の立ち下がりエッジのタイミングにて制御信号Ｃｔｒｌ２がローであることを検出して、パルス信号Ｌ＿ｏｕｔを出力する。この時、入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より大きいので、インダクタ９に流れる電流ＩＬの上昇の傾きは、低下の傾きより大きく、信号Ｓｌｏｐｅ１は引き続きローである。 The edge detector 28 detects that the control signal Ctrl2 is low at the timing of the falling edge of the control signal Ctrl1, and outputs the pulse signal L_out. At this time, since the difference between the input voltage Batt and the output voltage Vo1 is larger than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is larger than the falling slope, and the signal Slope1 is continuously low.
　これによって、単位遅延生成器２７に設定された遅延分は、ｔｄ＋２ｘから１単位を減少して、ｔｄ＋ｘとなる。 Thus, the delay amount set in the unit delay generator 27 is decreased by 1 unit from td + 2x to become td + x.
　４周期目：上述した３周期目の周期と同様の動作を行い、単位遅延生成器２７に設定された遅延分がｔｄとなる。 Fourth cycle: The same operation as the third cycle described above is performed, and the delay set in the unit delay generator 27 is td.
　５周期目：単位遅延生成器２７は、クロックＣＬＯＣＫ２＿１をｔｄ期間分遅延させて、クロックＣＬＯＣＫ２＿２として生成する。エッジ検出器２８は、制御信号Ｃｔｒｌ１の立ち下がりエッジのタイミングにて制御信号Ｃｔｒｌ２がハイであることを検出し、パルス信号Ｈ＿ｏｕｔを出力する。 5th cycle: The unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period td. The edge detector 28 detects that the control signal Ctrl2 is high at the timing of the falling edge of the control signal Ctrl1, and outputs a pulse signal H_out.
　この時、入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より大きいので、インダクタ９に流れる電流ＩＬの上昇の傾きは、低下の傾きより大きく、信号Ｓｌｏｐｅ１は引き続きローである。 At this time, since the difference between the input voltage Batt and the output voltage Vo1 is larger than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is larger than the falling slope, and the signal Slope1 is still low.
　これによって、単位遅延生成器２７に設定された遅延分は、ｔｄから１単位を増加して、ｔｄ＋ｘとなる。 Thus, the delay set in the unit delay generator 27 is increased by one unit from td to become td + x.
　６周期目以後（安定期間）
　パルス信号Ｈ＿ｏｕｔ，Ｌ＿ｏｕｔによって、単位遅延生成器２７に設定された遅延分は、周期毎にｔｄ＋ｘとｔｄの間を繰り返して設定される。 After the 6th cycle (stable period)
The delay set in the unit delay generator 27 by the pulse signals H_out and L_out is set repeatedly between td + x and td for each period.
　以上により、上記した動作によって、制御信号Ｃｔｒｌ１の立ち下がりエッジと制御信号Ｃｔｒｌ２の立ち上がりエッジまたは立ち下がりエッジをほぼ一致させることができる。 As described above, the falling edge of the control signal Ctrl1 and the rising edge or falling edge of the control signal Ctrl2 can be substantially matched by the above-described operation.
　これによって、制御信号Ｃｔｒｌ２の周波数を増加させることなくも、平滑用出力容量１０の入出力の電荷量の差を小さくすることができ、出力電圧Ｖｏ１のリップルを低減することができる。 This makes it possible to reduce the difference in charge amount between the input and output of the smoothing output capacitor 10 without increasing the frequency of the control signal Ctrl2, and to reduce the ripple of the output voltage Vo1.
　出力電圧Ｖｏ１を動作電源とする負荷４９は、上述したように例えばＡ／Ｄ変換器などのアナログ回路である。よって、出力電圧Ｖｏ１のリップルが低減することによって、Ａ／Ｄ変換器のアナログ／デジタル変換の精度を向上させることができる。 The load 49 using the output voltage Vo1 as an operation power supply is an analog circuit such as an A / D converter as described above. Therefore, the accuracy of analog / digital conversion of the A / D converter can be improved by reducing the ripple of the output voltage Vo1.
　また、スイッチング動作部２におけるスイッチング周波数を高めずに安定した出力電圧Ｖｏ２を生成することができるので、電源装置３２の損失を低減することができる。 Further, since the stable output voltage Vo2 can be generated without increasing the switching frequency in the switching operation unit 2, the loss of the power supply device 32 can be reduced.
　これにより、信頼性の高い高効率な電源装置３２を実現することができる。 Thereby, a highly reliable and highly efficient power supply device 32 can be realized.
　（実施の形態２）
　前記実施の形態１の技術では、図３などに示したように、制御信号Ｃｔｒｌ１のｄｕｔｙ比の変化に追従するために、クロックＣＬＯＣＫ２＿１とクロックＣＬＯＣＫ２＿２との遅延を相応しくなるまで調整するための時間がかかることになる。これによって、追従期間中、出力電圧Ｖｏ１のリップルが大きくなる。 (Embodiment 2)
In the technique of the first embodiment, as shown in FIG. 3 and the like, in order to follow the change in the duty ratio of the control signal Ctrl1, time for adjusting the delay between the clock CLOCK2_1 and the clock CLOCK2_2 until they become appropriate It will take. This increases the ripple of the output voltage Vo1 during the follow-up period.
　そこで、本実施の形態２では、追従期間中における出力電圧Ｖｏ１のリップルを低減する技術について説明する。 Therefore, in the second embodiment, a technique for reducing the ripple of the output voltage Vo1 during the follow-up period will be described.
　〈電源装置の構成例〉
　図５は、本実施の形態２による電源装置４１における構成の一例を示す説明図である。 <Configuration example of power supply device>
FIG. 5 is an explanatory diagram showing an example of the configuration of the power supply device 41 according to the second embodiment.
　なお、図５においても、上記した図１と同一の構成部分には同一符号を付している。また、図５において、電源装置４１を構成するスイッチング動作部２、クロック生成回路２６、および分周器２４と、負荷４９，５０とについては、図１と同様であるので説明を省略する。 In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 5, the switching operation unit 2, the clock generation circuit 26, the frequency divider 24, and the loads 49 and 50 configuring the power supply device 41 are the same as those in FIG.
　電源装置４１は、図５に示すように、スイッチング動作部１、スイッチング動作部２、および制御部１９を有する。この電源装置４１は、出力電圧Ｖｏ１，Ｖｏ２からの帰還電圧を制御部１９に入力する。そして、制御部１９が生成した制御信号Ｃｔｒｌ１，Ｃｔｒｌ２をスイッチング動作部１，２に入力して、スイッチング動作によって所望の出力電圧Ｖｏ１、Ｖｏ２を生成して、負荷５０、負荷４９の動作電圧として供給する。 The power supply device 41 includes a switching operation unit 1, a switching operation unit 2, and a control unit 19, as shown in FIG. The power supply device 41 inputs the feedback voltage from the output voltages Vo 1 and Vo 2 to the control unit 19. Then, the control signals Ctrl1 and Ctrl2 generated by the control unit 19 are input to the switching operation units 1 and 2, and desired output voltages Vo1 and Vo2 are generated by the switching operation and supplied as the operation voltages of the load 50 and the load 49. To do.
　スイッチング動作部１は、スイッチング素子７、スイッチング素子８、インダクタ９、平滑用出力容量１０、ドライバ１１、および電流検出器５７を有する。スイッチング素子７、スイッチング素子８、インダクタ９、平滑用出力容量１０、およびドライバ１１については、図１と同様であるので説明を省略する。電流検出器５７は、インダクタ９に流れる電流ＩＬを電圧値に変化して出力する。 The switching operation unit 1 includes a switching element 7, a switching element 8, an inductor 9, a smoothing output capacitor 10, a driver 11, and a current detector 57. Since the switching element 7, the switching element 8, the inductor 9, the smoothing output capacitor 10, and the driver 11 are the same as those in FIG. The current detector 57 changes the current IL flowing through the inductor 9 into a voltage value and outputs it.
　制御部１９は、制御器３３、制御器３４、分周器２４、電流検出比較部６０、およびクロック生成回路２６を有する。 The control unit 19 includes a controller 33, a controller 34, a frequency divider 24, a current detection comparison unit 60, and a clock generation circuit 26.
　電流検出比較部６０は、電流検出用ＡＤＣ５８および電流傾き比較器５９を有する。この電流検出比較部６０は、インダクタ９に流れる電流ＩＬの上昇と低下の傾きの大きさの関係を示す信号Ｓｌｏｐｅ２を生成する。 The current detection comparison unit 60 includes a current detection ADC 58 and a current gradient comparator 59. The current detection / comparison unit 60 generates a signal Slope 2 indicating the relationship between the magnitude of the increase and decrease in the current IL flowing through the inductor 9.
　電流検出用ＡＤＣ５８は、電流検出器５７が電流ＩＬを変換した電圧値をデジタル電圧値に変換する。電流傾き比較器５９は、スイッチング素子７とスイッチング素子８がスイッチングする１周期中に、インダクタ９に流れる電流ＩＬの上昇と電流ＩＬの低下の傾きの大きさを示す信号Ｓｌｏｐｅ２を電流検出用ＡＤＣ５８から出力されるデジタル電圧値に基づいて生成する。 The current detection ADC 58 converts the voltage value obtained by converting the current IL by the current detector 57 into a digital voltage value. The current slope comparator 59 outputs a signal Slope2 indicating the magnitude of the slope of the rise of the current IL flowing through the inductor 9 and the fall of the current IL from the current detection ADC 58 during one cycle when the switching elements 7 and 8 are switched. Generated based on the output digital voltage value.
　インダクタ９に流れる電流ＩＬの上昇の傾きが電流ＩＬの低下の傾きより大きい場合には、信号Ｓｌｏｐｅ２がローになる。インダクタ９に流れる電流ＩＬの上昇の傾きが電流ＩＬの低下の傾きより小さい場合には、信号Ｓｌｏｐｅ２がハイになる。 When the rising slope of the current IL flowing through the inductor 9 is larger than the falling slope of the current IL, the signal Slope2 becomes low. When the slope of increase of the current IL flowing through the inductor 9 is smaller than the slope of decrease of the current IL, the signal Slope2 becomes high.
　また、電流傾き比較器５９は、１周期中の電流ＩＬの上昇と低下の傾きを比較する回路であるため、信号Ｓｌｏｐｅ２の結果は、１周期前の電流ＩＬの上昇と低下の傾きの比較結果である。 Since the current slope comparator 59 is a circuit that compares the rise and fall slopes of the current IL during one cycle, the result of the signal Slope2 is the comparison result between the rise and fall slopes of the current IL one cycle before. It is.
　制御器３３は、ＡＤ変換器３７、ＰＩＤ制御器３６、およびＤＰＷＭ生成器３５を有する。この制御器３３は、出力電圧Ｖｏ１からの帰還電圧をＡＤ変換器３７によってデジタル帰還圧値に変換し、ＰＩＤ制御器３６にてデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎを生成する。 The controller 33 includes an AD converter 37, a PID controller 36, and a DPWM generator 35. The controller 33 converts the feedback voltage from the output voltage Vo1 into a digital feedback pressure value by the AD converter 37, and the PID controller 36 generates a digital control value Digital_in.
　そして、分周器２４が生成するクロックＣＬＯＣＫ１とＰＩＤ制御器３６が生成するデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎに基づいて、ＤＰＷＭ生成器３５が制御信号Ｃｔｒｌ１を生成するものであり、例えばマイコンなどのデジタル制御装置である。また、このデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎは、制御信号Ｃｔｒｌ１のハイの時間を表す。 The DPWM generator 35 generates the control signal Ctrl1 based on the clock CLOCK1 generated by the frequency divider 24 and the digital control value Digital_in generated by the PID controller 36. For example, in a digital control device such as a microcomputer. is there. The digital control value Digital_in represents the high time of the control signal Ctrl1.
　ＡＤ変換器３７は、出力電圧Ｖｏ１からの帰還電圧をデジタル帰還電圧値に変換するアナログデジタル変換回路である。 The AD converter 37 is an analog-digital conversion circuit that converts a feedback voltage from the output voltage Vo1 into a digital feedback voltage value.
　ＰＩＤ制御器３６は、ＡＤ変換器３７が変換したデジタル帰還電圧値を用いて、比例－積分－微分（Proportional-Integral-Differential）演算を行い、スイッチング動作部１が所望の出力電圧を生成できるようにデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎを生成する。 The PID controller 36 performs a proportional-integral-differential (Proportional-Integral-Differential) operation using the digital feedback voltage value converted by the AD converter 37 so that the switching operation unit 1 can generate a desired output voltage. A digital control value Digital_in is generated.
　ＤＰＷＭ生成器３５は、ＰＩＤ制御器３６からのデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎを用いて、分周器２４から出力されるクロックＣＬＯＣＫ１によって制御信号Ｃｔｒｌ１を生成する、いわゆるデジタルＰＷＭ（Pulse Width Modulation）回路である。 The DPWM generator 35 is a so-called digital PWM (Pulse Width Modulation) circuit that uses the digital control value Digital_in from the PID controller 36 to generate the control signal Ctrl1 by the clock CLOCK1 output from the frequency divider 24.
　制御器３４は、ＡＤ変換器４０、ＰＩＤ制御器３９、ＤＰＷＭ生成器３８、および可変遅延器４２を有する。この制御器３４は、マイコンのようなデジタル制御器である。 The controller 34 includes an AD converter 40, a PID controller 39, a DPWM generator 38, and a variable delay device 42. The controller 34 is a digital controller such as a microcomputer.
　具体的には、出力電圧Ｖｏ２からの帰還電圧をＡＤ変換器４０にてデジタル帰還圧値に変換する。そして、ＰＩＤ制御器３９にてデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ＿２を生成する。 Specifically, the feedback voltage from the output voltage Vo2 is converted into a digital feedback pressure value by the AD converter 40. Then, the digital control value Digital_in_2 is generated by the PID controller 39.
　続いて、可変遅延器４２において、デジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ＿２、ＰＩＤ制御器３６が生成するデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ、および分周器２４から出力されるクロックＣＬＯＣＫ２＿１によってクロックＣＬＯＣＫ２＿２を生成する。 Subsequently, in the variable delay unit 42, the clock CLOCK2_2 is generated by the digital control value Digital_in_2, the digital control value Digital_in generated by the PID controller 36, and the clock CLOCK2_1 output from the frequency divider 24.
　そして、ＰＩＤ制御器３９からのデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ＿２とクロックＣＬＯＣＫ２＿２とによってＤＰＷＭ生成器３８から制御信号Ｃｔｒｌ２を生成するものである。また、このデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ＿２は、制御信号Ｃｔｒｌ２のハイの時間を表す。 The control signal Ctrl2 is generated from the DPWM generator 38 based on the digital control value Digital_in_2 from the PID controller 39 and the clock CLOCK2_2. The digital control value Digital_in_2 represents the high time of the control signal Ctrl2.
　ＡＤ変換器４０は、出力電圧Ｖｏ２からの帰還電圧をデジタル帰還電圧値に変換するアナログデジタル変換回路である。ＰＩＤ制御器３９は、ＡＤ変換器４０からが変換したデジタル帰還電圧値を用いて、比例－積分－微分（Proportional-Integral-Differential）演算してスイッチング動作部２が所望の出力電圧を生成できるようにデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ＿２を生成する。 The AD converter 40 is an analog-digital conversion circuit that converts a feedback voltage from the output voltage Vo2 into a digital feedback voltage value. The PID controller 39 uses the digital feedback voltage value converted by the AD converter 40 to perform a proportional-integral-differential (Proportional-Integral-Differential) operation so that the switching operation unit 2 can generate a desired output voltage. The digital control value Digital_in_2 is generated.
　ＤＰＷＭ生成器３８は、ＰＩＤ制御器３９が生成したデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ＿２を用いてクロックＣＬＯＣＫ２＿２によって制御信号Ｃｔｒｌ２を生成するデジタルＰＷＭ（Pulse Width Modulation）回路である。 The DPWM generator 38 is a digital PWM (Pulse Width Modulation) circuit that generates the control signal Ctrl2 by the clock CLOCK2_2 using the digital control value Digital_in_2 generated by the PID controller 39.
　可変遅延器４２は、ＰＩＤ制御器３６が生成したデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ、およびＰＩＤ制御器３９が生成したデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ＿２と電流傾き比較器５９から出力される信号Ｓｌｏｐｅ２とによって遅延時間を設定し、分周器２４から出力されるクロックＣＬＯＣＫ２＿１を設定された遅延時間にて遅延させたクロックＣＬＯＣＫ２＿２を生成する。 The variable delay unit 42 sets the delay time by the digital control value Digital_in generated by the PID controller 36, the digital control value Digital_in_2 generated by the PID controller 39, and the signal Slope2 output from the current slope comparator 59, A clock CLOCK2_2 obtained by delaying the clock CLOCK2_1 output from the frequency divider 24 by a set delay time is generated.
　電流傾き比較器５９から出力される信号Ｓｌｏｐｅ２がハイの場合、遅延時間は、制御信号Ｃｔｒｌ１のハイの時間と制御信号Ｃｔｒｌ２のハイの時間の差分となる。電流傾き比較器５９から出力される信号Ｓｌｏｐｅ２がローの場合、遅延時間は、制御信号Ｃｔｒｌ１のハイの時間となる。 When the signal Slope2 output from the current slope comparator 59 is high, the delay time is the difference between the high time of the control signal Ctrl1 and the high time of the control signal Ctrl2. When the signal Slope2 output from the current slope comparator 59 is low, the delay time is the high time of the control signal Ctrl1.
　〈電源装置の動作例〉
　図６は、図５の電源装置４１における各信号の一例を示すタイミングチャートである。図７は、図５の電源装置４１における各信号の他の例を示すタイミングチャートである。 <Example of power supply operation>
FIG. 6 is a timing chart showing an example of each signal in the power supply device 41 of FIG. FIG. 7 is a timing chart showing another example of each signal in the power supply device 41 of FIG.
　図６は、図５に示す電源装置４１により、図２（ｂ）に示した制御信号Ｃｔｒｌ１の立ち下がりエッジと制御信号Ｃｔｒｌ２の立ち下がりエッジとを合わせる際の信号タイミングの例を示したものである。図７は、図５に示す電源装置４１により、図２（ａ）に示した制御信号Ｃｔｒｌ１の立ち下がりエッジと制御信号Ｃｔｒｌ２の立ち上がりエッジとを合わせる際の信号タイミングの例を示したものである。 FIG. 6 shows an example of signal timing when the power supply device 41 shown in FIG. 5 matches the falling edge of the control signal Ctrl1 and the falling edge of the control signal Ctrl2 shown in FIG. is there. FIG. 7 shows an example of signal timing when the power supply device 41 shown in FIG. 5 matches the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 shown in FIG. .
　また、図６および図７においては、上方から下方にかけて、クロックＣＬＯＣＫ１、クロックＣＬＯＣＫ２＿１、クロックＣＬＯＣＫ２＿２、デジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ、デジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ＿２、制御信号Ｃｔｒｌ１、制御信号Ｃｔｒｌ２、信号Ｓｌｏｐｅ２、および入力電圧Ｂａｔｔにおける信号タイミングをそれぞれ示している。 6 and 7, from the top to the bottom, the clock CLOCK1, the clock CLOCK2_1, the clock CLOCK2_2, the digital control value Digital_in, the digital control value Digital_in_2, the control signal Ctrl1, the control signal Ctrl2, the signal Slope2, and the input voltage Batt Each signal timing is shown.
　始めに、図６を用いて図２（ｂ）に示した制御信号Ｃｔｒｌ１の立ち下がりエッジと制御信号Ｃｔｒｌ２の立ち下がりエッジとを合わせる際の電源装置４１の動作について説明する。 First, the operation of the power supply device 41 when the falling edge of the control signal Ctrl1 and the falling edge of the control signal Ctrl2 shown in FIG.
　１周期目（安定期間）
　まず、分周器２４は、クロック生成回路２６から出力される基準クロックから、周波数が整数倍であるクロックＣＬＯＣＫ１，ＣＬＯＣＫ２＿１をそれぞれ生成する。ここで、制御信号Ｃｔｒｌ１および制御信号Ｃｔｒｌ２の周波数が略同じである時（Ｔｓ１＝Ｔｓ２）を一例として説明する。 1st cycle (stable period)
First, the frequency divider 24 generates clocks CLOCK1 and CLOCK2_1 whose frequencies are integer multiples from the reference clock output from the clock generation circuit 26, respectively. Here, a case where the frequencies of the control signal Ctrl1 and the control signal Ctrl2 are substantially the same (Ts1 = Ts2) will be described as an example.
　制御器３３は、出力電圧Ｖｏ１からの帰還電圧およびクロックＣＬＯＣＫ１から制御信号Ｃｔｒｌ１のハイの時間ｔ１を表すデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎを生成し、パルス幅が時間ｔ１の制御信号Ｃｔｒｌ１を生成する。 The controller 33 generates a digital control value Digital_in representing a high time t1 of the control signal Ctrl1 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t1.
　１周期前の入力電圧Ｂａｔｔと出力電圧Ｖｏ１と差が出力電圧Ｖｏ１より大きいので、インダクタ９に流れる電流ＩＬの上昇の傾きは、電流ＩＬの低下の傾きより大きく、信号Ｓｌｏｐｅ２がローになる。 Since the difference between the input voltage Batt and the output voltage Vo1 one cycle before is larger than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is larger than the falling slope of the current IL, and the signal Slope2 becomes low.
　このため、可変遅延器４２は、時間ｔ１を表すデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎによって遅延設定時間をｔ１に設定する。可変遅延器４２は、クロックＣＬＯＣＫ２＿１をｔ１期間分遅延させて、クロックＣＬＯＣＫ２＿２として生成する。 Therefore, the variable delay device 42 sets the delay setting time to t1 by the digital control value Digital_in representing the time t1. The variable delay device 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period t1.
　制御信号Ｃｔｒｌ２は、クロックＣＬＯＣＫ２＿２を基準クロックとして生成されるため、制御信号Ｃｔｒｌ１の立ち下がりエッジは、制御信号Ｃｔｒｌ２の立ち上がりエッジと一致する。 Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the rising edge of the control signal Ctrl2.
　２周期目（追従期間）
　入力電圧Ｂａｔｔの変化によって、制御器３３が生成した制御信号Ｃｔｒｌ１のｄｕｔｙ比がｔ１／Ｔｓ１からｔ２／Ｔｓ２に増加する。制御器３３は、出力電圧Ｖｏ１からの帰還電圧とクロックＣＬＯＣＫ１から時間ｔ２を表すデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎを生成し、パルス幅が時間ｔ２の制御信号Ｃｔｒｌ１を生成する。 Second period (follow-up period)
Due to the change in the input voltage Batt, the duty ratio of the control signal Ctrl1 generated by the controller 33 increases from t1 / Ts1 to t2 / Ts2. The controller 33 generates a digital control value Digital_in representing the time t2 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t2.
　２周期目の入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より大きいので、信号Ｓｌｏｐｅ２が引き続きローである。可変遅延器４２は、時間ｔ２を表すデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎによって遅延設定時間をｔ２に設定する。 Since the difference between the input voltage Batt and the output voltage Vo1 in the second cycle is larger than the output voltage Vo1, the signal Slope2 is still low. The variable delay device 42 sets the delay setting time to t2 by the digital control value Digital_in representing the time t2.
　可変遅延器４２は、クロックＣＬＯＣＫ２＿１をｔ２期間分遅延させて、クロックＣＬＯＣＫ２＿２として生成する。制御信号Ｃｔｒｌ２がクロックＣＬＯＣＫ２＿２を基準クロックとして生成されるため、制御信号Ｃｔｒｌ１の立ち下がりエッジは、制御信号Ｃｔｒｌ２の立ち上がりエッジと一致する。 The variable delay device 42 delays the clock CLOCK2_1 by the period t2, and generates the clock CLOCK2_2 as the clock CLOCK2_2. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the rising edge of the control signal Ctrl2.
　３周期目以後（安定期間）
　３周期目の入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より小さいので、信号Ｓｌｏｐｅ２がハイになる。可変遅延器４２は、時間ｔ２を表すデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎおよび時間ｔ３を表すデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ＿２によって遅延設定時間をｔ２－ｔ３に設定する。 After the 3rd cycle (stable period)
Since the difference between the input voltage Batt and the output voltage Vo1 in the third period is smaller than the output voltage Vo1, the signal Slope2 becomes high. The variable delay device 42 sets the delay setting time to t2-t3 by the digital control value Digital_in representing the time t2 and the digital control value Digital_in_2 representing the time t3.
　可変遅延器４２は、クロックＣＬＯＣＫ２＿１をｔ２－ｔ３期間分遅延させて、クロックＣＬＯＣＫ２＿２として生成する。制御信号Ｃｔｒｌ２がクロックＣＬＯＣＫ２＿２を基準クロックとして生成されるため、制御信号Ｃｔｒｌ１の立ち下がりエッジは、制御信号Ｃｔｒｌ２の立ち下がりエッジと一致する。 The variable delay device 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period t2-t3. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the falling edge of the control signal Ctrl2.
　続いて、図７を用いて図２（ａ）に示した制御信号Ｃｔｒｌ１の立ち下がりエッジと制御信号Ｃｔｒｌ２の立ち上がりエッジとを合わせる際の電源装置４１の動作について説明する。 Subsequently, the operation of the power supply device 41 when the falling edge of the control signal Ctrl1 and the rising edge of the control signal Ctrl2 shown in FIG.
　１周期目（安定期間）
　まず、分周器２４は、クロック生成回路２６から出力される基準クロックから周波数が整数倍であるクロックＣＬＯＣＫ１，ＣＬＯＣＫ２＿１を生成する。ここで、制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２との周波数が略同じである時（Ｔｓ１＝Ｔｓ２）を一例として説明する。 1st cycle (stable period)
First, the frequency divider 24 generates clocks CLOCK1 and CLOCK2_1 whose frequencies are integer multiples from the reference clock output from the clock generation circuit 26. Here, a case where the frequencies of the control signal Ctrl1 and the control signal Ctrl2 are substantially the same (Ts1 = Ts2) will be described as an example.
　制御器３３は、出力電圧Ｖｏ１からの帰還電圧とクロックＣＬＯＣＫ１から制御信号Ｃｔｒｌ１のハイの時間ｔ２を表すデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎを生成し、パルス幅が時間ｔ２の制御信号Ｃｔｒｌ１を生成する。 The controller 33 generates a digital control value Digital_in representing a high time t2 of the control signal Ctrl1 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t2.
　１周期前の入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より小さいので、インダクタ９に流れる電流ＩＬの上昇の傾きは電流ＩＬの低下の傾きより小さく、信号Ｓｌｏｐｅ２がハイになる。 Since the difference between the input voltage Batt one cycle before and the output voltage Vo1 is smaller than the output voltage Vo1, the rising slope of the current IL flowing through the inductor 9 is smaller than the falling slope of the current IL, and the signal Slope2 becomes high.
　可変遅延器４２は、時間ｔ２を表すデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎと時間ｔ３を表すデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ＿２とによって遅延設定時間をｔ２－ｔ３に設定する。 The variable delay device 42 sets the delay setting time to t2-t3 by the digital control value Digital_in representing the time t2 and the digital control value Digital_in_2 representing the time t3.
　可変遅延器４２は、クロックＣＬＯＣＫ２＿１をｔ２－ｔ３期間分遅延させたクロックＣＬＯＣＫ２＿２を生成する。制御信号Ｃｔｒｌ２は、クロックＣＬＯＣＫ２＿２を基準クロックとして生成されるため、制御信号Ｃｔｒｌ１の立ち下がりエッジは、制御信号Ｃｔｒｌ２の立ち下がりエッジと一致する。 The variable delay device 42 generates a clock CLOCK2_2 obtained by delaying the clock CLOCK2_1 by a period of t2-t3. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the falling edge of the control signal Ctrl2.
　２周期目（追従期間）
　入力電圧Ｂａｔｔの変化によって、制御器３３が生成した制御信号Ｃｔｒｌ１のｄｕｔｙ比がｔ２／Ｔｓ１からｔ１／Ｔｓ２に減少する。制御器３３は、出力電圧Ｖｏ１からの帰還電圧とクロックＣＬＯＣＫ１から時間ｔ２を表すデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎを生成し、パルス幅が時間ｔ１の制御信号Ｃｔｒｌ１を生成する。 Second period (follow-up period)
Due to the change in the input voltage Batt, the duty ratio of the control signal Ctrl1 generated by the controller 33 decreases from t2 / Ts1 to t1 / Ts2. The controller 33 generates a digital control value Digital_in representing time t2 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1, and generates a control signal Ctrl1 having a pulse width of time t1.
　２周期目の入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より大きいので、信号Ｓｌｏｐｅ２はローである。可変遅延器４２は、時間ｔ２を表すデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎと時間ｔ３を表すデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎ＿２とによって遅延設定時間をｔ１－ｔ３に設定する。 Since the difference between the input voltage Batt and the output voltage Vo1 in the second period is larger than the output voltage Vo1, the signal Slope2 is low. The variable delay device 42 sets the delay setting time to t1−t3 by the digital control value Digital_in representing the time t2 and the digital control value Digital_in_2 representing the time t3.
　可変遅延器４２は、クロックＣＬＯＣＫ２＿１をｔ２－ｔ３期間分遅延させて、クロックＣＬＯＣＫ２＿２として生成する。制御信号Ｃｔｒｌ２は、クロックＣＬＯＣＫ２＿２を基準クロックとして生成されるため、制御信号Ｃｔｒｌ１の立ち下がりエッジは、制御信号Ｃｔｒｌ２の立ち下がりエッジと一致する。 The variable delay device 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period t2-t3. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the falling edge of the control signal Ctrl2.
　３周期目以後（安定期間）
　３周期目の入力電圧Ｂａｔｔと出力電圧Ｖｏ１との差が出力電圧Ｖｏ１より大きいので、信号Ｓｌｏｐｅ２はローである。可変遅延器４２は、時間ｔ１を表すデジタル制御値Ｄｉｇｉｔａｌ＿ｉｎによって遅延設定時間をｔ１に設定する。 After the 3rd cycle (stable period)
Since the difference between the input voltage Batt and the output voltage Vo1 in the third period is larger than the output voltage Vo1, the signal Slope2 is low. The variable delay device 42 sets the delay setting time to t1 by the digital control value Digital_in representing the time t1.
　可変遅延器４２は、クロックＣＬＯＣＫ２＿１をｔ１期間分遅延させて、クロックＣＬＯＣＫ２＿２として生成する。制御信号Ｃｔｒｌ２は、クロックＣＬＯＣＫ２＿２を基準クロックとして生成されるため、制御信号Ｃｔｒｌ１の立ち下がりエッジは、制御信号Ｃｔｒｌ２の立ち上がりエッジと一致する。 The variable delay device 42 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period t1. Since the control signal Ctrl2 is generated using the clock CLOCK2_2 as a reference clock, the falling edge of the control signal Ctrl1 coincides with the rising edge of the control signal Ctrl2.
　上記した動作によって、制御信号Ｃｔｒｌ１の立ち下がりエッジと制御信号Ｃｔｒｌ２の立ち上がりエッジまたは立ち下がりエッジを常に一致させることを実現することができる。 By the operation described above, it is possible to always match the falling edge of the control signal Ctrl1 with the rising edge or falling edge of the control signal Ctrl2.
　これによって、制御信号Ｃｔｒｌ２の周波数を増加しなくても、平滑用出力容量１０の入出力の電荷量の差（図２のハッチングにて示す領域の面積）を小さくすることができる。その結果、出力電圧Ｖｏ１のリップルを低減することができ、電源装置４１の損失を減らすことができる。 Thereby, even if the frequency of the control signal Ctrl2 is not increased, the difference in charge amount between the input and output of the smoothing output capacitor 10 (area of the area shown by hatching in FIG. 2) can be reduced. As a result, the ripple of the output voltage Vo1 can be reduced, and the loss of the power supply device 41 can be reduced.
　さらに、図５に示す電源装置４１では、制御信号Ｃｔｒｌ１のｄｕｔｙ比が変化する際、制御信号Ｃｔｒｌ２の遅延時間の追従時間を短縮することができるため、追従期間中の出力電圧Ｖｏ１のリップルを抑制することができる。 Furthermore, in the power supply device 41 shown in FIG. 5, when the duty ratio of the control signal Ctrl1 changes, the tracking time of the delay time of the control signal Ctrl2 can be shortened, so that the ripple of the output voltage Vo1 during the tracking period is suppressed. can do.
　これにより、より高精度な出力電圧Ｖｏ１を生成することができ、電源装置４１の信頼性を向上させることができる。 Thereby, the output voltage Vo1 with higher accuracy can be generated, and the reliability of the power supply device 41 can be improved.
　（実施の形態３）
　上述した実施の形態１，２は、電源装置３２，４１の入力電圧Ｂａｔｔおよび出力電圧Ｖｏ１を把握し、図２に示したように制御信号ｃｔｒｌ１の立ち下がりエッジが制御信号ｃｔｒｌ２の立ち上がりエッジあるいは立ち下がりエッジのどちらかに合わせることを予め設定する必要がある。 (Embodiment 3)
In the first and second embodiments described above, the input voltage Batt and the output voltage Vo1 of the power supply devices 32 and 41 are grasped, and as shown in FIG. 2, the falling edge of the control signal ctrl1 is the rising edge or the rising edge of the control signal ctrl2. It is necessary to set in advance to match one of the falling edges.
　入力電圧Ｂａｔｔが大幅に変化し、平滑用出力容量１０の入力電流ＩＬの上昇と低下との傾きの関係が変わった場合には、適用できない。つまり、制御信号Ｃｔｒｌ１の立ち下がりエッジを制御信号Ｃｔｒｌ２の立ち上がりエッジに合わせることから制御信号Ｃｔｒｌ２の立ち下がりエッジに合わせることに変更する際には、適用することができない。 It is not applicable when the input voltage Batt changes significantly and the relationship between the rise and fall of the input current IL of the smoothing output capacitor 10 changes. That is, when the falling edge of the control signal Ctrl1 is matched with the rising edge of the control signal Ctrl2, it is not applicable when changing from the matching to the falling edge of the control signal Ctrl2.
　そこで本実施の形態３では、制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２との位相関係のフィードバック制御によって制御信号Ｃｔｒｌ１、Ｃｔｒｌ２間の遅延を調整するのではなく、出力電圧Ｖｏ１のリップルのフィードバック制御により、制御信号Ｃｔｒｌ１，Ｃｔｒｌ２の遅延を調整する技術について説明する。 Therefore, in the third embodiment, the control signal Ctrl1 and the control signal Ctrl2 are not adjusted by the feedback control of the phase relationship between the control signal Ctrl1 and the control signal Ctrl2, but the control signal Ctrl1 is controlled by the ripple feedback control of the output voltage Vo1. A technique for adjusting the delay of Ctrl1 and Ctrl2 will be described.
　〈電源装置の構成例〉
　図８は、本実施の形態３による電源装置４３における構成の一例を示す説明図である。 <Configuration example of power supply device>
FIG. 8 is an explanatory diagram showing an example of the configuration of the power supply device 43 according to the third embodiment.
　なお、図８においても、図１および図５と同一構成の部分には同一符号を付している。 In FIG. 8 as well, parts having the same configuration as those in FIGS. 1 and 5 are denoted by the same reference numerals.
　図８におけるスイッチング動作部１、スイッチング動作部２、負荷５０、負荷４９、クロック生成回路２６、分周器２４、ＰＩＤ制御器３６、ＤＰＷＭ生成器３５、ＡＤ変換器４０、ＰＩＤ制御器３９、ＤＰＷＭ生成器３８、および単位遅延生成器２７は、図１および図５と同様であるので説明を省略する。 Switching operation unit 1, switching operation unit 2, load 50, load 49, clock generation circuit 26, frequency divider 24, PID controller 36, DPWM generator 35, AD converter 40, PID controller 39, DPWM in FIG. The generator 38 and the unit delay generator 27 are the same as those in FIG. 1 and FIG.
　電源装置４３は、スイッチング動作部１、スイッチング動作部２、および制御部５１を有する。電源装置４３は、出力電圧Ｖｏ１，Ｖｏ２からの帰還電圧を制御部５１に入力し、制御部５１が生成した制御信号Ｃｔｒｌ１，Ｃｔｒｌ２をスイッチング動作部１，２に入力して、所望の出力電圧値を生成する。 The power supply device 43 includes a switching operation unit 1, a switching operation unit 2, and a control unit 51. The power supply device 43 inputs the feedback voltage from the output voltages Vo1 and Vo2 to the control unit 51, inputs the control signals Ctrl1 and Ctrl2 generated by the control unit 51 to the switching operation units 1 and 2, and outputs a desired output voltage value. Is generated.
　制御部５１は、制御器２５、制御器４４、分周器２４、クロック生成回路２６、および遅延調整回路４７を有する。制御器４４は、ＡＤ変換器４５、ＰＩＤ制御器３６、ＤＰＷＭ生成器３５を有する。 The control unit 51 includes a controller 25, a controller 44, a frequency divider 24, a clock generation circuit 26, and a delay adjustment circuit 47. The controller 44 includes an AD converter 45, a PID controller 36, and a DPWM generator 35.
　制御器４４は、例えばマイコンのようなデジタル制御器であり、スイッチング動作部１に入力する制御信号Ｃｔｒｌ１を生成する。具体的には、出力電圧Ｖｏ１からの帰還電圧がＡＤ変換器４５によってデジタル帰還圧値に変換され、ＰＩＤ制御器３６にてデジタル制御値を生成する。 The controller 44 is a digital controller such as a microcomputer, for example, and generates a control signal Ctrl1 to be input to the switching operation unit 1. Specifically, the feedback voltage from the output voltage Vo1 is converted into a digital feedback pressure value by the AD converter 45, and a digital control value is generated by the PID controller 36.
　そして、分周器２４から出力されるクロックＣＬＯＣＫ１とＰＩＤ制御器３６が生成したデジタル制御値によってＤＰＷＭ生成器３５から制御信号Ｃｔｒｌ１を生成する。 Then, the control signal Ctrl1 is generated from the DPWM generator 35 based on the clock CLOCK1 output from the frequency divider 24 and the digital control value generated by the PID controller 36.
　ＡＤ変換器４５は、出力電圧Ｖｏ１からの帰還電圧をデジタル帰還電圧値に変換するアナログデジタル変換回路である。このＡＤ変換器４５が変換したデジタル帰還電圧は、２つの用途がある。 The AD converter 45 is an analog-digital conversion circuit that converts a feedback voltage from the output voltage Vo1 into a digital feedback voltage value. The digital feedback voltage converted by the AD converter 45 has two uses.
　１つは、前記実施の形態２と同様に、ＰＩＤ制御器３６に入力される。もう１つは、制御信号Ｃｔｒｌ１の１周期前毎の出力電圧Ｖｏ１のリップルの大きさを測るためである。ＡＤ変換器４５と前記実施の形態２の図５のＡＤ変換器３７との違いは、サンプリング周波数である。 One is input to the PID controller 36 as in the second embodiment. The other is to measure the magnitude of the ripple of the output voltage Vo1 every one cycle before the control signal Ctrl1. The difference between the AD converter 45 and the AD converter 37 of FIG. 5 of the second embodiment is the sampling frequency.
　ＡＤ変換器３７のサンプリング周波数は、制御信号Ｃｔｒｌ１の周波数と同じである。制御信号Ｃｔｒｌ１の１周期前毎の出力電圧Ｖｏ１のリップルの大きさを正確に測るためには、ＡＤ変換器４５のサンプリング周波数が制御信号Ｃｔｒｌ１の周波数より、例えば２倍以上の高い周波数に設定する必要がある。 The sampling frequency of the AD converter 37 is the same as the frequency of the control signal Ctrl1. In order to accurately measure the magnitude of the ripple of the output voltage Vo1 every one cycle before the control signal Ctrl1, the sampling frequency of the AD converter 45 is set to a frequency that is, for example, twice or more higher than the frequency of the control signal Ctrl1. There is a need.
　遅延調整回路４７は、リップル比較器５２、サンプルホールド回路４８、リップル比較器４６、および単位遅延生成器２７を有する。遅延調整回路４７は、制御信号Ｃｔｒｌ１と制御信号Ｃｔｒｌ２との位相関係を調整する。また、リップル比較器５２およびサンプルホールド回路４８によって、検出器が構成される。 The delay adjustment circuit 47 includes a ripple comparator 52, a sample hold circuit 48, a ripple comparator 46, and a unit delay generator 27. The delay adjustment circuit 47 adjusts the phase relationship between the control signal Ctrl1 and the control signal Ctrl2. The ripple comparator 52 and the sample hold circuit 48 constitute a detector.
　リップル比較器５２は、ＡＤ変換器４５が変換した出力電圧Ｖｏ１のデジタル帰還電圧値を用いて、制御信号Ｃｔｒｌ１の１周期中の出力電圧Ｖｏ１のリップル値を求める。サンプルホールド回路４８は、制御信号Ｃｔｒｌ１の１周期前の出力電圧Ｖｏ１のリップル値を保存する。 The ripple comparator 52 obtains the ripple value of the output voltage Vo1 in one cycle of the control signal Ctrl1 using the digital feedback voltage value of the output voltage Vo1 converted by the AD converter 45. The sample hold circuit 48 stores the ripple value of the output voltage Vo1 one cycle before the control signal Ctrl1.
　リップル比較器４６は、制御信号Ｃｔｒｌ１の１周期前と１周期後の出力電圧Ｖｏ１のリップル値とを比較して、比較した結果をパルス信号Ｈ＿ｏｕｔ、Ｌ＿ｏｕｔとして出力する。制御信号Ｃｔｒｌ１の１周期前の出力電圧Ｖｏ１のリップル値が１周期後より大きい時、パルス信号Ｈ＿ｏｕｔを生成する。制御信号Ｃｔｒｌ１の１周期前の出力電圧Ｖｏ１のリップル値が１周期後より小さい時には、パルス信号Ｌ＿ｏｕｔを生成する。 The ripple comparator 46 compares the ripple value of the output voltage Vo1 before and after one cycle of the control signal Ctrl1, and outputs the comparison results as pulse signals H_out and L_out. When the ripple value of the output voltage Vo1 one cycle before the control signal Ctrl1 is larger than after one cycle, the pulse signal H_out is generated. When the ripple value of the output voltage Vo1 one cycle before the control signal Ctrl1 is smaller than after one cycle, the pulse signal L_out is generated.
　単位遅延生成器２７は、リップル比較器４６から検出されたパルス信号Ｈ＿ｏｕｔ，Ｌ＿ｏｕｔによって、分周器２４からのクロックＣＬＯＣＫ２＿１を所望の遅延時間で遅延させて、クロックＣＬＯＣＫ２＿２を生成する。 The unit delay generator 27 delays the clock CLOCK2_1 from the frequency divider 24 by a desired delay time based on the pulse signals H_out and L_out detected from the ripple comparator 46, and generates the clock CLOCK2_2.
　リップル比較器４６がパルス信号Ｈ＿ｏｕｔを生成する場合、分周器２４からのクロックＣＬＯＣＫ２＿１を１単位分の遅延時間を増加して遅延させたクロック（ＣＬＯＣＫ２＿２）を出力する。 When the ripple comparator 46 generates the pulse signal H_out, a clock (CLOCK2_2) obtained by delaying the clock CLOCK2_1 from the frequency divider 24 by increasing the delay time by one unit is output.
　一方、リップル比較器４６がパルス信号Ｌ＿ｏｕｔを生成する場合には、分周器２４からのクロックＣＬＯＣＫ２＿１を１単位分の遅延時間を減少して遅延させたクロックＣＬＯＣＫ２＿２を出力する。 On the other hand, when the ripple comparator 46 generates the pulse signal L_out, the clock CLOCK2_2 obtained by delaying the clock CLOCK2_1 from the frequency divider 24 by reducing the delay time by one unit is output.
　制御器２５は、ＡＤ変換器４０、ＰＩＤ制御器３９、およびＤＰＷＭ生成器３８を有する。制御器２５は、例えばマイコンなどのデジタル制御器であり、制御信号Ｃｔｒｌ２を生成する。 The controller 25 includes an AD converter 40, a PID controller 39, and a DPWM generator 38. The controller 25 is a digital controller such as a microcomputer, for example, and generates a control signal Ctrl2.
　具体的には、出力電圧Ｖｏ２からの帰還電圧をＡＤ変換器４０にてデジタル帰還圧値に変換して、ＰＩＤ制御器３９によりデジタル制御値を生成し、単位遅延生成器２７から出力されるクロックＣＬＯＣＫ２＿２とＰＩＤ制御器３９から出力されるデジタル制御値によって、ＤＰＷＭ生成器３８が制御信号Ｃｔｒｌ２を生成する。 Specifically, a feedback voltage from the output voltage Vo2 is converted into a digital feedback pressure value by the AD converter 40, a digital control value is generated by the PID controller 39, and a clock output from the unit delay generator 27 is generated. The DPWM generator 38 generates the control signal Ctrl2 based on the digital control value output from the CLOCK2_2 and the PID controller 39.
　〈電源装置の動作例〉
　続いて、図８の電源装置４３における動作の一例を図９を用いて説明する。 <Example of power supply operation>
Next, an example of the operation of the power supply device 43 in FIG. 8 will be described with reference to FIG.
　図９は、図８の電源装置４３における制御部５１における各信号の一例を示すタイミングチャートである。 FIG. 9 is a timing chart showing an example of each signal in the control unit 51 in the power supply device 43 of FIG.
　図９において、上方から下方にかけては、出力電圧Ｖｏ１のリップル、クロックＣＬＯＣＫ１、クロックＣＬＯＣＫ２＿１、クロックＣＬＯＣＫ２＿２、制御信号Ｃｔｒｌ１、制御信号Ｃｔｒｌ２、パルス信号Ｌ＿ｏｕｔ、およびパルス信号Ｈ＿ｏｕｔにおける信号タイミングをそれぞれ示している。 9, the signal timings of the ripple of the output voltage Vo1, the clock CLOCK1, the clock CLOCK2_1, the clock CLOCK2_2, the control signal Ctrl1, the control signal Ctrl2, the pulse signal L_out, and the pulse signal H_out are shown from the top to the bottom, respectively.
　１周期目（初期期間）
　まず、分周器２４は、クロック生成回路２６の基準クロックから周波数が整数倍であるクロックＣＬＯＣＫ１，ＣＬＯＣＫ２＿１を生成する。ここで、制御信号Ｃｔｒｌ１，Ｃｔｒｌ２の周波数が同じである時（Ｔｓ１＝Ｔｓ２）を一例として説明する。 1st cycle (initial period)
First, the frequency divider 24 generates clocks CLOCK 1 and CLOCK 2 _ 1 whose frequency is an integer multiple from the reference clock of the clock generation circuit 26. Here, a case where the frequencies of the control signals Ctrl1 and Ctrl2 are the same (Ts1 = Ts2) will be described as an example.
　制御器４４は、出力電圧Ｖｏ１からの帰還電圧およびクロックＣＬＯＣＫ１から制御信号Ｃｔｒｌ１を生成する。単位遅延生成器２７の初期遅延設定時間はｔｄとなる。単位遅延生成器２７は、クロックＣＬＯＣＫ２＿１をｔｄ期間分遅延させて、クロックＣＬＯＣＫ２＿２として生成する。 The controller 44 generates a control signal Ctrl1 from the feedback voltage from the output voltage Vo1 and the clock CLOCK1. The initial delay setting time of the unit delay generator 27 is td. The unit delay generator 27 generates the clock CLOCK2_2 by delaying the clock CLOCK2_1 by the period td.
　制御器２５は、出力電圧Ｖｏ２からの帰還電圧およびクロックＣＬＯＣＫ２＿２から制御信号Ｃｔｒｌ２＿２を生成する。リップル比較器４６は、制御信号Ｃｔｒｌ１の１周期前の出力電圧Ｖｏ１のリップル値が１周期後より大きいことを検出して、パルス信号Ｈ＿ｏｕｔを出力する。これによって、単位遅延生成器２７に設定された遅延分は、初期のｔｄから１単位を増加したｔｄ＋ｘとなる。 The controller 25 generates a control signal Ctrl2_2 from the feedback voltage from the output voltage Vo2 and the clock CLOCK2_2. The ripple comparator 46 detects that the ripple value of the output voltage Vo1 one cycle before the control signal Ctrl1 is larger than one cycle later, and outputs the pulse signal H_out. As a result, the delay set in the unit delay generator 27 becomes td + x which is increased by one unit from the initial td.
　２～３周期目（追従期間）
　２周期目：入力電圧Ｂａｔｔ、あるいは負荷４９，５０の動作状態などによって出力電圧Ｖｏ１に変化が生じて、制御器４４から生成した制御信号Ｃｔｒｌ１のｄｕｔｙ比が増加する。 2nd to 3rd period (follow-up period)
Second period: The output voltage Vo1 changes depending on the input voltage Batt or the operating state of the loads 49 and 50, and the duty ratio of the control signal Ctrl1 generated from the controller 44 increases.
　単位遅延生成器２７は、クロックＣＬＯＣＫ２＿１をｔｄ＋ｘ期間分遅延させて、クロックＣＬＯＣＫ２＿２として生成する。リップル比較器４６が制御信号Ｃｔｒｌ１の１周期前の出力電圧（Ｖｏ１）のリップル値が１周期後より大きいことを検出し、パルス信号Ｈ＿ｏｕｔを出力する。 The unit delay generator 27 delays the clock CLOCK2_1 by a period of td + x and generates the clock CLOCK2_2. The ripple comparator 46 detects that the ripple value of the output voltage (Vo1) before one cycle of the control signal Ctrl1 is larger than after one cycle, and outputs the pulse signal H_out.
　これによって、単位遅延生成器２７に設定された遅延分は、初期のｔｄから１単位を増加し、ｔｄ＋２ｘとなる。 Thus, the delay set in the unit delay generator 27 is increased by 1 unit from the initial td, and becomes td + 2x.
　３周期目：単位遅延生成器２７はクロックＣＬＯＣＫ２＿１をｔｄ＋２ｘ期間分遅延させて、クロックＣＬＯＣＫ２＿２として生成する。リップル比較器４６が制御信号Ｃｔｒｌ１の１周期前の出力電圧Ｖｏ１のリップル値が１周期後より小さいことを検出し、パルス信号Ｌ＿ｏｕｔを出力する。これによって、単位遅延生成器２７に設定された遅延分は、ｔｄ＋２ｘから１単位を減少し、ｔｄ＋ｘとなる。 Third period: The unit delay generator 27 delays the clock CLOCK2_1 by the period of td + 2x, and generates the clock CLOCK2_2. The ripple comparator 46 detects that the ripple value of the output voltage Vo1 before one cycle of the control signal Ctrl1 is smaller than after one cycle, and outputs the pulse signal L_out. As a result, the delay set in the unit delay generator 27 is decreased by one unit from td + 2x to become td + x.
　４周期目以後（安定期間）
　パルス信号Ｈ＿ｏｕｔあるいはパルス信号Ｌ＿ｏｕｔによって、単位遅延生成器２７に設定された遅延分は、周期毎にｔｄ＋２ｘとｔｄ＋ｘの間を繰り返して設定される。 After the 4th cycle (stable period)
The delay set in the unit delay generator 27 by the pulse signal H_out or the pulse signal L_out is set repeatedly between td + 2x and td + x for each period.
　上記の動作によって、入力電圧Ｂａｔｔが大幅に変化した場合であっても、制御信号Ｃｔｒｌ２の周波数を高くすることなく、出力電圧Ｖｏ１のリップルをより小さくすることができる。 Even if the input voltage Batt changes significantly by the above operation, the ripple of the output voltage Vo1 can be further reduced without increasing the frequency of the control signal Ctrl2.
　これにより、電源装置４３における損失をより減らしながら、高精度な出力電圧Ｖｏ１を生成することができ、電源装置４３の信頼性および電源効率をより向上させることができる。 Thus, it is possible to generate the output voltage Vo1 with high accuracy while further reducing the loss in the power supply device 43, and the reliability and power supply efficiency of the power supply device 43 can be further improved.
　以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
　なお、本発明は上記した実施の形態に限定されるものではなく、様々な変形例が含まれる。例えば、上記した実施の形態は本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。 Note that the present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described.
　また、ある実施の形態の構成の一部を他の実施の形態の構成に置き換えることが可能であり、また、ある実施の形態の構成に他の実施の形態の構成を加えることも可能である。また、各実施の形態の構成の一部について、他の構成の追加、削除、置換をすることが可能である。 Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.
　また、上記の各構成、機能、処理部、処理手段等は、それらの一部又は全部を、例えば集積回路で設計する等によりハードウェアで実現してもよい。また、上記の各構成、機能等は、プロセッサがそれぞれの機能を実現するプログラムを解釈し、実行することによりソフトウェアで実現してもよい。各機能を実現するプログラム、テーブル、ファイル等の情報は、メモリや、ハードディスク、ＳＳＤ（Solid State Drive）等の記録装置、または、ＩＣカード、ＳＤカード、ＤＶＤなどの記録媒体に置くことができる。 In addition, each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor. Information such as programs, tables, and files for realizing each function can be stored in a recording device such as a memory, a hard disk, an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.
　また、制御線や情報線は説明上必要と考えられるものを示しており、製品上必ずしも全ての制御線や情報線を示しているとは限らない。実際には殆ど全ての構成が相互に接続されていると考えてもよい。 Also, the control lines and information lines indicate what is considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. Actually, it may be considered that almost all the components are connected to each other.
１　スイッチング動作部
２　スイッチング動作部
３　制御部
５　制御部
６　位相制御部
７　スイッチング素子
８　スイッチング素子
９　インダクタ
１０　平滑用出力容量
１１　ドライバ
１２　制御回路
１４　スイッチング素子
１５　スイッチング素子
１６　インダクタ
１７　平滑用出力容量
１８　ドライバ
１９　制御部
２０　制御回路
２４　分周器
２５　制御器
２６　クロック生成回路
２７　単位遅延生成器
２８　エッジ検出器
２９　制御部
３２　電源装置
３３　制御器
３４　制御器
３５　ＤＰＷＭ生成器
３６　ＰＩＤ制御器
３７　ＡＤ変換器
３８　ＤＰＷＭ生成器
３９　ＰＩＤ制御器
４０　ＡＤ変換器
４１　電源装置
４２　可変遅延器
４３　電源装置
４４　制御器
４５　ＡＤ変換器
４６　リップル比較器
４７　遅延調整回路
４８　サンプルホールド回路
５１　制御部
５２　リップル比較器
５３　入力電圧検出器
５４　出力電圧検出器
５５　電圧比較器
５６　電圧検出比較部
５７　電流検出器
５９　電流傾き比較器
６０　電流検出比較器 DESCRIPTION OF SYMBOLS 1 Switching operation part 2 Switching operation part 3 Control part 5 Control part 6 Phase control part 7 Switching element 8 Switching element 9 Inductor 10 Smoothing output capacity 11 Driver 12 Control circuit 14 Switching element 15 Switching element 16 Inductor 17 Smoothing output capacity 18 Driver 19 Control unit 20 Control circuit 24 Frequency divider 25 Controller 26 Clock generation circuit 27 Unit delay generator 28 Edge detector 29 Control unit 32 Power supply device 33 Controller 34 Controller 35 DPWM generator 36 PID controller 37 AD conversion Unit 38 DPWM Generator 39 PID Controller 40 AD Converter 41 Power Supply Device 42 Variable Delay Device 43 Power Supply Device 44 Controller 45 AD Converter 46 Ripple Comparator 47 Delay Adjustment Circuit 48 Sample Hold Circuit 51 Control Unit 52 Ripple Comparator 53 Input voltage Can 54 output voltage detector 55 voltage comparator 56 the voltage detecting comparator unit 57 current detector 59 current slope comparator 60 current detector comparator

Claims (15)

  1. 　外部から入力される入力電圧から第１の出力電圧を生成する第１のスイッチング電源回路と、
    　前記第１の出力電圧から第２の出力電圧を生成する第２のスイッチング電源回路と、
    　前記第１のスイッチング電源回路が生成する前記第１の出力電圧を第１のクロックに基づいて制御する第１の制御回路と、
    　前記第２のスイッチング電源回路が生成する前記第２の出力電圧を第２のクロックに基づいて制御する第２の制御回路と、
    　前記第１のクロックの周波数と前記第２のクロックの周波数とを整数倍に調整して、前記第１のクロックと前記第２のクロックとの遅延を前記第１の出力電圧のリップルを低減するように制御する遅延生成部と、
    　を有する、電源装置。     A first switching power supply circuit that generates a first output voltage from an input voltage input from the outside;
    A second switching power supply circuit for generating a second output voltage from the first output voltage;
    A first control circuit for controlling the first output voltage generated by the first switching power supply circuit based on a first clock;
    A second control circuit for controlling the second output voltage generated by the second switching power supply circuit based on a second clock;
    The frequency of the first clock and the frequency of the second clock are adjusted to an integral multiple to reduce the delay between the first clock and the second clock to reduce the ripple of the first output voltage. A delay generator that controls
    Having a power supply.
  2. 　請求項１記載の電源装置において、
    　前記第１のスイッチング電源回路は、前記入力電圧をスイッチングする第１のスイッチング部を有し、
    　前記第２のスイッチング電源回路は、前記第１の出力電圧をスイッチングする第２のスイッチング部を有し、
    　前記第１の制御回路は、前記第１のクロックから前記第１のスイッチング部を制御する第１の制御信号を生成し、
    　前記第２の制御回路は、前記第２のクロックから前記第２のスイッチング部を制御する第２の制御信号を生成し、
    　前記遅延生成部は、前記第１の制御信号と前記第２の制御信号との位相を制御して、前記第１のクロックおよび前記第２のクロックの遅延を制御する、電源装置。     The power supply device according to claim 1, wherein
    The first switching power supply circuit includes a first switching unit that switches the input voltage,
    The second switching power supply circuit includes a second switching unit that switches the first output voltage,
    The first control circuit generates a first control signal for controlling the first switching unit from the first clock,
    The second control circuit generates a second control signal for controlling the second switching unit from the second clock,
    The delay generator controls a phase of the first control signal and the second control signal to control a delay between the first clock and the second clock.
  3. 　請求項２記載の電源装置において、
    　前記第１の制御信号と前記第２の制御信号との信号立ち上がりエッジまたは信号立ち下がりエッジを検出するエッジ検出器を有し、
    　前記遅延生成部は、前記第１の制御信号と前記第２の制御信号との信号立ち上がりエッジまたは信号立ち下がりエッジを揃えるように前記第１のクロックおよび前記第２のクロックの遅延を制御する、電源装置。     The power supply device according to claim 2, wherein
    An edge detector for detecting a signal rising edge or a signal falling edge of the first control signal and the second control signal;
    The delay generation unit controls delays of the first clock and the second clock so that signal rising edges or signal falling edges of the first control signal and the second control signal are aligned; Power supply.
  4. 　請求項２記載の電源装置において、
    　インダクタに流れるインダクタ電流の上昇およびインダクタ電流の低下の傾きを検出する電流検出器と、
    　前記電流検出器が検出する前記インダクタ電流の上昇および前記インダクタ電流の低下の傾きを比較して、前記インダクタ電流の上昇の傾きと前記インダクタ電流の低下の傾きのいずれの傾きが大きいかを判定する電流傾き比較器と、
    　を有し、
    　前記インダクタは、前記第１のスイッチング電源回路に設けられ、前記第１のスイッチング部のスイッチングによりエネルギを蓄積および放出し、
    　前記遅延生成部は、前記電流傾き比較器の判定結果に基づいて、前記第１の制御信号の信号立ち上がりエッジまたは信号立ち下がりエッジのいずれかと前記第２の制御信号の信号立ち上がりエッジまたは信号立ち下がりエッジのいずれかとを揃えるように制御する、電源装置。     The power supply device according to claim 2, wherein
    A current detector for detecting the rise of the inductor current flowing through the inductor and the slope of the decrease of the inductor current;
    The slope of the rise of the inductor current detected by the current detector and the slope of the decrease of the inductor current are compared to determine which slope of the rise of the inductor current and the slope of the decrease of the inductor current is greater A current slope comparator;
    Have
    The inductor is provided in the first switching power supply circuit, and stores and releases energy by switching of the first switching unit,
    The delay generation unit is configured to determine either the signal rising edge or the signal falling edge of the first control signal and the signal rising edge or the signal falling edge of the second control signal based on a determination result of the current slope comparator. A power supply that controls to align with one of the edges.
  5. 　請求項４記載の電源装置において、
    　前記遅延生成部は、前記電流傾き比較器が前記インダクタ電流の上昇の傾きが前記インダクタ電流の低下の傾きより大きいと判定した際に、前記第１のスイッチング部のオフ動作と、前記第２のスイッチング部のオン動作とが同時となり、前記インダクタ電流の上昇の傾きが前記インダクタ電流の低下の傾きよりも小さいと判定した際に、前記第１のスイッチング部のオフ動作と前記第２のスイッチング部のオフ動作とが同時となるように、前記第１の制御信号および前記第２の制御信号の信号立ち上がりエッジまたは信号立ち下がりエッジを制御する、電源装置。     The power supply device according to claim 4, wherein
    When the current slope comparator determines that the slope of the increase in the inductor current is larger than the slope of the decrease in the inductor current, the delay generation unit is configured to turn off the first switching unit and When the switching unit is turned on at the same time and it is determined that the slope of the increase in the inductor current is smaller than the slope of the decrease in the inductor current, the off operation of the first switching unit and the second switching unit A power supply apparatus that controls the signal rising edge or the signal falling edge of the first control signal and the second control signal so that the OFF operation of the first control signal and the second control signal are simultaneously performed.
  6. 　請求項３記載の電源装置において、
    　前記遅延生成部は、前記第１のクロックの周波数と前記第２のクロックの周波数とが等しい場合、前記第１のスイッチング部のオフ動作と前記第２のスイッチング部のオン動作とが同時になるように前記第１のクロックおよび前記第２のクロックの遅延を制御する、電源装置。     The power supply device according to claim 3, wherein
    The delay generator is configured to simultaneously turn off the first switching unit and turn on the second switching unit when the frequency of the first clock is equal to the frequency of the second clock. A power supply device for controlling a delay of the first clock and the second clock.
  7. 　請求項３記載の電源装置において、
    　前記遅延生成部は、前記第１のクロックの周波数と前記第２のクロックの周波数とが等しい場合、前記第１のスイッチング部のオフ動作と前記第２のスイッチング部のオフ動作とが同時になるように前記第１のクロックおよび前記第２のクロックの遅延を制御する、電源装置。     The power supply device according to claim 3, wherein
    The delay generator is configured to simultaneously turn off the first switching unit and the second switching unit when the frequency of the first clock is equal to the frequency of the second clock. A power supply device for controlling a delay of the first clock and the second clock.
  8. 　請求項３記載の電源装置において、
    　前記遅延生成部は、前記第２のクロックの周波数が前記第１のクロックの周波数の２倍以上となる場合、前記第１のスイッチング部のオフ動作と前記第２のスイッチング部のオン動作とが同時になるように前記第１のクロックおよび前記第２のクロックの遅延を制御する、電源装置。     The power supply device according to claim 3, wherein
    When the frequency of the second clock is twice or more than the frequency of the first clock, the delay generation unit performs an off operation of the first switching unit and an on operation of the second switching unit. A power supply apparatus that controls delays of the first clock and the second clock so as to be simultaneous.
  9. 　請求項３記載の電源装置において、
    　前記遅延生成部は、前記第２のクロックの周波数が前記第１のクロックの周波数の２倍以上となる場合、前記第１のスイッチング部のオフ動作と前記第２のスイッチング部のオフ動作とが同時になるように前記第１のクロックおよび前記第２のクロックの遅延を制御する、電源装置。     The power supply device according to claim 3, wherein
    When the frequency of the second clock is twice or more than the frequency of the first clock, the delay generation unit performs an off operation of the first switching unit and an off operation of the second switching unit. A power supply apparatus that controls delays of the first clock and the second clock so as to be simultaneous.
  10. 　請求項３記載の電源装置において、
    　前記第１のスイッチング電源回路に入力される前記入力電圧および前記第１のスイッチング電源回路が生成する前記第１の出力電圧の電圧レベルを検出する電圧検出部と、
    　前記電圧検出部が検出した前記入力電圧と前記第１の出力電圧とを比較して、その比較結果を出力する電圧比較器と、
    　を有し、
    　前記遅延生成部は、前記第１の制御信号の信号立ち上がりエッジまたは信号立ち下がりエッジのいずれかと前記第２の制御信号の信号立ち上がりエッジまたは信号立ち下がりエッジのいずれかとを揃えるように制御する、電源装置。     The power supply device according to claim 3, wherein
    A voltage detector for detecting a voltage level of the input voltage input to the first switching power supply circuit and the first output voltage generated by the first switching power supply circuit;
    A voltage comparator that compares the input voltage detected by the voltage detector with the first output voltage and outputs a comparison result;
    Have
    The delay generation unit is configured to control so that either a signal rising edge or a signal falling edge of the first control signal is aligned with either a signal rising edge or a signal falling edge of the second control signal. apparatus.
  11. 　請求項１０記載の電源装置において、
    　前記遅延生成部は、前記電圧比較器の比較結果に基づいて、前記入力電圧と前記第１の出力電圧との差が前記第１の出力電圧より大きい場合に、前記第１のスイッチング部のオフ動作と前記第２のスイッチング部のオン動作とが同時となり、前記入力電圧と前記第１の出力電圧との差が前記第１の出力電圧より小さい場合に、前記第１のスイッチング部のオフ動作と前記第２のスイッチング部のオフ動作とが同時となるように前記第１の制御信号および前記第２の制御信号を制御する、電源装置。     The power supply device according to claim 10, wherein
    The delay generator is configured to turn off the first switching unit when a difference between the input voltage and the first output voltage is larger than the first output voltage based on a comparison result of the voltage comparator. When the operation and the ON operation of the second switching unit are simultaneous, and the difference between the input voltage and the first output voltage is smaller than the first output voltage, the OFF operation of the first switching unit And the second control signal to control the first control signal and the second control signal so that the OFF operation of the second switching unit is simultaneous.
  12. 　請求項１記載の電源装置において、
    　前記第１の出力電圧のリップルを前記第１のクロックの１周期毎に測定する検出器と、
    　前記第１のクロックの１周期前の前記第１の出力電圧のリップルと前記第１のクロックの１周期後の前記第１の出力電圧のリップルの大きさを比較するリップル比較器と、
    　を有し、
    　前記遅延生成部は、前記リップル比較器の比較結果に基づいて、前記第１のクロックと前記第２のクロックとの遅延を制御する、電源装置。     The power supply device according to claim 1, wherein
    A detector for measuring the ripple of the first output voltage every period of the first clock;
    A ripple comparator that compares the ripple of the first output voltage one period before the first clock with the magnitude of the ripple of the first output voltage after one period of the first clock;
    Have
    The delay generator controls a delay between the first clock and the second clock based on a comparison result of the ripple comparator.
  13. 　請求項１２記載の電源装置において、
    　前記遅延生成部は、前記リップル比較器の比較結果が前記第１のクロックの１周期前の前記第１の出力電圧のリップルが前記第１のクロックの１周期後の前記第１の出力電圧のリップルより大きい場合に前記第１のクロックと前記第２のクロックとの遅延を増加させ、前記第１のクロックの１周期前の前記第１の出力電圧のリップルが前記第１のクロックの１周期後の前記第１の出力電圧のリップルより小さい場合に前記第１のクロックと前記第２のクロックとの遅延が減少するように制御する、電源装置。     The power supply device according to claim 12, wherein
    The delay generation unit is configured such that a comparison result of the ripple comparator indicates that the ripple of the first output voltage one cycle before the first clock is the first output voltage after one cycle of the first clock. When the ripple is larger than the ripple, the delay between the first clock and the second clock is increased, and the ripple of the first output voltage one cycle before the first clock is one cycle of the first clock. A power supply apparatus that controls to reduce a delay between the first clock and the second clock when the ripple is smaller than a ripple of the first output voltage later.
  14. 　請求項１２記載の電源装置において、
    　前記遅延生成部は、前記リップル比較器の比較結果が前記第１のクロックの１周期前の前記第１の出力電圧のリップルが前記第１のクロックの１周期後の前記第１の出力電圧のリップルより大きい場合に前記第１のクロックと前記第２のクロックとの遅延を減少させ、前記第１のクロックの１周期前の前記第１の出力電圧のリップルが前記第１のクロックの１周期後の前記第１の出力電圧のリップルより小さい場合に前記第１のクロックと前記第２のクロックとの遅延が増加するように制御する、電源装置。     The power supply device according to claim 12, wherein
    The delay generation unit is configured such that a comparison result of the ripple comparator indicates that the ripple of the first output voltage one cycle before the first clock is the first output voltage after one cycle of the first clock. When larger than the ripple, the delay between the first clock and the second clock is reduced, and the ripple of the first output voltage one cycle before the first clock is one cycle of the first clock. A power supply apparatus that controls to increase a delay between the first clock and the second clock when the ripple is smaller than a ripple of the first output voltage later.
  15. 　外部から入力される入力電圧から第１の出力電圧を生成する第１のスイッチング電源回路と、
    　前記第１の出力電圧から第２の出力電圧を生成する第２のスイッチング電源回路と、
    　前記第１のスイッチング電源回路が生成する前記第１の出力電圧を第１のクロックに基づいて制御する第１の制御回路と、
    　前記第２のスイッチング電源回路が生成する前記第２の出力電圧を第２のクロックに基づいて制御する第２の制御回路と、
    　前記第１のクロックの周波数と前記第２のクロックの周波数とを整数倍に調整して、前記第１のクロックと前記第２のクロックとの遅延を制御する遅延生成部と、
    　を有する、電源装置。     A first switching power supply circuit that generates a first output voltage from an input voltage input from the outside;
    A second switching power supply circuit for generating a second output voltage from the first output voltage;
    A first control circuit for controlling the first output voltage generated by the first switching power supply circuit based on a first clock;
    A second control circuit for controlling the second output voltage generated by the second switching power supply circuit based on a second clock;
    A delay generator that adjusts the frequency of the first clock and the frequency of the second clock to an integral multiple to control a delay between the first clock and the second clock;
    Having a power supply.
PCT/JP2017/031627 2017-02-10 2017-09-01 Power supply device WO2018146843A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119315820A (en) * 2024-12-16 2025-01-14 大连科技学院 A power conversion system and method for a DC microgrid

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01255469A (en) * 1988-04-01 1989-10-12 Matsushita Electric Works Ltd Power source device
JPH10225108A (en) * 1996-12-03 1998-08-21 Fujitsu Ltd Step-up / step-down DC / DC converter
JP2006141183A (en) * 2004-11-15 2006-06-01 Matsushita Electric Ind Co Ltd Step-up/down converter
JP2009081988A (en) * 2007-09-07 2009-04-16 Panasonic Corp Buck-boost switching regulator

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01255469A (en) * 1988-04-01 1989-10-12 Matsushita Electric Works Ltd Power source device
JPH10225108A (en) * 1996-12-03 1998-08-21 Fujitsu Ltd Step-up / step-down DC / DC converter
JP2006141183A (en) * 2004-11-15 2006-06-01 Matsushita Electric Ind Co Ltd Step-up/down converter
JP2009081988A (en) * 2007-09-07 2009-04-16 Panasonic Corp Buck-boost switching regulator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119315820A (en) * 2024-12-16 2025-01-14 大连科技学院 A power conversion system and method for a DC microgrid

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