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WO2018018371A1 - Procédé et système de calcul de tension de puce multi-cœur - Google Patents

Procédé et système de calcul de tension de puce multi-cœur Download PDF

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Publication number
WO2018018371A1
WO2018018371A1 PCT/CN2016/091594 CN2016091594W WO2018018371A1 WO 2018018371 A1 WO2018018371 A1 WO 2018018371A1 CN 2016091594 W CN2016091594 W CN 2016091594W WO 2018018371 A1 WO2018018371 A1 WO 2018018371A1
Authority
WO
WIPO (PCT)
Prior art keywords
threads
core
allocation policy
core chip
voltage calculation
Prior art date
Application number
PCT/CN2016/091594
Other languages
English (en)
Chinese (zh)
Inventor
张升泽
Original Assignee
张升泽
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 张升泽 filed Critical 张升泽
Priority to PCT/CN2016/091594 priority Critical patent/WO2018018371A1/fr
Publication of WO2018018371A1 publication Critical patent/WO2018018371A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof

Definitions

  • the present invention relates to the field of electronic chips, and in particular, to a multi-core chip voltage calculation method and system.
  • the chip also has its own unique place. In a broad sense, as long as it is a semiconductor wafer manufactured by microfabrication, it can be called a chip, and there is no circuit inside.
  • a semiconductor light source chip for example, a mechanical chip such as a MEMS gyroscope; or a biochip such as a DNA chip.
  • the intersection of the chip and the integrated circuit is on the "circuit on the silicon wafer.”
  • the chipset is a series of interrelated chipsets that are interdependent and can play a bigger role, such as the processor inside the computer and the North-South Bridge chipset, the RF, baseband and power management chipset in the phone. .
  • a multi-core chip voltage calculation method is provided, which solves the shortcomings that the prior art cannot realize voltage calculation and management.
  • a multi-core chip voltage calculation method comprising the following steps:
  • the voltage of each core is calculated based on the number of threads.
  • the obtaining, according to the allocation policy, the number of threads of each kernel is specific, including:
  • the number of threads per core is allocated according to the load balancing allocation policy.
  • the obtaining, according to the allocation policy, the number of threads of each kernel is specific, including:
  • the number of threads per core is allocated based on the number-averaged allocation policy.
  • a multi-core chip voltage calculation system comprising:
  • the obtaining unit is configured to acquire a total thread of the multi-core chip
  • An allocation unit for knowing the number of threads of each kernel according to an allocation policy
  • the allocating unit is specifically configured to allocate a number of threads of each core according to a load balancing allocation policy.
  • the allocating unit is specifically configured to allocate a number of threads of each core according to a quantity-averaged allocation policy.
  • the technical solution provided by the specific embodiment of the present invention acquires the total thread of the multi-core chip, learns the number of threads of each core according to the allocation strategy, and calculates the voltage of each core according to the number of threads, so it has the advantages of realizing multi-core chip voltage calculation and management. .
  • FIG. 1 is a flow chart of a method for calculating a multi-core chip voltage according to the present invention
  • FIG. 2 is a structural diagram of a multi-core chip voltage calculation system provided by the present invention.
  • FIG. 1 is a flowchart of a multi-core chip voltage calculation method according to a first preferred embodiment of the present invention. The method is implemented by an electronic chip. The method is as shown in FIG. 1 and includes the following steps:
  • Step S101 Acquire a total thread of the multi-core chip
  • Step S102 Obtain a number of threads of each kernel according to an allocation policy.
  • Step S103 Calculate the voltage of each core according to the number of threads.
  • the technical solution provided by the specific embodiment of the present invention acquires the total thread of the multi-core chip, learns the number of threads of each core according to the allocation strategy, and calculates the voltage of each core according to the number of threads, so it has the advantages of realizing multi-core chip voltage calculation and management. .
  • the implementation method of the foregoing step S102 may be specifically:
  • the number of threads per core is allocated according to the load balancing allocation policy.
  • the implementation method of the foregoing step S103 may be specifically:
  • the number of threads per core is allocated based on the number-averaged allocation policy.
  • FIG. 2 is a multi-core chip voltage calculation system according to a second preferred embodiment of the present invention.
  • the system includes:
  • the obtaining unit 201 is configured to acquire a total thread of the multi-core chip
  • the allocating unit 202 is configured to learn the number of threads of each kernel according to the allocation policy
  • the calculating unit 203 is configured to calculate the voltage of each core according to the number of threads.
  • the technical solution provided by the specific embodiment of the present invention acquires the total thread of the multi-core chip, learns the number of threads of each core according to the allocation strategy, and calculates the voltage of each core according to the number of threads, so it has the advantages of realizing multi-core chip voltage calculation and management. .
  • the foregoing allocating unit 202 is specifically configured to allocate a number of threads of each core according to a load balancing allocation policy.
  • the foregoing allocating unit 202 is specifically configured to allocate, according to the number-averaged allocation policy, the number of threads of each core.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • the computer readable medium may include random access memory (Random) Access Memory, RAM), Read-Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), Compact Disc Read-Only Memory, CD-ROM, or other optical disc storage, magnetic storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also. Any connection may suitably be a computer readable medium.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

L'invention concerne un procédé et un système de calcul de tension de puce multi-cœur. Le procédé comprend les étapes suivantes : acquérir un fil d'exécution complet d'une puce multi-cœur (101) ; obtenir le nombre de fils d'exécution de chaque cœur selon une politique d'attribution (102) ; et calculer la tension de chaque cœur selon le nombre de fils d'exécution (103). Le procédé et le système présentent les avantages du calcul et de la gestion de la tension.
PCT/CN2016/091594 2016-07-25 2016-07-25 Procédé et système de calcul de tension de puce multi-cœur WO2018018371A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/091594 WO2018018371A1 (fr) 2016-07-25 2016-07-25 Procédé et système de calcul de tension de puce multi-cœur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/091594 WO2018018371A1 (fr) 2016-07-25 2016-07-25 Procédé et système de calcul de tension de puce multi-cœur

Publications (1)

Publication Number Publication Date
WO2018018371A1 true WO2018018371A1 (fr) 2018-02-01

Family

ID=61015353

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/091594 WO2018018371A1 (fr) 2016-07-25 2016-07-25 Procédé et système de calcul de tension de puce multi-cœur

Country Status (1)

Country Link
WO (1) WO2018018371A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101076770A (zh) * 2004-09-28 2007-11-21 英特尔公司 根据可用并行数目改变每条指令能量的方法和设备
US20100299541A1 (en) * 2009-05-21 2010-11-25 Kabushiki Kaisha Toshiba Multi-core processor system
CN102567117A (zh) * 2010-09-30 2012-07-11 国际商业机器公司 调度处理器中的线程的方法和系统
US20130346774A1 (en) * 2012-03-13 2013-12-26 Malini K. Bhandaru Providing energy efficient turbo operation of a processor
CN103793041A (zh) * 2014-02-21 2014-05-14 珠海全志科技股份有限公司 多核对称多处理系统的电源管理方法及装置
CN106227639A (zh) * 2016-07-25 2016-12-14 张升泽 多核芯片电压计算方法及系统

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101076770A (zh) * 2004-09-28 2007-11-21 英特尔公司 根据可用并行数目改变每条指令能量的方法和设备
US20100299541A1 (en) * 2009-05-21 2010-11-25 Kabushiki Kaisha Toshiba Multi-core processor system
CN102567117A (zh) * 2010-09-30 2012-07-11 国际商业机器公司 调度处理器中的线程的方法和系统
US20130346774A1 (en) * 2012-03-13 2013-12-26 Malini K. Bhandaru Providing energy efficient turbo operation of a processor
CN103793041A (zh) * 2014-02-21 2014-05-14 珠海全志科技股份有限公司 多核对称多处理系统的电源管理方法及装置
CN106227639A (zh) * 2016-07-25 2016-12-14 张升泽 多核芯片电压计算方法及系统

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