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WO2018018373A1 - Procédé et système de calcul d'énergie pour puces multi-cœur - Google Patents

Procédé et système de calcul d'énergie pour puces multi-cœur Download PDF

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Publication number
WO2018018373A1
WO2018018373A1 PCT/CN2016/091596 CN2016091596W WO2018018373A1 WO 2018018373 A1 WO2018018373 A1 WO 2018018373A1 CN 2016091596 W CN2016091596 W CN 2016091596W WO 2018018373 A1 WO2018018373 A1 WO 2018018373A1
Authority
WO
WIPO (PCT)
Prior art keywords
core
threads
allocation policy
power calculation
power
Prior art date
Application number
PCT/CN2016/091596
Other languages
English (en)
Chinese (zh)
Inventor
张升泽
Original Assignee
张升泽
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 张升泽 filed Critical 张升泽
Priority to PCT/CN2016/091596 priority Critical patent/WO2018018373A1/fr
Publication of WO2018018373A1 publication Critical patent/WO2018018373A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Definitions

  • the present invention relates to the field of electronic chips, and in particular, to a power calculation method and system for multiple core chips.
  • the chip also has its own unique place. In a broad sense, as long as it is a semiconductor wafer manufactured by microfabrication, it can be called a chip, and there is no circuit inside.
  • a semiconductor light source chip for example, a mechanical chip such as a MEMS gyroscope; or a biochip such as a DNA chip.
  • the intersection of the chip and the integrated circuit is on the "circuit on the silicon wafer.”
  • the chipset is a series of interrelated chipsets that are interdependent and can play a bigger role, such as the processor inside the computer and the North-South Bridge chipset, the RF, baseband and power management chipset in the phone. .
  • a power calculation method for a plurality of core chips is provided, which solves the shortcomings in the calculation and management of power that cannot be realized in the prior art.
  • a power calculation method for a plurality of core chips comprising the steps of:
  • the power of each core is calculated based on the number of threads.
  • the obtaining, according to the allocation policy, the number of threads of each kernel is specific, including:
  • the number of threads per core is allocated according to the load balancing allocation policy.
  • the obtaining, according to the allocation policy, the number of threads of each kernel is specific, including:
  • the number of threads per core is allocated based on the number-averaged allocation policy.
  • a power calculation system for a plurality of core chips comprising:
  • the obtaining unit is configured to acquire a total thread of the multi-core chip
  • An allocation unit for knowing the number of threads of each kernel according to an allocation policy
  • the allocating unit is specifically configured to allocate a number of threads of each core according to a load balancing allocation policy.
  • the allocating unit is specifically configured to allocate a number of threads of each core according to a quantity-averaged allocation policy.
  • the technical solution provided by the specific embodiment of the present invention acquires the total thread of the multi-core chip, learns the number of threads of each core according to the allocation strategy, calculates the power of each core according to the number of threads, and therefore has power calculation for implementing multiple core chips.
  • FIG. 2 is a structural diagram of a power calculation system of a plurality of core chips according to the present invention.
  • FIG. 1 is a flowchart of a power calculation method for multiple core chips according to a first preferred embodiment of the present invention.
  • the method is implemented by an electronic chip.
  • the method is as shown in FIG. 1 and includes the following steps. :
  • Step S101 Acquire a total thread of the multi-core chip
  • Step S102 Obtain a number of threads of each kernel according to an allocation policy.
  • Step S103 Calculate the power of each core according to the number of threads.
  • the technical solution provided by the specific embodiment of the present invention acquires the total thread of the multi-core chip, learns the number of threads of each core according to the allocation strategy, calculates the power of each core according to the number of threads, and therefore has power calculation for implementing multiple core chips.
  • the implementation method of the foregoing step S102 may be specifically:
  • the number of threads per core is allocated according to the load balancing allocation policy.
  • the implementation method of the foregoing step S103 may be specifically:
  • the number of threads per core is allocated based on the number-averaged allocation policy.
  • FIG. 2 is a power calculation system for multiple core chips according to a second preferred embodiment of the present invention.
  • the system includes:
  • the obtaining unit 201 is configured to acquire a total thread of the multi-core chip
  • the allocating unit 202 is configured to learn the number of threads of each kernel according to the allocation policy
  • the calculating unit 203 is configured to calculate the power of each core according to the number of threads.
  • the technical solution provided by the specific embodiment of the present invention acquires the total thread of the multi-core chip, learns the number of threads of each core according to the allocation strategy, calculates the power of each core according to the number of threads, and therefore has power calculation for implementing multiple core chips.
  • the foregoing allocating unit 202 is specifically configured to allocate a number of threads of each core according to a load balancing allocation policy.
  • the foregoing allocating unit 202 is specifically configured to allocate, according to the number-averaged allocation policy, the number of threads of each core.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • the computer readable medium may include random access memory (Random) Access Memory, RAM), Read-Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), Compact Disc Read-Only Memory, CD-ROM, or other optical disc storage, magnetic storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also. Any connection may suitably be a computer readable medium.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

L'invention concerne un procédé et un système de calcul d'énergie pour puces multi-cœur. Le procédé comprend les étapes suivantes : acquérir un fil d'exécution complet d'une puce multi-cœur (101) ; obtenir le nombre de fils d'exécution de chaque cœur selon une stratégie d'attribution (102) ; et calculer l'énergie de chaque cœur selon le nombre de fils d'exécution (103). La solution technique fournie dans le procédé présente les avantages de calcul et de gestion d'énergie.
PCT/CN2016/091596 2016-07-25 2016-07-25 Procédé et système de calcul d'énergie pour puces multi-cœur WO2018018373A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/091596 WO2018018373A1 (fr) 2016-07-25 2016-07-25 Procédé et système de calcul d'énergie pour puces multi-cœur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/091596 WO2018018373A1 (fr) 2016-07-25 2016-07-25 Procédé et système de calcul d'énergie pour puces multi-cœur

Publications (1)

Publication Number Publication Date
WO2018018373A1 true WO2018018373A1 (fr) 2018-02-01

Family

ID=61015295

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/091596 WO2018018373A1 (fr) 2016-07-25 2016-07-25 Procédé et système de calcul d'énergie pour puces multi-cœur

Country Status (1)

Country Link
WO (1) WO2018018373A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101256515A (zh) * 2008-03-11 2008-09-03 浙江大学 多核处理器操作系统负载均衡的实现方法
CN101727172A (zh) * 2008-10-27 2010-06-09 联想(北京)有限公司 一种计算机进程功耗的测量方法及测量装置、计算机系统
US20160034310A1 (en) * 2014-07-30 2016-02-04 Empire Technology Development Llc Job assignment in a multi-core processor
CN105700959A (zh) * 2016-01-13 2016-06-22 南京邮电大学 一种面向多核平台的多线程划分及静态均衡调度策略
CN106227603A (zh) * 2016-07-25 2016-12-14 张升泽 多个内核芯片的功率计算方法及系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101256515A (zh) * 2008-03-11 2008-09-03 浙江大学 多核处理器操作系统负载均衡的实现方法
CN101727172A (zh) * 2008-10-27 2010-06-09 联想(北京)有限公司 一种计算机进程功耗的测量方法及测量装置、计算机系统
US20160034310A1 (en) * 2014-07-30 2016-02-04 Empire Technology Development Llc Job assignment in a multi-core processor
CN105700959A (zh) * 2016-01-13 2016-06-22 南京邮电大学 一种面向多核平台的多线程划分及静态均衡调度策略
CN106227603A (zh) * 2016-07-25 2016-12-14 张升泽 多个内核芯片的功率计算方法及系统

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