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WO2018018353A1 - Substrat de réseau et procédé de production de substrat de réseau - Google Patents

Substrat de réseau et procédé de production de substrat de réseau Download PDF

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Publication number
WO2018018353A1
WO2018018353A1 PCT/CN2016/091528 CN2016091528W WO2018018353A1 WO 2018018353 A1 WO2018018353 A1 WO 2018018353A1 CN 2016091528 W CN2016091528 W CN 2016091528W WO 2018018353 A1 WO2018018353 A1 WO 2018018353A1
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WO
WIPO (PCT)
Prior art keywords
layer
array substrate
hole
transmission line
signal transmission
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PCT/CN2016/091528
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English (en)
Chinese (zh)
Inventor
袁泽
余晓军
古普塔阿米特
赵继刚
魏鹏
Original Assignee
深圳市柔宇科技有限公司
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Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to CN201680015886.4A priority Critical patent/CN107454981A/zh
Priority to JP2019503520A priority patent/JP6752354B2/ja
Priority to PCT/CN2016/091528 priority patent/WO2018018353A1/fr
Priority to KR1020197003074A priority patent/KR102221442B1/ko
Publication of WO2018018353A1 publication Critical patent/WO2018018353A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to an array substrate and a method of fabricating the array substrate.
  • a thin film transistor As a switching element, a thin film transistor (TFT) is widely used in electronic display devices such as liquid crystal display (LCD) and organic light-emitting diode (OLED).
  • a thin film transistor generally includes a gate electrode, a gate insulating layer, an active layer, a source and a drain, etc., wherein a high quality gate insulating layer is an important parameter for realizing good electrical stability and small leakage current of the thin film transistor. key.
  • the gate insulating layer is mainly prepared by a plasma chemical vapor deposition method using an inorganic non-metal material (for example, SiO x , SiN x , etc.).
  • the gate insulating layer Due to the characteristics of the gate insulating layer and the limitation of the preparation conditions, the gate insulating layer usually has internal stress, and the gate insulating layer prepared by brittle SiO x , SiN x or the like is easily broken by internal stress; in particular, In a flexible display, the presence of internal stress also causes deformation of a layer structure of a flexible substrate, a gate insulating layer, and the like in a thin film transistor.
  • the present invention provides an array substrate, the array substrate comprising: a substrate, a signal transmission line and a gate disposed on the substrate, an insulating layer covering the signal transmission line and the gate, and An active layer on the insulating layer and a first metal layer, wherein a gap is formed between the gate and the signal transmission line; an isolation trench and a via hole are formed in the insulating layer, and the first metal layer
  • the signal transmission line is electrically connected through the through hole, and the isolation groove is disposed between the signal transmission line and the gate.
  • the array substrate further includes an organic layer disposed on the insulating layer and filling the isolation trench.
  • the array substrate further includes a second metal layer, the second metal layer being electrically connected to both ends of the active layer to form a source Pole and drain.
  • the first metal layer and the second metal layer are in a unitary structure.
  • the array substrate further includes an inorganic layer, the inorganic layer covering the active layer and the insulating layer; a first through hole, a second through hole, a third through hole and a fourth through hole; the first through hole is in communication with the through hole for conducting the signal transmission line and the first metal layer; The second through hole is in communication with the isolation groove; the third through hole and the fourth through hole are respectively disposed corresponding to both ends of the active layer for conducting the active layer and the source a pole and the drain.
  • the organic layer covers the inorganic layer; the organic layer defines a fifth through hole, a sixth through hole, and a seventh through hole, wherein The fifth through hole is disposed corresponding to the first through hole and communicates with the first through hole for conducting the signal transmission line and the first metal layer; the sixth through hole corresponds to the a third through hole is disposed and communicates with the third through hole; the seventh through hole is disposed corresponding to the fourth through hole and communicates with the fourth through hole; the sixth through hole and the seventh through hole A via hole is used to turn on the active layer and the source and the drain.
  • the surface of the organic layer facing away from the substrate is flush with the end surface of the insulating layer facing away from the substrate.
  • the array substrate further includes a protective layer and a pixel electrode, the protective layer covering the first metal layer and the second metal And forming a second via hole; the second via hole is disposed corresponding to the source; the pixel electrode covers the protective layer, and is electrically connected to the source through the second via hole.
  • the array substrate further includes an inorganic layer and a pixel electrode, the inorganic layer covering the first metal layer and the second metal layer And an eighth through hole corresponding to the source; the organic layer covers the inorganic layer, and a third through hole is opened corresponding to the eighth through hole; the pixel electrode covers the organic layer, and passes through The eighth through hole and the third through hole are electrically connected to the source.
  • the inorganic layer further defines a ninth through hole corresponding to the isolation groove, and the ninth through hole communicates with the isolation groove.
  • the array substrate further includes a buffer layer covering the substrate, the signal transmission line and the The gate is disposed on the buffer layer.
  • the buffer layer corresponds to The isolation groove defines a groove, and the groove communicates with the isolation groove, and the height of the groove is less than or equal to a thickness of the buffer layer.
  • the isolation trench is parallel to a warp axis of the array substrate.
  • the array substrate of the present invention can provide an isolation trench on the insulating layer, and the isolation trench can release the internal stress in the insulating layer, thereby preventing the brittle insulating layer from being broken by the internal stress and reducing the thin film transistor.
  • the deformation of the layer structure of the flexible substrate and the insulating layer improves the flexibility of the array substrate.
  • the insulating layer of the array substrate may further include an organic layer filling the isolation trench, the structure of the array substrate may be planarized, and the flexibility of the array substrate may be improved; the array substrate may further include an inorganic layer covering the active layer, and Protecting the active layer from contact with the plasma during plasma etching to form the via hole and the isolation trench; the array substrate may further include a protective layer that blocks oxygen in the external air to prevent The first metal layer and the second metal layer are oxidized and serve to support the structure of the array substrate.
  • the present invention also provides a method of fabricating an array substrate, the method comprising:
  • An organic layer in the via hole is removed, and a first metal layer is deposited in the via hole to conduct the signal transmission line.
  • the covering the organic layer on the insulating layer further includes:
  • the removing the organic layer in the via hole and depositing the first metal layer in the via hole to turn on the signal transmission line further includes:
  • Removing a portion of the organic layer on the active layer to expose the active layer, the organic layer and the A second metal layer is deposited on the active layer to form a source and a drain.
  • the method further includes:
  • the etching the insulating layer to form an isolation trench and etching the insulating layer to form a via hole to expose a portion of the data line further comprises: etching the inorganic layer;
  • the removing a portion of the organic layer on the active layer to expose the active layer further includes removing a portion of the inorganic layer on the active layer.
  • the method further includes:
  • a conductive layer is deposited on the protective layer, the source, and the drain to form a pixel electrode, and the drain is electrically connected to the pixel electrode.
  • the method further includes:
  • a conductive layer is deposited on the organic layer to form a pixel electrode, and the source or drain is electrically connected to the pixel electrode.
  • the method further includes:
  • the removing the organic layer in the via hole and depositing the first metal layer in the via hole to turn on the signal transmission line further includes: depositing a second on the organic layer and the active layer The metal layer forms a source and a drain.
  • the method further includes:
  • a conductive layer is deposited on the source and the protective layer to form a pixel electrode, and the source is electrically connected to the pixel electrode.
  • the forming the signal transmission line and the gate on the substrate includes:
  • a buffer layer is deposited on the substrate, and the signal transmission line and the gate are formed on the buffer layer.
  • the etching the insulating layer to form the isolation trench further includes: partially etching the buffer layer corresponding to the isolation trench.
  • the method for fabricating an array substrate comprises forming a signal transmission line and a gate on a substrate, a gap is provided between the signal transmission line and the gate; and the signal transmission line and the gate are Forming an insulating layer on the electrode; forming an active layer on the insulating layer, etching the insulating layer to form an isolation trench, and etching the insulating layer to form a via hole to expose the signal transmission line; covering the insulating layer with an organic layer Wherein the organic layer fills the isolation trench and the via, and removes an organic layer in the via, and deposits a first metal layer in the via to turn on the signal transmission line.
  • the isolation trench and the via hole for connecting the signal transmission line may be formed by a single mask and an etching process, simplifying the process steps of the array substrate, and forming the isolation trench to release internal stress in the insulating layer, thereby preventing brittleness.
  • the insulating layer is broken by the internal stress, and the deformation of the layer structure of the flexible substrate and the insulating layer in the thin film transistor is reduced, and the flexibility of the array substrate is improved.
  • the organic layer may further planarize the structure of the array substrate; and the inorganic layer covering the active layer may protect the through hole and the isolation trench during plasma etching
  • the active layer prevents the active layer from contacting the plasma and improves the electrical performance of the array substrate;
  • the array substrate may further include an organic layer to block oxygen in the environment, prevent oxidation of each electrode inside the array substrate, and may serve as a support. Stabilizing the structure of the array substrate.
  • FIG. 1 is a cross-sectional structural view of an array substrate in a first state according to a preferred embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view of an array substrate in a second state according to a preferred embodiment of the present invention
  • FIG. 3 is a cross-sectional structural view of an array substrate in a third state according to a preferred embodiment of the present invention.
  • FIG. 4 is a cross-sectional structural view of an array substrate in a fourth state according to a preferred embodiment of the present invention.
  • FIG. 5 is a cross-sectional structural view of an array substrate in a fifth state according to a preferred embodiment of the present invention.
  • FIG. 6 is a cross-sectional structural view of an array substrate in a sixth state according to a preferred embodiment of the present invention.
  • FIG. 7 is a cross-sectional structural view of an array substrate in a seventh state according to a preferred embodiment of the present invention.
  • FIG. 8 is a cross-sectional structural view of an array substrate in an eighth state according to a preferred embodiment of the present invention.
  • FIG. 9 is a cross-sectional structural view of an array substrate in a ninth state according to a preferred embodiment of the present invention.
  • FIG. 10 is a cross-sectional structural view of an array substrate in a tenth state according to a preferred embodiment of the present invention.
  • FIG. 11 is a schematic structural view showing the distribution of isolation trenches in an array substrate according to a preferred embodiment of the present invention.
  • FIG. 12 is a flow chart showing a method of fabricating an array substrate according to a first preferred embodiment of the present invention
  • FIGS. 13A to 13G are schematic views showing respective preparation steps in a method for preparing an array substrate according to a first preferred embodiment of the present invention
  • FIG. 14 is a flow chart showing a method of fabricating an array substrate according to a second preferred embodiment of the present invention.
  • 15A to 15H are schematic views showing respective preparation steps in a method for preparing an array substrate according to a second preferred embodiment of the present invention.
  • 16 is a flow chart showing a method of fabricating an array substrate according to a third preferred embodiment of the present invention.
  • 17A to 17H are schematic views showing respective preparation steps in a method of fabricating an array substrate according to a third preferred embodiment of the present invention.
  • FIG. 1 is a cross-sectional structural view of an array substrate in a first state according to a preferred embodiment of the present invention.
  • the array substrate includes:
  • a substrate 110 a signal transmission line 120 and a gate 130 disposed on the substrate 110, an insulating layer 140 covering the signal transmission line 120 and the gate 130, an active layer 150 disposed on the insulating layer 140, and a first metal layer 160, wherein a gap is formed between the gate 130 and the signal transmission line 120; an isolation trench 1401 and a via hole 1402 are defined in the insulating layer 140, and the first metal layer 160 passes through the The via hole 1402 is electrically connected to the signal transmission line 120, and the isolation trench 1401 is disposed between the signal transmission line 120 and the gate 130.
  • the array substrate of the present invention provides an isolation trench 1401 on the insulating layer 140, and the isolation trench 1401 can release internal stress in the insulating layer 140, thereby preventing the brittle insulating layer 140 from being under the action of internal stress.
  • the rupture reduces the deformation of the layer structure of the flexible substrate 110 and the insulating layer 140 in the thin film transistor, and improves the flexibility of the array substrate.
  • FIG. 2 is a cross-sectional structural diagram of an array substrate in a second state according to a preferred embodiment of the present invention.
  • the array substrate further includes an organic layer 170 disposed on the insulating layer 140 and filling the isolation trench 1401.
  • the isolation trench 1401 is filled with a flexible insulating material, which may be a polymer material, the flexible insulating material does not affect the flexibility of the array substrate, and may serve as a support;
  • the organic layer 170 can planarize the structure of the array substrate, so that the arrangement of the isolation trenches does not bring about an increase in the step structure in the array substrate structure, and the organic layer 170 can make the structure of the entire array substrate more stable and improve the bending flexibility of the array substrate. .
  • FIG. 3 is a cross-sectional structural view of the array substrate in a third state according to a preferred embodiment of the present invention.
  • the array substrate further includes a second metal layer, and the second metal layer is electrically connected to both ends of the active layer 150 to form a source 1601 and a drain 1602.
  • the first metal layer 160 and the second metal layer are integrated structures to reduce the arrangement of the outer pins in the array substrate.
  • the array substrate further includes an inorganic layer 180.
  • FIG. 4 is a cross-sectional structural view of the array substrate in a fourth state according to a preferred embodiment of the present invention.
  • the inorganic layer 180 covers the active layer 150 and the insulating layer 140; the inorganic layer 180 is provided with a first through hole, a second through hole, a third through hole and a fourth through hole; a through hole communicating with the through hole 1402 for conducting the signal transmission line 120 and the first metal layer 160; the second through hole communicating with the isolation groove 1401; the third through hole and the The fourth through holes are respectively disposed corresponding to both ends of the active layer 150 for conducting the active layer 150 and the source 1601 and the drain 1602.
  • the organic layer 170 covers the inorganic layer 180; the organic layer 170 defines a fifth through hole, a sixth through hole, and a seventh through hole, wherein the fifth through hole corresponds to the first a through hole is disposed in communication with the first through hole for conducting the signal transmission line 120 and the first metal layer 160; the sixth through hole is disposed corresponding to the third through hole and is opposite to the first through hole
  • the three through holes are connected to the fourth through holes and are in communication with the fourth through holes; the sixth through holes and the seventh through holes are used to conduct the active Layer 150 is coupled to source 1601 and drain 1602.
  • the material of the inorganic layer 180 may be that when the through hole 1402 and the isolation trench 1401 are formed by plasma etching, the active layer 150 is protected from contacting the active layer 150 with the plasma.
  • FIG. 5 is a cross-sectional structural view of the array substrate in a fifth state according to a preferred embodiment of the present invention.
  • the surface of the organic layer 170 facing away from the substrate 110 is flush with the end surface of the insulating layer 140 facing away from the substrate 110.
  • the array substrate further includes a protective layer 190 and a pixel electrode.
  • FIG. 6 is a cross-sectional structural view of the array substrate in a sixth state according to a preferred embodiment of the present invention.
  • FIG. 7 is a cross-sectional structural view of an array substrate in a seventh state according to a preferred embodiment of the present invention.
  • the protective layer 190 covers the first metal layer 160 and the second metal layer, and defines a second via hole 1402; the second via hole 1402 is disposed corresponding to the source 1601;
  • the protective layer 190 is electrically connected to the source 1601 through the second via 1402.
  • the protective layer 190 may be a material of the organic insulating layer 140, such as a resin or a polymer material, and the pixel electrode 200 is a transparent conductive film such as an indium tin oxide film (ITO film).
  • ITO film indium tin oxide film
  • FIG. 8 is a cross-sectional structural view of the array substrate in an eighth state according to a preferred embodiment of the present invention.
  • the array substrate further includes an inorganic layer 180 and a pixel electrode, the inorganic layer 180 covers the first metal layer 160 and the second metal layer, and an eighth is opened corresponding to the source 1601. a through hole; the organic layer 170 covers the inorganic layer 180, and a third through hole 1402 is defined corresponding to the eighth through hole; the pixel electrode covers the organic layer 170, and passes through the eighth through hole And the third via hole 1402 is electrically connected to the source 1601.
  • the material of the inorganic layer 180 in the embodiment may be an inorganic insulating material, such as any one or more of materials such as HfO 2 , ZrO 2 , Al 2 O 3 , SiO 2 , Si 3 N 4 , and the like. Each electrode covered by the inorganic layer 180 can be protected.
  • FIG. 9 is a cross-sectional structural view of the array substrate in a ninth state according to a preferred embodiment of the present invention.
  • the inorganic layer 180 further defines a ninth through hole corresponding to the isolation trench 1401.
  • the ninth through hole is in communication with the isolation groove 1401.
  • the array substrate further includes a buffer layer 210 covering the substrate 110 , and the signal transmission line 120 and the gate 130 are disposed on the buffer layer 210 .
  • FIG. 10 is a cross-sectional structural view of the array substrate in a tenth state according to a preferred embodiment of the present invention.
  • the buffer layer 210 defines a recess corresponding to the isolation trench 1401, and the recess communicates with the isolation trench 1401, and the height of the recess is less than or equal to the thickness of the buffer layer 210.
  • the isolation trench 1401 is parallel to the winding axis of the array substrate. Thereby, the flexibility of the array substrate is improved, so that the array substrate can obtain greater curvature.
  • the isolation trench can be a rectangular parallelepiped structure, a trapezoidal structure, a semi-cylindrical structure, etc., and the isolation trenches can be located in each pixel unit in the array substrate, or can be distributed in some pixel units according to a preset pattern.
  • the isolation trench is parallel to the winding axis of the array substrate.
  • FIG. 11 is a schematic structural view showing the distribution of the isolation trenches in the array substrate according to a preferred embodiment of the present invention, and FIG. 11 is a surface of the deposited thin film from the array substrate. Schematic diagram of the distribution of the isolation trenches in the array substrate when viewed from above. As shown in FIG.
  • the array substrate may include a plurality of pixel units, such as a first pixel unit 1101, a second pixel unit 1102, a third pixel unit 1103, and a fourth.
  • a pixel unit 1104 or the like each of the pixel units includes a thin film transistor that controls a switching state of the pixel unit, and each of the thin film transistors in the array substrate can
  • the structure of the array substrate is as shown in FIG. 1-10.
  • the isolation trench 1105 can be a rectangular parallelepiped structure.
  • the curling axis of the array substrate is parallel to the long side of the isolation trench 1105.
  • the isolation trench 1105 can also be disposed on the edge of the array substrate.
  • the intermediate isolation grooves 1105 of the respective pixel units in the winding axis direction may be connected or may be spaced apart.
  • the substrate 110 may be a glass substrate or a flexible substrate prepared from a polymer material;
  • the signal transmission line 120 may be a data line or a voltage line; in the present invention, the signal transmission line 120 and the gate 130
  • the material includes any one or more of materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni, Mo, Al, ITO, etc.;
  • the material of the insulating layer 140 may be HfO 2 , Any one or more of materials such as ZrO 2 , Al 2 O 3 , SiO 2 , Si 3 N 4 , etc.;
  • the active layer 150 includes a channel layer, a first doped region, and a second doped region.
  • the first doped region and the second doped region are both in contact with the channel layer, and the first doped region and the second doped region are spaced apart.
  • the material of the first metal layer 160 or the second metal layer may include any one or more of materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni, Mo, Al, ITO, and the like.
  • the first electrode 150 may be electrically connected to the second electrode 160 or the third electrode 170 through an outer lead, and the first metal layer 160 and the second metal layer may also be a unitary structure.
  • the array substrate of the present invention provides an isolation trench 1401 on the insulating layer 140, and the isolation trench 1401 can release internal stress in the insulating layer 140, thereby preventing the brittle insulating layer 140 from being under the action of internal stress.
  • the rupture reduces deformation of the layer structure of the substrate 110, the insulating layer 140, and the like in the thin film transistor, and improves the flexibility of the array substrate.
  • the insulating layer 140 of the array substrate may further include an organic layer 150 filling the isolation trenches, which can planarize the structure of the array substrate and improve the flexibility of the array substrate; the array substrate may further include an inorganic layer covering the active layer 150.
  • the layer 180 may protect the active layer 150 from contact with the plasma when the via hole 1402 and the isolation trench 1401 are formed by plasma etching; the array substrate may further include a protective layer 190, the protective layer The 190 can block oxygen in the external air, prevent oxidation of the first metal layer 160 and the second metal layer, and can serve as a support to stabilize the structure of the array substrate.
  • FIG. 12 is a flowchart of a method for fabricating an array substrate according to a first preferred embodiment of the present invention.
  • the method for preparing the array substrate includes:
  • Step S1210 Forming a signal transmission line 120 and a gate 130 on the substrate 110, and a gap is provided between the signal transmission line 120 and the gate 130. See Figure 13A.
  • a metal layer such as a gold (Au) layer may be deposited on the substrate 110 by a physical vapor deposition method, and the metal layer is patterned by a photomask and an etching process to form a signal transmission line 120 and a gate electrode 130.
  • Au gold
  • the method further includes: forming a buffer layer 210, the buffer layer 210 is disposed on the first surface of the substrate 110, and the signal transmission line 120 is disposed on the buffer layer
  • the surface of the substrate 110 is away from the surface of the substrate 110; the gate electrode 130 is disposed on a surface of the buffer layer 210 facing away from the substrate 110.
  • the buffer layer 210 may be an inorganic insulating material or a polymer insulating material.
  • the method of forming the buffer layer 210 may be a method such as chemical vapor deposition or physical vapor deposition.
  • the material of the signal transmission line 120 and the gate electrode 130 may be any one or more of materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni, Mo, Al, ITO, and the like. .
  • Step S1220 forming an insulating layer 140 on the signal transmission line 120 and the gate 130.
  • an insulating layer 140 may be deposited on the signal transmission line 120 and the gate 130 by a physical vapor deposition method.
  • the material of the insulating layer 140 may be HfO 2 , ZrO 2 , Al. Any one or more of 2 O 3 , SiO 2 , Si 3 N 4 and the like.
  • Step S1230 forming an active layer 150 on the insulating layer 140. See Figure 13C.
  • the active layer 150 is a semiconductor material, and the active layer 150 includes a channel layer, a first doped region, and a second doped region, and the first doped region and the second doped region are both Contacting the channel layer, and the first doped region is spaced apart from the second doped region.
  • the preparation technique of the active layer 150 is prior art, and the present invention is not described herein.
  • Step S1240 etching the insulating layer 140 to form the isolation trench 1401 and etching the insulating layer 140 to form a via hole 1402 to expose the signal transmission line 120.
  • the insulating layer 140 may be patterned by a photomask and an etching process to form isolation trenches 1401 and vias 1402.
  • a photoresist layer is coated on the surface of the insulating layer 140 facing away from the substrate; the photoresist layer is patterned, and a portion of the photoresist layer covering the insulating layer 140 is removed;
  • the photoresist layer is plasma etched by the photoresist layer as a mask to form the isolation trench 1401 and the via hole 1402 as shown in FIG. 13D.
  • the remaining photoresist layer is stripped.
  • the remaining photoresist layer may be peeled off with an organic solvent such as acetone.
  • Step S1250 covering the insulating layer 140 with the organic layer 170, wherein the organic layer 170 fills the isolation trench 1401 and the via hole 1402, see FIG. 13E.
  • the insulating layer 140 may be covered with an organic layer 170 by physical vapor deposition, chemical vapor deposition, or spin coating.
  • the organic layer 170 may be made of a polymer material.
  • Step S1260 removing the organic layer 170 in the via hole 1402.
  • a first metal layer 160 is deposited in the via hole 1402 to turn on the signal transmission line 120. See the array shown in FIG. 13G. Substrate.
  • the organic layer 170 may be wet etched by a photomask and an etching process to remove the organic layer 170 in the via hole 1402; when the organic layer 170 is a photosensitive organic material, the organic layer 170 may also be masked. Partial exposure removes the organic layer 170 in the via 1402 to form a patterned organic layer 170.
  • the first metal layer 160 is deposited in the via hole 1402 to conduct the signal transmission line 120 by physical vapor deposition.
  • step S1260 may further include: removing a portion of the organic layer 170 on the active layer 150 to expose the active layer 150, depositing a layer on the organic layer 170 and the active layer 150.
  • the two metal layers form a source 1601 and a drain 1602. See the array substrate shown in FIG.
  • the organic layer 170 on the active layer 150 may be wet etched by a mask and an etching process to remove a portion of the organic layer 170 to expose the active layer 150; when the organic layer 170 is a photosensitive organic material, The organic layer 170 may also be partially exposed by a photomask to remove the organic layer 170 in the via 1402 to expose the active layer 150 to form a patterned organic layer 170.
  • both ends of the active layer 150 are etched or exposed, and the first doped region and the second doped region of the active layer 150 are leaked out.
  • a second metal layer may be formed on a surface of the active layer 150 or a surface of the organic layer 170, and then the second metal layer is patterned by a photomask and an etching process to form a source 1601 and a drain 1602. . See the array substrate described in FIG.
  • the first metal layer 160 and the second metal layer may be integrally formed, wherein the first metal layer 160 may turn on the source 1601. See the array substrate described in FIG. Specifically, a first metal layer 160 may be deposited in the via hole 1402, and the first metal layer 160 is patterned to form the source 1601 and The drain 1602, wherein the source 1601 turns on the signal transmission line 120.
  • the method of manufacturing the array substrate may further include: forming an inorganic layer 180 on the active layer 150 and the insulating layer 140; step S1240 further includes: etching The inorganic layer 180 causes the via hole 1402 to penetrate the inorganic layer 180.
  • Step S1260 further includes: removing a portion of the inorganic layer 180 on the active layer 150 to expose the first doped region and the second doped region of the active layer 150, as shown in FIG. 4 The array substrate shown.
  • the inorganic layer 180 may be any one or more of materials such as HfO 2 , ZrO 2 , Al 2 O 3 , SiO 2 , and Si 3 N 4 .
  • the method for manufacturing the array substrate may further include: forming a protective layer 190 on the first metal layer 160 and the second metal layer; patterning the protective layer 190 to form a via hole The drain 1602 is exposed; a conductive layer 200 is deposited on the protective layer 190, the source 1601, and the drain 1602 to form a pixel electrode, and the drain 1602 is electrically connected to the pixel electrode. See the array substrate shown in Figure 6 or Figure 8.
  • the protective layer 190 may be a material such as a polymer or a rubber.
  • the protective layer 190 can be patterned using a mask and a wet etch process to form vias to expose the drain 1602.
  • a conductive layer 200 may be deposited on the protective layer 190, the source 1601, and the drain 1602 by physical vapor deposition to form a pixel electrode, and the drain 1602 is electrically connected to the pixel electrode, wherein
  • the conductive layer 200 is a transparent conductive film such as tin-doped indium trioxide (ITO), aluminum-doped zinc oxide (AZO), or the like.
  • the etching in the present invention may include dry etching and wet etching, and the dry etching gas may be CF4, SF6 or a mixed gas of CL2 and O2, and the wet etching liquid may be oxalic acid or sulfuric acid. , hydrochloric acid, or a mixture of oxalic acid, sulfuric acid and hydrochloric acid.
  • the patterning refers to a patterning process, which may include a photolithography process, or may include a photolithography process and an etching step, and may also include printing, inkjet, and the like for forming a predetermined pattern.
  • the lithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • the display device formed by the method for manufacturing the array substrate of the embodiment of the invention may be: a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED panel, an OLED television, an electronic paper, a digital photo frame, Mobile phones, etc.
  • the method for fabricating the array substrate forms a signal transmission line 120 and a gate 130 on the substrate 110, and a gap is provided between the signal transmission line 120 and the gate 130;
  • An insulating layer 140 is formed on the transmission line 120 and the gate 130;
  • an active layer 150 is formed on the insulating layer 140, the insulating layer 140 is etched to form an isolation trench 1401, and the insulating layer 140 is etched to form a via hole 1402 to be exposed.
  • the signal transmission line 120 covering the insulating layer 140 with an organic layer 170, wherein the organic layer 170 fills the isolation trench 1401 and the via hole 1402, and removes the organic layer 170 in the via hole 1402, and A first metal layer 160 is deposited in the via hole 1402 to conduct the signal transmission line 120.
  • the isolation trench 1401 and the via hole 1402 for connecting the signal transmission line 120 may be formed by a single mask and an etching process, simplifying the process steps of the array substrate, and the formed isolation trench 1401 can release the internal stress in the insulating layer 140. Therefore, the brittle insulating layer 140 is prevented from being broken by the internal stress, and the deformation of the layer structure of the flexible substrate 110, the insulating layer 140, and the like in the thin film transistor is reduced, and the flexibility of the array substrate is improved.
  • the organic layer 170 may also planarize the structure of the array substrate; the inorganic layer 180 covering the active layer 150 may form the via hole 1402 and the isolation trench 1401 by plasma etching.
  • the active layer 150 is protected from contact with the plasma to improve the electrical performance of the array substrate.
  • the array substrate may further include an organic layer 170 to block oxygen in the environment and prevent internal electrodes of the array substrate. Oxidized and supported to stabilize the structure of the array substrate.
  • FIG. 14 is a flowchart of a method for fabricating an array substrate according to a second preferred embodiment of the present invention.
  • the method for fabricating the array substrate includes:
  • step S1410 a signal transmission line 120 and a gate 130 are formed on the substrate 110, and a gap is provided between the signal transmission line 120 and the gate 130. Please refer to FIG. 15A.
  • Step S1420 forming an insulating layer 140 on the signal transmission line 120 and the gate 130. Please refer to FIG. 15B.
  • Step S1430 forming an active layer 150 on the insulating layer 140. Please refer to FIG. 15C.
  • Step S1440 etching the insulating layer 140 to form the isolation trench 1401 and etching the insulating layer 140 to form the via hole 1402 to expose the signal transmission line 120. Please refer to FIG. 15D.
  • Step S1450 depositing a first metal layer 160 in the via hole 1402 to turn on the signal transmission line 120, and depositing a second metal layer on the active layer 150, and patterning the second metal layer to form Source 1601 and drain 1602. Please refer to Figure 15E.
  • Step S1460 covering the first metal layer 160 and the second metal layer insulating layer 140 with an organic layer 170, wherein the organic layer 170 fills the isolation trench 1401, please refer to FIG. 15F.
  • the method may further include: etching the organic layer 170 to expose the source 1601, see FIG. 15G; depositing a conductive layer on the source 1601 and the organic layer 170 200, forming a pixel electrode, the source 1601 or the drain 1602 being electrically connected to the pixel electrode, please refer to FIG. 15H.
  • the method further includes: covering the first metal layer 160 and the second metal layer with the inorganic layer 180. Please refer to Figure 9.
  • the method for fabricating the array substrate forms an insulating layer 140 on the signal transmission line 120 and the gate 130 by forming spaced-apart signal transmission lines 120 and a gate 130 on the substrate 110.
  • the active layer 150 is formed by etching the insulating layer 140 to form the isolation trench 1401 and etching the insulating layer 140 to form a via hole 1402 to expose the signal transmission line 120.
  • the isolation trench 1401 and the via hole 1402 for connecting the signal transmission line 120 may be formed together by a mask and an etching process, simplifying the process steps of the array substrate, and the formed isolation trench 1401 may release the insulating layer 140.
  • the internal stress thereby preventing the brittle insulating layer 140 from being broken by the internal stress, reduces the deformation of the layer structure of the substrate 110, the insulating layer 140, and the like in the thin film transistor, and improves the flexibility of the array substrate.
  • the method for fabricating the array substrate provided by the present invention may include covering the first metal layer 160 and the inorganic layer 180 of the second metal to prevent oxidation of the metal.
  • FIG. 16 is a method for preparing an array substrate according to a third preferred embodiment of the present invention.
  • the preparation method of the array substrate described with reference to FIGS. 17A to 17H including:
  • Step S1610 Forming a signal transmission line 120 and a gate 130 on the substrate 110, and a gap is provided between the signal transmission line 120 and the gate 130. Please refer to FIG. 17A.
  • Step S1620 forming an insulating layer 140 on the signal transmission line 120 and the gate 130, please refer to FIG. 17B.
  • Step S1630 etching the insulating layer 140 to form the isolation trench 1401 and etching the insulating layer 140 to form the via hole 1402 to expose the signal transmission line 120. Please refer to FIG. 17C.
  • Step S1640 covering the insulating layer 140 with the organic layer 170, wherein the organic layer 170 fills the isolation trench 1401 and the via hole 1402, please refer to FIG. 17D.
  • Step S1650 removing the organic layer 170 on a portion of the insulating layer 140 to expose the insulating layer 140. Please refer to FIG. 17E.
  • Step S1660 forming an active layer 150 on the insulating layer 140; please refer to FIG. 17F.
  • Step S1670 removing the organic layer 170 in the via hole 1402, and depositing a first metal layer 160 in the via hole 1402 to turn on the signal transmission line 120.
  • the organic layer 170 in the via hole 1402 is removed to leak out the signal transmission line 120. Please refer to FIG. 17G.
  • a second metal layer is formed on the organic layer 170 and the active layer 150 to form a source 1601 and a drain 1602. Please refer to Figure 17H.
  • a protective layer 190 is formed on the first metal layer 160, the organic layer 170, and the second metal layer; the protective layer 190 is etched to expose the source 1601; The conductive layer 200 is deposited on the source electrode 1601 and the protective layer 190 to form a pixel electrode, and the source electrode 1601 is electrically connected to the pixel electrode.
  • a signal transmission line 120 and a gate electrode 130 are formed on the substrate 110, and an insulating layer 140 is formed on the signal transmission line 120 and the gate electrode 130.
  • the insulating layer 140 is etched to form the isolation trench 1401 and the insulating layer is etched.
  • the through hole 1402 is formed to expose the signal transmission line 120, and the organic layer 170 is covered on the insulating layer 140, wherein the organic layer 170 fills the isolation trench 1401 And the via hole 1402, removing the organic layer 170 on a part of the insulating layer 140 to expose the insulating layer 140, forming a planarized organic layer 170, which can serve as a support and form on the insulating layer 140.
  • the active layer 150 removes the organic layer 170 in the via hole 1402 and deposits a first metal layer 160 in the via hole 1402 to turn on the signal transmission line 120.
  • the isolation trench 1401 and the via hole 1402 can be simultaneously formed by a mask and an etching process, simplifying the process steps of the array substrate, and the formed isolation trench 1401 can release internal stress in the insulating layer 140, thereby preventing brittleness.
  • the insulating layer 140 is broken by the internal stress, and the deformation of the layer structure of the substrate 110, the insulating layer 140 of the gate electrode 130 in the thin film transistor is reduced, and the flexibility of the array substrate is improved.
  • the protective layer 190 can block oxygen in the environment, prevent oxidation of the respective electrodes inside the array substrate, and can serve as a support to stabilize the structure of the array substrate.

Landscapes

  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Liquid Crystal (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne un substrat de réseau et un procédé de fabrication d'un substrat de réseau. Le substrat de réseau comprend un substrat (110), une ligne de transmission de signal (120), une électrode de grille (130), une première couche isolante (140), une couche active (150), une première électrode (1601), une deuxième électrode (1602) et une troisième électrode (200). La première couche isolante (140) comprend une première partie isolante et une seconde partie isolante Une rainure d'isolation (1401) est disposée entre la première partie isolante recouvrant la ligne de transmission de signal (120) et la seconde partie isolante recouvrant l'électrode de grille (130). La rainure d'isolation (1401) peut libérer la contrainte interne dans la première couche isolante (140), empêchant ainsi la première couche isolante fragile (140) de se rompre facilement sous l'effet de la contrainte interne, et la réduction de la déformation de structures de couche telles qu'un substrat flexible (110) dans un transistor à couche mince et la première couche isolante (140), de façon à améliorer la flexibilité du substrat de réseau. La rainure d'isolation (1401) et un premier trou traversant (1402) pour connecter la première électrode (1601) et la ligne de transmission de signal (120) peuvent être formés ensemble au moyen d'un photo-masque et d'un processus de gravure une fois, ce qui simplifie les étapes de traitement du substrat de réseau et réduit les coûts de fabrication.
PCT/CN2016/091528 2016-07-25 2016-07-25 Substrat de réseau et procédé de production de substrat de réseau WO2018018353A1 (fr)

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JP2019503520A JP6752354B2 (ja) 2016-07-25 2016-07-25 アレイ基板及びアレイ基板の製造方法
PCT/CN2016/091528 WO2018018353A1 (fr) 2016-07-25 2016-07-25 Substrat de réseau et procédé de production de substrat de réseau
KR1020197003074A KR102221442B1 (ko) 2016-07-25 2016-07-25 어레이 기판 및 어레이 기판의 제조방법

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