WO2018018353A1 - Array substrate and manufacturing method for array substrate - Google Patents

Abstract

Disclosed are an array substrate and a manufacturing method for an array substrate. The array substrate comprises a substrate (110), a signal transmission line (120), a gate electrode (130), a first insulating layer (140), an active layer (150), a first electrode (1601), a second electrode (1602) and a third electrode (200). The first insulating layer (140) comprises a first insulating part and a second insulating part. An isolation groove (1401) is disposed between the first insulating part covering the signal transmission line (120) and the second insulating part covering the gate electrode (130). The isolation groove (1401) can release the internal stress in the first insulating layer (140), thereby preventing the brittle first insulating layer (140) from easily breaking under the effect of internal stress, and reducing the deformation of layer structures such as a flexible substrate (110) in a thin-film transistor and the first insulating layer (140), so as to improve the flexibility of the array substrate. The isolation groove (1401) and a first through hole (1402) for connecting the first electrode (1601) and the signal transmission line (120) can be formed together by means of a photomask and an etching process once, thereby simplifying the process steps of the array substrate and reducing the manufacturing costs.

Description

Array substrate and method for manufacturing array substrate Technical field

The present invention relates to the field of semiconductor technologies, and in particular, to an array substrate and a method of fabricating the array substrate.

Background technique

As a switching element, a thin film transistor (TFT) is widely used in electronic display devices such as liquid crystal display (LCD) and organic light-emitting diode (OLED). A thin film transistor generally includes a gate electrode, a gate insulating layer, an active layer, a source and a drain, etc., wherein a high quality gate insulating layer is an important parameter for realizing good electrical stability and small leakage current of the thin film transistor. key. The gate insulating layer is mainly prepared by a plasma chemical vapor deposition method using an inorganic non-metal material (for example, SiO _x , SiN _{x ,} etc.). Due to the characteristics of the gate insulating layer and the limitation of the preparation conditions, the gate insulating layer usually has internal stress, and the gate insulating layer prepared by brittle SiO _x , SiN _x or the like is easily broken by internal stress; in particular, In a flexible display, the presence of internal stress also causes deformation of a layer structure of a flexible substrate, a gate insulating layer, and the like in a thin film transistor.

Summary of the invention

In a first aspect, the present invention provides an array substrate, the array substrate comprising: a substrate, a signal transmission line and a gate disposed on the substrate, an insulating layer covering the signal transmission line and the gate, and An active layer on the insulating layer and a first metal layer, wherein a gap is formed between the gate and the signal transmission line; an isolation trench and a via hole are formed in the insulating layer, and the first metal layer The signal transmission line is electrically connected through the through hole, and the isolation groove is disposed between the signal transmission line and the gate.

In conjunction with the first aspect, in a first implementation of the first aspect, the array substrate further includes an organic layer disposed on the insulating layer and filling the isolation trench.

In conjunction with the first implementation of the first aspect, in the second implementation of the first aspect, the array substrate further includes a second metal layer, the second metal layer being electrically connected to both ends of the active layer to form a source Pole and drain.

In conjunction with the second implementation of the first aspect, in a third implementation of the first aspect, the first metal layer and the second metal layer are in a unitary structure.

With reference to the third implementation of the first aspect, in a fourth implementation of the first aspect, the array substrate further includes an inorganic layer, the inorganic layer covering the active layer and the insulating layer; a first through hole, a second through hole, a third through hole and a fourth through hole; the first through hole is in communication with the through hole for conducting the signal transmission line and the first metal layer; The second through hole is in communication with the isolation groove; the third through hole and the fourth through hole are respectively disposed corresponding to both ends of the active layer for conducting the active layer and the source a pole and the drain.

With reference to the fourth implementation of the first aspect, in a fifth implementation of the first aspect, the organic layer covers the inorganic layer; the organic layer defines a fifth through hole, a sixth through hole, and a seventh through hole, wherein The fifth through hole is disposed corresponding to the first through hole and communicates with the first through hole for conducting the signal transmission line and the first metal layer; the sixth through hole corresponds to the a third through hole is disposed and communicates with the third through hole; the seventh through hole is disposed corresponding to the fourth through hole and communicates with the fourth through hole; the sixth through hole and the seventh through hole A via hole is used to turn on the active layer and the source and the drain.

In conjunction with the second implementation of the first aspect, in the sixth implementation of the first aspect, the surface of the organic layer facing away from the substrate is flush with the end surface of the insulating layer facing away from the substrate.

With reference to the second to sixth implementations of the first aspect, in a seventh implementation of the first aspect, the array substrate further includes a protective layer and a pixel electrode, the protective layer covering the first metal layer and the second metal And forming a second via hole; the second via hole is disposed corresponding to the source; the pixel electrode covers the protective layer, and is electrically connected to the source through the second via hole.

With reference to the second implementation of the first aspect, in the eighth implementation of the first aspect, the array substrate further includes an inorganic layer and a pixel electrode, the inorganic layer covering the first metal layer and the second metal layer And an eighth through hole corresponding to the source; the organic layer covers the inorganic layer, and a third through hole is opened corresponding to the eighth through hole; the pixel electrode covers the organic layer, and passes through The eighth through hole and the third through hole are electrically connected to the source.

In conjunction with the first aspect, in the ninth implementation of the first aspect, the inorganic layer further defines a ninth through hole corresponding to the isolation groove, and the ninth through hole communicates with the isolation groove.

With reference to the first aspect, and the first to the nine implementations of the first aspect, in the tenth implementation of the first aspect, the array substrate further includes a buffer layer covering the substrate, the signal transmission line and the The gate is disposed on the buffer layer.

In conjunction with the tenth implementation of the first aspect, in the eleventh implementation of the first aspect, the buffer layer corresponds to The isolation groove defines a groove, and the groove communicates with the isolation groove, and the height of the groove is less than or equal to a thickness of the buffer layer.

In conjunction with the first aspect, in a twelfth implementation of the first aspect, the isolation trench is parallel to a warp axis of the array substrate.

Compared with the prior art, the array substrate of the present invention can provide an isolation trench on the insulating layer, and the isolation trench can release the internal stress in the insulating layer, thereby preventing the brittle insulating layer from being broken by the internal stress and reducing the thin film transistor. The deformation of the layer structure of the flexible substrate and the insulating layer improves the flexibility of the array substrate.

Moreover, the insulating layer of the array substrate may further include an organic layer filling the isolation trench, the structure of the array substrate may be planarized, and the flexibility of the array substrate may be improved; the array substrate may further include an inorganic layer covering the active layer, and Protecting the active layer from contact with the plasma during plasma etching to form the via hole and the isolation trench; the array substrate may further include a protective layer that blocks oxygen in the external air to prevent The first metal layer and the second metal layer are oxidized and serve to support the structure of the array substrate.

In a second aspect, the present invention also provides a method of fabricating an array substrate, the method comprising:

Forming a signal transmission line and a gate on the substrate, and providing a gap between the signal transmission line and the gate;

Forming an insulating layer on the signal transmission line and the gate;

Etching the insulating layer to form an isolation trench and etching the insulating layer to form a via hole to expose the signal transmission line;

Overlying the insulating layer with an organic layer, wherein the organic layer fills the isolation trench and the via;

An organic layer in the via hole is removed, and a first metal layer is deposited in the via hole to conduct the signal transmission line.

In conjunction with the second aspect, in a first implementation of the second aspect, the covering the organic layer on the insulating layer further includes:

Forming an active layer on the insulating layer;

The removing the organic layer in the via hole and depositing the first metal layer in the via hole to turn on the signal transmission line further includes:

Removing a portion of the organic layer on the active layer to expose the active layer, the organic layer and the A second metal layer is deposited on the active layer to form a source and a drain.

With reference to the first implementation of the second aspect, in a second implementation of the second aspect, the method further includes:

Forming an inorganic layer on the active layer and the insulating layer;

The etching the insulating layer to form an isolation trench and etching the insulating layer to form a via hole to expose a portion of the data line further comprises: etching the inorganic layer;

The removing a portion of the organic layer on the active layer to expose the active layer further includes removing a portion of the inorganic layer on the active layer.

With the second implementation of the second aspect, in a third implementation of the second aspect, the first metal layer turns on the source, the method further includes:

Forming a protective layer on the first metal layer and the second metal layer;

Patterning the protective layer to expose the drain;

A conductive layer is deposited on the protective layer, the source, and the drain to form a pixel electrode, and the drain is electrically connected to the pixel electrode.

With reference to the first implementation of the second aspect, in a fourth implementation of the second aspect, the method further includes:

Etching the organic layer to expose the source or drain;

A conductive layer is deposited on the organic layer to form a pixel electrode, and the source or drain is electrically connected to the pixel electrode.

With reference to the second aspect, in a fifth implementation of the second aspect, after the covering the organic layer on the insulating layer, the method further includes:

Removing the organic layer on a portion of the insulating layer to expose the insulating layer;

Forming an active layer on the insulating layer;

The removing the organic layer in the via hole and depositing the first metal layer in the via hole to turn on the signal transmission line further includes: depositing a second on the organic layer and the active layer The metal layer forms a source and a drain.

With reference to the fifth implementation of the second aspect, in a sixth implementation of the second aspect, the method further includes:

Forming a protective layer on the first metal layer, the organic layer, and the second metal layer;

Etching the protective layer to expose the source;

A conductive layer is deposited on the source and the protective layer to form a pixel electrode, and the source is electrically connected to the pixel electrode.

With reference to the second aspect, and the first to sixth implementations of the second aspect, in the seventh implementation of the second aspect, the forming the signal transmission line and the gate on the substrate includes:

A buffer layer is deposited on the substrate, and the signal transmission line and the gate are formed on the buffer layer.

With reference to the seventh implementation of the second aspect, in an eighth implementation of the second aspect, the etching the insulating layer to form the isolation trench further includes: partially etching the buffer layer corresponding to the isolation trench.

Compared with the prior art, the method for fabricating an array substrate provided by the present invention comprises forming a signal transmission line and a gate on a substrate, a gap is provided between the signal transmission line and the gate; and the signal transmission line and the gate are Forming an insulating layer on the electrode; forming an active layer on the insulating layer, etching the insulating layer to form an isolation trench, and etching the insulating layer to form a via hole to expose the signal transmission line; covering the insulating layer with an organic layer Wherein the organic layer fills the isolation trench and the via, and removes an organic layer in the via, and deposits a first metal layer in the via to turn on the signal transmission line. The isolation trench and the via hole for connecting the signal transmission line may be formed by a single mask and an etching process, simplifying the process steps of the array substrate, and forming the isolation trench to release internal stress in the insulating layer, thereby preventing brittleness. The insulating layer is broken by the internal stress, and the deformation of the layer structure of the flexible substrate and the insulating layer in the thin film transistor is reduced, and the flexibility of the array substrate is improved.

Moreover, in the method for fabricating the array substrate provided by the present invention, the organic layer may further planarize the structure of the array substrate; and the inorganic layer covering the active layer may protect the through hole and the isolation trench during plasma etching The active layer prevents the active layer from contacting the plasma and improves the electrical performance of the array substrate; the array substrate may further include an organic layer to block oxygen in the environment, prevent oxidation of each electrode inside the array substrate, and may serve as a support. Stabilizing the structure of the array substrate.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

1 is a cross-sectional structural view of an array substrate in a first state according to a preferred embodiment of the present invention;

2 is a schematic cross-sectional view of an array substrate in a second state according to a preferred embodiment of the present invention; Figure

3 is a cross-sectional structural view of an array substrate in a third state according to a preferred embodiment of the present invention;

4 is a cross-sectional structural view of an array substrate in a fourth state according to a preferred embodiment of the present invention;

5 is a cross-sectional structural view of an array substrate in a fifth state according to a preferred embodiment of the present invention;

6 is a cross-sectional structural view of an array substrate in a sixth state according to a preferred embodiment of the present invention;

7 is a cross-sectional structural view of an array substrate in a seventh state according to a preferred embodiment of the present invention;

8 is a cross-sectional structural view of an array substrate in an eighth state according to a preferred embodiment of the present invention;

9 is a cross-sectional structural view of an array substrate in a ninth state according to a preferred embodiment of the present invention;

10 is a cross-sectional structural view of an array substrate in a tenth state according to a preferred embodiment of the present invention;

11 is a schematic structural view showing the distribution of isolation trenches in an array substrate according to a preferred embodiment of the present invention;

12 is a flow chart showing a method of fabricating an array substrate according to a first preferred embodiment of the present invention;

13A to 13G are schematic views showing respective preparation steps in a method for preparing an array substrate according to a first preferred embodiment of the present invention;

14 is a flow chart showing a method of fabricating an array substrate according to a second preferred embodiment of the present invention;

15A to 15H are schematic views showing respective preparation steps in a method for preparing an array substrate according to a second preferred embodiment of the present invention;

16 is a flow chart showing a method of fabricating an array substrate according to a third preferred embodiment of the present invention.

17A to 17H are schematic views showing respective preparation steps in a method of fabricating an array substrate according to a third preferred embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

FIG. 1 is a cross-sectional structural view of an array substrate in a first state according to a preferred embodiment of the present invention. The array substrate includes:

a substrate 110, a signal transmission line 120 and a gate 130 disposed on the substrate 110, an insulating layer 140 covering the signal transmission line 120 and the gate 130, an active layer 150 disposed on the insulating layer 140, and a first metal layer 160, wherein a gap is formed between the gate 130 and the signal transmission line 120; an isolation trench 1401 and a via hole 1402 are defined in the insulating layer 140, and the first metal layer 160 passes through the The via hole 1402 is electrically connected to the signal transmission line 120, and the isolation trench 1401 is disposed between the signal transmission line 120 and the gate 130.

Compared with the prior art, the array substrate of the present invention provides an isolation trench 1401 on the insulating layer 140, and the isolation trench 1401 can release internal stress in the insulating layer 140, thereby preventing the brittle insulating layer 140 from being under the action of internal stress. The rupture reduces the deformation of the layer structure of the flexible substrate 110 and the insulating layer 140 in the thin film transistor, and improves the flexibility of the array substrate.

Referring to FIG. 2, FIG. 2 is a cross-sectional structural diagram of an array substrate in a second state according to a preferred embodiment of the present invention. In the embodiment of the present invention, the array substrate further includes an organic layer 170 disposed on the insulating layer 140 and filling the isolation trench 1401.

In the present embodiment, the isolation trench 1401 is filled with a flexible insulating material, which may be a polymer material, the flexible insulating material does not affect the flexibility of the array substrate, and may serve as a support; The organic layer 170 can planarize the structure of the array substrate, so that the arrangement of the isolation trenches does not bring about an increase in the step structure in the array substrate structure, and the organic layer 170 can make the structure of the entire array substrate more stable and improve the bending flexibility of the array substrate. .

Please refer to FIG. 3. FIG. 3 is a cross-sectional structural view of the array substrate in a third state according to a preferred embodiment of the present invention. In the embodiment of the present invention, the array substrate further includes a second metal layer, and the second metal layer is electrically connected to both ends of the active layer 150 to form a source 1601 and a drain 1602.

Optionally, the first metal layer 160 and the second metal layer are integrated structures to reduce the arrangement of the outer pins in the array substrate.

Optionally, the array substrate further includes an inorganic layer 180. Referring to FIG. 4, FIG. 4 is a cross-sectional structural view of the array substrate in a fourth state according to a preferred embodiment of the present invention. The inorganic layer 180 covers the active layer 150 and the insulating layer 140; the inorganic layer 180 is provided with a first through hole, a second through hole, a third through hole and a fourth through hole; a through hole communicating with the through hole 1402 for conducting the signal transmission line 120 and the first metal layer 160; the second through hole communicating with the isolation groove 1401; the third through hole and the The fourth through holes are respectively disposed corresponding to both ends of the active layer 150 for conducting the active layer 150 and the source 1601 and the drain 1602.

Optionally, the organic layer 170 covers the inorganic layer 180; the organic layer 170 defines a fifth through hole, a sixth through hole, and a seventh through hole, wherein the fifth through hole corresponds to the first a through hole is disposed in communication with the first through hole for conducting the signal transmission line 120 and the first metal layer 160; the sixth through hole is disposed corresponding to the third through hole and is opposite to the first through hole The three through holes are connected to the fourth through holes and are in communication with the fourth through holes; the sixth through holes and the seventh through holes are used to conduct the active Layer 150 is coupled to source 1601 and drain 1602.

The material of the inorganic layer 180 may be that when the through hole 1402 and the isolation trench 1401 are formed by plasma etching, the active layer 150 is protected from contacting the active layer 150 with the plasma.

Please refer to FIG. 5. FIG. 5 is a cross-sectional structural view of the array substrate in a fifth state according to a preferred embodiment of the present invention. The surface of the organic layer 170 facing away from the substrate 110 is flush with the end surface of the insulating layer 140 facing away from the substrate 110.

In this embodiment, the array substrate further includes a protective layer 190 and a pixel electrode. Please refer to FIG. 6 and FIG. 7. FIG. 6 is a cross-sectional structural view of the array substrate in a sixth state according to a preferred embodiment of the present invention. FIG. 7 is a cross-sectional structural view of an array substrate in a seventh state according to a preferred embodiment of the present invention. The protective layer 190 covers the first metal layer 160 and the second metal layer, and defines a second via hole 1402; the second via hole 1402 is disposed corresponding to the source 1601; The protective layer 190 is electrically connected to the source 1601 through the second via 1402.

It can be understood that, in the present invention, the protective layer 190 may be a material of the organic insulating layer 140, such as a resin or a polymer material, and the pixel electrode 200 is a transparent conductive film such as an indium tin oxide film (ITO film).

Please refer to FIG. 8. FIG. 8 is a cross-sectional structural view of the array substrate in an eighth state according to a preferred embodiment of the present invention. In the embodiment of the present invention, the array substrate further includes an inorganic layer 180 and a pixel electrode, the inorganic layer 180 covers the first metal layer 160 and the second metal layer, and an eighth is opened corresponding to the source 1601. a through hole; the organic layer 170 covers the inorganic layer 180, and a third through hole 1402 is defined corresponding to the eighth through hole; the pixel electrode covers the organic layer 170, and passes through the eighth through hole And the third via hole 1402 is electrically connected to the source 1601.

It can be understood that the material of the inorganic layer 180 in the embodiment may be an inorganic insulating material, such as any one or more of materials such as HfO ₂ , ZrO ₂ , Al ₂ O ₃ , SiO ₂ , Si ₃ N _{4 ,} and the like. Each electrode covered by the inorganic layer 180 can be protected.

Optionally, refer to FIG. 9. FIG. 9 is a cross-sectional structural view of the array substrate in a ninth state according to a preferred embodiment of the present invention. The inorganic layer 180 further defines a ninth through hole corresponding to the isolation trench 1401. The ninth through hole is in communication with the isolation groove 1401.

In the embodiment, the array substrate further includes a buffer layer 210 covering the substrate 110 , and the signal transmission line 120 and the gate 130 are disposed on the buffer layer 210 . Please refer to FIG. 10. FIG. 10 is a cross-sectional structural view of the array substrate in a tenth state according to a preferred embodiment of the present invention.

Optionally, the buffer layer 210 defines a recess corresponding to the isolation trench 1401, and the recess communicates with the isolation trench 1401, and the height of the recess is less than or equal to the thickness of the buffer layer 210.

In the embodiment, the isolation trench 1401 is parallel to the winding axis of the array substrate. Thereby, the flexibility of the array substrate is improved, so that the array substrate can obtain greater curvature.

It can be understood that the isolation trench can be a rectangular parallelepiped structure, a trapezoidal structure, a semi-cylindrical structure, etc., and the isolation trenches can be located in each pixel unit in the array substrate, or can be distributed in some pixel units according to a preset pattern. Preferably, the isolation trench is parallel to the winding axis of the array substrate. Please refer to FIG. 11. FIG. 11 is a schematic structural view showing the distribution of the isolation trenches in the array substrate according to a preferred embodiment of the present invention, and FIG. 11 is a surface of the deposited thin film from the array substrate. Schematic diagram of the distribution of the isolation trenches in the array substrate when viewed from above. As shown in FIG. 11, the array substrate may include a plurality of pixel units, such as a first pixel unit 1101, a second pixel unit 1102, a third pixel unit 1103, and a fourth. a pixel unit 1104 or the like, each of the pixel units includes a thin film transistor that controls a switching state of the pixel unit, and each of the thin film transistors in the array substrate can The structure of the array substrate is as shown in FIG. 1-10. The isolation trench 1105 can be a rectangular parallelepiped structure. The curling axis of the array substrate is parallel to the long side of the isolation trench 1105. The isolation trench 1105 can also be disposed on the edge of the array substrate. The intermediate isolation grooves 1105 of the respective pixel units in the winding axis direction may be connected or may be spaced apart.

It can be understood that, in the present invention, the substrate 110 may be a glass substrate or a flexible substrate prepared from a polymer material; the signal transmission line 120 may be a data line or a voltage line; in the present invention, the signal transmission line 120 and the gate 130 The material includes any one or more of materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni, Mo, Al, ITO, etc.; the material of the insulating layer 140 may be HfO ₂ , Any one or more of materials such as ZrO ₂ , Al ₂ O ₃ , SiO ₂ , Si ₃ N _{4 ,} etc.; the active layer 150 includes a channel layer, a first doped region, and a second doped region. The first doped region and the second doped region are both in contact with the channel layer, and the first doped region and the second doped region are spaced apart. The material of the first metal layer 160 or the second metal layer may include any one or more of materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni, Mo, Al, ITO, and the like. The first electrode 150 may be electrically connected to the second electrode 160 or the third electrode 170 through an outer lead, and the first metal layer 160 and the second metal layer may also be a unitary structure.

Compared with the prior art, the array substrate of the present invention provides an isolation trench 1401 on the insulating layer 140, and the isolation trench 1401 can release internal stress in the insulating layer 140, thereby preventing the brittle insulating layer 140 from being under the action of internal stress. The rupture reduces deformation of the layer structure of the substrate 110, the insulating layer 140, and the like in the thin film transistor, and improves the flexibility of the array substrate.

Moreover, the insulating layer 140 of the array substrate may further include an organic layer 150 filling the isolation trenches, which can planarize the structure of the array substrate and improve the flexibility of the array substrate; the array substrate may further include an inorganic layer covering the active layer 150. The layer 180 may protect the active layer 150 from contact with the plasma when the via hole 1402 and the isolation trench 1401 are formed by plasma etching; the array substrate may further include a protective layer 190, the protective layer The 190 can block oxygen in the external air, prevent oxidation of the first metal layer 160 and the second metal layer, and can serve as a support to stabilize the structure of the array substrate.

Referring to FIG. 12, FIG. 12 is a flowchart of a method for fabricating an array substrate according to a first preferred embodiment of the present invention. Referring to FIG. 13A to FIG. 13G, the method for preparing the array substrate includes:

Step S1210: Forming a signal transmission line 120 and a gate 130 on the substrate 110, and a gap is provided between the signal transmission line 120 and the gate 130. See Figure 13A.

Specifically, a metal layer such as a gold (Au) layer may be deposited on the substrate 110 by a physical vapor deposition method, and the metal layer is patterned by a photomask and an etching process to form a signal transmission line 120 and a gate electrode 130.

In this embodiment, after the step S120, the method further includes: forming a buffer layer 210, the buffer layer 210 is disposed on the first surface of the substrate 110, and the signal transmission line 120 is disposed on the buffer layer The surface of the substrate 110 is away from the surface of the substrate 110; the gate electrode 130 is disposed on a surface of the buffer layer 210 facing away from the substrate 110.

It can be understood that the buffer layer 210 may be an inorganic insulating material or a polymer insulating material. The method of forming the buffer layer 210 may be a method such as chemical vapor deposition or physical vapor deposition.

It can be understood that the material of the signal transmission line 120 and the gate electrode 130 may be any one or more of materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni, Mo, Al, ITO, and the like. .

Step S1220: forming an insulating layer 140 on the signal transmission line 120 and the gate 130.

Specifically, referring to FIG. 13B, an insulating layer 140 may be deposited on the signal transmission line 120 and the gate 130 by a physical vapor deposition method. The material of the insulating layer 140 may be HfO ₂ , ZrO ₂ , Al. Any one or more of ₂ O ₃ , SiO ₂ , Si ₃ N ₄ and the like.

Step S1230: forming an active layer 150 on the insulating layer 140. See Figure 13C.

Specifically, the active layer 150 is a semiconductor material, and the active layer 150 includes a channel layer, a first doped region, and a second doped region, and the first doped region and the second doped region are both Contacting the channel layer, and the first doped region is spaced apart from the second doped region. The preparation technique of the active layer 150 is prior art, and the present invention is not described herein.

Step S1240: etching the insulating layer 140 to form the isolation trench 1401 and etching the insulating layer 140 to form a via hole 1402 to expose the signal transmission line 120. Referring to FIG. 13D, in particular, the insulating layer 140 may be patterned by a photomask and an etching process to form isolation trenches 1401 and vias 1402.

Specifically, a photoresist layer is coated on the surface of the insulating layer 140 facing away from the substrate; the photoresist layer is patterned, and a portion of the photoresist layer covering the insulating layer 140 is removed; The photoresist layer is plasma etched by the photoresist layer as a mask to form the isolation trench 1401 and the via hole 1402 as shown in FIG. 13D. The remaining photoresist layer is stripped. In the present embodiment, the remaining photoresist layer may be peeled off with an organic solvent such as acetone.

Step S1250: covering the insulating layer 140 with the organic layer 170, wherein the organic layer 170 fills the isolation trench 1401 and the via hole 1402, see FIG. 13E.

Specifically, the insulating layer 140 may be covered with an organic layer 170 by physical vapor deposition, chemical vapor deposition, or spin coating. The organic layer 170 may be made of a polymer material.

Step S1260: removing the organic layer 170 in the via hole 1402. Referring to FIG. 13F, a first metal layer 160 is deposited in the via hole 1402 to turn on the signal transmission line 120. See the array shown in FIG. 13G. Substrate.

Specifically, the organic layer 170 may be wet etched by a photomask and an etching process to remove the organic layer 170 in the via hole 1402; when the organic layer 170 is a photosensitive organic material, the organic layer 170 may also be masked. Partial exposure removes the organic layer 170 in the via 1402 to form a patterned organic layer 170. The first metal layer 160 is deposited in the via hole 1402 to conduct the signal transmission line 120 by physical vapor deposition.

In this embodiment, step S1260 may further include: removing a portion of the organic layer 170 on the active layer 150 to expose the active layer 150, depositing a layer on the organic layer 170 and the active layer 150. The two metal layers form a source 1601 and a drain 1602. See the array substrate shown in FIG. Specifically, the organic layer 170 on the active layer 150 may be wet etched by a mask and an etching process to remove a portion of the organic layer 170 to expose the active layer 150; when the organic layer 170 is a photosensitive organic material, The organic layer 170 may also be partially exposed by a photomask to remove the organic layer 170 in the via 1402 to expose the active layer 150 to form a patterned organic layer 170. Preferably, both ends of the active layer 150 are etched or exposed, and the first doped region and the second doped region of the active layer 150 are leaked out.

Specifically, a second metal layer may be formed on a surface of the active layer 150 or a surface of the organic layer 170, and then the second metal layer is patterned by a photomask and an etching process to form a source 1601 and a drain 1602. . See the array substrate described in FIG.

The first metal layer 160 and the second metal layer may be integrally formed, wherein the first metal layer 160 may turn on the source 1601. See the array substrate described in FIG. Specifically, a first metal layer 160 may be deposited in the via hole 1402, and the first metal layer 160 is patterned to form the source 1601 and The drain 1602, wherein the source 1601 turns on the signal transmission line 120.

In this embodiment, after the step S1230 or the step S1240, the method of manufacturing the array substrate may further include: forming an inorganic layer 180 on the active layer 150 and the insulating layer 140; step S1240 further includes: etching The inorganic layer 180 causes the via hole 1402 to penetrate the inorganic layer 180. Step S1260 further includes: removing a portion of the inorganic layer 180 on the active layer 150 to expose the first doped region and the second doped region of the active layer 150, as shown in FIG. 4 The array substrate shown.

It should be noted that the inorganic layer 180 may be any one or more of materials such as HfO ₂ , ZrO ₂ , Al ₂ O ₃ , SiO ₂ , and Si ₃ N ₄ .

Optionally, after the step S1260, the method for manufacturing the array substrate may further include: forming a protective layer 190 on the first metal layer 160 and the second metal layer; patterning the protective layer 190 to form a via hole The drain 1602 is exposed; a conductive layer 200 is deposited on the protective layer 190, the source 1601, and the drain 1602 to form a pixel electrode, and the drain 1602 is electrically connected to the pixel electrode. See the array substrate shown in Figure 6 or Figure 8.

It should be noted that the protective layer 190 may be a material such as a polymer or a rubber. The protective layer 190 can be patterned using a mask and a wet etch process to form vias to expose the drain 1602. A conductive layer 200 may be deposited on the protective layer 190, the source 1601, and the drain 1602 by physical vapor deposition to form a pixel electrode, and the drain 1602 is electrically connected to the pixel electrode, wherein The conductive layer 200 is a transparent conductive film such as tin-doped indium trioxide (ITO), aluminum-doped zinc oxide (AZO), or the like.

It should be understood that the etching in the present invention may include dry etching and wet etching, and the dry etching gas may be CF4, SF6 or a mixed gas of CL2 and O2, and the wet etching liquid may be oxalic acid or sulfuric acid. , hydrochloric acid, or a mixture of oxalic acid, sulfuric acid and hydrochloric acid.

It should be understood that, in the present invention, the patterning refers to a patterning process, which may include a photolithography process, or may include a photolithography process and an etching step, and may also include printing, inkjet, and the like for forming a predetermined pattern. The lithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a film formation, exposure, development, and the like. The corresponding patterning process can be selected in accordance with the structure formed in the present invention.

The display device formed by the method for manufacturing the array substrate of the embodiment of the invention may be: a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED panel, an OLED television, an electronic paper, a digital photo frame, Mobile phones, etc.

Compared with the prior art, the method for fabricating the array substrate provided by the present invention forms a signal transmission line 120 and a gate 130 on the substrate 110, and a gap is provided between the signal transmission line 120 and the gate 130; An insulating layer 140 is formed on the transmission line 120 and the gate 130; an active layer 150 is formed on the insulating layer 140, the insulating layer 140 is etched to form an isolation trench 1401, and the insulating layer 140 is etched to form a via hole 1402 to be exposed. The signal transmission line 120; covering the insulating layer 140 with an organic layer 170, wherein the organic layer 170 fills the isolation trench 1401 and the via hole 1402, and removes the organic layer 170 in the via hole 1402, and A first metal layer 160 is deposited in the via hole 1402 to conduct the signal transmission line 120. The isolation trench 1401 and the via hole 1402 for connecting the signal transmission line 120 may be formed by a single mask and an etching process, simplifying the process steps of the array substrate, and the formed isolation trench 1401 can release the internal stress in the insulating layer 140. Therefore, the brittle insulating layer 140 is prevented from being broken by the internal stress, and the deformation of the layer structure of the flexible substrate 110, the insulating layer 140, and the like in the thin film transistor is reduced, and the flexibility of the array substrate is improved.

Moreover, in the method for fabricating the array substrate provided by the present invention, the organic layer 170 may also planarize the structure of the array substrate; the inorganic layer 180 covering the active layer 150 may form the via hole 1402 and the isolation trench 1401 by plasma etching. The active layer 150 is protected from contact with the plasma to improve the electrical performance of the array substrate. The array substrate may further include an organic layer 170 to block oxygen in the environment and prevent internal electrodes of the array substrate. Oxidized and supported to stabilize the structure of the array substrate.

Referring to FIG. 14, FIG. 14 is a flowchart of a method for fabricating an array substrate according to a second preferred embodiment of the present invention. Referring to FIG. 15A to FIG. 15H, the method for fabricating the array substrate includes:

In step S1410, a signal transmission line 120 and a gate 130 are formed on the substrate 110, and a gap is provided between the signal transmission line 120 and the gate 130. Please refer to FIG. 15A.

Step S1420: forming an insulating layer 140 on the signal transmission line 120 and the gate 130. Please refer to FIG. 15B.

Step S1430: forming an active layer 150 on the insulating layer 140. Please refer to FIG. 15C.

Step S1440: etching the insulating layer 140 to form the isolation trench 1401 and etching the insulating layer 140 to form the via hole 1402 to expose the signal transmission line 120. Please refer to FIG. 15D.

Step S1450: depositing a first metal layer 160 in the via hole 1402 to turn on the signal transmission line 120, and depositing a second metal layer on the active layer 150, and patterning the second metal layer to form Source 1601 and drain 1602. Please refer to Figure 15E.

Step S1460: covering the first metal layer 160 and the second metal layer insulating layer 140 with an organic layer 170, wherein the organic layer 170 fills the isolation trench 1401, please refer to FIG. 15F.

In this embodiment, after step S1460, the method may further include: etching the organic layer 170 to expose the source 1601, see FIG. 15G; depositing a conductive layer on the source 1601 and the organic layer 170 200, forming a pixel electrode, the source 1601 or the drain 1602 being electrically connected to the pixel electrode, please refer to FIG. 15H.

In this embodiment, after step S1450, the method further includes: covering the first metal layer 160 and the second metal layer with the inorganic layer 180. Please refer to Figure 9.

It can be understood that the preparation of each film layer in the manufacturing method of the array substrate described in FIG. 14 can refer to the manufacturing method of the array substrate described in FIG. 12, and the present invention is not described herein.

Compared with the prior art, the method for fabricating the array substrate provided by the present invention forms an insulating layer 140 on the signal transmission line 120 and the gate 130 by forming spaced-apart signal transmission lines 120 and a gate 130 on the substrate 110. The active layer 150 is formed by etching the insulating layer 140 to form the isolation trench 1401 and etching the insulating layer 140 to form a via hole 1402 to expose the signal transmission line 120. Depositing the first metal layer 160 in the via hole 1402 a signal transmission line 120, and depositing a second metal layer on the active layer 150, and patterning the second metal layer to form a source 1601 and a drain 1602, the first metal layer 160 and the The second metal layer insulating layer 140 is covered with an organic layer 170, wherein the organic layer 170 fills the isolation trench 1401. In the method, the isolation trench 1401 and the via hole 1402 for connecting the signal transmission line 120 may be formed together by a mask and an etching process, simplifying the process steps of the array substrate, and the formed isolation trench 1401 may release the insulating layer 140. The internal stress, thereby preventing the brittle insulating layer 140 from being broken by the internal stress, reduces the deformation of the layer structure of the substrate 110, the insulating layer 140, and the like in the thin film transistor, and improves the flexibility of the array substrate.

Moreover, the method for fabricating the array substrate provided by the present invention may include covering the first metal layer 160 and the inorganic layer 180 of the second metal to prevent oxidation of the metal.

Please refer to FIG. 16, which is a method for preparing an array substrate according to a third preferred embodiment of the present invention. For the flow chart, please refer to the preparation method of the array substrate described with reference to FIGS. 17A to 17H, including:

Step S1610: Forming a signal transmission line 120 and a gate 130 on the substrate 110, and a gap is provided between the signal transmission line 120 and the gate 130. Please refer to FIG. 17A.

Step S1620: forming an insulating layer 140 on the signal transmission line 120 and the gate 130, please refer to FIG. 17B.

Step S1630: etching the insulating layer 140 to form the isolation trench 1401 and etching the insulating layer 140 to form the via hole 1402 to expose the signal transmission line 120. Please refer to FIG. 17C.

Step S1640: covering the insulating layer 140 with the organic layer 170, wherein the organic layer 170 fills the isolation trench 1401 and the via hole 1402, please refer to FIG. 17D.

Step S1650: removing the organic layer 170 on a portion of the insulating layer 140 to expose the insulating layer 140. Please refer to FIG. 17E.

Step S1660: forming an active layer 150 on the insulating layer 140; please refer to FIG. 17F.

Step S1670: removing the organic layer 170 in the via hole 1402, and depositing a first metal layer 160 in the via hole 1402 to turn on the signal transmission line 120.

Specifically, the organic layer 170 in the via hole 1402 is removed to leak out the signal transmission line 120. Please refer to FIG. 17G.

In the present embodiment, a second metal layer is formed on the organic layer 170 and the active layer 150 to form a source 1601 and a drain 1602. Please refer to Figure 17H.

In this embodiment, a protective layer 190 is formed on the first metal layer 160, the organic layer 170, and the second metal layer; the protective layer 190 is etched to expose the source 1601; The conductive layer 200 is deposited on the source electrode 1601 and the protective layer 190 to form a pixel electrode, and the source electrode 1601 is electrically connected to the pixel electrode. Please refer to Figure 7.

It can be understood that the preparation of each film layer in the manufacturing method of the array substrate described in FIG. 16 can refer to the manufacturing method of the array substrate described in FIG. 12, and the present invention is not described herein.

Compared with the prior art, the method for manufacturing an array substrate of the present invention is passed

A signal transmission line 120 and a gate electrode 130 are formed on the substrate 110, and an insulating layer 140 is formed on the signal transmission line 120 and the gate electrode 130. The insulating layer 140 is etched to form the isolation trench 1401 and the insulating layer is etched. The through hole 1402 is formed to expose the signal transmission line 120, and the organic layer 170 is covered on the insulating layer 140, wherein the organic layer 170 fills the isolation trench 1401 And the via hole 1402, removing the organic layer 170 on a part of the insulating layer 140 to expose the insulating layer 140, forming a planarized organic layer 170, which can serve as a support and form on the insulating layer 140. The active layer 150 removes the organic layer 170 in the via hole 1402 and deposits a first metal layer 160 in the via hole 1402 to turn on the signal transmission line 120. The isolation trench 1401 and the via hole 1402 can be simultaneously formed by a mask and an etching process, simplifying the process steps of the array substrate, and the formed isolation trench 1401 can release internal stress in the insulating layer 140, thereby preventing brittleness. The insulating layer 140 is broken by the internal stress, and the deformation of the layer structure of the substrate 110, the insulating layer 140 of the gate electrode 130 in the thin film transistor is reduced, and the flexibility of the array substrate is improved.

Moreover, the protective layer 190 can block oxygen in the environment, prevent oxidation of the respective electrodes inside the array substrate, and can serve as a support to stabilize the structure of the array substrate.

The technical terms used in the embodiments of the present invention are only intended to illustrate specific embodiments and are not intended to limit the invention. In the present disclosure, the singular forms "a", "the" Further, the use of "including" and / or "comprising", in the specification, is used to mean the presence of the features, the whole, the steps, the operation, the elements and/or the components, but does not exclude the presence or addition of one or more Other features, integers, steps, operations, components and/or components.

The corresponding structures, materials, acts, and equivalents of the elements, and the equivalents of the functional elements, if any, are intended to include any structure, material, or action that is used to perform the function. The description of the present invention has been presented for purposes of illustration and description. Numerous modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The embodiments described in the present invention are able to better understand the principles and practical applications of the present invention, and may be understood by those of ordinary skill in the art.

The flowcharts described in the present invention are merely one embodiment, and various modifications may be made to the drawings or the steps of the present invention without departing from the spirit of the invention. For example, these steps can be performed in a different order, or some steps can be added, deleted, or modified. A person skilled in the art can understand that all or part of the process of implementing the above embodiments, and equivalent changes made according to the claims of the present invention, still fall within the scope of the invention.

Claims (22)

An array substrate, comprising: a substrate, a signal transmission line and a gate disposed on the substrate, an insulating layer covering the signal transmission line and the gate, and the insulating layer An upper active layer and a first metal layer, wherein a gap is formed between the gate and the signal transmission line; an isolation trench and a via hole are formed in the insulating layer, and the first metal layer passes through the through hole The hole is electrically connected to the signal transmission line, and the isolation groove is disposed between the signal transmission line and the gate. The array substrate according to claim 1, wherein the array substrate further comprises an organic layer disposed on the insulating layer and filling the isolation trench. The array substrate according to claim 2, wherein the array substrate further comprises a second metal layer, and the second metal layer is electrically connected to both ends of the active layer to form a source and a drain. The array substrate according to claim 3, wherein the first metal layer and the second metal layer are of a unitary structure. The array substrate according to claim 4, wherein the array substrate further comprises an inorganic layer covering the active layer and the insulating layer; the inorganic layer is provided with a first through hole, a second through hole, a third through hole and a fourth through hole; the first through hole is in communication with the through hole for conducting the signal transmission line and the first metal layer; the second through hole Communicating with the isolation trench; the third through hole and the fourth through hole are respectively disposed corresponding to opposite ends of the active layer, for conducting the active layer and the source and the drain pole. The array substrate according to claim 5, wherein the organic layer covers the inorganic layer; the organic layer defines a fifth through hole, a sixth through hole, and a seventh through hole, wherein the fifth layer a through hole corresponding to the first through hole and communicating with the first through hole for conducting the signal transmission line and the first metal layer; the sixth through hole corresponding to the third through hole setting And communicating with the third through hole; The seventh through hole is disposed corresponding to the fourth through hole and communicates with the fourth through hole; the sixth through hole and the seventh through hole are used for conducting the active layer and the source a pole and the drain. The array substrate according to claim 3, wherein the surface of the organic layer facing away from the substrate is flush with the end surface of the insulating layer facing away from the substrate. The array substrate according to any one of claims 3-7, wherein the array substrate further comprises a protective layer and a pixel electrode, the protective layer covering the first metal layer and the second metal layer And opening a second via hole; the second via hole is disposed corresponding to the source; the pixel electrode covers the protective layer, and is electrically connected to the source through the second via hole. The array substrate according to claim 3, wherein the array substrate further comprises an inorganic layer and a pixel electrode, the inorganic layer covering the first metal layer and the second metal layer, and corresponding to the The source layer has an eighth through hole; the organic layer covers the inorganic layer, and a third through hole is opened corresponding to the eighth through hole; the pixel electrode covers the organic layer, and passes through the eighth through The hole and the third via are electrically connected to the source. The array substrate according to claim 9, wherein the inorganic layer further defines a ninth through hole corresponding to the isolation groove, and the ninth through hole communicates with the isolation groove. The array substrate according to any one of claims 1 to 9, wherein the array substrate further comprises a buffer layer, the buffer layer covers the substrate, and the signal transmission line and the gate are disposed in the same On the buffer layer. The array substrate according to claim 11, wherein the buffer layer defines a groove corresponding to the isolation groove, and the groove is in communication with the isolation groove, and the height of the groove is less than or equal to the buffer. The thickness of the layer. The array substrate according to claim 1, wherein said isolation trench is parallel to said The curling axis of the array substrate. A method of fabricating an array substrate, characterized in that the method comprises Forming a signal transmission line and a gate on the substrate, and providing a gap between the signal transmission line and the gate; Forming an insulating layer on the signal transmission line and the gate; Etching the insulating layer to form an isolation trench and etching the insulating layer to form a via hole to expose the signal transmission line; Overlying the insulating layer with an organic layer, wherein the organic layer fills the isolation trench and the via; An organic layer in the via hole is removed, and a first metal layer is deposited in the via hole to conduct the signal transmission line. The method of manufacturing an array substrate according to claim 14, wherein before the covering the organic layer on the insulating layer, the method further comprises: Forming an active layer on the insulating layer; The removing the organic layer in the via hole and depositing the first metal layer in the via hole to turn on the signal transmission line further includes: A portion of the organic layer on the active layer is removed to expose the active layer, and a second metal layer is deposited on the organic layer and the active layer to form a source and a drain. The method of manufacturing an array substrate according to claim 15, wherein the method further comprises: Forming an inorganic layer on the active layer and the insulating layer; The etching the insulating layer to form an isolation trench and etching the insulating layer to form a via hole to expose a portion of the data line further comprises: etching the inorganic layer; The removing a portion of the organic layer on the active layer to expose the active layer further includes removing a portion of the inorganic layer on the active layer. The method of manufacturing an array substrate according to claim 16, wherein the first metal layer is turned on by the source, the method further comprising: Forming a protective layer on the first metal layer and the second metal layer; Patterning the protective layer to expose the drain; A conductive layer is deposited on the protective layer, the source, and the drain to form a pixel electrode, and the drain is electrically connected to the pixel electrode. The method of manufacturing an array substrate according to claim 15, wherein the method further comprises: Etching the organic layer to expose the source or drain; A conductive layer is deposited on the organic layer to form a pixel electrode, and the source or drain is electrically connected to the pixel electrode. The method of manufacturing an array substrate according to claim 14, wherein after the covering the organic layer on the insulating layer, the method further comprises: Removing the organic layer on a portion of the insulating layer to expose the insulating layer; Forming an active layer on the insulating layer; The removing the organic layer in the via hole and depositing the first metal layer in the via hole to turn on the signal transmission line further includes: depositing a second on the organic layer and the active layer The metal layer forms a source and a drain. The method of manufacturing an array substrate according to claim 19, wherein the method further comprises: Forming a protective layer on the first metal layer, the organic layer, and the second metal layer; Etching the protective layer to expose the source; A conductive layer is deposited on the source and the protective layer to form a pixel electrode, and the source is electrically connected to the pixel electrode. A method of manufacturing an array substrate according to any one of claims 14 to 19, characterized in that Forming the signal transmission line and the gate on the substrate includes: A buffer layer is deposited on the substrate, and the signal transmission line and the gate are formed on the buffer layer. The method of manufacturing an array substrate according to claim 21, wherein the etching the insulating layer to form the isolation trench further comprises: partially etching the buffer layer corresponding to the isolation trench.

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