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WO2017177705A1 - Plate-forme et procédé de validation formelle de circuits à très haut degré d'intégration (vlsi) - Google Patents

Plate-forme et procédé de validation formelle de circuits à très haut degré d'intégration (vlsi) Download PDF

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Publication number
WO2017177705A1
WO2017177705A1 PCT/CN2016/109582 CN2016109582W WO2017177705A1 WO 2017177705 A1 WO2017177705 A1 WO 2017177705A1 CN 2016109582 W CN2016109582 W CN 2016109582W WO 2017177705 A1 WO2017177705 A1 WO 2017177705A1
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WIPO (PCT)
Prior art keywords
script
setting
platform
verification
lib
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PCT/CN2016/109582
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English (en)
Chinese (zh)
Inventor
张永照
童元满
李仁刚
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浪潮电子信息产业股份有限公司
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Application filed by 浪潮电子信息产业股份有限公司 filed Critical 浪潮电子信息产业股份有限公司
Publication of WO2017177705A1 publication Critical patent/WO2017177705A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]

Definitions

  • the present invention relates to the field of chip formal verification technology, and in particular, to a VLSI form verification platform and method for a very large scale integrated circuit.
  • VLSI is an abbreviation for Very Large Scale Integration, which refers to an integrated circuit in which tens of millions of transistors are integrated on a silicon chip of several millimeters square and a line width is less than 1 micrometer. Since the transistor and the connection are completed at one time, the cost and cost of making several to millions of transistors are equivalent. Mass production ⁇ , hardware costs are almost insignificant, depending on design costs.
  • the technical problem to be solved by the present invention is: In view of the rapid development of the scale and complexity of today's integrated circuits, the integrated work faces various challenges, and the present invention proposes a VLSI VLS.
  • I formal verification platform and method taking into account the large scale of VLSI, the use of top-down integration has high resource requirements, large sales margins, the same chip level, module differences, the use of bottom Upward strategy, modular implementation of the components of the verification platform.
  • a VLSI formal verification platform for a very large scale integrated circuit includes components: a variable setting script, a Lib read script, a DUT read script, an Env setting script, and a report setting script, and the verification platform further includes The match/unmatch point extraction script that processes the output of the verification platform. Once the detection verification fails, there is an immatch point, which enables the iterative work to be performed automatically, where:
  • variable setting script uniformly sets macro variables such as a Lib/DUT read path, a result output path, and a top level name to be tested, and is responsible for setting variables such as top name, source path, report path, and library path of each DUT;
  • Lib reads the script, manages the standard cell library and various IP read-in, manages each module Lib separately, and reduces the read-in time; the entire chip uses a large variety of IPs, such as: interface and memory, etc.
  • IPs used by different modules are inconsistent or some modules do not use IP.
  • the library units of each integrated module are managed separately, and the library read-in time is greatly reduced.
  • the DUT reads the script, calls the corresponding setting in the variable setting script, reads the source design RTL code, separately manages each verification module, realizes verifying different levels and different modules, and accurately reading the corresponding RTL code;
  • the Env environment setting script sets the verification tool to deal with special cases such as warning, undriven, and bl ackbox, and completes the undriven signal, mismatch_messag e (mismatch information), and warning type. Settings such as processing methods;
  • the match/unmatch point extraction script is responsible for processing the unmatch output result to conform to the platform read format, and checking whether the match or aborted verified condition is reasonable; processing the unmatch and unverified aborted reports, so that It conforms to the platform read-in format, especially if there is an unmat ch point for iterative verification, and the output native format is processed into the set_user_match format, and the unchecked whether the unv erified and aborted cases meet the constraints set by the script;
  • Report setting script calling variable setting script, outputting analysis result, immatd ⁇ failing ), aborted (unscheduled), unverified (uncertified) and other information to the specified working directory;
  • the top.tcl file calls other setting scripts in a certain order, performs unified management and is responsible for starting the platform, and realizes consistent management of the entire project.
  • the Env environment setting script can be shared by all platforms.
  • the match/unmatch point extraction script is created using peri. Verify that there may be hundreds or even more unmatch points, and the platform output result format is a platform environment that cannot be directly read. Therefore, using peri's powerful text processing capabilities, a match/unmatch point extraction script is created. The verification verification does not pass the existence of the unmatch point, so that the iterative work can be automated.
  • Perl a feature-rich computer programming language that runs on more than 100 computer platforms, is available from mainframes to portable devices, from rapid prototyping to large-scale scalable bursts.
  • the reading order of the top.tcl file management script is: a variable setting script, a Lib reading script, an En V setting script, a DUT reading script, a platform control command, and a report script.
  • a VLSI formal verification method for a very large scale integrated circuit the method reasonably dividing a component of a formal verification platform, a Lib read script, a DUT read setting script, an Env environment setting script, a Report setting script, and added
  • the variable setting script processes the match/unmatch point extraction script of the output of the verification platform.
  • Each script is managed in a certain order by top.tcl, and the unified management of the entire project is realized, so that the entire formal verification work is more hierarchical and divided.
  • Hierarchies or sub-modules can be independently verified, enabling read-through shortening and parallelization of different sub-modules.
  • the method is incremented one level at a time according to the level of division.
  • the present invention uses perl to implement the processing of the result, and realizes the automation of the iterative verification of the unmatch point, and the source code of each module to be verified and Lib are respectively managed, which greatly reduces the consumption of reading and reading.
  • FIG. 1 is a schematic structural diagram of a verification platform. Embodiments of the invention
  • Embodiment 1 is a diagrammatic representation of Embodiment 1 :
  • a VLSI formal verification platform for a very large scale integrated circuit includes components: a variable setting script, a Lib read script, a DUT read script, an Env setting script, and a report setting script.
  • the verification platform further includes a match/unmatch point extraction script for processing the output of the verification platform. Once the detection verification fails, there is an immatch point, which enables the iterative work to be performed automatically, wherein:
  • variable setting script uniformly sets macro variables such as a Lib/DUT read path, a result output path, and a top level name to be tested, and is responsible for setting variables such as a top name, a source path, a report path, and a library path of each DUT.
  • macro variables such as a Lib/DUT read path, a result output path, and a top level name to be tested, and is responsible for setting variables such as a top name, a source path, a report path, and a library path of each DUT.
  • Lib reads the script, manages the reading of the standard cell library and various IPs (storage IP, PAD IP and other IP libraries), manages each module Lib separately, and reduces the read-in time; the entire chip will use a large amount of Various IPs, such as: interface and memory, etc., and the IP used by different modules is inconsistent or some modules do not use IP.
  • the library units of each integrated module are managed separately, and the library read-in is greatly reduced.
  • the DUT reads the script, calls the corresponding setting in the variable setting script, reads the source design RTL code, separately manages each verification module, realizes verifying different levels and different modules, and accurately reads the corresponding RTL code;
  • Env environment setting script responsible for managing the setting of the tool's own variable, setting the verification tool for the special case of warning, undriven blackbox, etc., and completing the setting of the undriven signal, the mismatch_m essage and the warning type processing mode;
  • the match/unmatch point extraction script is responsible for statistically verifying that the verification result is not responsible for the unmatch, and processing the form acceptable to the verification platform and feeding back to the verification platform; responsible for processing the unmatch output result to make it conform to the platform read Enter the format, check whether the match or aborted verify condition is reasonable; handle the unmatch, unverified ⁇ aborted report to make it conform to the platform read format, especially if there is an unmatch point, iterative verification, and the output format is processed.
  • Se t_ USer _mat C h format with check-inch unverified and aborted the situation meets the constraints set by the script;
  • Report setting script calling variable setting script, outputting analysis result, unmatch, failing, abort Ed, unverified and other information to the specified working directory, responsible for the printing and output of formal verification results;
  • top.tcl calls other setting scripts in a certain order, performs unified management and is responsible for starting the platform, and realizes consistent management of the entire project.
  • LIB There are two kinds of LIB, one is a static library, such as the C-Runtime library.
  • This LIB has function implementation code, which is generally used in static build, which adds the code in LIB to the target module (EXE). Or DLL) file, so after the link is complete, the LIB file is useless.
  • a LIB is used with the DLL. There is no code in it. The code is in the DLL.
  • This LIB is used to statically call the DLL. Therefore, the role is also a link function. The link is completed, and the LIB is useless.
  • the LIB file is not used at all. After the target module (EXE or DLL) file is generated, the LIB file is not needed;
  • the Env environment setting script described in this embodiment may be shared by all platforms.
  • the match/unmatch point extraction script described in this embodiment is created by perl. Verification may occur in hundreds or even more unmatch points, and the platform output result format is a platform environment that cannot be directly read. Therefore, using peri's powerful text processing capability, a match/un match point extraction script is created. Once the test verification does not pass the existence of the unmatch point, the automation of the iterative work can be performed.
  • Perl a feature-rich computer programming language that runs on more than 100 computer platforms, is suitable for a wide range of applications, from mainframe to portable devices, from rapid prototyping to large-scale scalable bursts; 'Practical Extraction and Report'
  • the reading order of the top.tcl file management script in this embodiment is: variable setting script, Lib reading script, Env setting script, DUT reading script, platform control command. , Rep ort script.
  • Embodiment 5 A VLSI formal verification method for a very large scale integrated circuit, the method reasonably dividing a component of a formal verification platform, a Lib read script, a DUT read setting script, an Env environment setting script, and a report setting script, and adding The variable setting script processes the match/unmatch point extraction script of the output of the verification platform.
  • Each script is managed in a certain order by top.tcl, and the unified management of the entire project is realized, so that the entire formal verification work is more hierarchical and divided. Hierarchies or sub-modules can be independently verified, enabling read-through shortening and parallelization of different sub-modules.

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  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
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Abstract

Plate-forme et procédé de validation formelle de circuits à très haut degré d'intégration (VLSI). La plate-forme de validation comporte les composants d'un script de spécification de variables, d'un script de lecture de Lib, d'un script de lecture de DUT, d'un script de spécification d'Env et d'un script de spécification de compte rendu. La plate-forme de validation comporte en outre un script d'extraction de points de concordance/non-concordance servant à traiter un résultat de sortie de la plate-forme de validation. La plate-forme et le procédé de validation utilisent perl pour réaliser le traitement d'un résultat, réaliser la validation itérative automatique de points de non-concordance, gérer respectivement un code source de chaque module à valider et de chaque Lib, et réduisent considérablement la consommation d'un temps de lecture.
PCT/CN2016/109582 2016-04-11 2016-12-13 Plate-forme et procédé de validation formelle de circuits à très haut degré d'intégration (vlsi) WO2017177705A1 (fr)

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CN201610219744.1A CN105893685A (zh) 2016-04-11 2016-04-11 一种超大规模集成电路vlsi形式化验证平台及方法
CN201610219744.1 2016-04-11

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CN105893685A (zh) * 2016-04-11 2016-08-24 浪潮电子信息产业股份有限公司 一种超大规模集成电路vlsi形式化验证平台及方法
CN106375658B (zh) * 2016-09-09 2019-05-24 北京控制工程研究所 一种甚高精度图像处理vlsi验证方法
CN107563025B (zh) * 2017-08-18 2021-08-20 北京东土军悦科技有限公司 一种验证平台管理方法及装置
CN107644128A (zh) * 2017-09-08 2018-01-30 郑州云海信息技术有限公司 一种DC综合与Formality形式化验证协同的方法及系统
CN114692538A (zh) * 2022-04-08 2022-07-01 山东云海国创云计算装备产业创新中心有限公司 一种并行形式验证方法、装置、计算机设备及介质

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