WO2017177705A1

WO2017177705A1 - Very-large-scale integration circuit (vlsi) formal verification platform and method

Info

Publication number: WO2017177705A1
Application number: PCT/CN2016/109582
Authority: WO
Inventors: 张永照; 童元满; 李仁刚
Original assignee: 浪潮电子信息产业股份有限公司
Priority date: 2016-04-11
Filing date: 2016-12-13
Publication date: 2017-10-19
Also published as: CN105893685A

Abstract

A very-large-scale integration circuit (VLSI) formal verification platform and method. The verification platform comprises the components of a variable setting script, a Lib reading script, a DUT reading script, an Env setting script and a Report setting script. The verification platform further comprises a match/unmatch point extraction script for processing an output result of the verification platform. The verification platform and method use perl to realize the processing of a result, realize the automatic iterative verification of unmatch points, respectively manage a source code of each module to be verified and Lib, and greatly reduce the consumption of a reading time.

Description

VLSI formal verification platform and method for ultra-large scale integrated circuit

[0001] The present invention relates to the field of chip formal verification technology, and in particular, to a VLSI form verification platform and method for a very large scale integrated circuit.

Background technique

[0002] Today's VLSIs are complex, large-scale, and multi-layered. The whole-chip overall verification (top-do wn strategy) has high resource requirements, large sales margins, and high iteration cost. Each level and module The mismatch situation is different, which makes it difficult to debug.

[0003] The integration degree of digital integrated circuits is getting higher and higher, the logic complexity and algorithms are becoming more and more complicated. On the basis of ensuring the order, taking into account the area and power consumption, the comprehensive work faces great challenges in the netlist. Before flowing into the back-end phase, it is necessary to ensure the equivalence of the integrated network table homologous code design function. Formal verification as a kind of inspection process, the speed and completeness of verification seriously affect the follow-up work. Therefore, the role of a reasonably efficient verification platform is important. For large-scale, high-complexity integrated circuits, formal verification faces many chip layers and many sub-modules. It also involves various IP libraries. Therefore, full-chip formal verification will consume a large number of machines. The diurnal resources will increase the iterative cost, which will seriously hinder the development process of the chip, so this method is basically unrealistic at present.

[0004] In order to solve the above problems, a bottom-up strategy is commonly used, but it is necessary to reasonably implement the verification hierarchy and the division of sub-modules. Efficient verification work requires efficient and reasonable verification scripts to build a verification platform and process the results, especially in the case of unmatched conditions.

[0005] VLSI is an abbreviation for Very Large Scale Integration, which refers to an integrated circuit in which tens of millions of transistors are integrated on a silicon chip of several millimeters square and a line width is less than 1 micrometer. Since the transistor and the connection are completed at one time, the cost and cost of making several to millions of transistors are equivalent. Mass production 吋, hardware costs are almost insignificant, depending on design costs.

technical problem

[0006] The technical problem to be solved by the present invention is: In view of the rapid development of the scale and complexity of today's integrated circuits, the integrated work faces various challenges, and the present invention proposes a VLSI VLS. I formal verification platform and method, taking into account the large scale of VLSI, the use of top-down integration has high resource requirements, large sales margins, the same chip level, module differences, the use of bottom Upward strategy, modular implementation of the components of the verification platform.

Problem solution

Technical solution

[0007] The technical solution adopted by the present invention is:

[0008] A VLSI formal verification platform for a very large scale integrated circuit, the verification platform includes components: a variable setting script, a Lib read script, a DUT read script, an Env setting script, and a report setting script, and the verification platform further includes The match/unmatch point extraction script that processes the output of the verification platform. Once the detection verification fails, there is an immatch point, which enables the iterative work to be performed automatically, where:

[0009] The variable setting script uniformly sets macro variables such as a Lib/DUT read path, a result output path, and a top level name to be tested, and is responsible for setting variables such as top name, source path, report path, and library path of each DUT;

[0010] Lib reads the script, manages the standard cell library and various IP read-in, manages each module Lib separately, and reduces the read-in time; the entire chip uses a large variety of IPs, such as: interface and memory, etc. The IPs used by different modules are inconsistent or some modules do not use IP. The library units of each integrated module are managed separately, and the library read-in time is greatly reduced.

[0011] The DUT reads the script, calls the corresponding setting in the variable setting script, reads the source design RTL code, separately manages each verification module, realizes verifying different levels and different modules, and accurately reading the corresponding RTL code;

[0012] The Env environment setting script sets the verification tool to deal with special cases such as warning, undriven, and bl ackbox, and completes the undriven signal, mismatch_messag e (mismatch information), and warning type. Settings such as processing methods;

[0013] The match/unmatch point extraction script is responsible for processing the unmatch output result to conform to the platform read format, and checking whether the match or aborted verified condition is reasonable; processing the unmatch and unverified aborted reports, so that It conforms to the platform read-in format, especially if there is an unmat ch point for iterative verification, and the output native format is processed into the set_user_match format, and the unchecked whether the unv erified and aborted cases meet the constraints set by the script;

[0014] Report setting script, calling variable setting script, outputting analysis result, immatd^ failing ), aborted (unscheduled), unverified (uncertified) and other information to the specified working directory;

[0015] The top.tcl file calls other setting scripts in a certain order, performs unified management and is responsible for starting the platform, and realizes consistent management of the entire project.

[0016] The Env environment setting script can be shared by all platforms.

[0017] The match/unmatch point extraction script is created using peri. Verify that there may be hundreds or even more unmatch points, and the platform output result format is a platform environment that cannot be directly read. Therefore, using peri's powerful text processing capabilities, a match/unmatch point extraction script is created. The verification verification does not pass the existence of the unmatch point, so that the iterative work can be automated.

[0018] Perl, a feature-rich computer programming language that runs on more than 100 computer platforms, is available from mainframes to portable devices, from rapid prototyping to large-scale scalable bursts.

[0019] The reading order of the top.tcl file management script is: a variable setting script, a Lib reading script, an En V setting script, a DUT reading script, a platform control command, and a report script.

[0020] A VLSI formal verification method for a very large scale integrated circuit, the method reasonably dividing a component of a formal verification platform, a Lib read script, a DUT read setting script, an Env environment setting script, a Report setting script, and added The variable setting script processes the match/unmatch point extraction script of the output of the verification platform. Each script is managed in a certain order by top.tcl, and the unified management of the entire project is realized, so that the entire formal verification work is more hierarchical and divided. Hierarchies or sub-modules can be independently verified, enabling read-through shortening and parallelization of different sub-modules.

[0021] After the verification of the lowest level module is completed, the method is incremented one level at a time according to the level of division.

Advantageous effects of the invention

Beneficial effect

[0022] The beneficial effects of the present invention are:

[0023] The present invention uses perl to implement the processing of the result, and realizes the automation of the iterative verification of the unmatch point, and the source code of each module to be verified and Lib are respectively managed, which greatly reduces the consumption of reading and reading.

Brief description of the drawing

DRAWINGS

1 is a schematic structural diagram of a verification platform. Embodiments of the invention

[0025] The present invention will be further described below in accordance with specific embodiments with reference to the accompanying drawings:

Embodiment 1 :

[0027] As shown in FIG. 1, a VLSI formal verification platform for a very large scale integrated circuit, the verification platform includes components: a variable setting script, a Lib read script, a DUT read script, an Env setting script, and a report setting script. The verification platform further includes a match/unmatch point extraction script for processing the output of the verification platform. Once the detection verification fails, there is an immatch point, which enables the iterative work to be performed automatically, wherein:

[0028] The variable setting script uniformly sets macro variables such as a Lib/DUT read path, a result output path, and a top level name to be tested, and is responsible for setting variables such as a top name, a source path, a report path, and a library path of each DUT. Full platform versatility;

[0029] Lib reads the script, manages the reading of the standard cell library and various IPs (storage IP, PAD IP and other IP libraries), manages each module Lib separately, and reduces the read-in time; the entire chip will use a large amount of Various IPs, such as: interface and memory, etc., and the IP used by different modules is inconsistent or some modules do not use IP. The library units of each integrated module are managed separately, and the library read-in is greatly reduced.

[0030] The DUT reads the script, calls the corresponding setting in the variable setting script, reads the source design RTL code, separately manages each verification module, realizes verifying different levels and different modules, and accurately reads the corresponding RTL code;

[0031] Env environment setting script, responsible for managing the setting of the tool's own variable, setting the verification tool for the special case of warning, undriven blackbox, etc., and completing the setting of the undriven signal, the mismatch_m essage and the warning type processing mode;

[0032] The match/unmatch point extraction script is responsible for statistically verifying that the verification result is not responsible for the unmatch, and processing the form acceptable to the verification platform and feeding back to the verification platform; responsible for processing the unmatch output result to make it conform to the platform read Enter the format, check whether the match or aborted verify condition is reasonable; handle the unmatch, unverified ^ aborted report to make it conform to the platform read format, especially if there is an unmatch point, iterative verification, and the output format is processed. as _{_Se} t_ _{USer _mat} _C h format, with check-inch unverified and aborted the situation meets the constraints set by the script;

[0033] Report setting script, calling variable setting script, outputting analysis result, unmatch, failing, abort Ed, unverified and other information to the specified working directory, responsible for the printing and output of formal verification results;

[0034] top.tcl calls other setting scripts in a certain order, performs unified management and is responsible for starting the platform, and realizes consistent management of the entire project.

[0035] There are two kinds of LIB, one is a static library, such as the C-Runtime library. This LIB has function implementation code, which is generally used in static build, which adds the code in LIB to the target module (EXE). Or DLL) file, so after the link is complete, the LIB file is useless. A LIB is used with the DLL. There is no code in it. The code is in the DLL. This LIB is used to statically call the DLL. Therefore, the role is also a link function. The link is completed, and the LIB is useless. As for the dynamic call of the DLL, the LIB file is not used at all. After the target module (EXE or DLL) file is generated, the LIB file is not needed;

[0036] DUT device under test.

Example 2

[0038] On the basis of Embodiment 1, the Env environment setting script described in this embodiment may be shared by all platforms.

Example 3

[0040] On the basis of Embodiment 1 or 2, the match/unmatch point extraction script described in this embodiment is created by perl. Verification may occur in hundreds or even more unmatch points, and the platform output result format is a platform environment that cannot be directly read. Therefore, using peri's powerful text processing capability, a match/un match point extraction script is created. Once the test verification does not pass the existence of the unmatch point, the automation of the iterative work can be performed.

[0041] Perl, a feature-rich computer programming language that runs on more than 100 computer platforms, is suitable for a wide range of applications, from mainframe to portable devices, from rapid prototyping to large-scale scalable bursts; 'Practical Extraction and Report'

Language) , you may also see "peri", all letters are lowercase. In general, "Peri", with the uppercase P, refers to the language itself, and "perl", lowercase p, refers to the interpreter that the program runs.

Embodiment 4

[0043] On the basis of the third embodiment, the reading order of the top.tcl file management script in this embodiment is: variable setting script, Lib reading script, Env setting script, DUT reading script, platform control command. , Rep ort script.

Embodiment 5 [0045] A VLSI formal verification method for a very large scale integrated circuit, the method reasonably dividing a component of a formal verification platform, a Lib read script, a DUT read setting script, an Env environment setting script, and a report setting script, and adding The variable setting script processes the match/unmatch point extraction script of the output of the verification platform. Each script is managed in a certain order by top.tcl, and the unified management of the entire project is realized, so that the entire formal verification work is more hierarchical and divided. Hierarchies or sub-modules can be independently verified, enabling read-through shortening and parallelization of different sub-modules.

Example 6

[0047] On the basis of Embodiment 5, after the verification of the lowest layer module is completed, the method described in this embodiment is incremented according to the level of the hierarchy.

The above embodiments are merely illustrative of the present invention, and are not intended to limit the invention, and various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, all equivalent technical solutions are also within the scope of the invention, and the scope of the invention should be defined by the claims.

Claims

Claim

[Claim 1] A VLSI formal verification platform for a very large scale integrated circuit, the verification platform includes components: a variable setting script, a Lib reading script, a DUT reading script, an Env setting script, and an R eport setting script, wherein The verification platform further includes a match/unmatch point extraction script that processes the output of the verification platform, where:

Variable setting script, unified setting Lib/DUT read path, result output path and top level name macro variable to be tested, responsible for completing the setting of top name, source path, report path and library path variable of each DUT;

Lib reads the script, manages the standard cell library and reads various IPs, and manages each module separately. Lib

, reducing reading time;

The DUT reads the script, calls the corresponding settings in the variable setting script, reads the source design RTL code, and manages each verification module separately;

The Env environment setting script sets the verification tool for the warning, undriven, and blackbox special cases, and completes the setting of the undriven signal, mismatch-message, and warning type processing modes.

Match/unmatch point extraction script, which is responsible for processing the unmatch output result, making it conform to the platform read format, and checking whether the match or aborted verified condition is reasonable; processing the unmatch, unverified. aborted report to match Platform read format;

Report setting script, call variable setting script, output analysis result, unmatc faili ng, aborted unverified information to the specified working directory; top.tcl file calls other setting scripts in a certain order, unified management and responsible for platform startup, realize the whole project Consistent management.

[Claim 2] A VLSI formal verification platform for a very large scale integrated circuit according to claim 1, wherein: the Env environment setting script is shared by the entire platform.

[Claim 3] A VLSI formal verification platform for a very large scale integrated circuit according to claim 1 or 2, wherein: the match/unmatch point extraction script is created using perl.

[Claim 4] A VLSI formal verification platform for a very large scale integrated circuit according to claim 3, The function of reading the top.tcl file management script is: a variable setting script, a Lib reading script, an Env setting script, a DUT reading script, a platform control command, and a report script.

[Claim 5] A VLSI formal verification method for a very large scale integrated circuit, characterized in that: the method reasonably divides a component of a formal verification platform, a Lib read script, a DUT read setting script, an Env environment setting script, and a report. Set the script, and add the variable setting script to process the match/unmatch point extraction script for the output of the verification platform. Each script is managed in a certain order by to p.tel, to achieve consistent management of the entire project, so that the entire formal verification work It is more hierarchical, and the hierarchical or sub-modules can be independently verified, and the read-in shortening and parallelization of different sub-modules are realized.

[Claim 6] A VLSI formal verification method for a very large scale integrated circuit according to claim 5, wherein: after the verification of the lowest level module is completed, the method is incrementally increased according to the level of the hierarchy. .