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WO2016000376A1 - Procédé de traitement de signal et appareil de traitement de signal basés sur des interfaces pci-e - Google Patents

Procédé de traitement de signal et appareil de traitement de signal basés sur des interfaces pci-e Download PDF

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Publication number
WO2016000376A1
WO2016000376A1 PCT/CN2014/090397 CN2014090397W WO2016000376A1 WO 2016000376 A1 WO2016000376 A1 WO 2016000376A1 CN 2014090397 W CN2014090397 W CN 2014090397W WO 2016000376 A1 WO2016000376 A1 WO 2016000376A1
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Prior art keywords
signal
pci
tlp
signal processing
input signal
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PCT/CN2014/090397
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English (en)
Chinese (zh)
Inventor
苏慧锐
孟凡虎
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中兴通讯股份有限公司
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Publication of WO2016000376A1 publication Critical patent/WO2016000376A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer

Definitions

  • the present invention relates to the field of signal processing, and in particular, to a signal processing method and a signal processing apparatus based on a PCI-E interface.
  • PCI-E Peripheral Component Interconnect Express
  • Intel Corporation in 2001. At the end of 2002, it merged with AMD, DELL, IBM and other companies to form a technical specification named PCI-E.
  • PCI-E uses the popular point-to-point serial connection in the industry. Each device has its own dedicated connection. It does not need to request bandwidth from the entire bus, and can increase the data transmission rate to a very high frequency.
  • PCI-E Dual simplex connections provide higher transfer rates and quality.
  • the PCI-E interface differs according to the bit width requirements of the bus interface, which are PCI-E 1X (250M/S), 2X, 4X, 8X, 16X, or even 32X.
  • the 1X rate is the lowest and the 32X rate is the highest.
  • This technology is widely used in industrial control, communication, and computer fields, and has become the mainstream of breakthrough transmission rate and fast interconnection.
  • Altera and Xilinx have introduced their own PCI-E core (PCI-E core) high-end FPGA (Field-Programmable Gate Array), also known as programmable controller ), the application of PCI-E to achieve 100G and 400G, more and more become the preferred solution for major communication vendors.
  • PCI-E core PCI-E core
  • FPGA Field-Programmable Gate Array
  • the implementation of the PCI-E technology is for a specific signal or a specific format, and the transmission mode is single, which is difficult to meet the requirements for multiple signal access.
  • the embodiment of the invention provides a signal processing method and a signal processing device based on a PCI-E interface, so as to at least solve the problem that the prior art can only perform for a specific signal or a specific format when adopting the PCI-E high-speed transmission technology. Transmission, and a single transmission method, it is difficult to meet the problem of the need for multiple signal access.
  • an embodiment of the present invention provides a signal processing method based on a PCI-E interface, including:
  • the TLP message of each input signal is output to the PCI-E controller.
  • the plurality of signals comprise at least two of an SDH overhead signal, an OTN overhead signal, a DVB signal, and a CPU signal.
  • the step of acquiring multiple types of input signals of different types is specifically: acquiring multiple types of input signals of different types, and storing each input signal in a cache unit, wherein the size of the cache unit is respectively Assigned according to the format of each input signal.
  • the step of converting each of the plurality of input signals into a TLP message that satisfies a PCI-E bus format and buffering, respectively includes:
  • each input signal is sequentially converted to obtain a TLP message satisfying each input signal of the PCI-E bus format and buffered.
  • the step of performing arbitration control on the TLP message of each input signal that is buffered includes:
  • the preset rule includes: a preset outflow order of each TLP packet, a preset priority between multiple TLP messages, a sending interval between TLP messages, and a processing method of an error packet.
  • the embodiment of the invention provides a signal processing device based on a PCI-E interface, including:
  • Obtaining a module configured to obtain a plurality of input signals of different types
  • a conversion module configured to convert each of the plurality of input signals into a TLP message that satisfies a PCI-E bus format and cache the same;
  • control module configured to arbitrate control of a TLP message of each input signal buffered
  • the transmission module is configured to output a TLP message of each input signal to the PCI-E controller for output according to the result of the arbitration control.
  • the acquiring module acquires multiple input signals of different types, and stores each input signal into a buffer unit, wherein the size of the buffer unit is respectively allocated according to a format of each input signal.
  • the conversion module includes:
  • a first obtaining unit configured to acquire processing priority of different types of signals
  • the conversion unit is configured to sequentially perform conversion processing on each input signal in the order of the processing priority to obtain a TLP message satisfying each input signal of the PCI-E bus format and buffering.
  • control module includes:
  • a second obtaining unit configured to acquire a preset rule
  • control unit configured to perform arbitration control on the TLP message according to the preset rule
  • the preset rule includes: a preset outflow order of each TLP packet, a preset priority between multiple TLP messages, a sending interval between TLP messages, and a processing method of an error packet.
  • the above solution realizes transmission control of multiple access signals by using arbitration control, and transmits to a PCI-E controller through a single interface. In this way, the setting of the PCI-E interface is reduced, and the processing efficiency of the signal is improved, and at the same time Improve equipment interconnection efficiency.
  • FIG. 2 is a block diagram showing the signal processing apparatus according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of signal access according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram showing a signal processing flow according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a module in an FPGA according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram showing a signal processing process of an arbitration module in an FPGA according to an embodiment of the present invention.
  • Fig. 7 is a diagram showing the signal conversion of the embodiment of the present invention.
  • the present invention is directed to the prior art that when the PCI-E high-speed transmission technology is adopted, the transmission can only be performed for a specific signal or a specific format, and the transmission mode is single, and it is difficult to meet the problem of demand for multiple signal access, and a problem is provided.
  • a signal processing method and a signal processing device based on a PCI-E interface are provided.
  • the signal processing method of the embodiment of the present invention includes:
  • Step 10 acquiring multiple types of input signals of different types
  • Step 20 Convert each input signal of the multiple input signals into a Transaction Layer Packet (TLP) message that satisfies the PCI-E bus format, and cache the signal;
  • TLP Transaction Layer Packet
  • Step 30 Perform arbitration control on the TLP message of each input signal that is buffered
  • Step 40 According to the result of the arbitration control, the TLP message of each input signal is output to the PCI-E controller.
  • transmission control of multiple access signals is realized by using arbitration control, and is transmitted to the PCI-E controller through a single interface, thereby reducing the setting of the PCI-E interface and improving the interconnection efficiency of the device.
  • each input signal may be a CPU signal, an OTN (Optical Transport Network) overhead signal, an SDH (Synchronous Digital Hierarchy) signal, or a DVB (Digital Video Broadcasting).
  • OTN Optical Transport Network
  • SDH Synchronous Digital Hierarchy
  • DVB Digital Video Broadcasting
  • each input signal is first stored in a buffer, and the buffer size occupied by the signal is correspondingly allocated according to the format of each input signal.
  • the step 20 in the embodiment of the present invention is specifically:
  • each input signal is sequentially converted to obtain a TLP message satisfying each input signal of the PCI-E bus format and buffered.
  • the type of each input signal in the buffer is obtained, and then according to the processing priority of different types of signals, which signal is first converted, for example, the processing order of the signal is CPU signal, OTN overhead signal, if both of the above are exist in the buffer
  • the signal firstly converts the format of the CPU signal.
  • the format conversion of the OTN overhead signal is performed.
  • the preset conversion rule corresponding to the signal is called according to the type of each signal. , complete the format conversion of this kind of signal.
  • the preset rule mainly includes: a preset outflow order of each TLP message, a priority between preset multiple TLP messages, a sending interval between TLP messages, and an error packet.
  • the packet check is performed on each TLP packet, and the TLP packet can be sent only after the check is passed.
  • the TLP packet is sequentially transmitted according to the priority order of the TLP packet. After the data in all the TLP packets is transmitted in the sequence, the next TLP packet can be transmitted after the preset interval is reached.
  • arbitration control is actually processing a signal, that is, the PCI-E standard packet format, which simplifies the processing flow.
  • the PCI-E controller After the TLP packet is transmitted to the PCI-E controller, the PCI-E controller sends the TLP packet to the corresponding device to output the TLP packet according to the type of the TLP packet.
  • the received multiple input signals are respectively converted into corresponding data packets satisfying the PCI-E bus format, and then the data packets are respectively sent to the PCI-E by an interface through arbitration control.
  • -E controller can receive multiple different signals through one interface, reduce interface settings, improve signal processing efficiency, improve device interconnection efficiency, and simplify signal docking between boards, saving The cost.
  • the signal processing apparatus of the embodiment of the present invention includes:
  • Obtaining module 1 configured to acquire a plurality of input signals of different types
  • the conversion module 2 is configured to respectively convert each of the plurality of input signals into a TLP message that satisfies the PCI-E bus format and cache the same;
  • the control module 3 is configured to perform arbitration control on the TLP message of each input signal buffered
  • the sending module 4 is configured to output a TLP message of each input signal to the PCI-E controller according to the result of the arbitration control.
  • the obtaining module 1 is configured to acquire different types of input signals of different types, and store each input signal into the buffer unit separately, and the size of the buffer unit is respectively allocated according to the format of each input signal. of.
  • the conversion module 2 includes:
  • a first obtaining unit configured to acquire processing priority of different types of signals
  • the conversion unit is configured to sequentially perform conversion processing on each input signal in the order of the processing priority to obtain a TLP message satisfying each input signal of the PCI-E bus format and buffering.
  • control module 3 includes:
  • a second obtaining unit configured to acquire a preset rule
  • the control unit is configured to perform arbitration control on the TLP message according to the preset rule.
  • the preset rule acquired by the second acquiring unit mainly includes: a preset outflow order of each TLP packet, a preset priority between multiple TLP packets, and a TLP packet.
  • the sending interval and the processing method of the error packet mainly includes: a preset outflow order of each TLP packet, a preset priority between multiple TLP packets, and a TLP packet.
  • the signal processing device embodiment is a signal processing device corresponding to the above signal processing method, and all implementations of the signal processing method are applicable to the signal processing device embodiment, and can also achieve the signal processing method. The same technical effect.
  • PCI-E core PCI-E core
  • the core is used for PCI-E transmission, and the transmission rate setting and PCI-E core setting can be configured according to the configuration wizard in an IDE (Integrated Drive Electronics) development environment.
  • the PCI-E core includes SERDES (short for SERializer/DESerializer) and PCI-E, and the signal is transmitted between the PCI-E core and the arbitration module, all inputs.
  • the signals (CPU signal, OTN overhead signal, SDH signal, DVB signal, etc.) are all connected to the arbitration module through the dedicated signal access pin of the FPGA, and then stored in the buffer (RAM), after the format conversion of the input signal is performed. Then, the various converted signals are subjected to abnormal processing, and the converted signal is subjected to arbitration control according to the arbitration profile accessed by the control signal, and then the converted signal is respectively sent to the PCI-E core via the cache.
  • the processing flow of the signal is: a plurality of different kinds of input signals (such as CPU signal, OTN overhead signal, SDH signal) are first stored in the buffer RAM, and then the input signals in the buffer RAM are respectively passed.
  • the corresponding format conversion rule is converted into a TLP message having a unified format, and then the flow control module performs exception processing on the signals according to the arbitration configuration information (ie, the preset rule described above) and outputs an abnormal processing result, and after the processing is completed,
  • the TLP packets corresponding to the input signals are separately transmitted through the PCI-E core interface.
  • the FPGA module includes a PCI-E module and an arbitration module;
  • the PCI-E module is instantiated using Vivado (Vivado Design Suite, an integrated design environment released by FPGA manufacturer Xilinx in 2012), consisting of a PCI-E core and a configuration module.
  • the PCI-E core is mainly composed of PCI-E core.
  • SERDES and PCI-E the PCI-E module is mainly configured to complete the conversion of the PCI-E serial interface and process the PCI-E related protocol; wherein the PCI-E core is used by the IP core (IP core is used for Product application specific integrated circuit (ASIC) or FPGA logic block or data block is generated.
  • IP core IP core is used for Product application specific integrated circuit (ASIC) or FPGA logic block or data block is generated.
  • the configuration module Due to the complicated configuration of PCI-E, the configuration module is implemented separately outside the IP core. This configuration module not only completes the configuration of the RC (Root Complex) side. And complete the configuration of the EP (End Point) end (by configuring the TLP
  • the configuration module is composed of a Completion Decoder, a Controller, a Packet Generator, and a TX Mux.
  • the configuration module is configured to send and receive service TLP packets. Only for transparent transmission, the PCI-E core and the configuration module are connected by AXI4-Stream (a bus protocol) interface, and the PCI-E module and the signal processing device are also connected using the AXI4-Stream interface.
  • AXI4-Stream a bus protocol
  • the arbitration module is in the PCI-E sending direction, and the module completes the arbitration of the CPU_TLP packet, the OTN_TLP packet, and the like, and uses a sequential polling mechanism (which can be modified by the configuration file cfg_file) as an example, and various TLPs.
  • the packets have the same priority and are sequentially sent.
  • the PCI-E receiving direction it is necessary to determine the response of the received packet to which signal, and according to the determination result, the packet is sent to the corresponding module; in addition, the arbitration module further It is necessary to implement the TLP packet reception failure determination function, and start timing after transmission.
  • the TLP packet reception failure is reported, and the failure indication signal is valid for at least one clock cycle.
  • the number of failure registers is incremented by one, and the next TLP packet can be sent.
  • the AXI bus is no longer occupied.
  • the arbitration module also implements the AXI interface with the PCI-E IPcore, if the receiving clock and transmission are provided by the PCI-E IPcore. If the clock is not a clock, the module needs to perform cross-clock domain processing on the received TLP packet with FIFO (First Input First Output), and convert the received TLP packet into a transmission clock domain, for example, a cross-clock domain. After processing, the frequency of the receive and transmit clocks is 37.25MHz, but the frequency has a slight deviation.
  • the TLP message after the signal conversion is completed is stored in the corresponding cache.
  • the TLP message completed by the CPU signal conversion is recorded as CPU_TLP
  • the CPU_TLP is stored in the cache
  • the cache field is recorded as CPU_TLP_BUFFER
  • the OTN message completed by the OTN signal is recorded as OTN_TLP
  • the OTN_TLP is stored in the buffer
  • the buffer field is recorded as OTN_TLP_BUFFER
  • the flow control module FLOW_CTRL
  • the CPU_TLP and the OTN_TLP are respectively transmitted through the AXI interface; after the flow control module receives the signal transmitted by the AXI interface, the signal is also subjected to arbitration control according to the configuration file (Cfg_file), and then the received signal is transmitted.
  • arbitration module implements various control functions such as polling control, burst control, priority programmable control, and packet interval programmable control.
  • the signal transmission is bidirectional, when receiving the TLP message sent in the PCI-E direction, it first determines the response of the received TLP message to which signal, and then separately reports the TLP.
  • the text is converted into a signal conforming to the device by using the corresponding format conversion rule, and then the format converted signal is sent to the corresponding device; when the signal sent by the device is received, the corresponding format conversion rule is used.
  • the signal format is converted into a TLP message, and then the TLP message is transmitted.
  • the PCI-E interface-based signal processing method and the signal processing apparatus provided by the embodiments of the present invention have the following beneficial effects: transmission control of multiple access signals is implemented by using arbitration control, and is sent to a single interface.
  • the PCI-E controller reduces the setting of the PCI-E interface, improves the processing efficiency of the signal, and improves the interconnection efficiency of the device.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

La présente invention concerne le domaine du traitement des signaux. La présente invention concerne un procédé de traitement de signal et un appareil de traitement de signal basés sur des interfaces PCI-E. Le procédé de traitement de signal comprend les étapes suivantes : acquisition de multiples types différents de signaux d'entrée ; conversion de chacun des multiples types de signaux d'entrée en un paquet de couche de transaction (TLP) conforme à un format de bus PCI-E et mise en mémoire tampon du paquet TLP ; exécution d'une commande d'arbitrage sur le paquet TLP mis en mémoire tampon de chaque type de signal d'entrée ; et remise du paquet TLP de chaque type de signal d'entrée à un contrôleur PCI-E en vue de sa sortie conformément au résultat de la commande d'arbitrage. Selon la solution, la commande de transmission de multiples types de signaux d'accès est réalisée par commande d'arbitrage. Grâce à la solution, un petit nombre d'interfaces PCI-E sont disposées et l'efficacité d'interconnexion entre dispositifs est améliorée.
PCT/CN2014/090397 2014-06-30 2014-11-05 Procédé de traitement de signal et appareil de traitement de signal basés sur des interfaces pci-e WO2016000376A1 (fr)

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CN201410307173.8A CN105306421A (zh) 2014-06-30 2014-06-30 一种基于pci-e接口的信号处理方法及信号处理装置

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CN110543439A (zh) * 2019-09-10 2019-12-06 南方科技大学 一种信号处理系统
CN113961494A (zh) * 2021-10-21 2022-01-21 上海安路信息科技股份有限公司 一种pcie总线与axi总线的桥接系统
CN114938680A (zh) * 2020-10-12 2022-08-23 株式会社电装天 声音信号处理装置以及声音信号处理方法

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CN112668263B (zh) * 2020-12-29 2022-08-16 中国电子科技集团公司第五十八研究所 基于PCIe总线的处理层设计方法、结构及应用
CN117389935B (zh) * 2023-12-11 2024-03-08 井芯微电子技术(天津)有限公司 一种协议转换系统及方法

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CN110543439B (zh) * 2019-09-10 2023-05-12 南方科技大学 一种信号处理系统
CN114938680A (zh) * 2020-10-12 2022-08-23 株式会社电装天 声音信号处理装置以及声音信号处理方法
CN113961494A (zh) * 2021-10-21 2022-01-21 上海安路信息科技股份有限公司 一种pcie总线与axi总线的桥接系统
CN113961494B (zh) * 2021-10-21 2023-09-15 上海安路信息科技股份有限公司 一种pcie总线与axi总线的桥接系统

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