WO2016000376A1 - Signal processing method and signal processing apparatus based on pci-e interfaces - Google Patents

Abstract

The present invention relates to the field of signal processing. The present invention provides a signal processing method and a signal processing apparatus based on PCI-E interfaces. The signal processing method comprises: acquiring multiple different types of input signals; converting each of the multiple types of input signals into a transaction layer packet (TLP) packet satisfying a PCI-E bus format and buffering the TLP packet; performing arbitration control on the buffered TLP packet of each type of input signal; and providing the TLP packet of each type of input signal to a PCI-E controller for output according to the result of arbitration control. According to the solution, transmission control of multiple types of access signals is realized by arbitration control. By means of the solution, few PCI-E interfaces are arranged, and device interconnection efficiency is improved.

Description

Signal processing method and signal processing device based on PCI-E interface Technical field

The present invention relates to the field of signal processing, and in particular, to a signal processing method and a signal processing apparatus based on a PCI-E interface.

Background technique

PCI-E (Peripheral Component Interconnect Express) technology was proposed by Intel Corporation in 2001. At the end of 2002, it merged with AMD, DELL, IBM and other companies to form a technical specification named PCI-E. The third generation I/O bus standard. PCI-E uses the popular point-to-point serial connection in the industry. Each device has its own dedicated connection. It does not need to request bandwidth from the entire bus, and can increase the data transmission rate to a very high frequency. PCI-E Dual simplex connections provide higher transfer rates and quality. The PCI-E interface differs according to the bit width requirements of the bus interface, which are PCI-E 1X (250M/S), 2X, 4X, 8X, 16X, or even 32X. The 1X rate is the lowest and the 32X rate is the highest. This technology is widely used in industrial control, communication, and computer fields, and has become the mainstream of breakthrough transmission rate and fast interconnection. In the field of communications, Altera and Xilinx have introduced their own PCI-E core (PCI-E core) high-end FPGA (Field-Programmable Gate Array), also known as programmable controller ), the application of PCI-E to achieve 100G and 400G, more and more become the preferred solution for major communication vendors.

However, in the existing technical solution, the implementation of the PCI-E technology is for a specific signal or a specific format, and the transmission mode is single, which is difficult to meet the requirements for multiple signal access.

Summary of the invention

The embodiment of the invention provides a signal processing method and a signal processing device based on a PCI-E interface, so as to at least solve the problem that the prior art can only perform for a specific signal or a specific format when adopting the PCI-E high-speed transmission technology. Transmission, and a single transmission method, it is difficult to meet the problem of the need for multiple signal access.

In order to solve the above technical problem, an embodiment of the present invention provides a signal processing method based on a PCI-E interface, including:

Obtain different types of input signals of different types;

Converting each of the plurality of input signals into a transaction layer packet TLP message that satisfies the PCI-E bus format and buffering;

Arbitral control of the TLP message of each input signal buffered;

According to the result of the arbitration control, the TLP message of each input signal is output to the PCI-E controller.

Optionally, the plurality of signals comprise at least two of an SDH overhead signal, an OTN overhead signal, a DVB signal, and a CPU signal.

Optionally, the step of acquiring multiple types of input signals of different types is specifically: acquiring multiple types of input signals of different types, and storing each input signal in a cache unit, wherein the size of the cache unit is respectively Assigned according to the format of each input signal.

Optionally, the step of converting each of the plurality of input signals into a TLP message that satisfies a PCI-E bus format and buffering, respectively, includes:

Obtain processing priorities for different types of signals;

According to the order of processing priorities, each input signal is sequentially converted to obtain a TLP message satisfying each input signal of the PCI-E bus format and buffered.

Optionally, the step of performing arbitration control on the TLP message of each input signal that is buffered includes:

Get preset rules;

Performing arbitration control on the TLP message according to the preset rule;

The preset rule includes: a preset outflow order of each TLP packet, a preset priority between multiple TLP messages, a sending interval between TLP messages, and a processing method of an error packet.

The embodiment of the invention provides a signal processing device based on a PCI-E interface, including:

Obtaining a module, configured to obtain a plurality of input signals of different types;

a conversion module, configured to convert each of the plurality of input signals into a TLP message that satisfies a PCI-E bus format and cache the same;

a control module configured to arbitrate control of a TLP message of each input signal buffered;

The transmission module is configured to output a TLP message of each input signal to the PCI-E controller for output according to the result of the arbitration control.

Optionally, the acquiring module acquires multiple input signals of different types, and stores each input signal into a buffer unit, wherein the size of the buffer unit is respectively allocated according to a format of each input signal.

Optionally, the conversion module includes:

a first obtaining unit, configured to acquire processing priority of different types of signals;

The conversion unit is configured to sequentially perform conversion processing on each input signal in the order of the processing priority to obtain a TLP message satisfying each input signal of the PCI-E bus format and buffering.

Optionally, the control module includes:

a second obtaining unit, configured to acquire a preset rule;

a control unit, configured to perform arbitration control on the TLP message according to the preset rule;

The preset rule includes: a preset outflow order of each TLP packet, a preset priority between multiple TLP messages, a sending interval between TLP messages, and a processing method of an error packet.

The beneficial effects of the invention are:

The above solution realizes transmission control of multiple access signals by using arbitration control, and transmits to a PCI-E controller through a single interface. In this way, the setting of the PCI-E interface is reduced, and the processing efficiency of the signal is improved, and at the same time Improve equipment interconnection efficiency.

DRAWINGS

1 is a general flowchart of the signal processing method according to an embodiment of the present invention;

2 is a block diagram showing the signal processing apparatus according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of signal access according to an embodiment of the present invention; FIG.

4 is a schematic diagram showing a signal processing flow according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a module in an FPGA according to an embodiment of the present invention; FIG.

6 is a schematic diagram showing a signal processing process of an arbitration module in an FPGA according to an embodiment of the present invention;

Fig. 7 is a diagram showing the signal conversion of the embodiment of the present invention.

detailed description

The present invention will be described in detail below with reference to the drawings and specific embodiments.

The present invention is directed to the prior art that when the PCI-E high-speed transmission technology is adopted, the transmission can only be performed for a specific signal or a specific format, and the transmission mode is single, and it is difficult to meet the problem of demand for multiple signal access, and a problem is provided. A signal processing method and a signal processing device based on a PCI-E interface.

As shown in FIG. 1, the signal processing method of the embodiment of the present invention includes:

Step 10: acquiring multiple types of input signals of different types;

Step 20: Convert each input signal of the multiple input signals into a Transaction Layer Packet (TLP) message that satisfies the PCI-E bus format, and cache the signal;

Step 30: Perform arbitration control on the TLP message of each input signal that is buffered;

Step 40: According to the result of the arbitration control, the TLP message of each input signal is output to the PCI-E controller.

According to the above solution of the present invention, transmission control of multiple access signals is realized by using arbitration control, and is transmitted to the PCI-E controller through a single interface, thereby reducing the setting of the PCI-E interface and improving the interconnection efficiency of the device.

It should be noted that each input signal may be a CPU signal, an OTN (Optical Transport Network) overhead signal, an SDH (Synchronous Digital Hierarchy) signal, or a DVB (Digital Video Broadcasting). a signal and any signal capable of satisfying the PCI-E bus format after signal format conversion, the plurality of input signals comprising at least two of the above signals.

Specifically, after receiving a plurality of signals, each input signal is first stored in a buffer, and the buffer size occupied by the signal is correspondingly allocated according to the format of each input signal.

After the signal is received, the input signal needs to be formatted and converted into a transaction packet TLP packet that can satisfy the PCI-E bus format. The step 20 in the embodiment of the present invention is specifically:

Obtain processing priorities for different types of signals;

According to the order of processing priorities, each input signal is sequentially converted to obtain a TLP message satisfying each input signal of the PCI-E bus format and buffered.

First, the type of each input signal in the buffer is obtained, and then according to the processing priority of different types of signals, which signal is first converted, for example, the processing order of the signal is CPU signal, OTN overhead signal, if both of the above are exist in the buffer The signal firstly converts the format of the CPU signal. When the conversion of the CPU signal format is completed, the format conversion of the OTN overhead signal is performed. When the format conversion is performed, the preset conversion rule corresponding to the signal is called according to the type of each signal. , complete the format conversion of this kind of signal.

It should be noted that the signal format conversion process is well known to those skilled in the art and will not be described in detail herein.

After the format conversion of each input signal is completed, the transmission of each TLP message is performed. Before the transmission, the TLP message of each transaction packet needs to be sent and controlled. Therefore, the steps of the embodiment of the present invention are performed. 30 is specifically:

Get preset rules;

And performing arbitration control on the TLP message according to the preset rule.

It should be noted that the preset rule mainly includes: a preset outflow order of each TLP message, a priority between preset multiple TLP messages, a sending interval between TLP messages, and an error packet. According to the preset rule, the packet check is performed on each TLP packet, and the TLP packet can be sent only after the check is passed. In the transmission, the TLP packet is sequentially transmitted according to the priority order of the TLP packet. After the data in all the TLP packets is transmitted in the sequence, the next TLP packet can be transmitted after the preset interval is reached.

It should be noted that the arbitration control is actually processing a signal, that is, the PCI-E standard packet format, which simplifies the processing flow.

After the TLP packet is transmitted to the PCI-E controller, the PCI-E controller sends the TLP packet to the corresponding device to output the TLP packet according to the type of the TLP packet.

In the above solution, the received multiple input signals are respectively converted into corresponding data packets satisfying the PCI-E bus format, and then the data packets are respectively sent to the PCI-E by an interface through arbitration control. -E controller can receive multiple different signals through one interface, reduce interface settings, improve signal processing efficiency, improve device interconnection efficiency, and simplify signal docking between boards, saving The cost.

As shown in FIG. 2, the signal processing apparatus of the embodiment of the present invention includes:

Obtaining module 1, configured to acquire a plurality of input signals of different types;

The conversion module 2 is configured to respectively convert each of the plurality of input signals into a TLP message that satisfies the PCI-E bus format and cache the same;

The control module 3 is configured to perform arbitration control on the TLP message of each input signal buffered;

The sending module 4 is configured to output a TLP message of each input signal to the PCI-E controller according to the result of the arbitration control.

It should be noted that the obtaining module 1 is configured to acquire different types of input signals of different types, and store each input signal into the buffer unit separately, and the size of the buffer unit is respectively allocated according to the format of each input signal. of.

Specifically, the conversion module 2 includes:

a first obtaining unit, configured to acquire processing priority of different types of signals;

The conversion unit is configured to sequentially perform conversion processing on each input signal in the order of the processing priority to obtain a TLP message satisfying each input signal of the PCI-E bus format and buffering.

Specifically, the control module 3 includes:

a second obtaining unit, configured to acquire a preset rule;

The control unit is configured to perform arbitration control on the TLP message according to the preset rule.

It should be noted that the preset rule acquired by the second acquiring unit mainly includes: a preset outflow order of each TLP packet, a preset priority between multiple TLP packets, and a TLP packet. The sending interval and the processing method of the error packet.

It should be noted that the signal processing device embodiment is a signal processing device corresponding to the above signal processing method, and all implementations of the signal processing method are applicable to the signal processing device embodiment, and can also achieve the signal processing method. The same technical effect.

The following is a detailed description of the specific working process of the above signal control device. (It should be noted that since the flow direction of the signal is two-wire, the signal processing mechanism in the two directions is the same. The following example only uses the signal flow to the PCI-E. To illustrate: Take an FPGA with integrated PCI-E core (PCI-E core) as an example. PCI-E is integrated in the FPGA. The core is used for PCI-E transmission, and the transmission rate setting and PCI-E core setting can be configured according to the configuration wizard in an IDE (Integrated Drive Electronics) development environment.

As shown in FIG. 3, the PCI-E core includes SERDES (short for SERializer/DESerializer) and PCI-E, and the signal is transmitted between the PCI-E core and the arbitration module, all inputs. The signals (CPU signal, OTN overhead signal, SDH signal, DVB signal, etc.) are all connected to the arbitration module through the dedicated signal access pin of the FPGA, and then stored in the buffer (RAM), after the format conversion of the input signal is performed. Then, the various converted signals are subjected to abnormal processing, and the converted signal is subjected to arbitration control according to the arbitration profile accessed by the control signal, and then the converted signal is respectively sent to the PCI-E core via the cache.

As shown in FIG. 4, the processing flow of the signal is: a plurality of different kinds of input signals (such as CPU signal, OTN overhead signal, SDH signal) are first stored in the buffer RAM, and then the input signals in the buffer RAM are respectively passed. The corresponding format conversion rule is converted into a TLP message having a unified format, and then the flow control module performs exception processing on the signals according to the arbitration configuration information (ie, the preset rule described above) and outputs an abnormal processing result, and after the processing is completed, The TLP packets corresponding to the input signals are separately transmitted through the PCI-E core interface.

The following uses the xilinx FPGA as an example to describe the usage scenarios of the above methods in detail.

As shown in FIG. 5, the FPGA module includes a PCI-E module and an arbitration module;

The PCI-E module is instantiated using Vivado (Vivado Design Suite, an integrated design environment released by FPGA manufacturer Xilinx in 2012), consisting of a PCI-E core and a configuration module. The PCI-E core is mainly composed of PCI-E core. SERDES and PCI-E, the PCI-E module is mainly configured to complete the conversion of the PCI-E serial interface and process the PCI-E related protocol; wherein the PCI-E core is used by the IP core (IP core is used for Product application specific integrated circuit (ASIC) or FPGA logic block or data block is generated. Due to the complicated configuration of PCI-E, the configuration module is implemented separately outside the IP core. This configuration module not only completes the configuration of the RC (Root Complex) side. And complete the configuration of the EP (End Point) end (by configuring the TLP), it should be noted that the RC and the EP are respectively two modes of PCI-E;

The configuration module is composed of a Completion Decoder, a Controller, a Packet Generator, and a TX Mux. The configuration module is configured to send and receive service TLP packets. Only for transparent transmission, the PCI-E core and the configuration module are connected by AXI4-Stream (a bus protocol) interface, and the PCI-E module and the signal processing device are also connected using the AXI4-Stream interface.

As shown in FIG. 6, the arbitration module is in the PCI-E sending direction, and the module completes the arbitration of the CPU_TLP packet, the OTN_TLP packet, and the like, and uses a sequential polling mechanism (which can be modified by the configuration file cfg_file) as an example, and various TLPs. The packets have the same priority and are sequentially sent. In the PCI-E receiving direction, it is necessary to determine the response of the received packet to which signal, and according to the determination result, the packet is sent to the corresponding module; in addition, the arbitration module further It is necessary to implement the TLP packet reception failure determination function, and start timing after transmission. If the packet is not received after N ms (N is a parameter, which can be modified), the TLP packet reception failure is reported, and the failure indication signal is valid for at least one clock cycle. The number of failure registers is incremented by one, and the next TLP packet can be sent. The AXI bus is no longer occupied. In addition, the arbitration module also implements the AXI interface with the PCI-E IPcore, if the receiving clock and transmission are provided by the PCI-E IPcore. If the clock is not a clock, the module needs to perform cross-clock domain processing on the received TLP packet with FIFO (First Input First Output), and convert the received TLP packet into a transmission clock domain, for example, a cross-clock domain. After processing, the frequency of the receive and transmit clocks is 37.25MHz, but the frequency has a slight deviation.

The specific implementation of the processing flow of the signal in the arbitration module is:

As shown in FIG. 6, the TLP message after the signal conversion is completed is stored in the corresponding cache. For example, the TLP message completed by the CPU signal conversion is recorded as CPU_TLP, and the CPU_TLP is stored in the cache, and the cache field is recorded as CPU_TLP_BUFFER, the OTN message completed by the OTN signal is recorded as OTN_TLP, and the OTN_TLP is stored in the buffer, the buffer field is recorded as OTN_TLP_BUFFER, and then the flow control module (FLOW_CTRL) arbitrates the signal according to the configuration file (Cfg_file), and then The CPU_TLP and the OTN_TLP are respectively transmitted through the AXI interface; after the flow control module receives the signal transmitted by the AXI interface, the signal is also subjected to arbitration control according to the configuration file (Cfg_file), and then the received signal is transmitted.

It should be noted that the above arbitration module implements various control functions such as polling control, burst control, priority programmable control, and packet interval programmable control.

As shown in Figure 7, because the signal transmission is bidirectional, when receiving the TLP message sent in the PCI-E direction, it first determines the response of the received TLP message to which signal, and then separately reports the TLP. The text is converted into a signal conforming to the device by using the corresponding format conversion rule, and then the format converted signal is sent to the corresponding device; when the signal sent by the device is received, the corresponding format conversion rule is used. The signal format is converted into a TLP message, and then the TLP message is transmitted.

It should be noted that the above solution realizes flexible configuration, improves access speed, and saves cost by implementing multiple signal access on one device and simultaneously implementing arbitration control of multiple signals.

The above is a preferred embodiment of the present invention, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present invention. Within the scope of protection of the invention.

Industrial applicability

As described above, the PCI-E interface-based signal processing method and the signal processing apparatus provided by the embodiments of the present invention have the following beneficial effects: transmission control of multiple access signals is implemented by using arbitration control, and is sent to a single interface. The PCI-E controller reduces the setting of the PCI-E interface, improves the processing efficiency of the signal, and improves the interconnection efficiency of the device.

Claims (9)

A signal processing method based on a PCI-E interface, comprising: Obtain different types of input signals of different types; Converting each of the plurality of input signals into a transaction layer packet TLP message that satisfies the PCI-E bus format and buffering; Arbitral control of the TLP message of each input signal buffered; According to the result of the arbitration control, the TLP message of each input signal is output to the PCI-E controller. The signal processing method according to claim 1, wherein said plurality of signals comprise at least two of an SDH overhead signal, an OTN overhead signal, a DVB signal, and a CPU signal. The signal processing method according to claim 1, wherein the step of acquiring different types of input signals is specifically: acquiring different types of input signals, and storing each input signal in a cache unit, wherein The size of the cache unit is allocated according to the format of each input signal. The signal processing method according to claim 1, wherein the step of converting each of the plurality of input signals into a TLP message that satisfies a PCI-E bus format and buffering each comprises: Obtain processing priorities for different types of signals; According to the order of processing priorities, each input signal is sequentially converted to obtain a TLP message satisfying each input signal of the PCI-E bus format and buffered. The signal processing method according to claim 1, wherein said step of arbitrating control of a TLP message of each of the buffered input signals comprises: Get preset rules; Performing arbitration control on the TLP message according to the preset rule; The preset rule includes: a preset outflow order of each TLP packet, a preset priority between multiple TLP messages, a sending interval between TLP messages, and a processing method of an error packet. A signal processing device based on a PCI-E interface, comprising: Obtaining a module, configured to obtain a plurality of input signals of different types; a conversion module, configured to convert each of the plurality of input signals into a TLP message that satisfies a PCI-E bus format and cache the same; a control module configured to arbitrate control of a TLP message of each input signal buffered; The transmission module is configured to output a TLP message of each input signal to the PCI-E controller for output according to the result of the arbitration control. The signal processing device according to claim 6, wherein the acquisition module is configured to acquire a plurality of input signals of different types, and store each input signal in a cache unit, wherein the size of the cache unit is They are assigned according to the format of each input signal. The signal processing device of claim 6, wherein the conversion module comprises: a first obtaining unit, configured to acquire processing priority of different types of signals; The conversion unit is configured to sequentially perform conversion processing on each input signal in the order of the processing priority to obtain a TLP message satisfying each input signal of the PCI-E bus format and buffering. The signal processing device of claim 6, wherein the control module comprises: a second obtaining unit, configured to acquire a preset rule; a control unit, configured to perform arbitration control on the TLP message according to the preset rule; The preset rule includes: a preset outflow order of each TLP packet, a preset priority between multiple TLP messages, a sending interval between TLP messages, and a processing method of an error packet.

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