+

WO2013161116A1 - Dispositif semi-conducteur et son procédé de fabrication - Google Patents

Dispositif semi-conducteur et son procédé de fabrication Download PDF

Info

Publication number
WO2013161116A1
WO2013161116A1 PCT/JP2012/081140 JP2012081140W WO2013161116A1 WO 2013161116 A1 WO2013161116 A1 WO 2013161116A1 JP 2012081140 W JP2012081140 W JP 2012081140W WO 2013161116 A1 WO2013161116 A1 WO 2013161116A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor device
drift layer
conductivity type
impurity
Prior art date
Application number
PCT/JP2012/081140
Other languages
English (en)
Japanese (ja)
Inventor
和也 小西
中田　修平
梨菜 田中
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Publication of WO2013161116A1 publication Critical patent/WO2013161116A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/047—Making n or p doped regions or layers, e.g. using diffusion using ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/051—Manufacture or treatment of Schottky diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions

Definitions

  • the present invention relates to a super junction (SJ) structure of a semiconductor device.
  • Patent Document 1 discloses that an SJ structure is formed by selectively etching an n-type semiconductor layer to form a groove and epitaxially growing a p-layer inside the groove.
  • Patent Document 2 an n-type semiconductor layer is selectively etched to form a groove, a p-type semiconductor layer is formed on the side surface of the groove by an ion implantation method, and then the groove is filled with an insulator layer. A method of forming an SJ structure is shown.
  • Patent Document 1 it is necessary to go through an epitaxial process a plurality of times to form the SJ structure, which requires a great deal of cost and time. In addition, it has been difficult to stably perform a plurality of epitaxial processes on a SiC substrate.
  • an object of the present invention is to provide a semiconductor device having an SJ structure having further improved low on-resistance and high breakdown voltage, and a method for manufacturing the same.
  • a semiconductor device includes a semiconductor substrate and a first layer formed on the semiconductor substrate, and the first layer is disposed from the front surface to the back surface in contact with the semiconductor substrate and formed by epitaxial growth.
  • the first impurity region of the second conductivity type disposed in a distance, and the impurity concentration of the first impurity region decreases in the depth direction from the surface.
  • the method for manufacturing a semiconductor device includes: (a) a step of preparing a semiconductor substrate; (b) a step of forming a first conductivity type drift layer on the semiconductor substrate by epitaxial growth; Forming a groove having a predetermined depth; (d) implanting a second conductivity type impurity into the side wall of the groove to form a second conductivity type first impurity region; And a step (d) is a step of forming a first impurity region in which the impurity density decreases in the depth direction of the groove.
  • a semiconductor device includes a semiconductor substrate and a first layer formed on the semiconductor substrate, and the first layer is disposed from the front surface to the back surface in contact with the semiconductor substrate and formed by epitaxial growth.
  • the semiconductor device has a low on-resistance and a high breakdown voltage.
  • the method for manufacturing a semiconductor device includes: (a) a step of preparing a semiconductor substrate; (b) a step of forming a first conductivity type drift layer on the semiconductor substrate by epitaxial growth; Forming a groove having a predetermined depth; (d) implanting a second conductivity type impurity into the side wall of the groove to form a second conductivity type first impurity region; And a step (d) is a step of forming a first impurity region in which the impurity density decreases in the depth direction of the groove.
  • the SJ structure that realizes a low on-resistance and a high breakdown voltage is formed by one etching process and one ion implantation process, and the breakdown voltage is higher than that when the concentration of the second impurity region is uniformly formed. improves.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. It is a figure which shows the impurity concentration distribution of p layer. It is a figure which shows electric field strength distribution of the semiconductor device of this invention. It is a figure which shows the electric field strength distribution of an n drift layer. It is a figure which compares differential resistivity with normal SBD and the semiconductor device of this invention. It is a figure which shows the current density-voltage characteristic of the semiconductor device of this invention.
  • 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 6 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment.
  • 11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment.
  • FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment.
  • FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment.
  • FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment.
  • FIG. FIG. 6 is a cross-sectional view of a semiconductor device according to a third embodiment.
  • FIG. 6 is a cross-sectional view of a semiconductor device according to a fourth embodiment.
  • FIG. 6 is a cross-sectional view of a semiconductor device according to a fifth embodiment. It is sectional drawing of the semiconductor device which concerns on a premise technique. It is a figure which shows the electric field strength distribution of the semiconductor device which concerns on a premise technique.
  • FIG. 24 is a cross-sectional view of a Schottky barrier diode (SBD) as a semiconductor device of the prerequisite technology of the present invention.
  • the base technology SBD includes a substrate 1, a cathode electrode 11, an n drift layer 3, a p layer 6, and an anode electrode 9.
  • the substrate 1 is an n + type substrate, for example, a silicon carbide (SiC) substrate.
  • a cathode electrode 11 is formed on the lower surface of the substrate 1.
  • the thicknesses of the n drift layer 3 and the p layer 6 are all T1, and the anode electrode 9 is formed on these layers.
  • the anode electrode 9 is in Schottky contact with the n drift layer 3 and is in ohmic contact with the p layer 6.
  • the p-type impurity concentration of the p layer 6 is constant in the depth direction.
  • FIG. 25 shows a simulation result of the electric field intensity distribution in the portion D in the figure when a reverse voltage is applied between the anode electrode 9 and the cathode electrode 11 in the SBD of the base technology shown in FIG.
  • the width of the n drift layer 3 and the p layer 6 is 10 ⁇ m
  • the thickness of the n drift layer 3 and the p layer 6 is 22 ⁇ m
  • the impurity concentration of the n drift layer 3 is 1.5 ⁇ 10 16 / cm 3
  • the impurity concentration was calculated as 1 ⁇ 10 17 cm ⁇ 3 .
  • FIG. 25 shows that the darker the region is, the stronger the electric field strength.
  • n drift layer 3 for example, a portion where the electric field is locally high is formed at the interface between the n drift layer 3 and the anode electrode 9. An electric field of 2 MV / cm is applied to this portion when a reverse voltage of 2.5 kV is applied, and the electric field is uniformly distributed over the entire drift layer, which is a feature of the SJ structure, and a breakdown voltage cannot be secured.
  • the impurity concentration of the p layer 6 has a distribution in the depth direction so that the electric field is uniformly distributed throughout the drift layer when the reverse voltage is applied.
  • Embodiment 1 > ⁇ B-1.
  • Configuration> 1 is a cross-sectional view of a Schottky barrier diode (SBD) as a semiconductor device according to the first embodiment.
  • the SBD of the present embodiment includes a substrate 1, a cathode electrode 11, an n drift layer 3, an insulating layer 5, a p layer 6, and an anode electrode 9.
  • the substrate 1 is an n + type substrate, for example, a silicon carbide (SiC) substrate.
  • a cathode electrode 11 is formed on the lower surface of the substrate 1.
  • An n drift layer 3 and an insulating layer 5 are formed on the substrate 1 so as to be separated from each other. Further, the insulating layer 5 is sandwiched from both side surfaces so as to fill the gap between the insulating layer 5 and the n drift layer 3. Is formed.
  • the thicknesses of the n drift layer 3, the p layer 6, and the insulating layer 5 are all T1, and the anode electrode 9 is formed on these layers.
  • the anode electrode 9 is in Schottky contact with the n drift layer 3 and is in ohmic contact with the p layer 6.
  • the Schottky barrier diode of the first embodiment has an SJ structure in which an n drift layer 3, a p layer 6, and an insulating layer 5 are sequentially formed in the lateral direction as a first layer on the substrate 1.
  • FIG. 1 shows a structure in which the n drift layer 3, the p layer 6, the insulating layer 5, and the p layer 6 are repeated a plurality of times in this order in the horizontal direction, but the number of repetitions is not particularly limited.
  • the width L1 of the n drift layer 3 is 10 ⁇ m
  • the width L2 of the p layer 6 is 0.5 ⁇ m
  • the width L3 of the insulating layer 5 is 10 ⁇ m
  • the thickness T1 of these layers is 22 ⁇ m.
  • FIG. 2A is an enlarged view of a portion A in FIG. 1 and shows the insulating layer 5, the p layer 6, and the n drift layer 3.
  • FIG. 2B shows the impurity concentration distribution of the p layer 6 in the y-axis direction along BB ′ in FIG.
  • the impurity concentration of the p layer 6 has a distribution that decreases while having a flat region from the surface of the n drift layer 3 toward the substrate 1 side (back surface side).
  • the impurity concentration of the p layer 6 may be about 1 ⁇ 10 17 cm ⁇ 3 at the highest level, and 0 cm ⁇ 3 at the lowest level.
  • the distribution is such that it is the darkest on the substrate 1 side, the concentration is about 70 to 80% on the substrate 1 side, and is 0 cm ⁇ 3 at the bottom, the distribution width is somewhat increased.
  • the uniformity of the electric field strength can be improved and the breakdown voltage is improved.
  • the current is controlled by the Schottky barrier at the contact portion between the anode electrode 9 and the n drift layer 3, and the n drift layer 3
  • the depletion layer at the junction with the p layer 6 expands, and as a result, the n drift layer 3 becomes a depletion layer over the entire width direction.
  • the current in the reverse direction is cut off and a high breakdown voltage is realized.
  • FIG. 3 shows the electric field intensity distribution and equipotential lines in part A of FIG. 1 when a reverse voltage of 3.3 kV is applied between the anode electrode 9 and the cathode electrode 11.
  • the simulation was performed by setting the width of the n drift layer 3 and the insulating layer 5 to 10 ⁇ m, the width of the p layer 6 to 0.5 ⁇ m, and the thickness of each layer to 22 ⁇ m.
  • FIG. 3 shows the electric field intensity distributions of the n drift layer 3 and the insulating layer 5 by a width of 5 ⁇ m.
  • the impurity concentration of the n drift layer 3 is 1.5 ⁇ 10 16 / cm 3 .
  • the boundary portion with the p layer 6 and the upper portion on the CC ′ axis in FIG. 3 are regions with particularly strong electric field strength, both of which are 2 MV / cm or less.
  • FIG. 4 shows the electric field intensity distribution in the y-axis direction (see FIG. 3) along the C-C ′ axis of the n-type drift layer 3.
  • FIG. 4 shows a flat electric field strength characteristic in the depth range of 4 to 16 ⁇ m. For this reason, it is possible to reduce the thickness of the element and increase the impurity concentration of the n-type drift layer 3, and to improve the breakdown voltage while reducing the steady loss.
  • FIG. 5 shows the relationship between the breakdown voltage and the forward differential resistivity (relative value) in a normal SBD having no SJ structure, and the differential of the SBD of this embodiment having a breakdown voltage of 3.3 kV.
  • the resistivity is indicated by a square point.
  • a normal SBD has a differential resistivity of about 30 with a breakdown voltage of 3.3 kV, whereas in the present embodiment, the differential resistivity is significantly reduced to about 12.
  • FIG. 6 shows the forward current density characteristics of the SBD of the present embodiment.
  • the voltage value that changes from the SBD mode to the PN diode mode is much smaller than that of a normal JBS (JunctionuncBarrier Schottky diode) or the like. Has characteristics. This result leads to improvement of inrush current capability.
  • n + type substrate 1 is prepared, and an n type drift layer 3 is epitaxially grown thereon (FIG. 7).
  • a mask 13 is formed on the n drift layer 3.
  • the material of the mask 13 is not particularly limited, but tantalum carbide (TaC), aluminum nitride (AlN), diamond, or other materials can be used.
  • TaC tantalum carbide
  • AlN aluminum nitride
  • diamond diamond
  • an opening pattern is formed in the mask 13 using a lithography method, and the n drift layer 3 is partially removed by RIE using the mask 13. As a result, a groove 7 penetrating the n drift layer 3 is formed as shown in FIG.
  • sacrificial oxidation treatment is performed on the inner peripheral surface of the groove 7.
  • oxidation is performed at 1150 ° C.
  • a sacrificial oxide film is formed on the wafer surface.
  • the sacrificial oxide film is removed by etching with dilute hydrofluoric acid. Thereby, damage caused by etching by RIE at the time of forming the groove 7 is removed.
  • oblique rotation ion implantation is performed from the groove 7 to form the p layer 6 on the side wall of the groove (FIG. 9).
  • the p-layer 8 having an arbitrary impurity concentration distribution is formed on the side wall of the groove by performing oblique rotation ion implantation while changing the ion incident angle.
  • the p layer 6 having an impurity concentration distribution as shown in FIG. 2B is formed.
  • the implanted ions are B or Al, and the impurity concentration is, for example, 1 ⁇ 10 17 / cm 3 on the largest surface side.
  • a mask 14 having a pattern in which the groove 7 is opened is formed (FIG. 10), and the insulating layer 5 is formed inside the groove 7 by sputtering. Thereafter, the mask 14 is removed (FIG. 11).
  • sacrificial oxidation treatment is performed to cover the surfaces of the n drift layer 3, the p layer 6, and the insulating layer 5 with an oxide film.
  • oxidation is performed at 1150 ° C.
  • a sacrificial oxide film is formed on the wafer surface.
  • the sacrificial oxide film is removed by etching with dilute hydrofluoric acid.
  • an anode electrode 9 that covers the n drift layer 3, the p layer 6, and the insulating layer 5 is formed by a sputtering method.
  • Any material can be used for the anode electrode 9 as long as it can make Schottky contact with the n drift layer 3 and can make ohmic contact with the p layer 6.
  • titanium (Ti), molybdenum (Mo), or the like can be used.
  • the cathode electrode 11 is formed on the back surface of the substrate 1 by metal sputtering (FIG. 12).
  • the SBD having the configuration shown in FIG. 1 can be easily realized by a single etching step and ion implantation step without performing a plurality of epitaxial steps and etching steps.
  • the grooves 7 are formed in the n drift layer 3 in the same manner as in the manufacturing method 1 up to the step shown in FIG. Thereafter, oblique ion implantation is performed on the side wall near the bottom of the groove 7 under a low dose condition (FIG. 13).
  • the insulating layer 5 is formed up to about half the height of the groove 7, and oblique ion implantation is performed on the side wall of the groove 7 under medium dose conditions (FIG. 14).
  • the insulating layer 5 is formed to a height of about 2/3 of the groove 7, and oblique ion implantation is performed on the side wall of the groove 7 under a high dose condition (FIG. 15). In this manner, the formation of the insulating layer 5 and the ion implantation into the sidewall of the groove 7 are alternately repeated, and the dose amount of the ion implantation is increased each time it is repeated, whereby the p layer 6 having the impurity concentration distribution in the depth direction. Can be formed. Except for the process of forming the p layer 6 and the insulating layer 5, the manufacturing method 1 is the same as that of the manufacturing method 1, and the description thereof is omitted.
  • the groove 7 since the groove 7 penetrating the n drift layer 3 is formed, the groove 7 is formed with good controllability by utilizing the difference in material between the substrate 1 and the n drift layer 3. It is possible. However, the groove 7 may have a depth up to the middle of the n drift layer 3 to form an SBD having the structure shown in FIG. In the case where the depth of the groove 7 is halfway through the n drift layer 3, the etching time can be shortened and the cost can be reduced.
  • the semiconductor device of the present embodiment includes a substrate 1 (semiconductor substrate) and a first layer formed on the substrate 1.
  • the first layer is arranged from the front surface to the back surface in contact with the substrate 1 and is formed by epitaxial growth of the first conductivity type n drift layer 3 (drift layer), and n drift from the surface to a predetermined depth.
  • An insulating layer 5 spaced apart from the layer 3, and a second conductivity type p layer 6 in contact with and sandwiched between the insulating layer 5 and the n drift layer 3 over a predetermined depth from the surface)
  • the impurity concentration of the p layer 6 decreases from the surface in the depth direction.
  • the impurity concentration of the p layer 6 (first impurity region) has a distribution that decreases while having a region having a constant concentration in the center from the surface toward the depth direction.
  • the semiconductor device of the present embodiment further includes an anode electrode 9 formed on the surface of the first layer, and the anode electrode 9 is in Schottky contact with the n drift layer 3 and in ohmic contact with the p layer 6. . Therefore, a high breakdown voltage SBD is obtained in which the electric field strength during reverse voltage application is uniform in the n drift layer 3.
  • the first layer for maintaining the withstand voltage can be formed thinner, so that the on-resistance can be further reduced.
  • the manufacturing method of the first semiconductor device of the present embodiment includes (a) a step of preparing a substrate 1 (semiconductor substrate), and (b) a first conductivity type n drift layer 3 (drift layer) on the substrate 1. (C) a step of forming a trench 7 having a predetermined depth in the n drift layer 3, and (d) an impurity of the second conductivity type is implanted into the side wall of the trench 7 to form a second A step of forming a p-type conductive layer 6 (first impurity region); and (e) a step of filling the insulating layer 5 in the groove 7.
  • an SJ structure including the n drift layer 3, the p layer 6, and the insulating layer 5 can be easily formed by a single etching process and ion implantation process without going through a plurality of epitaxial processes.
  • the p layer 6 (first impurity region) in which the impurity concentration decreases in the depth direction of the groove 7 is formed. Therefore, compared with the case where the p layer 6 is formed with a constant impurity concentration, It becomes possible to make the electric field intensity when applying the reverse voltage more uniform, and the breakdown voltage is improved.
  • the impurity concentration of the p layer 6 (first impurity region) has a distribution that decreases while having a constant concentration region at the center in the depth direction of the groove 7. Since the p layer 6 is formed, it is possible to make the electric field strength when the reverse voltage is applied more uniform than when the p layer 6 is formed with a constant impurity concentration, and the breakdown voltage of the semiconductor device is improved. .
  • the p-type layer 6 is formed on the side wall of the groove 7 by implanting the second conductivity type impurity obliquely with respect to the depth direction of the groove 7. Further, by implanting while changing the implantation angle, it becomes possible to form the p layer 6 with the impurity concentration distribution in the depth direction.
  • the etching time can be shortened and the cost can be reduced.
  • the step (e) is a step of filling the insulating layer 5 in the groove 7 in a plurality of times, and the step (d) is repeatedly performed alternately with the step (e).
  • the p layer 6 can be formed with an impurity concentration distribution in the depth direction.
  • FIG. 20 is a cross-sectional view showing a configuration of an SBD as a semiconductor device according to the second embodiment. Except for the insulating layer 5 having a tapered shape, it is the same as the SBD of the first embodiment shown in FIG.
  • n type drift layer 3 is epitaxially grown on an n + type substrate 1.
  • a mask 13 is formed on the n drift layer 3.
  • an opening pattern is formed in the mask 13 using a lithography method, and a tapered groove 17 having an opening that increases from the bottom to the surface side is formed using the mask 13 (FIG. 17).
  • the tapered shape of the groove 17 is formed by side etching with respect to the mask 13, and the taper angle is set to several degrees to about 30 degrees.
  • N or P is ion-implanted perpendicularly to the wafer using the mask 13 to form an n + layer 18 on the side wall near the bottom of the groove 17 (FIG. 18).
  • the mask 13 is removed and then B or Al is ion-implanted as a p-type impurity to form the p layer 6 (FIG. 19).
  • the impurity concentration is lower than in the region where the p-type impurity is ion-implanted into the n layer 3. Therefore, it is possible to form the p layer 6 having a distribution in which the impurity concentration decreases while having a flat region from the surface of the n drift layer 3 toward the substrate 1 side without performing oblique ion implantation. Thereby, since the uniformity of the electric field strength can be improved, the breakdown voltage can be improved and a stable SJ structure can be produced.
  • the p layer 6 is removed from the upper surface of the n drift layer 3, and the anode electrode 9 and the cathode electrode 11 are formed in the same manner as in the manufacturing method of the first embodiment (FIG. 20).
  • the groove 7 is formed in a tapered shape in the step (c), and (g) the groove 7 is formed between the step (c) and the step (d) for forming the p layer 6. Since the first conductivity type impurity is implanted into the side wall near the bottom of the substrate from the direction perpendicular to the substrate 1, the impurity concentration is increased in the depth direction without controlling the implantation angle and performing oblique implantation. A decreasing p-layer 6 can be formed.
  • FIG. 21 is a cross-sectional view of a JBS as a semiconductor device according to the third embodiment.
  • the p-layer 6 is selectively formed on the surface of the n drift layer 3 in the configuration of the SBD according to the first embodiment shown in FIG.
  • the depletion layer spreads from the p layer 16 when a reverse voltage is applied, so that the electric field strength can be made more uniform and the leakage current can be reduced.
  • the semiconductor device of the present embodiment has a second conductivity type p layer 16 (second layer) selectively disposed on the surface of the n drift layer 3 (drift layer).
  • the JBS further includes an impurity region. When a reverse voltage is applied, a depletion layer extends from the p layer 16 to the n drift layer 3, so that the electric field strength can be made more uniform and the leakage current is reduced.
  • the first layer for maintaining the withstand voltage can be formed thinner, so that the on-resistance can be further reduced.
  • FIG. 22 is a cross-sectional view of a metal oxide semiconductor (MOS) as a semiconductor device according to the fourth embodiment.
  • the MOS according to the fourth embodiment is a MOS to which the SJ structure according to the first embodiment shown in FIG. 1 is applied, and can secure a sufficient breakdown voltage as compared with the conventional MOS. Therefore, the impurity concentration of the n drift layer 3 is reduced. Can be high. For this reason, the electrical resistance of the current path can be set low.
  • a p base region 21, a p body region 22, and an n + source layer 23 are provided on the surface of the n drift layer 3 in the SBD structure shown in FIG.
  • a drain electrode 25 is provided in place of the electrode 24 in place of the cathode electrode 11.
  • a gate electrode 27 is provided on the n + source layer 23, the p base region 21, and the n drift layer 3 through the gate oxide film 19. The gate electrode 27 and the source electrode 24 are insulated by the interlayer insulating film 20.
  • the MOS according to the present embodiment is selectively provided on the surface of the n drift layer 3 with a p base region 21 and on the surface of the p base region 21 with an impurity concentration higher than that of the p base region 21.
  • FIG. 23 is a cross-sectional view of a trench MOS as a semiconductor device according to the fifth embodiment.
  • the trench MOS according to the fifth embodiment is a trench MOS to which the SJ structure according to the first embodiment shown in FIG. 1 is applied, and a sufficient breakdown voltage can be secured as compared with the conventional trench MOS. Impurity concentration can be increased. For this reason, the electrical resistance of the current path can be set low.
  • the trench MOS of the fifth embodiment is obtained by changing the gate electrode 27 to a trench gate in the MOS of the fourth embodiment shown in FIG. That is, the trench 26 is formed in the n drift layer 3 from the surface to a predetermined depth, and the p base region 21 is selectively formed on the surface of the n drift layer 3 sandwiching the trench 26. On the surface of the p base region 21, a p body region 22 having an impurity concentration higher than that of the p base region 21 and an n + source layer 23 having an impurity concentration higher than that of the n drift layer 3 are selectively provided. The n + source layer 23 is provided adjacent to the trench 26. A gate oxide film 19 is provided in the trench 26, and a gate electrode 27 is provided on the gate oxide film 19 so as to be embedded in the trench 26. The other configuration is the same as that of the MOS of the fourth embodiment.
  • the trench 26 is selectively formed from the surface of the n drift layer 3 to a predetermined depth, and is selectively provided on the surface of the n drift layer 3 sandwiching the trench 26.
  • a source electrode 24 formed on the n + source layer 23, and a drain electrode 25 formed on the back surface of the substrate 1 are provided.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'objet de la présente invention est un dispositif semi-conducteur ayant une faible résistance à l'état passant et une haute tension de tenue, et un procédé de fabrication du dispositif semi-conducteur. Le dispositif semi-conducteur comporte un substrat (1), et une première couche formée sur le substrat (1). La première couche comporte : une couche de dérive de type n (3), laquelle est disposée sur la surface avant vers la surface arrière en contact avec le substrat (1), et est formée par croissance épitaxique ; une couche isolante (5), laquelle est disposée pour une profondeur préétablie depuis la surface avant en étant séparée de la couche de dérive de type n (3) ; et une couche du second type de conductivité p (6), laquelle est disposée pour une profondeur préétablie depuis la surface avant en étant en contact avec et intercalée entre la couche isolante (5) et la couche de dérive de type n (3). La concentration en impuretés de la couche de type p (6) est réduite dans la direction de la profondeur depuis la surface avant.
PCT/JP2012/081140 2012-04-26 2012-11-30 Dispositif semi-conducteur et son procédé de fabrication WO2013161116A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012-100852 2012-04-26
JP2012100852 2012-04-26

Publications (1)

Publication Number Publication Date
WO2013161116A1 true WO2013161116A1 (fr) 2013-10-31

Family

ID=49482477

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/081140 WO2013161116A1 (fr) 2012-04-26 2012-11-30 Dispositif semi-conducteur et son procédé de fabrication

Country Status (2)

Country Link
JP (1) JPWO2013161116A1 (fr)
WO (1) WO2013161116A1 (fr)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104393055A (zh) * 2014-11-10 2015-03-04 电子科技大学 一种具有浮岛结构的沟槽型二极管
WO2015174380A1 (fr) * 2014-05-12 2015-11-19 ローム株式会社 Dispositif à semi-conducteurs et procédé de fabrication de dispositif à semi-conducteurs
JP2016129226A (ja) * 2014-12-22 2016-07-14 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ ストライプ状トレンチゲート構造とゲートコネクタ構造とを有する半導体装置
WO2017119066A1 (fr) * 2016-01-05 2017-07-13 三菱電機株式会社 Dispositif à semi-conducteur au carbure de silicium
JP2018010983A (ja) * 2016-07-14 2018-01-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN108269848A (zh) * 2016-12-31 2018-07-10 朱江 一种沟槽肖特基半导体装置
JP2019057729A (ja) * 2018-12-11 2019-04-11 ローム株式会社 ＳｉＣ半導体装置およびその製造方法
JP2019517132A (ja) * 2016-04-07 2019-06-20 アーベーベー・シュバイツ・アーゲー 短チャネルのトレンチパワーｍｏｓｆｅｔ
JP2020013059A (ja) * 2018-07-20 2020-01-23 株式会社東芝 装置の製造方法
CN112514037A (zh) * 2018-07-27 2021-03-16 日产自动车株式会社 半导体装置及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02137368A (ja) * 1988-11-18 1990-05-25 Toshiba Corp 半導体整流装置
JP2004072068A (ja) * 2002-06-14 2004-03-04 Fuji Electric Holdings Co Ltd 半導体素子
JP2005197288A (ja) * 2003-12-26 2005-07-21 Rohm Co Ltd 半導体装置の製造方法および半導体装置
JP2007019146A (ja) * 2005-07-06 2007-01-25 Toshiba Corp 半導体素子
JP2007235080A (ja) * 2006-01-31 2007-09-13 Fuji Electric Holdings Co Ltd 半導体装置の製造方法
US20090179298A1 (en) * 2008-01-11 2009-07-16 Icemos Technology Ltd. Superjunction device having a dielectric termination and methods for manufacturing the device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006186145A (ja) * 2004-12-28 2006-07-13 Toshiba Corp 半導体装置及びその製造方法
JP2008124346A (ja) * 2006-11-14 2008-05-29 Toshiba Corp 電力用半導体素子
JP2009004668A (ja) * 2007-06-25 2009-01-08 Toshiba Corp 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02137368A (ja) * 1988-11-18 1990-05-25 Toshiba Corp 半導体整流装置
JP2004072068A (ja) * 2002-06-14 2004-03-04 Fuji Electric Holdings Co Ltd 半導体素子
JP2005197288A (ja) * 2003-12-26 2005-07-21 Rohm Co Ltd 半導体装置の製造方法および半導体装置
JP2007019146A (ja) * 2005-07-06 2007-01-25 Toshiba Corp 半導体素子
JP2007235080A (ja) * 2006-01-31 2007-09-13 Fuji Electric Holdings Co Ltd 半導体装置の製造方法
US20090179298A1 (en) * 2008-01-11 2009-07-16 Icemos Technology Ltd. Superjunction device having a dielectric termination and methods for manufacturing the device

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113054038B (zh) * 2014-05-12 2024-07-02 罗姆股份有限公司 半导体装置及半导体装置的制造方法
WO2015174380A1 (fr) * 2014-05-12 2015-11-19 ローム株式会社 Dispositif à semi-conducteurs et procédé de fabrication de dispositif à semi-conducteurs
JP2015216270A (ja) * 2014-05-12 2015-12-03 ローム株式会社 半導体装置および半導体装置の製造方法
CN106463546B (zh) * 2014-05-12 2022-01-04 罗姆股份有限公司 半导体装置及半导体装置的制造方法
CN106463546A (zh) * 2014-05-12 2017-02-22 罗姆股份有限公司 半导体装置及半导体装置的制造方法
US20170077318A1 (en) * 2014-05-12 2017-03-16 Rohm Co., Ltd. Semiconductor device and semiconductor device manufacturing method
CN113054038A (zh) * 2014-05-12 2021-06-29 罗姆股份有限公司 半导体装置及半导体装置的制造方法
US10109749B2 (en) 2014-05-12 2018-10-23 Rohm Co., Ltd. Semiconductor device and semiconductor device manufacturing method
US9876124B2 (en) 2014-05-12 2018-01-23 Rohm Co., Ltd. Semiconductor device and semiconductor device manufacturing method
CN104393055A (zh) * 2014-11-10 2015-03-04 电子科技大学 一种具有浮岛结构的沟槽型二极管
US9960243B2 (en) 2014-12-22 2018-05-01 Infineon Technologies Ag Semiconductor device with stripe-shaped trench gate structures and gate connector structure
JP2016129226A (ja) * 2014-12-22 2016-07-14 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ ストライプ状トレンチゲート構造とゲートコネクタ構造とを有する半導体装置
JPWO2017119066A1 (ja) * 2016-01-05 2018-04-19 三菱電機株式会社 炭化珪素半導体装置
US20180337175A1 (en) * 2016-01-05 2018-11-22 Mitsubishi Electric Corporation Silicon carbide semiconductor device
WO2017119066A1 (fr) * 2016-01-05 2017-07-13 三菱電機株式会社 Dispositif à semi-conducteur au carbure de silicium
US10529709B2 (en) 2016-01-05 2020-01-07 Mitsubishi Electric Corporation Silicon carbide semiconductor device having high breakdown voltage and low on resistance
JP2019517132A (ja) * 2016-04-07 2019-06-20 アーベーベー・シュバイツ・アーゲー 短チャネルのトレンチパワーｍｏｓｆｅｔ
CN107623025A (zh) * 2016-07-14 2018-01-23 瑞萨电子株式会社 半导体器件及其制造方法
JP2018010983A (ja) * 2016-07-14 2018-01-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10727105B2 (en) 2016-07-14 2020-07-28 Rensas Electronics Corporation Semiconductor device and manufacturing method therefor
CN108269848A (zh) * 2016-12-31 2018-07-10 朱江 一种沟槽肖特基半导体装置
JP2020013059A (ja) * 2018-07-20 2020-01-23 株式会社東芝 装置の製造方法
CN112514037A (zh) * 2018-07-27 2021-03-16 日产自动车株式会社 半导体装置及其制造方法
JP2019057729A (ja) * 2018-12-11 2019-04-11 ローム株式会社 ＳｉＣ半導体装置およびその製造方法

Also Published As

Publication number Publication date
JPWO2013161116A1 (ja) 2015-12-21

Similar Documents

Publication Publication Date Title
TWI605596B (zh) 絕緣閘切換裝置及其製造方法
WO2013161116A1 (fr) Dispositif semi-conducteur et son procédé de fabrication
KR102204272B1 (ko) 게이트 트렌치들 및 매립된 종단 구조체들을 갖는 전력 반도체 디바이스들 및 관련 방법들
US20190288107A1 (en) Silicon carbide semiconductor device and method for manufacturing same
JP5745997B2 (ja) スイッチング素子とその製造方法
JP5395309B2 (ja) 半導体装置およびその製造方法
JP6475635B2 (ja) ゲート酸化膜層において電界を低下させた半導体デバイス
JP6214680B2 (ja) 炭化珪素半導体装置
JP5697744B2 (ja) 半導体装置およびその製造方法
JP2017139440A (ja) 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JPWO2015049815A1 (ja) 炭化珪素半導体装置
CN107039268B (zh) 碳化硅半导体装置及碳化硅半导体装置的制造方法
JP6766512B2 (ja) 半導体装置および半導体装置の製造方法
JP5473397B2 (ja) 半導体装置およびその製造方法
JP6903222B2 (ja) 炭化珪素半導体装置およびその製造方法
WO2012098861A1 (fr) Dispositif à semiconducteur et procédé pour sa fabrication
JP2015207723A (ja) 炭化珪素半導体装置およびその製造方法
WO2012105170A1 (fr) Dispositif semi-conducteur et procédé de fabrication associé
JP5473398B2 (ja) 半導体装置およびその製造方法
JP2015023115A (ja) ショットキーダイオードを内蔵するｆｅｔ
US9548399B2 (en) Junction field effect transistor cell with lateral channel region
WO2014102979A1 (fr) Dispositif à semiconducteurs et son procédé de fabrication
US11024502B2 (en) Semiconductor devices and methods for forming semiconductor devices
JP6539026B2 (ja) 半導体装置及びその製造方法
KR20130017054A (ko) 반도체 소자 및 그 제조 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12875627

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2014512295

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12875627

Country of ref document: EP

Kind code of ref document: A1

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载