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WO2013161116A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2013161116A1
WO2013161116A1 PCT/JP2012/081140 JP2012081140W WO2013161116A1 WO 2013161116 A1 WO2013161116 A1 WO 2013161116A1 JP 2012081140 W JP2012081140 W JP 2012081140W WO 2013161116 A1 WO2013161116 A1 WO 2013161116A1
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Prior art keywords
layer
semiconductor device
drift layer
conductivity type
impurity
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PCT/JP2012/081140
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French (fr)
Japanese (ja)
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和也 小西
中田　修平
梨菜 田中
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三菱電機株式会社
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Publication of WO2013161116A1 publication Critical patent/WO2013161116A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/047—Making n or p doped regions or layers, e.g. using diffusion using ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/051—Manufacture or treatment of Schottky diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions

Definitions

  • the present invention relates to a super junction (SJ) structure of a semiconductor device.
  • Patent Document 1 discloses that an SJ structure is formed by selectively etching an n-type semiconductor layer to form a groove and epitaxially growing a p-layer inside the groove.
  • Patent Document 2 an n-type semiconductor layer is selectively etched to form a groove, a p-type semiconductor layer is formed on the side surface of the groove by an ion implantation method, and then the groove is filled with an insulator layer. A method of forming an SJ structure is shown.
  • Patent Document 1 it is necessary to go through an epitaxial process a plurality of times to form the SJ structure, which requires a great deal of cost and time. In addition, it has been difficult to stably perform a plurality of epitaxial processes on a SiC substrate.
  • an object of the present invention is to provide a semiconductor device having an SJ structure having further improved low on-resistance and high breakdown voltage, and a method for manufacturing the same.
  • a semiconductor device includes a semiconductor substrate and a first layer formed on the semiconductor substrate, and the first layer is disposed from the front surface to the back surface in contact with the semiconductor substrate and formed by epitaxial growth.
  • the first impurity region of the second conductivity type disposed in a distance, and the impurity concentration of the first impurity region decreases in the depth direction from the surface.
  • the method for manufacturing a semiconductor device includes: (a) a step of preparing a semiconductor substrate; (b) a step of forming a first conductivity type drift layer on the semiconductor substrate by epitaxial growth; Forming a groove having a predetermined depth; (d) implanting a second conductivity type impurity into the side wall of the groove to form a second conductivity type first impurity region; And a step (d) is a step of forming a first impurity region in which the impurity density decreases in the depth direction of the groove.
  • a semiconductor device includes a semiconductor substrate and a first layer formed on the semiconductor substrate, and the first layer is disposed from the front surface to the back surface in contact with the semiconductor substrate and formed by epitaxial growth.
  • the semiconductor device has a low on-resistance and a high breakdown voltage.
  • the method for manufacturing a semiconductor device includes: (a) a step of preparing a semiconductor substrate; (b) a step of forming a first conductivity type drift layer on the semiconductor substrate by epitaxial growth; Forming a groove having a predetermined depth; (d) implanting a second conductivity type impurity into the side wall of the groove to form a second conductivity type first impurity region; And a step (d) is a step of forming a first impurity region in which the impurity density decreases in the depth direction of the groove.
  • the SJ structure that realizes a low on-resistance and a high breakdown voltage is formed by one etching process and one ion implantation process, and the breakdown voltage is higher than that when the concentration of the second impurity region is uniformly formed. improves.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. It is a figure which shows the impurity concentration distribution of p layer. It is a figure which shows electric field strength distribution of the semiconductor device of this invention. It is a figure which shows the electric field strength distribution of an n drift layer. It is a figure which compares differential resistivity with normal SBD and the semiconductor device of this invention. It is a figure which shows the current density-voltage characteristic of the semiconductor device of this invention.
  • 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment.
  • FIG. 6 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment.
  • 11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment.
  • FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment.
  • FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment.
  • FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment.
  • FIG. FIG. 6 is a cross-sectional view of a semiconductor device according to a third embodiment.
  • FIG. 6 is a cross-sectional view of a semiconductor device according to a fourth embodiment.
  • FIG. 6 is a cross-sectional view of a semiconductor device according to a fifth embodiment. It is sectional drawing of the semiconductor device which concerns on a premise technique. It is a figure which shows the electric field strength distribution of the semiconductor device which concerns on a premise technique.
  • FIG. 24 is a cross-sectional view of a Schottky barrier diode (SBD) as a semiconductor device of the prerequisite technology of the present invention.
  • the base technology SBD includes a substrate 1, a cathode electrode 11, an n drift layer 3, a p layer 6, and an anode electrode 9.
  • the substrate 1 is an n + type substrate, for example, a silicon carbide (SiC) substrate.
  • a cathode electrode 11 is formed on the lower surface of the substrate 1.
  • the thicknesses of the n drift layer 3 and the p layer 6 are all T1, and the anode electrode 9 is formed on these layers.
  • the anode electrode 9 is in Schottky contact with the n drift layer 3 and is in ohmic contact with the p layer 6.
  • the p-type impurity concentration of the p layer 6 is constant in the depth direction.
  • FIG. 25 shows a simulation result of the electric field intensity distribution in the portion D in the figure when a reverse voltage is applied between the anode electrode 9 and the cathode electrode 11 in the SBD of the base technology shown in FIG.
  • the width of the n drift layer 3 and the p layer 6 is 10 ⁇ m
  • the thickness of the n drift layer 3 and the p layer 6 is 22 ⁇ m
  • the impurity concentration of the n drift layer 3 is 1.5 ⁇ 10 16 / cm 3
  • the impurity concentration was calculated as 1 ⁇ 10 17 cm ⁇ 3 .
  • FIG. 25 shows that the darker the region is, the stronger the electric field strength.
  • n drift layer 3 for example, a portion where the electric field is locally high is formed at the interface between the n drift layer 3 and the anode electrode 9. An electric field of 2 MV / cm is applied to this portion when a reverse voltage of 2.5 kV is applied, and the electric field is uniformly distributed over the entire drift layer, which is a feature of the SJ structure, and a breakdown voltage cannot be secured.
  • the impurity concentration of the p layer 6 has a distribution in the depth direction so that the electric field is uniformly distributed throughout the drift layer when the reverse voltage is applied.
  • Embodiment 1 > ⁇ B-1.
  • Configuration> 1 is a cross-sectional view of a Schottky barrier diode (SBD) as a semiconductor device according to the first embodiment.
  • the SBD of the present embodiment includes a substrate 1, a cathode electrode 11, an n drift layer 3, an insulating layer 5, a p layer 6, and an anode electrode 9.
  • the substrate 1 is an n + type substrate, for example, a silicon carbide (SiC) substrate.
  • a cathode electrode 11 is formed on the lower surface of the substrate 1.
  • An n drift layer 3 and an insulating layer 5 are formed on the substrate 1 so as to be separated from each other. Further, the insulating layer 5 is sandwiched from both side surfaces so as to fill the gap between the insulating layer 5 and the n drift layer 3. Is formed.
  • the thicknesses of the n drift layer 3, the p layer 6, and the insulating layer 5 are all T1, and the anode electrode 9 is formed on these layers.
  • the anode electrode 9 is in Schottky contact with the n drift layer 3 and is in ohmic contact with the p layer 6.
  • the Schottky barrier diode of the first embodiment has an SJ structure in which an n drift layer 3, a p layer 6, and an insulating layer 5 are sequentially formed in the lateral direction as a first layer on the substrate 1.
  • FIG. 1 shows a structure in which the n drift layer 3, the p layer 6, the insulating layer 5, and the p layer 6 are repeated a plurality of times in this order in the horizontal direction, but the number of repetitions is not particularly limited.
  • the width L1 of the n drift layer 3 is 10 ⁇ m
  • the width L2 of the p layer 6 is 0.5 ⁇ m
  • the width L3 of the insulating layer 5 is 10 ⁇ m
  • the thickness T1 of these layers is 22 ⁇ m.
  • FIG. 2A is an enlarged view of a portion A in FIG. 1 and shows the insulating layer 5, the p layer 6, and the n drift layer 3.
  • FIG. 2B shows the impurity concentration distribution of the p layer 6 in the y-axis direction along BB ′ in FIG.
  • the impurity concentration of the p layer 6 has a distribution that decreases while having a flat region from the surface of the n drift layer 3 toward the substrate 1 side (back surface side).
  • the impurity concentration of the p layer 6 may be about 1 ⁇ 10 17 cm ⁇ 3 at the highest level, and 0 cm ⁇ 3 at the lowest level.
  • the distribution is such that it is the darkest on the substrate 1 side, the concentration is about 70 to 80% on the substrate 1 side, and is 0 cm ⁇ 3 at the bottom, the distribution width is somewhat increased.
  • the uniformity of the electric field strength can be improved and the breakdown voltage is improved.
  • the current is controlled by the Schottky barrier at the contact portion between the anode electrode 9 and the n drift layer 3, and the n drift layer 3
  • the depletion layer at the junction with the p layer 6 expands, and as a result, the n drift layer 3 becomes a depletion layer over the entire width direction.
  • the current in the reverse direction is cut off and a high breakdown voltage is realized.
  • FIG. 3 shows the electric field intensity distribution and equipotential lines in part A of FIG. 1 when a reverse voltage of 3.3 kV is applied between the anode electrode 9 and the cathode electrode 11.
  • the simulation was performed by setting the width of the n drift layer 3 and the insulating layer 5 to 10 ⁇ m, the width of the p layer 6 to 0.5 ⁇ m, and the thickness of each layer to 22 ⁇ m.
  • FIG. 3 shows the electric field intensity distributions of the n drift layer 3 and the insulating layer 5 by a width of 5 ⁇ m.
  • the impurity concentration of the n drift layer 3 is 1.5 ⁇ 10 16 / cm 3 .
  • the boundary portion with the p layer 6 and the upper portion on the CC ′ axis in FIG. 3 are regions with particularly strong electric field strength, both of which are 2 MV / cm or less.
  • FIG. 4 shows the electric field intensity distribution in the y-axis direction (see FIG. 3) along the C-C ′ axis of the n-type drift layer 3.
  • FIG. 4 shows a flat electric field strength characteristic in the depth range of 4 to 16 ⁇ m. For this reason, it is possible to reduce the thickness of the element and increase the impurity concentration of the n-type drift layer 3, and to improve the breakdown voltage while reducing the steady loss.
  • FIG. 5 shows the relationship between the breakdown voltage and the forward differential resistivity (relative value) in a normal SBD having no SJ structure, and the differential of the SBD of this embodiment having a breakdown voltage of 3.3 kV.
  • the resistivity is indicated by a square point.
  • a normal SBD has a differential resistivity of about 30 with a breakdown voltage of 3.3 kV, whereas in the present embodiment, the differential resistivity is significantly reduced to about 12.
  • FIG. 6 shows the forward current density characteristics of the SBD of the present embodiment.
  • the voltage value that changes from the SBD mode to the PN diode mode is much smaller than that of a normal JBS (JunctionuncBarrier Schottky diode) or the like. Has characteristics. This result leads to improvement of inrush current capability.
  • n + type substrate 1 is prepared, and an n type drift layer 3 is epitaxially grown thereon (FIG. 7).
  • a mask 13 is formed on the n drift layer 3.
  • the material of the mask 13 is not particularly limited, but tantalum carbide (TaC), aluminum nitride (AlN), diamond, or other materials can be used.
  • TaC tantalum carbide
  • AlN aluminum nitride
  • diamond diamond
  • an opening pattern is formed in the mask 13 using a lithography method, and the n drift layer 3 is partially removed by RIE using the mask 13. As a result, a groove 7 penetrating the n drift layer 3 is formed as shown in FIG.
  • sacrificial oxidation treatment is performed on the inner peripheral surface of the groove 7.
  • oxidation is performed at 1150 ° C.
  • a sacrificial oxide film is formed on the wafer surface.
  • the sacrificial oxide film is removed by etching with dilute hydrofluoric acid. Thereby, damage caused by etching by RIE at the time of forming the groove 7 is removed.
  • oblique rotation ion implantation is performed from the groove 7 to form the p layer 6 on the side wall of the groove (FIG. 9).
  • the p-layer 8 having an arbitrary impurity concentration distribution is formed on the side wall of the groove by performing oblique rotation ion implantation while changing the ion incident angle.
  • the p layer 6 having an impurity concentration distribution as shown in FIG. 2B is formed.
  • the implanted ions are B or Al, and the impurity concentration is, for example, 1 ⁇ 10 17 / cm 3 on the largest surface side.
  • a mask 14 having a pattern in which the groove 7 is opened is formed (FIG. 10), and the insulating layer 5 is formed inside the groove 7 by sputtering. Thereafter, the mask 14 is removed (FIG. 11).
  • sacrificial oxidation treatment is performed to cover the surfaces of the n drift layer 3, the p layer 6, and the insulating layer 5 with an oxide film.
  • oxidation is performed at 1150 ° C.
  • a sacrificial oxide film is formed on the wafer surface.
  • the sacrificial oxide film is removed by etching with dilute hydrofluoric acid.
  • an anode electrode 9 that covers the n drift layer 3, the p layer 6, and the insulating layer 5 is formed by a sputtering method.
  • Any material can be used for the anode electrode 9 as long as it can make Schottky contact with the n drift layer 3 and can make ohmic contact with the p layer 6.
  • titanium (Ti), molybdenum (Mo), or the like can be used.
  • the cathode electrode 11 is formed on the back surface of the substrate 1 by metal sputtering (FIG. 12).
  • the SBD having the configuration shown in FIG. 1 can be easily realized by a single etching step and ion implantation step without performing a plurality of epitaxial steps and etching steps.
  • the grooves 7 are formed in the n drift layer 3 in the same manner as in the manufacturing method 1 up to the step shown in FIG. Thereafter, oblique ion implantation is performed on the side wall near the bottom of the groove 7 under a low dose condition (FIG. 13).
  • the insulating layer 5 is formed up to about half the height of the groove 7, and oblique ion implantation is performed on the side wall of the groove 7 under medium dose conditions (FIG. 14).
  • the insulating layer 5 is formed to a height of about 2/3 of the groove 7, and oblique ion implantation is performed on the side wall of the groove 7 under a high dose condition (FIG. 15). In this manner, the formation of the insulating layer 5 and the ion implantation into the sidewall of the groove 7 are alternately repeated, and the dose amount of the ion implantation is increased each time it is repeated, whereby the p layer 6 having the impurity concentration distribution in the depth direction. Can be formed. Except for the process of forming the p layer 6 and the insulating layer 5, the manufacturing method 1 is the same as that of the manufacturing method 1, and the description thereof is omitted.
  • the groove 7 since the groove 7 penetrating the n drift layer 3 is formed, the groove 7 is formed with good controllability by utilizing the difference in material between the substrate 1 and the n drift layer 3. It is possible. However, the groove 7 may have a depth up to the middle of the n drift layer 3 to form an SBD having the structure shown in FIG. In the case where the depth of the groove 7 is halfway through the n drift layer 3, the etching time can be shortened and the cost can be reduced.
  • the semiconductor device of the present embodiment includes a substrate 1 (semiconductor substrate) and a first layer formed on the substrate 1.
  • the first layer is arranged from the front surface to the back surface in contact with the substrate 1 and is formed by epitaxial growth of the first conductivity type n drift layer 3 (drift layer), and n drift from the surface to a predetermined depth.
  • An insulating layer 5 spaced apart from the layer 3, and a second conductivity type p layer 6 in contact with and sandwiched between the insulating layer 5 and the n drift layer 3 over a predetermined depth from the surface)
  • the impurity concentration of the p layer 6 decreases from the surface in the depth direction.
  • the impurity concentration of the p layer 6 (first impurity region) has a distribution that decreases while having a region having a constant concentration in the center from the surface toward the depth direction.
  • the semiconductor device of the present embodiment further includes an anode electrode 9 formed on the surface of the first layer, and the anode electrode 9 is in Schottky contact with the n drift layer 3 and in ohmic contact with the p layer 6. . Therefore, a high breakdown voltage SBD is obtained in which the electric field strength during reverse voltage application is uniform in the n drift layer 3.
  • the first layer for maintaining the withstand voltage can be formed thinner, so that the on-resistance can be further reduced.
  • the manufacturing method of the first semiconductor device of the present embodiment includes (a) a step of preparing a substrate 1 (semiconductor substrate), and (b) a first conductivity type n drift layer 3 (drift layer) on the substrate 1. (C) a step of forming a trench 7 having a predetermined depth in the n drift layer 3, and (d) an impurity of the second conductivity type is implanted into the side wall of the trench 7 to form a second A step of forming a p-type conductive layer 6 (first impurity region); and (e) a step of filling the insulating layer 5 in the groove 7.
  • an SJ structure including the n drift layer 3, the p layer 6, and the insulating layer 5 can be easily formed by a single etching process and ion implantation process without going through a plurality of epitaxial processes.
  • the p layer 6 (first impurity region) in which the impurity concentration decreases in the depth direction of the groove 7 is formed. Therefore, compared with the case where the p layer 6 is formed with a constant impurity concentration, It becomes possible to make the electric field intensity when applying the reverse voltage more uniform, and the breakdown voltage is improved.
  • the impurity concentration of the p layer 6 (first impurity region) has a distribution that decreases while having a constant concentration region at the center in the depth direction of the groove 7. Since the p layer 6 is formed, it is possible to make the electric field strength when the reverse voltage is applied more uniform than when the p layer 6 is formed with a constant impurity concentration, and the breakdown voltage of the semiconductor device is improved. .
  • the p-type layer 6 is formed on the side wall of the groove 7 by implanting the second conductivity type impurity obliquely with respect to the depth direction of the groove 7. Further, by implanting while changing the implantation angle, it becomes possible to form the p layer 6 with the impurity concentration distribution in the depth direction.
  • the etching time can be shortened and the cost can be reduced.
  • the step (e) is a step of filling the insulating layer 5 in the groove 7 in a plurality of times, and the step (d) is repeatedly performed alternately with the step (e).
  • the p layer 6 can be formed with an impurity concentration distribution in the depth direction.
  • FIG. 20 is a cross-sectional view showing a configuration of an SBD as a semiconductor device according to the second embodiment. Except for the insulating layer 5 having a tapered shape, it is the same as the SBD of the first embodiment shown in FIG.
  • n type drift layer 3 is epitaxially grown on an n + type substrate 1.
  • a mask 13 is formed on the n drift layer 3.
  • an opening pattern is formed in the mask 13 using a lithography method, and a tapered groove 17 having an opening that increases from the bottom to the surface side is formed using the mask 13 (FIG. 17).
  • the tapered shape of the groove 17 is formed by side etching with respect to the mask 13, and the taper angle is set to several degrees to about 30 degrees.
  • N or P is ion-implanted perpendicularly to the wafer using the mask 13 to form an n + layer 18 on the side wall near the bottom of the groove 17 (FIG. 18).
  • the mask 13 is removed and then B or Al is ion-implanted as a p-type impurity to form the p layer 6 (FIG. 19).
  • the impurity concentration is lower than in the region where the p-type impurity is ion-implanted into the n layer 3. Therefore, it is possible to form the p layer 6 having a distribution in which the impurity concentration decreases while having a flat region from the surface of the n drift layer 3 toward the substrate 1 side without performing oblique ion implantation. Thereby, since the uniformity of the electric field strength can be improved, the breakdown voltage can be improved and a stable SJ structure can be produced.
  • the p layer 6 is removed from the upper surface of the n drift layer 3, and the anode electrode 9 and the cathode electrode 11 are formed in the same manner as in the manufacturing method of the first embodiment (FIG. 20).
  • the groove 7 is formed in a tapered shape in the step (c), and (g) the groove 7 is formed between the step (c) and the step (d) for forming the p layer 6. Since the first conductivity type impurity is implanted into the side wall near the bottom of the substrate from the direction perpendicular to the substrate 1, the impurity concentration is increased in the depth direction without controlling the implantation angle and performing oblique implantation. A decreasing p-layer 6 can be formed.
  • FIG. 21 is a cross-sectional view of a JBS as a semiconductor device according to the third embodiment.
  • the p-layer 6 is selectively formed on the surface of the n drift layer 3 in the configuration of the SBD according to the first embodiment shown in FIG.
  • the depletion layer spreads from the p layer 16 when a reverse voltage is applied, so that the electric field strength can be made more uniform and the leakage current can be reduced.
  • the semiconductor device of the present embodiment has a second conductivity type p layer 16 (second layer) selectively disposed on the surface of the n drift layer 3 (drift layer).
  • the JBS further includes an impurity region. When a reverse voltage is applied, a depletion layer extends from the p layer 16 to the n drift layer 3, so that the electric field strength can be made more uniform and the leakage current is reduced.
  • the first layer for maintaining the withstand voltage can be formed thinner, so that the on-resistance can be further reduced.
  • FIG. 22 is a cross-sectional view of a metal oxide semiconductor (MOS) as a semiconductor device according to the fourth embodiment.
  • the MOS according to the fourth embodiment is a MOS to which the SJ structure according to the first embodiment shown in FIG. 1 is applied, and can secure a sufficient breakdown voltage as compared with the conventional MOS. Therefore, the impurity concentration of the n drift layer 3 is reduced. Can be high. For this reason, the electrical resistance of the current path can be set low.
  • a p base region 21, a p body region 22, and an n + source layer 23 are provided on the surface of the n drift layer 3 in the SBD structure shown in FIG.
  • a drain electrode 25 is provided in place of the electrode 24 in place of the cathode electrode 11.
  • a gate electrode 27 is provided on the n + source layer 23, the p base region 21, and the n drift layer 3 through the gate oxide film 19. The gate electrode 27 and the source electrode 24 are insulated by the interlayer insulating film 20.
  • the MOS according to the present embodiment is selectively provided on the surface of the n drift layer 3 with a p base region 21 and on the surface of the p base region 21 with an impurity concentration higher than that of the p base region 21.
  • FIG. 23 is a cross-sectional view of a trench MOS as a semiconductor device according to the fifth embodiment.
  • the trench MOS according to the fifth embodiment is a trench MOS to which the SJ structure according to the first embodiment shown in FIG. 1 is applied, and a sufficient breakdown voltage can be secured as compared with the conventional trench MOS. Impurity concentration can be increased. For this reason, the electrical resistance of the current path can be set low.
  • the trench MOS of the fifth embodiment is obtained by changing the gate electrode 27 to a trench gate in the MOS of the fourth embodiment shown in FIG. That is, the trench 26 is formed in the n drift layer 3 from the surface to a predetermined depth, and the p base region 21 is selectively formed on the surface of the n drift layer 3 sandwiching the trench 26. On the surface of the p base region 21, a p body region 22 having an impurity concentration higher than that of the p base region 21 and an n + source layer 23 having an impurity concentration higher than that of the n drift layer 3 are selectively provided. The n + source layer 23 is provided adjacent to the trench 26. A gate oxide film 19 is provided in the trench 26, and a gate electrode 27 is provided on the gate oxide film 19 so as to be embedded in the trench 26. The other configuration is the same as that of the MOS of the fourth embodiment.
  • the trench 26 is selectively formed from the surface of the n drift layer 3 to a predetermined depth, and is selectively provided on the surface of the n drift layer 3 sandwiching the trench 26.
  • a source electrode 24 formed on the n + source layer 23, and a drain electrode 25 formed on the back surface of the substrate 1 are provided.

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Abstract

The purpose of the present invention is to provide a semiconductor device having a low on-resistance and a high withstand voltage, and a method for manufacturing the semiconductor device. This semiconductor device is provided with a substrate (1), and a first layer formed on the substrate (1). The first layer is provided with: an n drift layer (3), which is disposed over the front surface to the rear surface in contact with the substrate (1), and which is formed by means of epitaxial growing; an insulating layer (5), which is disposed for a predetermined depth from the front surface by being spaced apart from the n drift layer (3); and a second conductivity type p layer (6), which is disposed for a predetermined depth from the front surface by being in contact with and being sandwiched between the insulating layer (5) and the n drift layer (3). The impurity concentration of the p layer (6) is reduced in the depth direction from the front surface.

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof

　この発明は、半導体装置のスーパージャンクション（ＳＪ）構造に関する。 The present invention relates to a super junction (SJ) structure of a semiconductor device.

　パワーデバイスのオン抵抗を小さくするためには、ドリフト層の不純物濃度を上げる必要がある。しかし、ドリフト層の不純物濃度が大きくなると電界強度が大きくなり、耐圧が減少する。このように、半導体の耐圧と抵抗値はトレードオフの関係にある。この関係を改善する構造として、ｐｎ接合を横方向に交互に配置したスーパージャンクション（Super Junction：ＳＪ）構造が提案されている。 In order to reduce the on-resistance of the power device, it is necessary to increase the impurity concentration of the drift layer. However, as the impurity concentration in the drift layer increases, the electric field strength increases and the breakdown voltage decreases. Thus, the breakdown voltage and resistance value of the semiconductor are in a trade-off relationship. As a structure for improving this relationship, a super junction (SJ) structure in which pn junctions are alternately arranged in a lateral direction has been proposed.

　特許文献１では、ｎ型半導体層を選択的にエッチングして溝を形成し、当該溝の内部にｐ層をエピタキシャル成長させることによって、ＳＪ構造を形成することが示されている。 Patent Document 1 discloses that an SJ structure is formed by selectively etching an n-type semiconductor layer to form a groove and epitaxially growing a p-layer inside the groove.

　また、特許文献２では、ｎ型半導体層を選択的にエッチングして溝を形成し、イオン注入法により溝の側面にｐ型半導体層を形成し、その後、溝を絶縁体層で埋めることによりＳＪ構造を形成する方法が示されている。 In Patent Document 2, an n-type semiconductor layer is selectively etched to form a groove, a p-type semiconductor layer is formed on the side surface of the groove by an ion implantation method, and then the groove is filled with an insulator layer. A method of forming an SJ structure is shown.

特開２００７－０４２９９７号公報JP 2007-042997 A 特開平１０－２２３８９６号公報JP-A-10-223896

　しかし、特許文献１の方法によればＳＪ構造の形成にエピタキシャル工程を複数回経る必要があるため、多大な費用と時間を必要とするものであった。また、ＳｉＣ基板に対しては、複数回のエピタキシャル工程を安定的に行うことは困難であった。 However, according to the method of Patent Document 1, it is necessary to go through an epitaxial process a plurality of times to form the SJ structure, which requires a great deal of cost and time. In addition, it has been difficult to stably perform a plurality of epitaxial processes on a SiC substrate.

　また、特許文献２の半導体装置ではｐ型半導体層の不純物濃度が一定であるため、ｎ型半導体層の電界強度の一様性は十分ではなく、耐圧をさらに改善する余地があった。 Also, in the semiconductor device of Patent Document 2, since the impurity concentration of the p-type semiconductor layer is constant, the uniformity of the electric field strength of the n-type semiconductor layer is not sufficient, and there is room for further improvement of the breakdown voltage.

　本発明はこの問題に鑑み、さらに改善された低いオン抵抗と高い耐圧を有するＳＪ構造の半導体装置及びその製造方法の提供を目的とする。 In view of this problem, an object of the present invention is to provide a semiconductor device having an SJ structure having further improved low on-resistance and high breakdown voltage, and a method for manufacturing the same.

　本発明に係る半導体装置は、半導体基板と、半導体基板上に形成された第１の層とを備え、第１の層は、表面から半導体基板に接する裏面に亘って配置されエピタキシャル成長で形成された第１導電型のドリフト層と、表面から所定の深さに亘って、ドリフト層と離間して配置された絶縁層と、表面から所定の深さに亘って絶縁層とドリフト層に接し且つ挟まれて配置された第２導電型の第１不純物領域とを備え、第１不純物領域の不純物濃度は、表面から深さ方向に向かって低下する。 A semiconductor device according to the present invention includes a semiconductor substrate and a first layer formed on the semiconductor substrate, and the first layer is disposed from the front surface to the back surface in contact with the semiconductor substrate and formed by epitaxial growth. A first conductivity type drift layer; an insulating layer spaced from the drift layer over a predetermined depth from the surface; and an insulating layer and the drift layer in contact with and sandwiched between the surface from the surface over a predetermined depth And the first impurity region of the second conductivity type disposed in a distance, and the impurity concentration of the first impurity region decreases in the depth direction from the surface.

　本発明に係る半導体装置の製造方法は、（ａ）半導体基板を準備する工程と、（ｂ）半導体基板上に第１導電型のドリフト層をエピタキシャル成長で形成する工程と、（ｃ）ドリフト層に所定の深さの溝を形成する工程と、（ｄ）溝の側壁に第２導電型の不純物を注入して、第２導電型の第１不純物領域を形成する工程と、（ｅ）溝の内部に絶縁層を充填する工程とを備え、工程（ｄ）は、溝の深さ方向に不純物密度が減少する第１不純物領域を形成する工程である。 The method for manufacturing a semiconductor device according to the present invention includes: (a) a step of preparing a semiconductor substrate; (b) a step of forming a first conductivity type drift layer on the semiconductor substrate by epitaxial growth; Forming a groove having a predetermined depth; (d) implanting a second conductivity type impurity into the side wall of the groove to form a second conductivity type first impurity region; And a step (d) is a step of forming a first impurity region in which the impurity density decreases in the depth direction of the groove.

　本発明に係る半導体装置は、半導体基板と、半導体基板上に形成された第１の層とを備え、第１の層は、表面から半導体基板に接する裏面に亘って配置されエピタキシャル成長で形成された第１導電型のドリフト層と、表面から所定の深さに亘って、ドリフト層と離間して配置された絶縁層と、表面から所定の深さに亘って絶縁層とドリフト層に接し且つ挟まれて配置された第２導電型の第１不純物領域とを備え、第１不純物領域の不純物濃度は、表面から深さ方向に向かって低下する。よって、低いオン抵抗と高い耐圧を有する半導体装置となる。 A semiconductor device according to the present invention includes a semiconductor substrate and a first layer formed on the semiconductor substrate, and the first layer is disposed from the front surface to the back surface in contact with the semiconductor substrate and formed by epitaxial growth. A first conductivity type drift layer; an insulating layer spaced from the drift layer over a predetermined depth from the surface; and an insulating layer and the drift layer in contact with and sandwiched between the surface from the surface over a predetermined depth And the first impurity region of the second conductivity type disposed in a distance, and the impurity concentration of the first impurity region decreases in the depth direction from the surface. Therefore, the semiconductor device has a low on-resistance and a high breakdown voltage.

　本発明に係る半導体装置の製造方法は、（ａ）半導体基板を準備する工程と、（ｂ）半導体基板上に第１導電型のドリフト層をエピタキシャル成長で形成する工程と、（ｃ）ドリフト層に所定の深さの溝を形成する工程と、（ｄ）溝の側壁に第２導電型の不純物を注入して、第２導電型の第１不純物領域を形成する工程と、（ｅ）溝の内部に絶縁層を充填する工程とを備え、工程（ｄ）は、溝の深さ方向に不純物密度が減少する第１不純物領域を形成する工程である。よって、低いオン抵抗と高い耐圧を実現するＳＪ構造を、１回のエッチング工程と１回のイオン注入工程で形成すると共に、第２不純物領域の濃度を一様に形成した場合と比べて耐圧が向上する。 The method for manufacturing a semiconductor device according to the present invention includes: (a) a step of preparing a semiconductor substrate; (b) a step of forming a first conductivity type drift layer on the semiconductor substrate by epitaxial growth; Forming a groove having a predetermined depth; (d) implanting a second conductivity type impurity into the side wall of the groove to form a second conductivity type first impurity region; And a step (d) is a step of forming a first impurity region in which the impurity density decreases in the depth direction of the groove. Therefore, the SJ structure that realizes a low on-resistance and a high breakdown voltage is formed by one etching process and one ion implantation process, and the breakdown voltage is higher than that when the concentration of the second impurity region is uniformly formed. improves.

　この発明の目的、特徴、態様、および利点は、以下の詳細な説明と添付図面とによって、より明白となる。 The objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

実施の形態１に係る半導体装置の断面図である。1 is a cross-sectional view of a semiconductor device according to a first embodiment. ｐ層の不純物濃度分布を示す図である。It is a figure which shows the impurity concentration distribution of p layer. 本発明の半導体装置の電界強度分布を示す図である。It is a figure which shows electric field strength distribution of the semiconductor device of this invention. ｎドリフト層の電界強度分布を示す図である。It is a figure which shows the electric field strength distribution of an n drift layer. 通常のＳＢＤと本発明の半導体装置で微分抵抗率を比較する図である。It is a figure which compares differential resistivity with normal SBD and the semiconductor device of this invention. 本発明の半導体装置の電流密度－電圧特性を示す図である。It is a figure which shows the current density-voltage characteristic of the semiconductor device of this invention. 実施の形態１に係る半導体装置の製造工程を示す断面図である。7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 実施の形態１に係る半導体装置の製造工程を示す断面図である。7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 実施の形態１に係る半導体装置の製造工程を示す断面図である。7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 実施の形態１に係る半導体装置の製造工程を示す断面図である。7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 実施の形態１に係る半導体装置の製造工程を示す断面図である。7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 実施の形態１に係る半導体装置の製造工程を示す断面図である。7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 実施の形態１に係る半導体装置の製造工程を示す断面図である。7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 実施の形態１に係る半導体装置の製造工程を示す断面図である。7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 実施の形態１に係る半導体装置の製造工程を示す断面図である。7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 実施の形態１の変形例に係る半導体装置の断面図である。FIG. 6 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment. 実施の形態２に係る半導体装置の製造工程を示す断面図である。11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment. FIG. 実施の形態２に係る半導体装置の製造工程を示す断面図である。11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment. FIG. 実施の形態２に係る半導体装置の製造工程を示す断面図である。11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment. FIG. 実施の形態２に係る半導体装置の製造工程を示す断面図である。11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment. FIG. 実施の形態３に係る半導体装置の断面図である。FIG. 6 is a cross-sectional view of a semiconductor device according to a third embodiment. 実施の形態４に係る半導体装置の断面図である。FIG. 6 is a cross-sectional view of a semiconductor device according to a fourth embodiment. 実施の形態５に係る半導体装置の断面図である。FIG. 6 is a cross-sectional view of a semiconductor device according to a fifth embodiment. 前提技術に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on a premise technique. 前提技術に係る半導体装置の電界強度分布を示す図である。It is a figure which shows the electric field strength distribution of the semiconductor device which concerns on a premise technique.

　＜Ａ．前提技術＞
　図２４は、本発明の前提技術の半導体装置としてのショットキーバリアダイオード（Ｓｃｈｏｔｔｋｙ　Ｄｉｏｄｅ：ＳＢＤ）の断面図である。前提技術のＳＢＤは、基板１と、カソード電極１１と、ｎドリフト層３と、ｐ層６と、アノード電極９を備えている。基板１はｎ＋型の基板であり、例えば炭化珪素（ＳｉＣ）基板が用いられる。基板１の下面にはカソード電極１１が形成される。基板１上には、ｎドリフト層３とｐ層６が横方向に順に形成されたＳＪ構造が存在する。ｎドリフト層３、ｐ層６の厚みは全てＴ１であり、これらの層の上にはアノード電極９が形成されている。アノード電極９はｎドリフト層３とショットキー接触し、ｐ層６とオーミック接触している。ｐ層６のｐ型不純物濃度は深さ方向に一定である。 <A. Prerequisite technology>
FIG. 24 is a cross-sectional view of a Schottky barrier diode (SBD) as a semiconductor device of the prerequisite technology of the present invention. The base technology SBD includes a substrate 1, a cathode electrode 11, an n drift layer 3, a p layer 6, and an anode electrode 9. The substrate 1 is an n + type substrate, for example, a silicon carbide (SiC) substrate. A cathode electrode 11 is formed on the lower surface of the substrate 1. On the substrate 1, there is an SJ structure in which an n drift layer 3 and a p layer 6 are sequentially formed in the lateral direction. The thicknesses of the n drift layer 3 and the p layer 6 are all T1, and the anode electrode 9 is formed on these layers. The anode electrode 9 is in Schottky contact with the n drift layer 3 and is in ohmic contact with the p layer 6. The p-type impurity concentration of the p layer 6 is constant in the depth direction.

　図２５は、図２４に示した前提技術のＳＢＤにおいて、アノード電極９－カソード電極１１間に逆方向電圧を印加したときの、図中Ｄ部における電界強度分布のシミュレーション結果を示している。なお、ｎドリフト層３及びｐ層６の幅を１０μｍ、ｎドリフト層３及びｐ層６の厚みを２２μｍ、ｎドリフト層３の不純物濃度を１．５×１０１６／ｃｍ３、ｐ層６の不純物濃度を１×１０１７ｃｍ－３として計算した。図２５では、色の濃い領域ほど電界強度が強い領域であることを示している。ｎドリフト層３の中で、例えばｎドリフト層３とアノード電極９の界面などに局所的に電界が高い部分ができている。この部分には、逆方向電圧２．５ｋＶを印加した時に２ＭＶ／ｃｍの電界がかかり、ＳＪ構造の特徴であるドリフト層全体に均一に電界を分布させ、耐圧を確保することが出来ていない。 FIG. 25 shows a simulation result of the electric field intensity distribution in the portion D in the figure when a reverse voltage is applied between the anode electrode 9 and the cathode electrode 11 in the SBD of the base technology shown in FIG. The width of the n drift layer 3 and the p layer 6 is 10 μm, the thickness of the n drift layer 3 and the p layer 6 is 22 μm, the impurity concentration of the n drift layer 3 is 1.5 × 10 16 / cm 3 , The impurity concentration was calculated as 1 × 10 17 cm −3 . FIG. 25 shows that the darker the region is, the stronger the electric field strength. In the n drift layer 3, for example, a portion where the electric field is locally high is formed at the interface between the n drift layer 3 and the anode electrode 9. An electric field of 2 MV / cm is applied to this portion when a reverse voltage of 2.5 kV is applied, and the electric field is uniformly distributed over the entire drift layer, which is a feature of the SJ structure, and a breakdown voltage cannot be secured.

　そこで実施の形態１では、以下に示すようにｐ層６の不純物濃度に深さ方向の分布を持たせることによって、逆方向電圧印加時に電界がドリフト層全体により均一に分布するようにする。 Therefore, in the first embodiment, as shown below, the impurity concentration of the p layer 6 has a distribution in the depth direction so that the electric field is uniformly distributed throughout the drift layer when the reverse voltage is applied.

　＜Ｂ．実施の形態１＞
　＜Ｂ－１．構成＞
　図１は、実施の形態１に係る半導体装置としてのショットキーバリアダイオード（Ｓｃｈｏｔｔｋｙ　Ｄｉｏｄｅ：ＳＢＤ）の断面図である。本実施の形態のＳＢＤは、基板１と、カソード電極１１と、ｎドリフト層３と、絶縁層５と、ｐ層６と、アノード電極９を備えている。 <B. Embodiment 1>
<B-1. Configuration>
1 is a cross-sectional view of a Schottky barrier diode (SBD) as a semiconductor device according to the first embodiment. The SBD of the present embodiment includes a substrate 1, a cathode electrode 11, an n drift layer 3, an insulating layer 5, a p layer 6, and an anode electrode 9.

　基板１はｎ＋型の基板であり、例えば炭化珪素（ＳｉＣ）基板が用いられる。基板１の下面にはカソード電極１１が形成される。基板１上には、ｎドリフト層３と絶縁層５が離間して形成され、さらに絶縁層５を両側面から挟みこみ、絶縁層５とｎドリフト層３の間を埋めるようにしてｐ層６が形成される。ｎドリフト層３、ｐ層６、絶縁層５の厚みは全てＴ１であり、これらの層の上にはアノード電極９が形成されている。アノード電極９はｎドリフト層３とショットキー接触し、ｐ層６とオーミック接触している。 The substrate 1 is an n + type substrate, for example, a silicon carbide (SiC) substrate. A cathode electrode 11 is formed on the lower surface of the substrate 1. An n drift layer 3 and an insulating layer 5 are formed on the substrate 1 so as to be separated from each other. Further, the insulating layer 5 is sandwiched from both side surfaces so as to fill the gap between the insulating layer 5 and the n drift layer 3. Is formed. The thicknesses of the n drift layer 3, the p layer 6, and the insulating layer 5 are all T1, and the anode electrode 9 is formed on these layers. The anode electrode 9 is in Schottky contact with the n drift layer 3 and is in ohmic contact with the p layer 6.

　すなわち、実施の形態１のショットキーバリアダイオードは、基板１上に第１の層として、ｎドリフト層３、ｐ層６、絶縁層５が横方向に順に形成されたＳＪ構造を有している。とりわけ図１では、ｎドリフト層３、ｐ層６、絶縁層５、ｐ層６がこの順で横方向に複数回繰り返された構造を示しているが、繰り返し回数は特に限定しない。寸法例として、ｎドリフト層３の幅Ｌ１を１０μｍ、ｐ層６の幅Ｌ２を０．５μｍ、絶縁層５の幅Ｌ３を１０μｍとし、これらの層の厚みＴ１を２２μｍとする。 That is, the Schottky barrier diode of the first embodiment has an SJ structure in which an n drift layer 3, a p layer 6, and an insulating layer 5 are sequentially formed in the lateral direction as a first layer on the substrate 1. . In particular, FIG. 1 shows a structure in which the n drift layer 3, the p layer 6, the insulating layer 5, and the p layer 6 are repeated a plurality of times in this order in the horizontal direction, but the number of repetitions is not particularly limited. As a dimension example, the width L1 of the n drift layer 3 is 10 μm, the width L2 of the p layer 6 is 0.5 μm, the width L3 of the insulating layer 5 is 10 μm, and the thickness T1 of these layers is 22 μm.

　図２（ａ）は、図１のＡ部拡大図であり、絶縁層５、ｐ層６、及びｎドリフト層３を示している。図２（ｂ）は、図２（ａ）のＢ－Ｂ’に沿ったｙ軸方向におけるｐ層６の不純物濃度分布を示している。ｐ層６の不純物濃度は、ｎドリフト層３の表面から基板１側（裏面側）に向かって平坦な領域をもちながら低下する分布を有している。ｐ層６の不純物濃度は、最も多いところで１×１０１７ｃｍ－３オーダー程度なら良く、最も低いところで０ｃｍ－３となる。またその分布は、基板１側で最も濃く、中部で基板１側の７～８割程度の濃度で、最下部で０ｃｍ－３に向かうような分布であれば、分布の幅を多少持たせても、電界強度の一様性を改善可能であり、耐圧が向上する。 FIG. 2A is an enlarged view of a portion A in FIG. 1 and shows the insulating layer 5, the p layer 6, and the n drift layer 3. FIG. 2B shows the impurity concentration distribution of the p layer 6 in the y-axis direction along BB ′ in FIG. The impurity concentration of the p layer 6 has a distribution that decreases while having a flat region from the surface of the n drift layer 3 toward the substrate 1 side (back surface side). The impurity concentration of the p layer 6 may be about 1 × 10 17 cm −3 at the highest level, and 0 cm −3 at the lowest level. If the distribution is such that it is the darkest on the substrate 1 side, the concentration is about 70 to 80% on the substrate 1 side, and is 0 cm −3 at the bottom, the distribution width is somewhat increased. However, the uniformity of the electric field strength can be improved and the breakdown voltage is improved.

　＜Ｂ－２．動作、特性＞
　次に、図１に示したＳＢＤの動作を簡単に説明する。アノード電極９－カソード電極１１間に順方向電圧が印加されると、ｎドリフト層３とｐ層６との接合部における空乏層が収縮し、アノード電極９とカソード電極１１との間に電流経路が生じて電流が流れる。また、後述するようにＳＪ構造にすることで十分な耐圧を確保できるので、ｎドリフト層３の不純物濃度を高く出来る。このため、電流経路の電気抵抗を低く設定できる。 <B-2. Operation and characteristics>
Next, the operation of the SBD shown in FIG. 1 will be briefly described. When a forward voltage is applied between the anode electrode 9 and the cathode electrode 11, the depletion layer at the junction between the n drift layer 3 and the p layer 6 contracts, and a current path is formed between the anode electrode 9 and the cathode electrode 11. Occurs and current flows. Further, as described later, since the SJ structure can secure a sufficient breakdown voltage, the impurity concentration of the n drift layer 3 can be increased. For this reason, the electrical resistance of the current path can be set low.

　次に、アノード電極９－カソード電極１１間に逆方向電圧が印加されると、アノード電極９とｎドリフト層３との接触部におけるショットキー障壁によって電流が制御されると共に、ｎドリフト層３とｐ層６との接合部における空乏層が拡大し、結果的にｎドリフト層３は幅方向の全体に亘って空乏層化される。この結果、逆方向の電流は遮断され、高い耐圧が実現する。 Next, when a reverse voltage is applied between the anode electrode 9 and the cathode electrode 11, the current is controlled by the Schottky barrier at the contact portion between the anode electrode 9 and the n drift layer 3, and the n drift layer 3 The depletion layer at the junction with the p layer 6 expands, and as a result, the n drift layer 3 becomes a depletion layer over the entire width direction. As a result, the current in the reverse direction is cut off and a high breakdown voltage is realized.

　図３は、アノード電極９－カソード電極１１間に逆方向電圧３．３ｋＶを印加したときの、図１のＡ部における電界強度分布と等電位線を示している。なお、ｎドリフト層３及び絶縁層５の幅を１０μｍ、ｐ層６の幅を０．５μｍとし、各層の厚みを２２μｍとしてシミュレーションを行った。しかし、ｎドリフト層３と絶縁層５はそれぞれ左右対称な電界強度分布を有するので、図３にはｎドリフト層３と絶縁層５の電界強度分布をそれぞれ幅５μｍだけ示している。ｎドリフト層３の不純物濃度は１．５×１０１６／ｃｍ３とする。図３では、色の濃い領域ほど電界強度が強い領域であることを示している。ｎドリフト層３の中では、ｐ層６との境界部と図３のＣ－Ｃ’軸上の上部が特に電界強度の強い領域となるが、いずれも２ＭＶ／ｃｍ以下である。 FIG. 3 shows the electric field intensity distribution and equipotential lines in part A of FIG. 1 when a reverse voltage of 3.3 kV is applied between the anode electrode 9 and the cathode electrode 11. The simulation was performed by setting the width of the n drift layer 3 and the insulating layer 5 to 10 μm, the width of the p layer 6 to 0.5 μm, and the thickness of each layer to 22 μm. However, since the n drift layer 3 and the insulating layer 5 have symmetrical electric field intensity distributions, FIG. 3 shows the electric field intensity distributions of the n drift layer 3 and the insulating layer 5 by a width of 5 μm. The impurity concentration of the n drift layer 3 is 1.5 × 10 16 / cm 3 . FIG. 3 shows that the darker region is the region where the electric field strength is higher. In the n drift layer 3, the boundary portion with the p layer 6 and the upper portion on the CC ′ axis in FIG. 3 are regions with particularly strong electric field strength, both of which are 2 MV / cm or less.

　図４は、ｎ型ドリフト層３のＣ－Ｃ’軸に沿ったｙ軸方向（図３参照）の電界強度分布を示している。図４から、深さ４～１６μｍの範囲で平坦な電界強度特性を示している。このため、素子を薄くし、ｎ型ドリフト層３の不純物濃度を高濃度化することが可能であり、定常損失を低減しつつ耐圧を向上することができる。 FIG. 4 shows the electric field intensity distribution in the y-axis direction (see FIG. 3) along the C-C ′ axis of the n-type drift layer 3. FIG. 4 shows a flat electric field strength characteristic in the depth range of 4 to 16 μm. For this reason, it is possible to reduce the thickness of the element and increase the impurity concentration of the n-type drift layer 3, and to improve the breakdown voltage while reducing the steady loss.

　図５は、ＳＪ構造を有しない通常のＳＢＤにおける、耐圧と順方向の微分抵抗率（相対値）の関係を示しており、併せて３．３ｋＶの耐圧を有する本実施の形態のＳＢＤの微分抵抗率を四角点で示している。通常のＳＢＤでは３．３ｋＶの耐圧で３０程度の微分抵抗率を有するのに対し、本実施の形態では１２程度と微分抵抗率が大幅に低減されている。 FIG. 5 shows the relationship between the breakdown voltage and the forward differential resistivity (relative value) in a normal SBD having no SJ structure, and the differential of the SBD of this embodiment having a breakdown voltage of 3.3 kV. The resistivity is indicated by a square point. A normal SBD has a differential resistivity of about 30 with a breakdown voltage of 3.3 kV, whereas in the present embodiment, the differential resistivity is significantly reduced to about 12.

　図６は、本実施の形態のＳＢＤの順方向電流密度特性を示している。本実施の形態のＳＢＤではｐ層６が基板１の近傍にも存在するため、ＳＢＤモードからＰＮダイオードモードに変化する電圧値が通常のＪＢＳ（Junction Barrier Schottky diode）等に比べて非常に小さくなる特徴を持つ。この結果は突入電流耐量の向上に結びつく。 FIG. 6 shows the forward current density characteristics of the SBD of the present embodiment. In the SBD of the present embodiment, since the p layer 6 is also present in the vicinity of the substrate 1, the voltage value that changes from the SBD mode to the PN diode mode is much smaller than that of a normal JBS (JunctionuncBarrier Schottky diode) or the like. Has characteristics. This result leads to improvement of inrush current capability.

　＜Ｂ－３．製造方法１＞
　図７～図１２に沿って、図１に示したＳＢＤの製造方法１を説明する。まず、ｎ＋型の基板１を用意し、その上にｎ型ドリフト層３をエピタキシャル成長させる（図７）。 <B-3. Manufacturing Method 1>
A method 1 for manufacturing the SBD shown in FIG. 1 will be described with reference to FIGS. First, an n + type substrate 1 is prepared, and an n type drift layer 3 is epitaxially grown thereon (FIG. 7).

　次に、ｎドリフト層３上にマスク１３を形成する。マスク１３の材質は特に限定しないが、タンタルカーバイド（ＴａＣ）、窒化アルミニウム（ＡｌＮ）やダイヤモンドその他の材料を用いることが出来る。そして、リソグラフィ法を用いて開口パターンをマスク１３に形成し、マスク１３を用いてｎドリフト層３をＲＩＥにより部分的に除去する。この結果、図８に示すようにｎドリフト層３を貫通する溝７が形成される。 Next, a mask 13 is formed on the n drift layer 3. The material of the mask 13 is not particularly limited, but tantalum carbide (TaC), aluminum nitride (AlN), diamond, or other materials can be used. Then, an opening pattern is formed in the mask 13 using a lithography method, and the n drift layer 3 is partially removed by RIE using the mask 13. As a result, a groove 7 penetrating the n drift layer 3 is formed as shown in FIG.

　その後、溝７の内周面について犠牲酸化処理を行う。例えば、１１５０℃で酸化を行う。これにより、ウェハ表面上に犠牲酸化膜が形成される。その後、希フッ酸により犠牲酸化膜をエッチング除去する。これにより、溝７の形成時にＲＩＥによるエッチングで生じたダメージが除去される。 Thereafter, sacrificial oxidation treatment is performed on the inner peripheral surface of the groove 7. For example, oxidation is performed at 1150 ° C. Thereby, a sacrificial oxide film is formed on the wafer surface. Thereafter, the sacrificial oxide film is removed by etching with dilute hydrofluoric acid. Thereby, damage caused by etching by RIE at the time of forming the groove 7 is removed.

　次に、溝７から斜め回転イオン注入を実施することにより、溝の側壁にｐ層６を形成する（図９）。ここでは、イオン入射角度を変えながら斜め回転イオン注入を実施することにより、溝の側壁に任意の不純物濃度分布を持ったｐ層８を形成する。ウェハに垂直な方向からの仰角θを徐々に小さくしながらイオン注入を行うことにより、図２（ｂ）に示すような不純物濃度分布を持つｐ層６が形成される。これにより、逆方向電圧を印加したときの電界強度の一様性を改善できるため、耐圧が向上する。注入イオンはＢまたはＡｌであり、不純物濃度は、例えば最も大きい表面側で１×１０１７／ｃｍ３となるようにする。ｐ層６を形成した後、マスク１３を除去する。 Next, oblique rotation ion implantation is performed from the groove 7 to form the p layer 6 on the side wall of the groove (FIG. 9). Here, the p-layer 8 having an arbitrary impurity concentration distribution is formed on the side wall of the groove by performing oblique rotation ion implantation while changing the ion incident angle. By performing ion implantation while gradually decreasing the elevation angle θ from the direction perpendicular to the wafer, the p layer 6 having an impurity concentration distribution as shown in FIG. 2B is formed. Thereby, since the uniformity of the electric field strength when a reverse voltage is applied can be improved, the breakdown voltage is improved. The implanted ions are B or Al, and the impurity concentration is, for example, 1 × 10 17 / cm 3 on the largest surface side. After the p layer 6 is formed, the mask 13 is removed.

　次に、溝７を開口したパターンのマスク１４を形成し（図１０）、絶縁層５をスパッタ法により溝７の内部に形成する。その後、マスク１４を除去する（図１１）。 Next, a mask 14 having a pattern in which the groove 7 is opened is formed (FIG. 10), and the insulating layer 5 is formed inside the groove 7 by sputtering. Thereafter, the mask 14 is removed (FIG. 11).

　次に、犠牲酸化処理を行ってｎドリフト層３、ｐ層６、絶縁層５の表面を酸化膜で覆う。例えば、１１５０℃で酸化を行う。これによりウェハ表面上に犠牲酸化膜が形成される。その後、希フッ酸により犠牲酸化膜をエッチング除去する。 Next, sacrificial oxidation treatment is performed to cover the surfaces of the n drift layer 3, the p layer 6, and the insulating layer 5 with an oxide film. For example, oxidation is performed at 1150 ° C. Thereby, a sacrificial oxide film is formed on the wafer surface. Thereafter, the sacrificial oxide film is removed by etching with dilute hydrofluoric acid.

　次に、スパッタリング法によりｎドリフト層３、ｐ層６、絶縁層５を覆うアノード電極９を形成する。アノード電極９には、ｎドリフト層３とショットキー接触可能で、ｐ層６とオーミック接触可能な材料であれば任意の材料を用いることが出来る。例えば、チタン（Ｔｉ）、モリブデン（Ｍｏ）などを用いることができる。また、基板１の裏面に、金属スパッタリングによりカソード電極１１を形成する（図１２）。 Next, an anode electrode 9 that covers the n drift layer 3, the p layer 6, and the insulating layer 5 is formed by a sputtering method. Any material can be used for the anode electrode 9 as long as it can make Schottky contact with the n drift layer 3 and can make ohmic contact with the p layer 6. For example, titanium (Ti), molybdenum (Mo), or the like can be used. Further, the cathode electrode 11 is formed on the back surface of the substrate 1 by metal sputtering (FIG. 12).

　このようにして、図１に示す構成のＳＢＤを、複数回のエピタキシャル工程やエッチング工程を実施することなく、１度のエッチング工程とイオン注入工程により簡単に実現できる。 Thus, the SBD having the configuration shown in FIG. 1 can be easily realized by a single etching step and ion implantation step without performing a plurality of epitaxial steps and etching steps.

　＜Ｂ－４．製造方法２＞
　次に、図１３～１５に沿って、図１に示したＳＢＤの製造方法２を説明する。図８に示す工程までは製造方法１と同様にして、ｎドリフト層３に溝７を形成する。その後、溝７の底部近傍の側壁に低ドーズ条件で斜めイオン注入を行う（図１３）。次に、溝７の半分ほどの高さまで絶縁層５を形成し、溝７の側壁に中ドーズ条件で斜めイオン注入を行う（図１４）。さらに、溝７の２／３ほどの高さまで絶縁層５を形成し、溝７の側壁に高ドーズ条件で斜めイオン注入を行う（図１５）。このように、絶縁層５の形成と溝７の側壁へのイオン注入を交互に繰り返し行い、繰り返す度にイオン注入のドーズ量を増やすことにより、深さ方向に不純物濃度の分布を有するｐ層６を形成することが出来る。ｐ層６と絶縁層５の形成工程以外は製造方法１と同様であるので、説明を省略する。 <B-4. Production Method 2>
Next, a method 2 for manufacturing the SBD shown in FIG. 1 will be described with reference to FIGS. The grooves 7 are formed in the n drift layer 3 in the same manner as in the manufacturing method 1 up to the step shown in FIG. Thereafter, oblique ion implantation is performed on the side wall near the bottom of the groove 7 under a low dose condition (FIG. 13). Next, the insulating layer 5 is formed up to about half the height of the groove 7, and oblique ion implantation is performed on the side wall of the groove 7 under medium dose conditions (FIG. 14). Further, the insulating layer 5 is formed to a height of about 2/3 of the groove 7, and oblique ion implantation is performed on the side wall of the groove 7 under a high dose condition (FIG. 15). In this manner, the formation of the insulating layer 5 and the ion implantation into the sidewall of the groove 7 are alternately repeated, and the dose amount of the ion implantation is increased each time it is repeated, whereby the p layer 6 having the impurity concentration distribution in the depth direction. Can be formed. Except for the process of forming the p layer 6 and the insulating layer 5, the manufacturing method 1 is the same as that of the manufacturing method 1, and the description thereof is omitted.

　＜Ｂ－５．変形例＞
　なお、上記の製造方法１，２では、ｎドリフト層３を貫通する溝７を形成しているので、基板１とｎドリフト層３の材料の違いを利用して制御性良く溝７を形成することが可能である。しかし、溝７はｎドリフト層３の途中までの深さとすることにより、図１６に示す構造のＳＢＤを形成しても良い。溝７の深さをｎドリフト層３の途中までとする場合には、エッチング時間を短縮でき、コスト低減が可能である。 <B-5. Modification>
In the manufacturing methods 1 and 2 described above, since the groove 7 penetrating the n drift layer 3 is formed, the groove 7 is formed with good controllability by utilizing the difference in material between the substrate 1 and the n drift layer 3. It is possible. However, the groove 7 may have a depth up to the middle of the n drift layer 3 to form an SBD having the structure shown in FIG. In the case where the depth of the groove 7 is halfway through the n drift layer 3, the etching time can be shortened and the cost can be reduced.

　＜Ｂ－６．効果＞
　本実施の形態の半導体装置は、基板１（半導体基板）と、基板１上に形成された第１の層とを備える。第１の層は、表面から基板１に接する裏面に亘って配置されエピタキシャル成長で形成された第１導電型のｎドリフト層３（ドリフト層）と、前記表面から所定の深さに亘ってｎドリフト層３と離間して配置された絶縁層５と、前記表面から所定の深さに亘って絶縁層５とｎドリフト層３に接し且つ挟まれて配置された第２導電型のｐ層６（第１不純物領域）とを備え、ｐ層６の不純物濃度は、前記表面から深さ方向に向かって減少する。これにより、一定の不純物濃度でｐ層６を形成した場合に比べて、逆方向電圧印加時の電界強度をより一様にすることが可能となり、耐圧が向上する。 <B-6. Effect>
The semiconductor device of the present embodiment includes a substrate 1 (semiconductor substrate) and a first layer formed on the substrate 1. The first layer is arranged from the front surface to the back surface in contact with the substrate 1 and is formed by epitaxial growth of the first conductivity type n drift layer 3 (drift layer), and n drift from the surface to a predetermined depth. An insulating layer 5 spaced apart from the layer 3, and a second conductivity type p layer 6 (in contact with and sandwiched between the insulating layer 5 and the n drift layer 3 over a predetermined depth from the surface) The impurity concentration of the p layer 6 decreases from the surface in the depth direction. Thereby, compared with the case where the p-layer 6 is formed with a constant impurity concentration, the electric field strength at the time of applying the reverse voltage can be made more uniform, and the breakdown voltage is improved.

　また、ｐ層６（第１不純物領域）の不純物濃度は、前記表面から深さ方向に向かって中央部で濃度が一定の領域を有しながら減少する分布を有する。これにより、一定の不純物濃度でｐ層６を形成した場合に比べて、逆方向電圧印加時の電界強度をより一様にすることが可能となり、耐圧が向上する。 The impurity concentration of the p layer 6 (first impurity region) has a distribution that decreases while having a region having a constant concentration in the center from the surface toward the depth direction. Thereby, compared with the case where the p-layer 6 is formed with a constant impurity concentration, the electric field strength at the time of applying the reverse voltage can be made more uniform, and the breakdown voltage is improved.

　また、本実施の形態の半導体装置は、第１の層の表面上に形成されたアノード電極９をさらに備え、アノード電極９はｎドリフト層３とショットキー接触し、ｐ層６とオーミック接触する。よって、逆方向電圧印加時の電界強度がｎドリフト層３内で一様な、高耐圧のＳＢＤとなる。 The semiconductor device of the present embodiment further includes an anode electrode 9 formed on the surface of the first layer, and the anode electrode 9 is in Schottky contact with the n drift layer 3 and in ohmic contact with the p layer 6. . Therefore, a high breakdown voltage SBD is obtained in which the electric field strength during reverse voltage application is uniform in the n drift layer 3.

　また、基板１にＳｉＣ基板を用いる場合には、耐圧を保持するための第１の層をより薄く形成することが可能であるので、より低オン抵抗にすることが可能である。 Further, when an SiC substrate is used as the substrate 1, the first layer for maintaining the withstand voltage can be formed thinner, so that the on-resistance can be further reduced.

　本実施の形態の第１の半導体装置の製造方法は、（ａ）基板１（半導体基板）を準備する工程と、（ｂ）基板１上に第１導電型のｎドリフト層３（ドリフト層）をエピタキシャル成長で形成する工程と、（ｃ）ｎドリフト層３に所定の深さの溝７を形成する工程と、（ｄ）溝７の側壁に第２導電型の不純物を注入して、第２導電型のｐ層６（第１不純物領域）を形成する工程と、（ｅ）溝７の内部に絶縁層５を充填する工程とを備える。よって、複数のエピタキシャル工程を経ることなく、１度のエッチング工程とイオン注入工程により、簡単にｎドリフト層３、ｐ層６、絶縁層５からなるＳＪ構造を形成することが出来る。また、工程（ｄ）では、溝７の深さ方向に不純物濃度が減少するｐ層６（第１不純物領域）を形成するので、一定の不純物濃度でｐ層６を形成した場合に比べて、逆方向電圧印加時の電界強度をより一様にすることが可能となり、耐圧が向上する。 The manufacturing method of the first semiconductor device of the present embodiment includes (a) a step of preparing a substrate 1 (semiconductor substrate), and (b) a first conductivity type n drift layer 3 (drift layer) on the substrate 1. (C) a step of forming a trench 7 having a predetermined depth in the n drift layer 3, and (d) an impurity of the second conductivity type is implanted into the side wall of the trench 7 to form a second A step of forming a p-type conductive layer 6 (first impurity region); and (e) a step of filling the insulating layer 5 in the groove 7. Therefore, an SJ structure including the n drift layer 3, the p layer 6, and the insulating layer 5 can be easily formed by a single etching process and ion implantation process without going through a plurality of epitaxial processes. Further, in the step (d), the p layer 6 (first impurity region) in which the impurity concentration decreases in the depth direction of the groove 7 is formed. Therefore, compared with the case where the p layer 6 is formed with a constant impurity concentration, It becomes possible to make the electric field intensity when applying the reverse voltage more uniform, and the breakdown voltage is improved.

　また、工程（ｄ）では、ｐ層６（第１不純物領域）の不純物濃度が、溝７の深さ方向に向かって中央部に濃度が一定の領域を有しながら低下する分布を有するようにｐ層６を形成するので、一定の不純物濃度でｐ層６を形成した場合に比べて、逆方向電圧印加時の電界強度をより一様にすることが可能となり、半導体装置の耐圧が向上する。 Further, in the step (d), the impurity concentration of the p layer 6 (first impurity region) has a distribution that decreases while having a constant concentration region at the center in the depth direction of the groove 7. Since the p layer 6 is formed, it is possible to make the electric field strength when the reverse voltage is applied more uniform than when the p layer 6 is formed with a constant impurity concentration, and the breakdown voltage of the semiconductor device is improved. .

　また、工程（ｄ）では、溝７の深さ方向に対して斜めから第２導電型の不純物を注入することにより、溝７の側壁にｐ層６が形成される。また、注入角度を変化させながら注入することによって、深さ方向に不純物濃度の分布を持たせてｐ層６を形成することが可能になる。 In the step (d), the p-type layer 6 is formed on the side wall of the groove 7 by implanting the second conductivity type impurity obliquely with respect to the depth direction of the groove 7. Further, by implanting while changing the implantation angle, it becomes possible to form the p layer 6 with the impurity concentration distribution in the depth direction.

　また、（ｆ）工程（ｅ）の後、ｎドリフト層３とショットキー接触し、ｐ層６とオーミック接触されたアノード電極９（電極）を形成する工程とを備えるので、低オン抵抗かつ耐圧の高いショットキーバリアダイオードを製造できる。 And (f) a step of forming an anode electrode 9 (electrode) in Schottky contact with the n drift layer 3 and in ohmic contact with the p layer 6 after the step (e). High Schottky barrier diode can be manufactured.

　また、工程（ｃ）では、ｎドリフト層３を貫通しない溝７を形成するので、エッチング時間を短縮でき、コスト低減が可能である。 Further, in the step (c), since the groove 7 that does not penetrate the n drift layer 3 is formed, the etching time can be shortened and the cost can be reduced.

　また、工程（ｅ）は、複数回に分けて溝７の内部に絶縁層５を充填する工程であり、工程（ｄ）は工程（ｅ）と交互に繰り返し行われる。工程（ｅ）におけるイオン注入のドーズ量を繰り返す度に増やすことによって、ｐ層６を深さ方向に不純物濃度の分布を持たせて形成することが出来る。 Further, the step (e) is a step of filling the insulating layer 5 in the groove 7 in a plurality of times, and the step (d) is repeatedly performed alternately with the step (e). By increasing the dose amount of ion implantation in the step (e) each time, the p layer 6 can be formed with an impurity concentration distribution in the depth direction.

　また、基板１にＳｉＣ基板を用いる場合には、複数回のエピタキシャル工程を安定的に行う事が困難であるところ、本実施の形態の半導体装置の製造方法では１度のエッチング工程とイオン注入工程により、安定的にＳＪ構造を形成することが可能である。 In addition, when a SiC substrate is used as the substrate 1, it is difficult to stably perform a plurality of epitaxial processes. In the method for manufacturing a semiconductor device of the present embodiment, a single etching process and an ion implantation process are performed. Thus, it is possible to stably form the SJ structure.

　＜Ｃ．実施の形態２＞
　＜Ｃ－１．構造、製造方法＞
　図２０は、実施の形態２に係る半導体装置としてのＳＢＤの構成を示す断面図である。絶縁層５がテーパー形状となっている他は、図１に示す実施の形態１のＳＢＤと同様である。 <C. Second Embodiment>
<C-1. Structure, Manufacturing Method>
FIG. 20 is a cross-sectional view showing a configuration of an SBD as a semiconductor device according to the second embodiment. Except for the insulating layer 5 having a tapered shape, it is the same as the SBD of the first embodiment shown in FIG.

　以下、図１７～２０に沿って、図１に示すＳＢＤの実施の形態２の製造方法を説明する。ｎ＋型の基板１に、ｎ型ドリフト層３をエピタキシャル成長させる。次に、ｎドリフト層３上にマスク１３を形成する。そして、リソグラフィ法を用いて開口パターンをマスク１３に形成し、マスク１３を用いて、底部から表面側にかけて開口が大きくなるテーパー形状の溝１７を形成する（図１７）。溝１７のテーパー形状はマスク１３に対するサイドエッチングによって形成され、テーパー角度は数度から３０度程度とする。 Hereinafter, the manufacturing method of the second embodiment of the SBD shown in FIG. 1 will be described with reference to FIGS. An n type drift layer 3 is epitaxially grown on an n + type substrate 1. Next, a mask 13 is formed on the n drift layer 3. Then, an opening pattern is formed in the mask 13 using a lithography method, and a tapered groove 17 having an opening that increases from the bottom to the surface side is formed using the mask 13 (FIG. 17). The tapered shape of the groove 17 is formed by side etching with respect to the mask 13, and the taper angle is set to several degrees to about 30 degrees.

　次に、マスク１３を用いてＮもしくはＰをウェハに対して垂直にイオン注入し、溝１７の底部近傍の側壁にｎ＋層１８を形成する（図１８）。 Next, N or P is ion-implanted perpendicularly to the wafer using the mask 13 to form an n + layer 18 on the side wall near the bottom of the groove 17 (FIG. 18).

　この後、マスク１３を除去してからｐ型不純物としてＢもしくはＡｌをイオン注入し、ｐ層６を形成する（図１９）。ｎ＋層１８に対してｐ型不純物をイオン注入した領域では、ｎ層３に対してｐ型不純物をイオン注入した領域と比べて不純物濃度が小さくなる。そのため、斜めイオン注入をすることなく、不純物濃度がｎドリフト層３の表面から基板１側に向かって平坦な領域を持ちながら低下している分布を持つｐ層６を形成できる。これにより、電界強度の一様性を改善できるため耐圧を向上でき、安定なＳＪ構造を作製できる。 Thereafter, the mask 13 is removed and then B or Al is ion-implanted as a p-type impurity to form the p layer 6 (FIG. 19). In the region where the p-type impurity is ion-implanted into the n + layer 18, the impurity concentration is lower than in the region where the p-type impurity is ion-implanted into the n layer 3. Therefore, it is possible to form the p layer 6 having a distribution in which the impurity concentration decreases while having a flat region from the surface of the n drift layer 3 toward the substrate 1 side without performing oblique ion implantation. Thereby, since the uniformity of the electric field strength can be improved, the breakdown voltage can be improved and a stable SJ structure can be produced.

　その後、ｎドリフト層３の上面からｐ層６を除去し、実施の形態１の製造方法と同様にしてアノード電極９とカソード電極１１を形成する（図２０）。 Thereafter, the p layer 6 is removed from the upper surface of the n drift layer 3, and the anode electrode 9 and the cathode electrode 11 are formed in the same manner as in the manufacturing method of the first embodiment (FIG. 20).

　＜Ｃ－２．効果＞
　本実施の形態の半導体装置の製造方法では、工程（ｃ）で溝７をテーパー形状に形成し、工程（ｃ）とｐ層６を形成する工程（ｄ）の間に、（ｇ）溝７の底部近傍の側壁に第１導電型の不純物を基板１に対して垂直な方向から注入する工程を備えるので、注入角度を制御して斜め注入を行わなくても、深さ方向に不純物濃度が減少するｐ層６を形成できる。 <C-2. Effect>
In the manufacturing method of the semiconductor device of the present embodiment, the groove 7 is formed in a tapered shape in the step (c), and (g) the groove 7 is formed between the step (c) and the step (d) for forming the p layer 6. Since the first conductivity type impurity is implanted into the side wall near the bottom of the substrate from the direction perpendicular to the substrate 1, the impurity concentration is increased in the depth direction without controlling the implantation angle and performing oblique implantation. A decreasing p-layer 6 can be formed.

　＜Ｄ．実施の形態３＞
　＜Ｄ－１．構造＞
　図２１は、実施の形態３に係る半導体装置としてのＪＢＳの断面図である。実施の形態３に係るＪＢＳは、図１に示す実施の形態１に係るＳＢＤの構成において、ｎドリフト層３の表面にｐ層６が選択的に形成されている。ＳＪ構造に加えてＪＢＳ構造を採用することにより、逆方向電圧を印加したときにｐ層１６から空乏層が広がるので、電界強度をより一様にすることができ、リーク電流が低減する。 <D. Embodiment 3>
<D-1. Structure>
FIG. 21 is a cross-sectional view of a JBS as a semiconductor device according to the third embodiment. In the JBS according to the third embodiment, the p-layer 6 is selectively formed on the surface of the n drift layer 3 in the configuration of the SBD according to the first embodiment shown in FIG. By adopting the JBS structure in addition to the SJ structure, the depletion layer spreads from the p layer 16 when a reverse voltage is applied, so that the electric field strength can be made more uniform and the leakage current can be reduced.

　＜Ｄ－２．効果＞
　本実施の形態の半導体装置は、実施の形態１の半導体装置の構成に加えて、ｎドリフト層３（ドリフト層）の表面に選択的に配置された第２導電型のｐ層１６（第２不純物領域）をさらに備えたＪＢＳである。逆方向電圧の印加時にはｐ層１６からもｎドリフト層３に空乏層が広がるため、電界強度をより一様にすることができ、リーク電流が低減する。 <D-2. Effect>
In addition to the configuration of the semiconductor device of the first embodiment, the semiconductor device of the present embodiment has a second conductivity type p layer 16 (second layer) selectively disposed on the surface of the n drift layer 3 (drift layer). The JBS further includes an impurity region. When a reverse voltage is applied, a depletion layer extends from the p layer 16 to the n drift layer 3, so that the electric field strength can be made more uniform and the leakage current is reduced.

　また、基板１にＳｉＣ基板を用いる場合には、耐圧を保持するための第１の層をより薄く形成することが可能であるので、より低オン抵抗にすることが可能である。 Further, when an SiC substrate is used as the substrate 1, the first layer for maintaining the withstand voltage can be formed thinner, so that the on-resistance can be further reduced.

　＜Ｅ．実施の形態４＞
　＜Ｅ－１．構造＞
　図２２は、実施の形態４に係る半導体装置としてのＭＯＳ（Metal Oxide Semiconductor）の断面図である。実施の形態４に係るＭＯＳは、図１に示す実施の形態１に係るＳＪ構造を適用したＭＯＳであり、従来のＭＯＳに比べて十分な耐圧を確保できるので、ｎドリフト層３の不純物濃度を高く出来る。このため、電流経路の電気抵抗を低く設定できる。 <E. Embodiment 4>
<E-1. Structure>
FIG. 22 is a cross-sectional view of a metal oxide semiconductor (MOS) as a semiconductor device according to the fourth embodiment. The MOS according to the fourth embodiment is a MOS to which the SJ structure according to the first embodiment shown in FIG. 1 is applied, and can secure a sufficient breakdown voltage as compared with the conventional MOS. Therefore, the impurity concentration of the n drift layer 3 is reduced. Can be high. For this reason, the electrical resistance of the current path can be set low.

　実施の形態４のＭＯＳは、図１に示したＳＢＤの構造において、ｎドリフト層３の表面にｐベース領域２１、ｐボディ領域２２、ｎ＋ソース層２３が設けられ、アノード電極９に代えてソース電極２４を、カソード電極１１に代えてドレイン電極２５をそれぞれ設けたものである。また、ｎ＋ソース層２３、ｐベース領域２１、ｎドリフト層３上に亘って、ゲート酸化膜１９を介してゲート電極２７が設けられる。ゲート電極２７とソース電極２４は層間絶縁膜２０により絶縁される。 In the MOS transistor of the fourth embodiment, a p base region 21, a p body region 22, and an n + source layer 23 are provided on the surface of the n drift layer 3 in the SBD structure shown in FIG. A drain electrode 25 is provided in place of the electrode 24 in place of the cathode electrode 11. A gate electrode 27 is provided on the n + source layer 23, the p base region 21, and the n drift layer 3 through the gate oxide film 19. The gate electrode 27 and the source electrode 24 are insulated by the interlayer insulating film 20.

　＜Ｅ－２．効果＞
　本実施の形態のＭＯＳは、ｎドリフト層３の表面に選択的に設けられたｐベース領域２１と、ｐベース領域２１の表面にｐベース領域２１よりも高い不純物濃度で選択的に設けられたｐボディ領域２２と、ｐベース領域２１の表面にｎドリフト層３よりも高い不純物濃度で選択的に設けられたｎ＋ソース層２３と、ｐベース領域２１を跨るように設けられたゲート酸化膜１９と、ゲート酸化膜１９上に設けられたゲート電極２７と、ｎ＋ソース層２３上に形成されたソース電極２４と、基板１の裏面に形成されたドレイン電極２５と、を備える。このようなＭＯＳ構造に実施の形態１のＳＪ構造を適用することにより十分な耐圧を確保できるので、ｎドリフト層３の不純物濃度を高くすることが可能で、電流経路の電気抵抗を低く設定できる。 <E-2. Effect>
The MOS according to the present embodiment is selectively provided on the surface of the n drift layer 3 with a p base region 21 and on the surface of the p base region 21 with an impurity concentration higher than that of the p base region 21. A p body region 22, an n + source layer 23 selectively provided on the surface of the p base region 21 with an impurity concentration higher than that of the n drift layer 3, and a gate oxide film 19 provided so as to straddle the p base region 21. A gate electrode 27 provided on the gate oxide film 19, a source electrode 24 formed on the n + source layer 23, and a drain electrode 25 formed on the back surface of the substrate 1. By applying the SJ structure of the first embodiment to such a MOS structure, a sufficient breakdown voltage can be secured, so that the impurity concentration of the n drift layer 3 can be increased and the electric resistance of the current path can be set low. .

　＜Ｆ．実施の形態５＞
　＜Ｆ－１．構造＞
　図２３は、実施の形態５に係る半導体装置としてのトレンチＭＯＳの断面図である。実施の形態５に係るトレンチＭＯＳは、図１に示す実施の形態１に係るＳＪ構造を適用したトレンチＭＯＳであり、従来のトレンチＭＯＳに比べて十分な耐圧を確保できるので、ｎドリフト層３の不純物濃度を高く出来る。このため、電流経路の電気抵抗を低く設定できる。 <F. Embodiment 5>
<F-1. Structure>
FIG. 23 is a cross-sectional view of a trench MOS as a semiconductor device according to the fifth embodiment. The trench MOS according to the fifth embodiment is a trench MOS to which the SJ structure according to the first embodiment shown in FIG. 1 is applied, and a sufficient breakdown voltage can be secured as compared with the conventional trench MOS. Impurity concentration can be increased. For this reason, the electrical resistance of the current path can be set low.

　実施の形態５のトレンチＭＯＳは、図２３に示した実施の形態４のＭＯＳにおいて、ゲート電極２７をトレンチゲートに変更したものである。すなわち、ｎドリフト層３には表面から所定の深さにまでトレンチ２６が形成され、トレンチ２６を挟むｎドリフト層３の表面には、ｐベース領域２１が選択的に形成される。ｐベース領域２１の表面には、ｐベース領域２１よりも高い不純物濃度でｐボディ領域２２が、ｎドリフト層３よりも高い不純物濃度でｎ＋ソース層２３がそれぞれ選択的に設けられる。ｎ＋ソース層２３はトレンチ２６に隣接して設けられる。トレンチ内２６にはゲート酸化膜１９が設けられ、ゲート酸化膜１９上にはトレンチ２６に埋め込むようにしてゲート電極２７が設けられる。これ以外の構成は実施の形態４のＭＯＳと同様である。 The trench MOS of the fifth embodiment is obtained by changing the gate electrode 27 to a trench gate in the MOS of the fourth embodiment shown in FIG. That is, the trench 26 is formed in the n drift layer 3 from the surface to a predetermined depth, and the p base region 21 is selectively formed on the surface of the n drift layer 3 sandwiching the trench 26. On the surface of the p base region 21, a p body region 22 having an impurity concentration higher than that of the p base region 21 and an n + source layer 23 having an impurity concentration higher than that of the n drift layer 3 are selectively provided. The n + source layer 23 is provided adjacent to the trench 26. A gate oxide film 19 is provided in the trench 26, and a gate electrode 27 is provided on the gate oxide film 19 so as to be embedded in the trench 26. The other configuration is the same as that of the MOS of the fourth embodiment.

　＜Ｆ－２．効果＞
　本実施の形態の半導体装置であるトレンチＭＯＳでは、ｎドリフト層３の表面から所定の深さにまで選択的にトレンチ２６が形成され、ｎドリフト層３のトレンチ２６を挟む表面に選択的に設けられた第２導電型のｐベース領域２１と、ｐベース領域２１の表面にｐベース領域２１よりも高い不純物濃度で選択的に設けられた第２導電型のｐボディ領域２２と、ｐベース領域２１の表面にｎドリフト層３よりも高い不純物濃度で選択的に設けられた第１導電型のｎ＋ソース層２３と、トレンチ２６内に設けられたゲート酸化膜１９と、トレンチ２６内においてゲート酸化膜１９上に設けられたゲート電極２７と、ｎ＋ソース層２３上に形成されたソース電極２４と、基板１の裏面に形成されたドレイン電極２５を備える。このようなトレンチＭＯＳ構造に実施の形態１のＳＪ構造を適用することによりチャンネル抵抗、ＪＦＥＴ抵抗だけでなくドリフト抵抗も耐圧を保ったまま低減できるため、より低損失にできる。 <F-2. Effect>
In the trench MOS that is the semiconductor device of the present embodiment, the trench 26 is selectively formed from the surface of the n drift layer 3 to a predetermined depth, and is selectively provided on the surface of the n drift layer 3 sandwiching the trench 26. Second conductivity type p base region 21, second conductivity type p body region 22 selectively provided on the surface of p base region 21 at a higher impurity concentration than p base region 21, and p base region The n + source layer 23 of the first conductivity type selectively provided on the surface of 21 with an impurity concentration higher than that of the n drift layer 3, the gate oxide film 19 provided in the trench 26, and the gate oxidation in the trench 26 A gate electrode 27 provided on the film 19, a source electrode 24 formed on the n + source layer 23, and a drain electrode 25 formed on the back surface of the substrate 1 are provided. By applying the SJ structure of the first embodiment to such a trench MOS structure, not only the channel resistance and JFET resistance but also the drift resistance can be reduced while maintaining the withstand voltage, so that the loss can be further reduced.

　なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。 It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

　この発明は詳細に説明されたが、上記した説明は、すべての態様において、例示であって、この発明がそれに限定されるものではない。例示されていない無数の変形例が、この発明の範囲から外れることなく想定され得るものと解される。 Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.

　１　基板、３　ｎドリフト層、５　絶縁層、６　ｐ層、７，１７　溝、９　アノード電極、１１　カソード電極、１３，１４　マスク、１６　ｐ層、１８　ｎ＋層、１９　ゲート酸化膜、２０　ｎ＋ソース層、２１　ｐベース領域、２２　ｐボディ領域、２３　ｎ＋ソース層、２４　ソース電極、２５　ドレイン電極、２６　トレンチ、２７　ゲート電極。 1 substrate, 3 n drift layer, 5 insulating layer, 6 p layer, 7, 17 groove, 9 anode electrode, 11 cathode electrode, 13, 14 mask, 16 p layer, 18 n + layer, 19 gate oxide film, 20 n + source Layer, 21 p base region, 22 p body region, 23 n + source layer, 24 source electrode, 25 drain electrode, 26 trench, 27 gate electrode.

Claims (16)

　半導体基板と、
　前記半導体基板上に形成された第１の層とを備え、
　前記第１の層は、
　表面から前記半導体基板に接する裏面に亘って配置されエピタキシャル成長で形成された第１導電型のドリフト層と、
　前記表面から所定の深さに亘って、前記ドリフト層と離間して配置された絶縁層と、
　前記表面から前記所定の深さに亘って前記絶縁層と前記ドリフト層に接し且つ挟まれて配置された第２導電型の第１不純物領域とを備え、
　第１不純物領域の不純物濃度は、前記表面から深さ方向に向かって減少する、
半導体装置。 A semiconductor substrate;
A first layer formed on the semiconductor substrate,
The first layer is
A drift layer of a first conductivity type disposed by epitaxial growth from the front surface to the back surface in contact with the semiconductor substrate;
An insulating layer disposed away from the drift layer over a predetermined depth from the surface;
A first impurity region of a second conductivity type disposed between and in contact with the insulating layer and the drift layer from the surface to the predetermined depth;
The impurity concentration of the first impurity region decreases in the depth direction from the surface.
Semiconductor device. 　第１不純物領域の不純物濃度は、表面から深さ方向に向かって中央部に濃度が一定の領域を有しながら減少する分布を有する、
請求項１に記載の半導体装置。 The impurity concentration of the first impurity region has a distribution that decreases while having a region having a constant concentration in the center from the surface toward the depth direction.
The semiconductor device according to claim 1. 　前記第１の層の前記表面上に形成された電極をさらに備え、
　前記電極は前記ドリフト層とショットキー接触し、前記第１不純物領域とオーミック接触する、
請求項２に記載の半導体装置。 An electrode formed on the surface of the first layer;
The electrode is in Schottky contact with the drift layer and in ohmic contact with the first impurity region;
The semiconductor device according to claim 2. 　前記ドリフト層の前記表面に選択的に配置された第２導電型の第２不純物領域をさらに備える、
請求項１～３のいずれかに記載の半導体装置。 A second impurity region of a second conductivity type selectively disposed on the surface of the drift layer;
The semiconductor device according to any one of claims 1 to 3. 　前記半導体基板はＳｉＣ基板である、
請求項１～３のいずれかに記載の半導体装置。 The semiconductor substrate is a SiC substrate;
The semiconductor device according to any one of claims 1 to 3. 　前記半導体基板はＳｉＣ基板である、
請求項４に記載の半導体装置。 The semiconductor substrate is a SiC substrate;
The semiconductor device according to claim 4. 　前記ドリフト層の前記表面に選択的に設けられた第２導電型のベース領域と、
　前記ベース領域の表面に前記ベース領域よりも高い不純物濃度で選択的に設けられた第２導電型のボディ領域と、
　前記ベース領域の表面に前記ドリフト層よりも高い不純物濃度で選択的に設けられた第１導電型のソース層と、
　前記ベース領域と前記ドリフト層に跨るように設けられたゲート酸化膜と、
　前記ゲート酸化膜上に設けられたゲート電極と、
　前記ソース層上に形成されたソース電極と、
　前記半導体基板の裏面に形成されたドレイン電極と、をさらに備える、
請求項２に記載の半導体装置。 A base region of a second conductivity type selectively provided on the surface of the drift layer;
A second conductivity type body region selectively provided on the surface of the base region with an impurity concentration higher than that of the base region;
A source layer of a first conductivity type selectively provided on the surface of the base region with an impurity concentration higher than that of the drift layer;
A gate oxide film provided to straddle the base region and the drift layer;
A gate electrode provided on the gate oxide film;
A source electrode formed on the source layer;
A drain electrode formed on the back surface of the semiconductor substrate;
The semiconductor device according to claim 2. 　前記ドリフト層は前記表面から所定の深さにまで選択的にトレンチが形成され、
　前記ドリフト層の前記トレンチを挟む前記表面に選択的に設けられた第２導電型のベース領域と、
　前記ベース領域の表面に前記ベース領域よりも高い不純物濃度で選択的に設けられた第２導電型のボディ領域と、
　前記ベース領域の表面に前記ドリフト層よりも高い不純物濃度で選択的に設けられた第１導電型のソース層と、
　前記トレンチ内に設けられたゲート酸化膜と、
　前記トレンチ内において前記ゲート酸化膜上に設けられたゲート電極と、
　前記ソース層上に形成されたソース電極と、
　前記半導体基板の裏面に形成されたドレイン電極と、をさらに備える、
請求項２に記載の半導体装置。 The drift layer is selectively formed with a trench from the surface to a predetermined depth,
A base region of a second conductivity type selectively provided on the surface of the drift layer sandwiching the trench;
A second conductivity type body region selectively provided on the surface of the base region with an impurity concentration higher than that of the base region;
A source layer of a first conductivity type selectively provided on the surface of the base region with an impurity concentration higher than that of the drift layer;
A gate oxide film provided in the trench;
A gate electrode provided on the gate oxide film in the trench;
A source electrode formed on the source layer;
A drain electrode formed on the back surface of the semiconductor substrate;
The semiconductor device according to claim 2. 　（ａ）半導体基板を準備する工程と、
　（ｂ）前記半導体基板上に第１導電型のドリフト層をエピタキシャル成長で形成する工程と、
　（ｃ）前記ドリフト層に所定の深さの溝を形成する工程と、
　（ｄ）前記溝の側壁に第２導電型の不純物を注入して、第２導電型の第１不純物領域を形成する工程と、
　（ｅ）前記溝の内部に絶縁層を充填する工程とを備え、
　前記工程（ｄ）は、前記溝の深さ方向に不純物密度が減少する前記第１不純物領域を形成する工程である、
半導体装置の製造方法。 (A) preparing a semiconductor substrate;
(B) forming a first conductivity type drift layer on the semiconductor substrate by epitaxial growth;
(C) forming a groove having a predetermined depth in the drift layer;
(D) implanting a second conductivity type impurity into the side wall of the groove to form a second conductivity type first impurity region;
(E) filling the inside of the groove with an insulating layer,
The step (d) is a step of forming the first impurity region in which the impurity density decreases in the depth direction of the groove.
A method for manufacturing a semiconductor device. 　前記工程（ｄ）は、第１不純物領域の不純物濃度が、前記溝の深さ方向に向かって中央部に濃度が一定の領域を有しながら低下する分布を有するように前記第１不純物領域を形成する工程である、
請求項９に記載の半導体装置の製造方法。 In the step (d), the first impurity region is distributed so that the impurity concentration of the first impurity region has a distribution that decreases while having a region having a constant concentration in the central portion in the depth direction of the groove. A process of forming,
A method for manufacturing a semiconductor device according to claim 9. 　前記工程（ｄ）は、前記溝の深さ方向に対して斜めから前記第２導電型の不純物を注入する工程である、
請求項９に記載の半導体装置の製造方法。 The step (d) is a step of implanting the second conductivity type impurity obliquely with respect to the depth direction of the groove.
A method for manufacturing a semiconductor device according to claim 9. 　（ｆ）前記工程（ｅ）の後、前記ドリフト層とショットキー接触し、前記第１不純物領域とオーミック接触された電極を形成する工程とを備える、
請求項９に記載の半導体装置の製造方法。 (F) After the step (e), including a step of forming an electrode in Schottky contact with the drift layer and in ohmic contact with the first impurity region.
A method for manufacturing a semiconductor device according to claim 9. 　前記工程（ｃ）は、前記溝をテーパー形状に形成する工程であり、
　（ｇ）前記工程（ｃ）と（ｄ）の間に、前記溝の底部近傍の側壁に第１導電型の不純物を前記半導体基板に対して垂直な方向から注入する工程をさらに備える、
請求項９に記載の半導体装置の製造方法。 The step (c) is a step of forming the groove into a tapered shape.
(G) Further comprising a step of injecting a first conductivity type impurity into the side wall near the bottom of the groove from a direction perpendicular to the semiconductor substrate between the steps (c) and (d).
A method for manufacturing a semiconductor device according to claim 9. 　前記工程（ｃ）は、前記ドリフト層を貫通しない前記溝を形成する工程である、
請求項９に記載の半導体装置の製造方法。 The step (c) is a step of forming the groove that does not penetrate the drift layer.
A method for manufacturing a semiconductor device according to claim 9. 　前記工程（ｅ）は、複数回に分けて前記溝の内部に絶縁層を充填する工程であり、
　前記工程（ｄ）は、前記工程（ｅ）と交互に繰り返し行われる、
請求項９に記載の半導体装置の製造方法。 The step (e) is a step of filling the groove with an insulating layer divided into a plurality of times,
The step (d) is repeatedly performed alternately with the step (e).
A method for manufacturing a semiconductor device according to claim 9. 　前記工程（ａ）は、ＳｉＣからなる前記半導体基板を準備する工程である、
請求項９に記載の半導体装置の製造方法。 The step (a) is a step of preparing the semiconductor substrate made of SiC.
A method for manufacturing a semiconductor device according to claim 9.
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