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WO2013038978A1 - Dispositif de transmission de signal et procédé de transmission de signal - Google Patents

Dispositif de transmission de signal et procédé de transmission de signal Download PDF

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Publication number
WO2013038978A1
WO2013038978A1 PCT/JP2012/072697 JP2012072697W WO2013038978A1 WO 2013038978 A1 WO2013038978 A1 WO 2013038978A1 JP 2012072697 W JP2012072697 W JP 2012072697W WO 2013038978 A1 WO2013038978 A1 WO 2013038978A1
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WO
WIPO (PCT)
Prior art keywords
transmission
signal
reception
level
data
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Application number
PCT/JP2012/072697
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English (en)
Japanese (ja)
Inventor
進吾 野村
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シャープ株式会社
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Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2013038978A1 publication Critical patent/WO2013038978A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J7/00—Multiplex systems in which the amplitudes or durations of the signals in individual channels are characteristic of those channels

Definitions

  • the present invention relates to a signal transmission device and a signal transmission method, and more particularly, to a signal transmission device and a signal transmission method suitable for transmitting a plurality of types of data.
  • LVDS Low Voltage Differential Signaling
  • a level shift circuit is provided in the input portion of the source driver, and the amplitude of data serially transmitted from the output buffer of the controller IC to the source driver is set to the level.
  • a display device that boosts voltage by a shift circuit is disclosed. According to such a configuration, since the amplitude of data to be transmitted from the controller IC to the source driver can be reduced, data transmission with low power consumption can be realized as in the case of the LVDS.
  • an object of the present invention is to provide a signal transmission device and a signal transmission method that can transmit a plurality of data while suppressing an increase in cost.
  • a first aspect of the present invention is a signal transmission device that serially transmits a plurality of types of data between a transmission unit and a reception unit through a single transmission line
  • the transmitter is To receive a first clock signal that periodically changes, a second clock signal obtained by multiplying the frequency of the first clock signal by N (N is an integer of 2 or more), and N transmission-side data signals to be transmitted from the outside.
  • the sending input terminal of The N transmission-side data signals are sequentially sampled in synchronization with the second clock signal every one cycle of the first clock signal, and the voltage levels of the sampled N transmission-side data signals are made different from each other.
  • a transmission side signal processing unit for generating a transmission signal by A transmission side output terminal for outputting the transmission signal to the transmission line
  • the receiver is A receiving-side input terminal for receiving the first clock signal, the second clock signal, and the transmission signal from the transmission path;
  • the transmission signal is sampled in synchronization with the second clock signal for each cycle of the first clock signal, and the voltage levels of the sampled transmission signal are set to the N transmission sides before the voltage level changes.
  • a receiving-side signal processing unit that generates N receiving-side data signals by changing to a voltage level corresponding to the data signal;
  • a reception side output terminal for outputting the N reception side data signals to the outside.
  • the transmission-side signal processing unit includes a transmission-side phase control unit that varies the phases of the N transmission-side data signals by a period corresponding to one cycle of the second clock signal in synchronization with the second clock signal. It is characterized by that.
  • the transmission-side signal processing unit samples the N transmission-side data signals in synchronization with the second clock signal every cycle of the first clock signal, and the voltage level of each transmission data signal is transmitted.
  • the voltage level of the transmission data signal By converting the voltage level of the transmission data signal into one or the other of any two voltage levels of the N + 1 predetermined voltage levels, respectively, It further includes a transmission signal converter that generates the transmission signal having N + 1 types of voltage levels.
  • the transmission signal converting unit further converts a transmission-side second level of a preceding transmission-side data signal out of two transmission-side data signals in which periods to be sampled in each cycle of the first clock signal are continuous.
  • the subsequent voltage level and the voltage level after the conversion of the transmission side first level of the subsequent transmission side data signal are made the same.
  • the transmission-side phase control unit and the transmission signal conversion unit are realized as one processing device.
  • the reception-side signal processing unit samples the transmission signal in synchronization with the second clock signal for each cycle of the first clock signal, and the transmission signal of the sampled voltage level of the transmission signal.
  • the voltage converted from the first level on the transmission side in the conversion unit is converted to the first level on the reception side corresponding to the first level on the transmission side, and the voltage level converted from the second level on the transmission side is converted to the transmission side.
  • a transmission signal inverse conversion unit that generates the N reception side data signals by converting the reception side second level corresponding to the second level is included.
  • a seventh aspect of the present invention is the sixth aspect of the present invention.
  • the reception-side signal processing unit further includes a reception-side phase control unit that synchronizes the N reception-side data signals with each other in synchronization with the second clock signal.
  • the transmission signal inverse conversion unit and the reception-side phase control unit are realized as one processing device.
  • the transmission unit further includes a level shift signal generation unit that generates N level shift signals having different voltage levels.
  • the transmission-side signal processing unit is characterized in that the voltage levels of the sampled N transmission-side data signals are different from each other based on the N level-shifted signals.
  • a tenth aspect of the present invention is a signal transmission method in a signal transmission device that performs serial transmission of a plurality of types of data through a single transmission path between a transmission unit and a reception unit, N transmissions to be transmitted in synchronization with a second clock signal obtained by multiplying the frequency of the first clock signal by N (N is an integer of 2 or more) for each period of the periodically changing first clock signal.
  • the transmitter unit sequentially samples the N transmission-side data signals based on the timings of the first clock signal and the second clock signal, and changes their voltage levels.
  • the generated transmission signal is generated and transmitted from the transmitting unit to the receiving unit via one transmission path.
  • N reception-side data signals respectively corresponding to the voltage levels of the portions corresponding to the N transmission-side data signals in the transmission signal are based on the first clock signal and the second clock signal.
  • the voltage levels of the portions corresponding to the N transmission-side data signals in the transmission signal are different from each other. Based on the difference in level, for example, transmission defects can be reduced.
  • N pieces of data are reliably transmitted using one transmission path.
  • a plurality of types of data can be transmitted while suppressing an increase in cost.
  • the amount of data transmission per transmission line is increased, data transmission can be performed more efficiently than in the past.
  • N transmission-side data signals in each cycle of the first clock signal can be sampled in order.
  • the voltage level of the transmission side data signal when the voltage level of the transmission side data signal is the transmission side first level or the transmission side second level, the voltage level of the transmission side data signal is N + 1 predetermined values.
  • the type of the voltage level of the transmission signal becomes N + 1.
  • the transmitting side of the preceding transmitting side data signal out of the two transmitting side data signals in which the period to be sampled in each cycle of the first clock signal continues.
  • the voltage level after the two-level conversion is the same as the voltage level after the conversion of the transmission-side first level of the subsequent transmission-side data signal.
  • both the transmitter first level and the transmitter second level of the transmitter data signal to be sampled first in each period of the first clock signal should be sampled last in each period of the first clock signal. It is assumed that the transmission side data signal is larger than both the transmission side first level and the transmission side second level.
  • a reception unit that can generate N reception-side data signals from transmission signals having N + 1 types of voltage levels is used to change the voltage level of the transmission signal.
  • the first period of the second clock signal in each period of the first clock signal can be determined, the synchronization shift can be eliminated.
  • the transmission-side phase control unit and the transmission signal conversion unit are realized as one processing device. For this reason, the scale of a transmission part can be reduced by sharing a common component with each other in a transmission side phase control part and a transmission signal conversion part.
  • each of the N transmission sides of the transmission signal in the first cycle to the Nth cycle of the second clock signal in each cycle of the first clock signal is sampled, and the voltage level of each of the N receiving data signals is determined based on the voltage level of the portion corresponding to the N transmitting data signals of the transmission signal.
  • the phases of N reception-side data signals can be aligned and output.
  • the transmission signal inverse conversion unit and the reception-side phase control unit are realized as one processing device. For this reason, it is possible to reduce the size of the reception unit by sharing the common components in the transmission signal inverse conversion unit and the reception-side phase control unit.
  • a ninth aspect of the present invention by generating a voltage level for generating a transmission signal from N transmission-side data signals using a level shift signal generation unit, Similar effects can be achieved.
  • the same effect as in the first aspect of the present invention can be achieved.
  • 1 is a block diagram illustrating a configuration of a signal transmission system according to a first embodiment of the present invention. It is a block diagram which shows the structure of the transmission part in the said 1st Embodiment. It is a block diagram which shows the structure of the transmission side level control processor in the said 1st Embodiment. It is a block diagram which shows the structure of the receiving part in the said 1st Embodiment. It is a block diagram which shows the structure of the receiving side level control processor in the said 1st Embodiment. It is a signal waveform diagram which shows the transmission side data signal before the transmission side phase control process in the said 1st Embodiment.
  • FIG. 1 is a block diagram showing the configuration of the signal transmission system according to the present embodiment.
  • This signal transmission system is used, for example, for transmission of image data from a display control circuit in a display device to a source driver.
  • the signal transmission system includes a host 1 and a signal transmission device 2.
  • the host 1 is typically a CPU, and provides the signal transmission apparatus 2 with a transmission side control signal CT and a reception side control signal CR.
  • the three types of transmission side data signals DTa to DTc are referred to as first to third transmission side data signals, respectively, and the three types of reception side data signals DRa to DRc are respectively referred to as first to third reception side data signals. That's it.
  • the first to third transmission side data signals DTa to DTc and the first to third reception side data signals DRa to DRc are composed of bit strings.
  • system period and “sampling period”, respectively, and are denoted by symbols TA and TB, respectively, in the subsequent signal waveform diagrams.
  • the X (X is an integer of 2 or more) sampling period is represented by “XTB”.
  • the first to third sampling periods in each system period are referred to as “first to third sampling periods”, respectively.
  • the signal transmission device 2 includes a transmission unit 3, a reception unit 4, and a single transmission path 5 for connecting the transmission unit 3 and the reception unit 4 to each other.
  • the transmission line 5 may be either a differential transmission line or a single-ended transmission line.
  • “One transmission line” means a pair of transmission lines in the case of differential transmission.
  • the transmission unit 3 and the reception unit 4 are supplied with a power supply voltage by means not shown.
  • the transmission unit 3 receives the first to third transmission side data signals DTa to DTc, the system clock SYS, the sampling clock SAM, and the power supply voltage, and generates a transmission signal TS based on these.
  • the transmission signal TS is transmitted from the transmission unit 3 to the reception unit 4 via the transmission path 5.
  • the receiving unit 4 receives the transmission signal TS, the system clock SYS, the sampling clock SAM, and the power supply voltage, and generates the first to third receiving side data signals DRa to DRc based on these. That is, in the signal transmission device 2, the three types of first to third transmission side data signals DTa to DTc received by the transmission unit 3 are respectively converted into three types of first to third reception side data signals DRa to DRc. Is transmitted.
  • FIG. 2 is a block diagram illustrating a configuration of the transmission unit 3 in the present embodiment.
  • the transmission unit 3 includes input terminals IT1, IT2, IT3a to IT3c, IT4a to IT4c, and IT5a to IT5c, an output terminal OT, a transmission side level shifter 30, and a transmission side level control processor 31.
  • the input terminals IT1, IT2, IT3a to IT3c correspond to transmission side input terminals.
  • the output terminal OT corresponds to the transmission side output terminal.
  • the input terminal IT1 is a terminal for receiving the system clock SYS.
  • the input terminal IT2 is a terminal for receiving the sampling clock SAM.
  • Input terminals IT3a to IT3c are terminals for receiving first to third transmission side data signals DTa to DTc, respectively.
  • Input terminals IT4a to IT4c are terminals for receiving first to third transmission side control signals CTa to CTc, respectively.
  • the input terminals IT5a to IT5c are terminals for receiving the transmission side first to third power supply voltages VHa to VHc as the power supply voltages, respectively.
  • the output terminal OT is a terminal for outputting the transmission signal TS.
  • the transmission-side first to third power supply voltages VHa to VHc have different voltage levels.
  • the voltage levels of the transmission-side first to third power supply voltages VHa to VHc may also be represented by VHa to VHc, respectively.
  • the magnitude relationship between the VHa to VHc levels is VHa> VHb> VHc.
  • the transmission side level shifter 30 receives the first to third transmission side control signals CTa to CTc and the transmission side first to third power supply voltages VHa to VHc, and sets the voltage levels of the first to third transmission side control signals CTa to CTc.
  • First to third transmission side level shift signals LSTa to LSTc which are signals shifted to VHa to VHc levels, are generated and output.
  • the voltage levels of the first to third transmission side control signals CTa to CTc are fixed when the signal transmission device 2 is in operation.
  • the voltage levels of the first to third transmission side control signals CTa to CTc may be different from each other or the same.
  • the voltage levels of the first to third transmission side control signals CTa to CTc are typically smaller than the VHa to VHc levels, respectively.
  • the transmission side level control processor 31 includes first to third transmission side data signals DTa to DTc, a system clock SYS, a sampling clock SAM, and first to third transmission side level shift signals LSTa output from the transmission side level shifter 30. LSTc is received, and based on these, a transmission signal TS is generated and output.
  • the transmission side signal processing unit is realized by the transmission side level shifter 30 and the transmission side level control processor 31.
  • FIG. 3 is a block diagram showing a configuration of the transmission side level control processor 31 in the present embodiment.
  • the transmission side level control processor 31 includes a transmission side input buffer 310, a transmission side delay circuit 311, a transmission side data discrimination circuit 312, a transmission signal conversion circuit 313 as a transmission signal conversion unit, and a transmission side output.
  • a buffer 314 is provided.
  • the transmission side input buffer 310 is a buffer for receiving the first to third transmission side data signals DTa to DTc.
  • the transmission side delay circuit 311 receives the first to third transmission side data signals DTa to DTc via the transmission side input buffer 310, and based on the timing of the sampling clock SAM, these first to third transmission side data signals DTa. .. DTc are output with different phases.
  • transmission side phase control process the process of making the phases of the first to third transmission side data signals DTa to DTc different from each other in this way is referred to as “transmission side phase control process”.
  • a transmission side phase control unit is realized by the transmission side delay circuit 311.
  • the transmission side data discriminating circuit 312 has the bit data (referred to as data indicating “1” or “0”) of the first to third transmission side data signals DTa to DTc after the transmission side phase control processing being “1”. Whether “0” is indicated is determined based on the timing of the sampling clock SAM, and first to third transmission side determination signals RTa to RTc are output as the determination results.
  • the voltage level of the bit data indicating “1” in each transmission side data signal corresponds to the first level on the transmission side
  • the voltage level of bit data indicating “0” corresponds to the second level on the transmission side.
  • the transmission signal conversion circuit 313 receives the first to third transmission side discrimination signals RTa to RTc, and based on the timings of the system clock SYS and the sampling clock SAM, the first to third transmission side discrimination signals RTa to RTc (that is, the first transmission side discrimination signals RTa to RTc). (Bit data of third transmission side data signals DTa to DTc) are sequentially sampled, and one transmission signal TS is generated and output by converting the voltage level of these data. Specifically, the transmission signal conversion circuit 313 is a voltage at which the first transmission side discrimination signal RTa (that is, the bit data of the first transmission side data signal DTa) sampled in the first sampling period indicates “1” or “0”.
  • the second transmission side discrimination signal RTb that is, bit data of the second transmission side data signal DTb sampled in the second sampling period is “1” or “0”.
  • the third transmission side discrimination signal RTc that is, the bit data of the third transmission side data signal DTc sampled in the third sampling period is “1” or “0”.
  • VHc level or GND level as a predetermined voltage level. Converted to le (ground level).
  • the transmission signal conversion circuit 313 arranges the first to third transmission side discrimination signals RTa to RTc in order for each system period, and also converts one transmission signal TS obtained by converting these voltage levels as described above. Generate and output.
  • portions of the transmission signal TS corresponding to the bit data of the first to third transmission side data signals DTa to DTc are referred to as “first to third transmission / reception data”, respectively, and are represented by symbols TR1 to TR3, respectively.
  • the transmission signal conversion circuit 313 may be provided with the function of the transmission side data determination circuit 312 and the transmission side data determination circuit 312 may not be provided.
  • the voltage level corresponding to “0” of the first transmission / reception data TR1 and the voltage level corresponding to “1” of the second transmission / reception data TR2 are the same VHb level.
  • the voltage level corresponding to “0” of the second transmission / reception data TR2 and the voltage level corresponding to “1” of the third transmission / reception data TR3 are the same VHc level. That is, the voltage level after conversion of “0” of the preceding transmission side data signal of the two transmission side data signals in which the period to be sampled in each system period is continuous, and “1” of the subsequent transmission side data signal.
  • the converted voltage levels are the same as each other.
  • the voltage level corresponding to “1” of the first transmission / reception data TR1 (bit data indicating “1” of the first transmission side data signal DTa sampled in the first sampling period which is the first sampling period of each system period) Is the VHa level, and the VHa level does not overlap with others.
  • the voltage level corresponding to “0” of the third transmission / reception data TR3 (the voltage level after conversion of the third transmission side data signal DTc sampled in the third sampling period which is the last sampling period of each system period) Is a GND level, and the GND level does not overlap with other.
  • the transmission side output buffer 314 is a buffer for serially outputting the transmission signal TS.
  • the transmission signal TS output from the transmission side output buffer 314 is transmitted to the receiving unit 4 via the transmission path 5.
  • FIG. 4 is a block diagram showing a configuration of the receiving unit 4 in the present embodiment.
  • the receiving unit 4 includes input terminals IR1 to IR5, output terminals ORa to ORc, a receiving side level shifter 40, and a receiving side level control processor 41.
  • the input terminals IR1 to IR3 correspond to receiving side input terminals.
  • the output terminals ORa to ORc correspond to reception side output terminals.
  • the input terminal IR1 is a terminal for receiving the system clock SYS.
  • the input terminal IR2 is a terminal for receiving the sampling clock SAM.
  • the input terminal IR3 is a terminal for receiving the transmission signal TS.
  • the input terminal IR4 is a signal for receiving the receiving side control signal CR.
  • the input terminal IR5 is a terminal for receiving the reception-side power supply voltage VH as the power supply voltage.
  • the voltage level of the reception-side power supply voltage VH may also be expressed as VH.
  • the output terminals ORa to ORc are terminals for outputting the first to third receiving side data signals DRa to DRc, respectively.
  • the reception-side level shifter 40 receives the reception-side control signal CR and the transmission-side power supply voltage VH, and generates and outputs a reception-side level shift signal LSR that is a signal obtained by shifting the voltage level of the reception-side control signal CR to the VH level.
  • the voltage level of the reception-side control signal CR is fixed when the signal transmission device 2 operates.
  • the voltage level of the reception side control signal CR is typically smaller than the VH level.
  • the receiving side level control processor 41 receives the transmission signal TS, the system clock SYS, the sampling clock SAM, and the receiving side level shift signal LSR outputted from the receiving side level shifter 40, and based on these, the first to third receiving side data Generate and output signals DRa to DRc.
  • the reception side signal processing unit is realized by the reception side level shifter 40 and the reception side level control processor 41.
  • FIG. 5 is a block diagram showing a configuration of the receiving side level control processor 41 in the present embodiment.
  • the reception-side level control processor 41 includes a reception-side input buffer 410, a reception-side data determination circuit 411, a transmission signal inverse conversion circuit 412 as a transmission signal inverse conversion unit, a reception-side delay circuit 413, and a reception side.
  • a side output buffer 414 is provided.
  • the receiving side input buffer 410 is a buffer for receiving the transmission signal TS serially.
  • the reception-side data determination circuit 411 determines whether the first to third transmission / reception data TR1 to TR3 of the transmission signal TS indicate VHa to VHc or the GND level based on the timing of the sampling clock SAM, and these determinations. As a result, the receiving side discrimination signal RR is output.
  • the transmission signal inverse conversion circuit 412 receives the reception side determination signal RR and samples the reception side determination signal RR (that is, the first to third transmission / reception data TR1 to TR3) based on the timings of the system clock SYS and the sampling clock SAM. At the same time, by converting the voltage levels of the first to third transmission / reception data TR1 to TR3, the first to third reception-side data signals DRa to DRc are generated and output, respectively. Specifically, the transmission signal inverse conversion circuit 412 indicates “1” if the reception side determination signal RR is at the VHa or VHb level when the reception side determination signal RR corresponding to the first transmission / reception data TR1 is sampled.
  • a first receiving side data signal DRa having a voltage level (here, assumed to be VH level) or a voltage level indicating “0” (here, assumed to be GND level) is generated. Further, the transmission signal inverse conversion circuit 412 sets “1” or “0” if the reception side determination signal RR is at the VHb or VHc level when the reception side determination signal RR corresponding to the second transmission / reception data TR2 is sampled. The second receiving side data signal DRb having the voltage level shown is generated. In addition, the transmission signal inverse conversion circuit 412 sets “1” or “0” if the reception side determination signal RR is VHc or GND level when the reception side determination signal RR corresponding to the third transmission / reception data TR3 is sampled.
  • the third receiving side data DRc having the voltage level shown is generated.
  • the voltage level indicating “1” of the first to third receiving side data signals DRa to DRc corresponds to the receiving side first level
  • the voltage level indicating “0” corresponds to the receiving side second level.
  • the first to third receiving side data signals DRa to DRc generated here have different phases.
  • the transmission signal inverse conversion circuit 412 may be provided with the function of the reception side data determination circuit 411 and the reception side data determination circuit 411 may not be provided.
  • the reception-side delay circuit 413 receives the first to third reception-side data signals DRa to DRc output from the transmission signal inverse conversion circuit 412, and based on the timing of the sampling clock SAM, these first to third reception-side data
  • the signals DRa to DRc are output with the same phase.
  • the process of making the phases of the first to third reception-side data signals DRa to DRc identical to each other is referred to as “reception-side phase control process”.
  • a reception-side phase control unit is realized by the reception-side delay circuit 413.
  • the reception-side output buffer 414 is a buffer for outputting the first to third reception-side data signals DRa to DRc that are in phase with each other by the reception-side phase control process. These first to third reception side data signals DRa to DRc are output to the outside via the reception side output buffer 414.
  • FIG. 6 is a signal waveform diagram showing the first to third transmission side data signals DTa to DTc before the transmission side phase control processing in this embodiment.
  • each of the first to third transmission side data signals DTa to DTc represents one piece of data in units of 8 bits.
  • 8-bit data of the first transmission-side data signal DTa is represented by A0 to A7
  • 8-bit data of the second transmission-side data signal DTb is represented by B0 to B7, respectively
  • 8 of the third transmission-side data signal DTc Bit data are represented by C0 to C7, respectively.
  • Each of the first to third reception side data signals DRa to DRc is also 8-bit data, and the 8-bit data of the first reception side data signal DRa is also represented by A0 to A7, respectively.
  • the 8-bit data is also represented by B0 to B7, respectively, and the 8-bit data of the third receiving side data signal DRc is also represented by C0 to C7, respectively.
  • a first transmission side data signal DTa first reception side data signal DRa
  • a second transmission side data signal DTb The second reception side data signal DRb
  • the third transmission side data signal DTc third reception side data signal DRc
  • bit data of each transmission-side data signal is blank in two sampling periods (2 TB) for each 2-bit data.
  • such blank data is referred to as “NULL data”, and in FIG. 6 and the subsequent drawings, the data is represented by “NULL”.
  • the bit data of each reception-side data signal changes at the timing when the voltage level of the sampling clock SAM rises every two sampling periods (2TB).
  • FIG. 7 is a signal waveform diagram for explaining the operation of the transmission side delay circuit 311 in this embodiment.
  • the transmission-side delay circuit 311 performs transmission-side phase control processing based on the timing of the sampling clock SAM on the first to third transmission-side data signals DTa to DTc.
  • the first transmission side data signal DTa is subjected to processing in which the second transmission side data signal DTb and the third transmission side data signal DTc are delayed by one sampling period and two sampling periods, respectively.
  • the first to third transmission side data signals DTa to DTc after such transmission side phase control processing are given to the transmission side data determination circuit 312 and then the first to third transmission side determination signals RTa to RTc described above. Is output as
  • FIG. 8 is a signal waveform diagram for explaining the operation of the transmission signal conversion circuit 313 in this embodiment.
  • the first to third transmission side data signals DTa to DTc shown in the figure are actually equivalent to the first to third transmission side discrimination signals RTa to RTc, respectively.
  • Explanation will be given as first to third transmission side data signals DTa to DTc (the same applies to FIG. 17 described later).
  • eight consecutive system periods TA are referred to as “0th to 7th system periods”, respectively, and are represented by symbols TA0 to TA7, respectively.
  • the first to third transmission side data signals DTa to DTc for 8 bits (that is, data for a total of 24 bits) in the 0th to seventh system periods TA0 to TA7.
  • a corresponding transmission signal TS is generated.
  • the first to third transmission side data signals DTa to DTc for 8 bits are “11101101”, “01100101”, and “10111001”, respectively. ". Note that NULL data is not considered as data.
  • the transmission signal conversion circuit 313 determines the voltage level of the transmission signal TS based on the bit data of the first to third transmission side data signals DTa to DTc.
  • the bit data A0 in which the first transmission side data signal DTa to be sampled is “1” indicates the first transmission / reception data TR1 of the transmission signal TS.
  • the voltage level becomes a VHa level corresponding to “1” of the first transmission side data DTa.
  • the second transmission side data signal DTb to be sampled indicates the bit data B0 which is “0”
  • the voltage level of the second transmission / reception data TR2 of the transmission signal TS is the second transmission side data signal. It becomes the VHc level corresponding to “0” of DTb.
  • the transmission signal TS for one system period indicates bit data for one bit of each transmission-side data signal (that is, bit data for a total of three bits).
  • bit data A1 in which the first transmission side data signal DTa to be sampled is “1” indicates the first transmission / reception data TR1 of the transmission signal TS.
  • the voltage level becomes a VHa level corresponding to “1” of the first transmission side data signal DTa.
  • bit data B1 in which the second transmission side data DTb to be sampled is “1” indicates the voltage level of the second transmission / reception data TR2 of the transmission signal TS is the second transmission side data signal DTb.
  • the third transmission side data signal DTc to be sampled indicates bit data C0 that is “0”, so the voltage level of the third transmission / reception data TR3 of the transmission signal TS is the third transmission side data signal. It becomes the GND level corresponding to “0” of DTc.
  • the transmission signal TS is determined in the transmission signal conversion circuit 313 by determining the voltage level of each transmission / reception data of the transmission signal TS by the same procedure. Is generated.
  • the transmission signal TS generated in this way is transmitted to the receiving unit 2 via the transmission side output buffer 314 and the transmission path 5.
  • FIG. 9 is a signal waveform diagram for explaining the operation of the transmission signal inverse conversion circuit 412 in this embodiment. Note that the first to third reception side data signals DRa to DRc shown in this figure are actually obtained based on the reception side determination signal RR generated based on the transmission signal TS. In the following description, these first to third receiving side data signals DRa to DRc will be described as being obtained directly from the transmission signal TS (the same applies to FIG. 18 described later).
  • the transmission signal inverse conversion circuit 412 in this embodiment in the 0th to 7th system periods TA0 to TA7, based on the transmission signal TS, 8-bit first to third receiving side data signals DRa to DRc (ie, A total of 24 bits of data) is generated. Since the 0th to 7th system periods TA0 to TA7 are names for convenience, the timings of the 0th to 7th system periods TA0 to TA7 on the transmitting side and the receiving side do not have to coincide with each other.
  • the transmission signal inverse conversion circuit 412 samples the first to third transmission / reception data TR1 to TR3 of the transmission signal TS, and the first to third transmission / reception data TR1.
  • Bit data of the first to third receiving data signals DRa to DRa are determined based on the voltage levels of .about.TR3, respectively.
  • bit data A0 of the first reception side data signal DRa becomes “1”.
  • bit data indicating “1” is realized by the VH level
  • bit data indicating “0” is realized by the GND level.
  • the bit data B0 of the second reception side data signal DRb is “0”.
  • the bit data C0 of the third reception-side data signal DRc is “1”. In this manner, 1-bit bit data of each reception-side data signal (that is, bit data for a total of 3 bits) is obtained from the transmission signal TS for one system period.
  • the bit data A1 of the first reception side data DRa becomes “1”.
  • the bit data B1 of the second reception side data signal DRb is “1”.
  • the bit data C1 of the third reception-side data signal DRc is “0”.
  • the bit data of the first to third reception side data signals DRa to DTa is determined by the same procedure, so that the reception side phase control is performed.
  • First to third receiving side data signals DRa to DRc before processing are generated.
  • the first to third receiving side data signals DRa to DRc indicate “11101101”, “01100101”, and “10111001”, respectively. That is, the first to third reception side data signals DRa to DRc indicate the same bit data as the first to third transmission side data signals DTa to DTc, respectively.
  • NULL data is not considered as described above.
  • the first to third reception-side data signals DRa to DRc before the reception-side phase control processing generated in this way are given to the reception-side delay circuit 413.
  • FIG. 10 is a signal waveform diagram showing the first to third reception side data signals DRa to DRc before the reception side phase control processing.
  • the bit data of each reception side data signal changes at the timing when the voltage level of the sampling clock SAM rises every three sampling periods (3TB).
  • the present invention is not limited to this, and for example, NULL data is inserted in the same manner as each transmission side data signal. May be.
  • FIG. 11 is a signal waveform diagram for explaining the operation of the reception side delay circuit 413.
  • the reception-side delay circuit 413 performs reception-side phase control processing based on the timing of the sampling clock SAM on the first to third reception-side data signals DRa to DRc.
  • the second receiving side data signal DRb and the first receiving side data signal DRa are subjected to processing for delaying the first receiving side data signal DRc and the first receiving side data signal DRa by 1 sampling period and 2 sampling periods, respectively.
  • the phases of the first to third receiving data signals DRa to DRc are the same.
  • the first to third reception side data signals DRa to DRc after such reception side phase control processing are output via the reception side output buffer 414.
  • the first to third transmission / reception data TR1 to TR3 are at different voltage levels as described above. Therefore, in each of the first to third sampling periods in each system period, there are two types of voltage levels of the transmission signal TS (specifically, the reception side determination signal RR) to be sampled by the transmission signal inverse conversion circuit 412. That is, there are two types of voltage levels of the transmission signal TS (first transmission / reception data TR1) to be sampled in the first sampling period, the VHa level and the VHb level, and the transmission signal TS (second transmission / reception data) to be sampled in the second sampling period.
  • the transmission signal TS first transmission / reception data TR1
  • the voltage level of the data TR2) is two types of VHb level and VHc level
  • the voltage level of the transmission signal TS (third transmission / reception data TR3) to be sampled in the third sampling period is two types of VHc level and GND level. .
  • the VHc level or the GND level can be corrected to a VHb level close to the VHc level or the GND level among the VHa level and the VHb level corresponding to the first transmission / reception data TR1. It is also considered that a transmission defect has occurred when the voltage level of the second transmission / reception data TR2 is the VHa level or the GND level.
  • the VHa level close to the VHb level corresponding to the second transmission / reception data TR2 can be corrected to the VHb level and corrected to the GND level close to the VHc level corresponding to the second transmission / reception data TR2. It is also considered that a transmission defect has occurred when the voltage level of the third transmission / reception data TR3 is the VHa level or the VHb level. In this case, the VHa level or VHb level can be corrected to a VHc level close to the VHa level or the VHb level among the VHc level and the GND level corresponding to the third transmission / reception data TR3.
  • the first transmission / reception data TR1 which are transmission signals TS to be sampled in the third sampling period and the first sampling period before and after the switching of each system period
  • the first transmission / reception data TR1 Both the corresponding VHa level and VHb level are larger than VHc, which is the larger of the two voltage levels corresponding to the third transmission / reception data TR3.
  • the voltage level corresponding to the second transmission / reception data TR2 is the same as or smaller than the voltage level corresponding to the first transmission / reception data TR1.
  • the voltage level corresponding to the third transmission / reception data TR3 is the same as or smaller than the voltage level corresponding to the second transmission / reception data TR2.
  • the voltage level of the transmission signal TS increases only when the third sampling period shifts to the first sampling period. For this reason, even if a synchronization shift occurs, the sampling period in which the voltage level of the transmission signal TS is larger than the immediately preceding sampling period can be determined as the first sampling period, and thus the synchronization shift can be eliminated.
  • the transmission unit 3 sequentially samples the first to third transmission side data signals DTa to DTc based on the timings of the system clock SYS and the sampling clock SAM, and changes their voltage levels.
  • a transmission signal TS is generated and transmitted from the transmission unit 3 to the reception unit 4 via one transmission path 5.
  • the receiving unit 4 based on the timings of the system clock SYS and the sampling clock SAM, the first to third reception-side data signals corresponding to the voltage levels of the first to third transmission / reception data TR1 to TR3 of the transmission signal TS, respectively.
  • DRa to DRc are generated.
  • the voltage level corresponding to “0” of the first transmission / reception data TR1 and the voltage level corresponding to “1” of the second transmission / reception data TR2 are the same VHb level.
  • the voltage level corresponding to “0” of the second transmission / reception data TR2 and the voltage level corresponding to “1” of the third transmission / reception data TR3 are the same VHc level.
  • the voltage level corresponding to “1” of the first transmission / reception data TR1 is the VHa level, and the VHa level does not overlap with the others.
  • the voltage level corresponding to “0” of the third transmission / reception data TR3 is the GND level, and the GND level is not duplicated.
  • N + 1 types (four types) of voltage levels for realizing the transmission signal TS there are N + 1 types (four types) of voltage levels for realizing the transmission signal TS in the present embodiment. For this reason, even if a synchronization shift occurs, the sampling period in which the voltage level of the transmission signal TS is larger than the immediately preceding sampling period can be determined as the first sampling period, and thus the synchronization shift can be eliminated. Thereby, a plurality of types of data transmission can be transmitted more reliably.
  • the voltage level for generating the transmission signal TS from the first to third transmission side data signals DTa to DTc, and the first to third reception side data signals DRa to DRc from the transmission signal TS. can be generated using the transmission-side level shifter 30 and the reception-side level shifter 40, respectively.
  • the transmission side level shifter 30 is used, so that a plurality of voltage levels are not supplied from the host 1 (that is, the first to third transmission side control signals CTa ⁇ ). Even if the voltage levels of CTc are the same, a plurality of different voltage levels can be generated.
  • the bit data “1” and “0” of the first transmission side data signal DTa correspond to the VHa level and VHb level, respectively
  • the bit of the second transmission side data signal DTb Data “1” and “0” correspond to the VHb level and VHc level, respectively
  • bit data “1” and “0” of the third transmission side data signal DTc correspond to the VHc level and GND level, respectively.
  • the present invention is not limited to this.
  • both of the voltage levels corresponding to “1” and “0” of the bit data of each transmission side data signal and the voltage levels corresponding to “1” and “0” of the bit data of other transmission side data signals By making the two different from each other, the transmission signal TS having N ⁇ 2 types (six types in the present embodiment) of voltage levels may be generated.
  • Second Embodiment> ⁇ 2.1 Overall configuration> Since the second embodiment of the present invention has the same configuration and the like as the first embodiment except for the transmission side level control processor 31 and the reception side level control processor 41, description of the common part is omitted. In addition, the same elements as those of the first embodiment among the components of the present embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.
  • FIG. 12 is a block diagram showing a configuration of the transmission side level control processor 31 in the present embodiment. As shown in FIG. 12, the transmission side level control processor 31 is different from that in the first embodiment in that a transmission side delay circuit 311, a transmission side data discrimination circuit 312 and a transmission signal conversion circuit 313 are converted. A processor (processing device) 315 is provided.
  • the conversion processor 315 includes the functions of the transmission side delay circuit 311, the transmission side data determination circuit 312, and the transmission signal conversion circuit 313, and includes the transmission side delay circuit 311 and the transmission side data described in the first embodiment.
  • the operations of the determination circuit 312 and the transmission signal conversion circuit 313 are realized. That is, the conversion processor 315 receives the first to third transmission data signals DTa to DTc, the system clock SYS, the sampling clock SAM, and the first output from the transmission level shifter 30 that are input via the transmission input buffer 310.
  • the third transmission side level shift signals LSTa to LSTc are received, the transmission signal TS is generated based on these, and output to the transmission side output buffer 314.
  • the detailed operation of the conversion processor 315 is the same as the operation of the transmission side delay circuit 311, the transmission side data determination circuit 312, and the transmission signal conversion circuit 313 in the first embodiment, and a description thereof will be omitted. To do.
  • FIG. 13 is a block diagram showing a configuration of the receiving side level control processor 41 in the present embodiment. As shown in FIG. 13, the receiving side level control processor 41 is different from that in the first embodiment in place of the receiving side data discriminating circuit 411, the transmission signal inverse converting circuit 412, and the receiving side delay circuit 413. An inverse conversion processor (processing device) 415 is provided.
  • the inverse conversion processor 415 includes functions of a reception side data determination circuit 411, a transmission signal reverse conversion circuit 412, and a reception side delay circuit 413.
  • the detailed operation of the inverse conversion processor 415 is the same as the operation of the reception side data determination circuit 411, the transmission signal inverse conversion circuit 412, and the reception side delay circuit 413 in the first embodiment. Is omitted.
  • the transmission side delay circuit 311, the transmission side data determination circuit 312, and the transmission signal conversion circuit 313 are converted into the reception side data determination circuit 411, the transmission signal inverse conversion circuit 412, and the reception side delay by the conversion processor 315.
  • the circuits 413 are each realized as one component by the inverse conversion processor 415.
  • the transmission side delay circuit 311, the transmission side data discrimination circuit 312, and the transmission signal conversion circuit 313 share common components, and the reception side data discrimination circuit 411, the transmission signal inverse conversion circuit 412, and the reception side By sharing common components in the side delay circuit 413, the circuit scale of the transmission unit 3 and the reception unit 4 can be reduced.
  • Third Embodiment> ⁇ 3.1 Overall configuration> Since the third embodiment of the present invention has the same configuration and the like as the first embodiment except for the transmission side level control processor 31 and the reception side level control processor 41, description of the common part is omitted. In addition, among the components of the present embodiment, the same elements as those of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • FIG. 14 is a block diagram showing a configuration of the transmission side level control processor 31 in the present embodiment.
  • the transmission-side level control processor 31 is different from that in the first embodiment, and instead of the transmission-side delay circuit 311, three FIFO (First In First Out) memories 316 a to 316 c and transmission A side readout control circuit 317 is provided.
  • the three FIFO memories 316a to 316c are referred to as “first to third transmission side FIFO memories”, respectively.
  • the first to third transmission side FIFO memories 316a to 316c are memories that perform a buffer operation of reading data written first.
  • the first to third transmission side FIFO memories 316a to 316c store bit data of the first to third transmission side data signals DTa to DTc input via the transmission side input buffer 300, respectively.
  • the first to third transmission side data signals DTa to DTc input via the transmission side input buffer 300 have NULL data inserted every two bits as in the first embodiment. It may be a thing, and the thing in which NULL data is not inserted may be sufficient.
  • the transmission side read control circuit 317 controls the read timing of the bit data of the first to third transmission side data signals DTa to DTc written in the first to third transmission side FIFO memories 316a to 316c, respectively. Specifically, the transmission side read control circuit 317 indicates the first side based on the transmission side read control signal RCT and the sampling clock SAM given from the outside (for example, the host 1) indicating the transmission side FIFO memory to be the read source. Read bit data sequentially from the third transmission side FIFO memories 316a to 316c every sampling period. The read bit data of the first to third transmission side data signals DTa to DTc are supplied to the transmission side data discrimination circuit 312.
  • the bit data of the first to third transmission side data signals DTa to DTc are read from the first to third transmission side FIFO memories 316a to 316c in order every sampling period, so that the first The first to third transmission side data signals DTa to DTc subjected to the transmission side phase control process similar to the embodiment are given to the transmission side data discrimination circuit 302.
  • the transmission-side phase control unit is realized by the first to third transmission-side FIFO memories 316 a to 316 c and the transmission-side read control circuit 317.
  • the writing of bit data to the first to third transmission side FIFO memories 316a to 316c is continuously performed, while the reading of bit data from the first to third transmission side FIFO memories 316a to 316c is 3 It is performed in turn at a frequency of once. For this reason, it is desirable that the reading speed of the bit data from each transmission side FIFO memory is three times the writing speed of the bit data to the first to third transmission side FIFO memories 316a to 316c. Thereby, the writing speed of the bit data to the first to third transmitting side FIFO memories 316a to 316c and the reading speed of the bit data from the first to third transmitting side FIFO memories 316a to 316c can be made substantially equal. it can.
  • the bit data writing speed to the first to third transmission side FIFO memories 316a to 316c and the bit data reading speed from each transmission side FIFO memory may be equal to each other.
  • the third transmission side FIFO memories 316a to 316c may run out of space for storing bit data.
  • a memory for saving data is provided in the signal transmission system by means (not shown), and the first to third transmission side data to be stored in the first to third transmission side FIFO memories 316a to 316c, respectively. It is desirable to temporarily store bit data of signals DTa to DTc. As a result, it is possible to prevent the first to third transmission side FIFO memories 316a to 316c from becoming free for storing bit data.
  • the components other than the first to third transmission side FIFO memories 316a to 316c and the transmission side read control circuit 317 of the transmission side level control processor 31 in the present embodiment are the same as those in the first embodiment. Therefore, the description is omitted.
  • FIG. 15 is a block diagram showing the configuration of the receiving side level control processor 41 in the present embodiment.
  • the receiving side level control processor 41 differs from that in the first embodiment in that it has three FIFO memories 416a to 416c and a receiving side read control circuit 417 instead of the receiving side delay circuit 413. I have.
  • the three FIFO memories 416a to 416c are referred to as “first to third reception side FIFO memories”, respectively.
  • the first to third reception side FIFO memories 416a to 416c are memories that perform the same buffer operation as the first to third transmission side FIFO memories 316a to 316c.
  • the first to third reception side FIFO memories 416a to 416c store bit data of the first to third reception side data signals DRa to DRc output from the transmission signal inverse conversion circuit 412, respectively.
  • the reception side read control circuit 417 controls the read timing of the bit data of the first to third reception side data signals DRa to DRc written in the first to third reception side FIFO memories 416a to 416c, respectively.
  • the reception-side read control circuit 417 is configured to receive first to third reception-side FIFO memories 416a to 416a based on a reception-side read control signal RCR (which may be the system clock SYS) given from the outside (for example, the host 1).
  • RCR which may be the system clock SYS
  • the bit data of the first to third receiving side data signals DRa to DRc are read from 416c at the same timing.
  • the read first to third reception side data signals DRa to DRc are applied to the reception side output buffer 414.
  • the bit data of the first to third reception side data signals DRa to DRc are read from the first to third reception side FIFO memories 416a to 416c at the same timing, so that substantially the first embodiment described above.
  • the first to third reception side data signals DRa to DRc that have been subjected to the same reception side phase control processing as described above are applied to the reception side output buffer 414.
  • the reception-side phase control unit is realized by the first to third reception-side FIFO memories 416a to 416c and the reception-side read control circuit 417.
  • the reading speed of bit data from each receiving side FIFO memory is three times the writing speed of bit data to the first to third receiving side FIFO memories 416a to 416c. It is desirable to be. It is to be noted that a data saving memory similar to that on the transmission side is provided, and the writing speed of bit data to the first to third receiving side FIFO memories 416a to 416c and the reading speed of bit data from the receiving side FIFO memory are mutually set. It may be equal.
  • FIG. 16 is a signal waveform diagram for explaining the operation of the transmission side read control circuit 307 in the present embodiment.
  • the first to third transmission side FIFO memories 316a to 316c are first to each at the timing when the voltage level of the sampling clock SAM rises.
  • the bit data of the third transmission side data signals DTa to DTc are read.
  • the transmission-side FIFO memory serving as a reading source is switched every sampling period in the order of the first to third transmission-side FIFO memories 316a to 316c.
  • the second transmission-side data signal DTb and the third transmission-side data signal DTc are each one sampling period with respect to the first transmission-side data signal DTa. And a delay of 2 sampling periods.
  • the bit data of the first to third transmission side data signals DTa to DTc read out as described above are given to the transmission side data discrimination circuit 303. Since the operation of the transmission side data discrimination circuit 303 is the same as that in the first embodiment, description thereof is omitted.
  • FIG. 17 is a signal waveform diagram for explaining the operation of the transmission signal conversion circuit 313 in this embodiment. Also in this embodiment, as in the first embodiment, the transmission signal conversion circuit 313 uses the first to third transmission side data signals DTa to DTc for 8 bits (that is, data for a total of 24 bits). Thus, a transmission signal TS is generated. Note that details of the operation of the transmission signal conversion circuit 313 are as described in the first embodiment, and a description thereof will be omitted.
  • FIG. 18 is a signal waveform diagram for explaining the operation of the transmission signal inverse conversion circuit 412 in this embodiment. Also in this embodiment, the first to third reception side data signals DRa to DRc for 8 bits before the reception side phase control processing are performed based on the transmission signal TS by the transmission signal inverse conversion circuit 412 in the first embodiment. (That is, a total of 24 bits of data) is generated. The details of the operation of the transmission signal inverse conversion circuit 412 are as described in the first embodiment, and the description thereof is omitted.
  • the first to third reception side data signals DRa to DRc generated by the transmission signal inverse conversion circuit 412 are sequentially stored in the first to third reception side FIFO memories 416a to 416c, respectively.
  • FIG. 19 is a signal waveform diagram for explaining the operation of the receiving side read control circuit 417 in the present embodiment.
  • the reception-side read control circuit 417 starts from the first to third reception-side FIFO memories 416a to 416c at the timing when the voltage level of the reception-side read control signal RCR (which may be the system clock SYS) rises.
  • the bit data of the first to third receiving side data signals DRa to DRc are read simultaneously. For this reason, as in the reception-side phase control process of the first embodiment, the phases of the first to third reception-side data signals DRa to DRc are the same.
  • the first to third reception-side data signals DRa to DRc after such reception-side phase control processing are output via the reception-side output buffer 414.
  • the first to third transmission side FIFO memories 316a to 316c and the transmission side read control circuit 317 realize the transmission side phase control unit, and the first to third reception side FIFO memories 416a to 416c and the reception side.
  • the same effects as in the first embodiment can be obtained.
  • the bit data of each transmission side data signal is set to two sampling periods, and NULL data of two sampling periods is inserted every two bits.
  • the present invention is not limited to this. Absent.
  • the bit data of each transmission side data signal may be in units of 3 sampling periods, and NULL data may not be inserted. In this case, it is not necessary to perform transmission-side phase control processing on the first to third transmission-side data signals DTa to DTc, so that the transmission-side delay circuit 311 is not provided.
  • the bit data of each transmission side data signal may be set as one sampling period unit, and NULL data of two sampling periods may be inserted between the bit data.
  • the present invention is not limited to this.
  • the present invention can also be applied to the case of transmitting two data, or the case of transmitting four or more data.
  • the frequency of the sampling clock SAM is a value obtained by multiplying the frequency of the system clock SYS by the number of data.
  • the transmission signal conversion circuit 313 and the transmission signal inverse conversion circuit 412 each use the GND level that is the ground level, but other voltage levels may be used instead.
  • the present invention it is possible to provide a signal transmission device and a signal transmission method capable of transmitting a plurality of data while suppressing an increase in cost.
  • the present invention can be applied to a signal transmission apparatus and a signal transmission method for performing a plurality of types of data transmission.
  • Reception side input buffer (reception buffer unit) 411... Reception side data discrimination circuit 412... Transmission signal reverse conversion circuit (transmission signal reverse conversion unit) 413 ... Reception side delay circuit (reception side phase control unit) 414 ... Reception side output buffer 415 ...

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Abstract

La présente invention a pour objectif de proposer un dispositif de transmission de signal qui soit apte à transmettre une pluralité de données sans que cela entraîne une augmentation des coûts. Afin d'atteindre l'objectif visé, la présente invention se rapporte à un dispositif de transmission de signal (2) comprenant un transmetteur (3), un récepteur (4) et une voie de transmission de données (5). Le transmetteur (3) échantillonne, en séquence, des données binaires indiquées par des premier à troisième signaux de données sur le côté de transmission (DTa à DTc) et il convertit le niveau de tension des données binaires. C'est ainsi qu'un signal de transmission (TS) est généré et délivré en sortie. Le récepteur (4) échantillonne des parties de première à troisième données de transmission et de réception (TR1 à TR3) du signal de transmission (TS) qui correspondent aux données binaires indiquées par les premier à troisième signaux de données sur le côté de transmission (DTa à DTc), en se basant sur une horloge système (SYS) et une horloge d'échantillonnage (SAM). Ensuite, le récepteur (4) convertit le niveau de tension des première à troisième données de transmission et de réception (TR1 à TR3). C'est ainsi que des signaux de données sur le côté de réception (DRa à DRc) sont générés et délivrés en sortie.
PCT/JP2012/072697 2011-09-13 2012-09-06 Dispositif de transmission de signal et procédé de transmission de signal WO2013038978A1 (fr)

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JP2011-199285 2011-09-13

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004046054A (ja) * 2001-10-03 2004-02-12 Nec Corp 表示装置及び半導体装置
WO2006038660A1 (fr) * 2004-10-06 2006-04-13 Matsushita Electric Industrial Co., Ltd. Système de communication de données

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004046054A (ja) * 2001-10-03 2004-02-12 Nec Corp 表示装置及び半導体装置
WO2006038660A1 (fr) * 2004-10-06 2006-04-13 Matsushita Electric Industrial Co., Ltd. Système de communication de données

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