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WO2012046365A1 - Dispositif à semi-conducteurs et son procédé de fabrication - Google Patents

Dispositif à semi-conducteurs et son procédé de fabrication Download PDF

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Publication number
WO2012046365A1
WO2012046365A1 PCT/JP2011/003129 JP2011003129W WO2012046365A1 WO 2012046365 A1 WO2012046365 A1 WO 2012046365A1 JP 2011003129 W JP2011003129 W JP 2011003129W WO 2012046365 A1 WO2012046365 A1 WO 2012046365A1
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Prior art keywords
insulating film
gate electrode
region
semiconductor device
transistor
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PCT/JP2011/003129
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English (en)
Japanese (ja)
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後藤　覚
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パナソニック株式会社
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Publication of WO2012046365A1 publication Critical patent/WO2012046365A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/0142—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a plurality of transistors having different sidewall widths and a manufacturing method thereof.
  • LDD Lightly Doped Drain
  • impurities having a concentration lower than that of the source / drain regions are implanted on both sides of the gate electrode of the transistor, sidewalls are then formed on the sidewalls of the gate electrode, and impurities having a high concentration are implanted through the sidewalls. Source / drain regions are formed.
  • the sidewall width of a transistor having a high power supply voltage needs to be larger than that of a transistor having a low power supply voltage.
  • the sidewall width of the transistor is smaller than the design value, the change in the impurity concentration in the boundary region between the source / drain and the channel becomes steep. As a result, carriers flowing through the channel obtain energy and become so-called hot carriers, which are injected into the gate insulating film. Hot carriers injected into the gate insulating film cause defects in the gate insulating film or are trapped in the gate insulating film. As a result, the threshold value of the transistor varies and the reliability decreases.
  • a sidewall having a small width is formed by etching the oxide film for forming the sidewall for a long time.
  • etching is performed for a long time, not only the oxide film for forming the sidewall but also the element isolation region is etched in the vicinity of the boundary between the element isolation region and the active region, and the pn junction may be exposed on the side surface of the active region. .
  • the pn junction is exposed on the side surface of the active region, it causes a junction leak when the silicide layer is formed.
  • the sidewall oxide film may not be etched at the portion where the etching mask overlaps, and may remain in a thin column shape. . If the oxide film remaining in a thin columnar shape is broken during the manufacturing process, particles are generated and the product yield is lowered. Further, the particles adversely affect the post-process equipment.
  • An object of the present disclosure is to solve the above-described problem and to accurately form a plurality of transistors having different sidewall widths on a substrate without causing etching of an element isolation region.
  • the present disclosure discloses a method for manufacturing a semiconductor device, in which a sidewall is formed from a plurality of stacked insulating films, and the sidewall width is changed by changing the number of stacked insulating films.
  • the configuration is to be controlled.
  • the semiconductor device manufacturing method of the first example includes a step (a) of forming a first region and a second region that are separated from each other by an element isolation region on a substrate, and a step above the first region. (B) forming a first gate electrode with a first gate insulating film interposed therebetween, and forming a second gate electrode with a second gate insulating film interposed on the second region; The step (c) of sequentially forming the first insulating film and the second insulating film so as to cover the first gate electrode and the second gate electrode, and the second insulating film after the step (c) A step (d) of removing a portion formed on the first region in step (d), a step (e) of forming a third insulating film on the substrate after the step (d), and a step (e ), The second insulating film and the third insulating film are etched back to form the first gate electrode on the side surface.
  • first outer side wall made of three insulating films and forming a second outer side wall made of the second insulating film and the third insulating film on the side surface of the second gate electrode (f) And after the step (f), the portion of the first insulating film that is not covered by the first outer sidewall and the second outer sidewall is removed, so that the first gate electrode is exposed on the side surface of the first gate electrode.
  • the gate length is long, and the first insulating film and the second insulating film are made of different materials, and the second insulating film and the third insulating film are made of the same material.
  • a step (d) of removing a portion formed on the first region in the second insulating film, and a step on the substrate after the step (d) are performed.
  • the third insulating film is formed on the side surface of the first gate electrode by etching back the second insulating film and the third insulating film after the step (e) of forming the third insulating film and the step (e).
  • the width of the first outer sidewall and the width of the second outer sidewall can be accurately controlled.
  • the first insulating film is formed under the second insulating film, the element isolation region, the gate insulating film, and the like are etched when the second insulating film and the third insulating film are etched. There is no.
  • the second insulating film may be removed by wet etching.
  • the first outer side wall may be narrower than the second outer side wall.
  • the first gate insulating film may be thinner than the second gate insulating film.
  • the first region is a formation region of the first transistor
  • the second region is a formation region of the second transistor
  • the first transistor is a power source.
  • the voltage may be greater than or equal to 1.1 V and less than or equal to 2.0 V
  • the second transistor may have a structure in which the power supply voltage is greater than or equal to 3.3 V and less than or equal to 7.0 V.
  • the first gate electrode has a gate length of 30 nm to 180 nm
  • the second gate electrode has a gate length of 200 nm to 700 nm. Good.
  • the second insulating film and the third insulating film are formed until a portion of the first insulating film formed on the first gate electrode is exposed. And after the step (f1), the second insulating film and the third insulating film are exposed until a portion of the first insulating film formed on the second gate electrode is exposed.
  • the manufacturing method of the semiconductor device of the first example further includes a step (h) of forming a fourth insulating film on the substrate after the step (b) and before the step (c).
  • a step (h) of forming a fourth insulating film on the substrate after the step (b) and before the step (c).
  • the exposed portion of the fourth insulating film may be removed.
  • the method of manufacturing the semiconductor device of the first example includes a step (h) of forming a fourth insulating film on the substrate after the step (b) and before the step (c),
  • the method may further comprise a step (i) of forming an offset spacer on the side surfaces of the first gate electrode and the second gate electrode by selectively removing the insulating film.
  • the fourth insulating film may be a silicon oxide film.
  • the first insulating film may be a silicon nitride film
  • the second insulating film and the third insulating film may be silicon oxide films.
  • the semiconductor device of the second example includes a first transistor formed in the first region of the substrate and a second transistor formed in the second region, and the first transistor is formed on the substrate over the first transistor. Formed on the side wall of the first gate electrode, a first inner side wall formed on the side surface of the first gate electrode, and a first inner side wall.
  • a second transistor having a first outer sidewall and a second gate electrode formed on the substrate with a second gate insulating film interposed between the second gate electrode and a side surface of the second gate electrode; A second inner sidewall formed on the second inner sidewall; a second outer sidewall formed on the second inner sidewall; and the first inner sidewall, the second inner sidewall, and the first inner sidewall. Outside sidewalls and number
  • the outer side wall made of different materials, a first outer side wall is made of a single layer film, a second outer side wall is made of a laminated film.
  • the method for manufacturing a semiconductor device of the present disclosure it is possible to accurately form a plurality of transistors having different sidewall widths on a substrate without causing etching of an element isolation region.
  • (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment to process order.
  • (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment to process order.
  • (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment to process order. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on one Embodiment. It is sectional drawing which shows the problem of the manufacturing method of the conventional side wall.
  • (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st modification of one Embodiment in order of a process.
  • (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd modification of one Embodiment to process order.
  • (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd modification of one Embodiment to process order.
  • (A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd modification of one Embodiment to process order.
  • (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd modification of one Embodiment to process order.
  • (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd modification of one Embodiment to process order.
  • (A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd modification of one Embodiment to process order.
  • (A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd modification of one Embodiment to process order.
  • an element isolation region 102 having a shallow trench (STI) structure made of a silicon oxide film having a thickness of 300 nm is formed on a substrate 101 such as a silicon substrate.
  • An element region is formed.
  • a first P well 131 is formed above the element region, and a second transistor that is a high breakdown voltage transistor is formed.
  • a second P well 141 is formed above the element region.
  • the first gate insulating film 133 and the first gate electrode 134 of the first transistor, and the second gate insulating film 143 and the second gate electrode of the second transistor are used.
  • a gate electrode 144 is formed. Specifically, a silicon oxide film having a thickness of 2 nm is formed on the first region 103, a silicon oxide film having a thickness of 20 nm is formed on the second region 104, and then the first region is formed. A polysilicon film having a thickness of 200 nm is formed on the third region 104 and the second region 104. Subsequently, patterning using lithography is performed and etching is performed.
  • first gate insulating film 133 and the first gate electrode 134 are formed on the first region 103, and the second gate insulating film 143 and the second gate electrode are formed on the second region 104.
  • 144 is formed.
  • the first gate electrode 134 has a gate length of 180 nm, and the second gate electrode 144 has a gate length of 600 nm.
  • a resist mask is patterned by lithography to form a resist film 171 that covers the first region 103 and exposes the second region 104.
  • Phosphorus (P) ions are implanted into the second region 104 using the resist film 171 as an implantation mask.
  • the acceleration voltage is set to 80 keV, and the dose amount is set to 2 ⁇ 10 13 / cm 2 .
  • the second N-type extension diffusion layer 145 for the second transistor is formed on the second region 104.
  • a resist mask is patterned by a lithography method to cover the second region 104 and to expose the first region 103.
  • Phosphorus ions are implanted into the first region 103 using the resist film 172 as an implantation mask.
  • the acceleration voltage is set to 12 keV, and the dose is set to 5 ⁇ 10 14 cm 2 .
  • the first N-type extension diffusion layer 135 for the first transistor is formed on the first region 103.
  • a first silicon nitride film having a thickness of 15 nm is formed so as to cover the first gate electrode 134 and the second gate electrode 144.
  • a second insulating film 152 made of a silicon oxide film having a thickness of 40 nm is deposited.
  • a resist film 173 that covers the second region 104 and exposes the first region 103 is formed, and subsequently formed on the first region 103 by wet etching.
  • the second insulating film 152 is removed.
  • the second insulating film 152 made of a silicon oxide film may be etched using, for example, dilute hydrofluoric acid in which hydrofluoric acid (HF) and water are mixed at a ratio of 1:20.
  • the first gate insulating film 133 and the element isolation region 102 are not etched because they are covered with the first insulating film 151 made of a silicon nitride film.
  • a third insulating film 153 made of a silicon oxide film having a thickness of 50 nm is deposited as shown in FIG.
  • the first outer side wall 136 is formed on the side surface of the first gate electrode 134 by the entire surface etch back, and the second side electrode 136 is formed on the side surface of the second gate electrode 144.
  • Outer sidewalls 146 are formed.
  • Etchback of the third insulating film 153 and the second insulating film 152 may be performed until part of the first insulating film 151 is exposed in the second region 104 by dry etching.
  • dry etching uses a lower one-frequency RIE etching apparatus that applies high-frequency power of a single frequency (for example, 13.56 MHz) only to the lower electrode, and uses perfluorocyclobutane (C 4 F 8 ) as an etching gas.
  • Argon (Ar) and oxygen (O 2 ) are supplied into the chamber at a flow rate of 22 sccm (standard state cm 3 / min), 1500 sccm and 4 sccm, respectively, and the pressure in the chamber is set to 30 mTorr (about 4 Pa). Is 250 W and the substrate temperature is 20 ° C. By using such etching conditions, the selection ratio between the silicon oxide film and the silicon nitride film can be about 5.
  • the thickness of the silicon oxide film deposited on the first insulating film 151 is the sum of the thickness of the second insulating film 152 and the thickness of the third insulating film 153. It is 90 nm.
  • the thickness of the silicon oxide film deposited on the first insulating film 151 is 50 nm.
  • an overetch amount of about 20% is added to the thickness of the silicon oxide film, and etching equivalent to 108 nm is performed as the silicon oxide film. There is a need.
  • the first insulating film 151 is etched by about 4 nm.
  • overetching corresponding to 58 nm occurs as a silicon oxide film, and the first insulating film 151 is etched by about 12 nm.
  • the selectivity between the silicon oxide film and the silicon nitride film If the thickness is about 5, the etching can be stopped in the first insulating film 151 made of the silicon nitride film, and the substrate 101 and the element isolation region 102 are not etched.
  • the first insulating film 151 is removed by etching the entire surface until the substrate 101 is exposed. At this time, the first insulating film 151 on the first gate electrode 134 and the second gate electrode 144 is also removed. As a result, a first sidewall 138 having a first inner sidewall 137 and a first outer sidewall 136 is formed on the side surface of the first gate electrode 134, and the second gate electrode 144 is disposed on the side surface. A second sidewall 148 having a second inner sidewall 147 and a second outer sidewall 146 is formed.
  • the first insulating film is etched using, for example, a lower one-frequency RIE etching apparatus, and an etching gas of carbon tetrafluoride (CF 4 ), ethylene difluoride (CH 2 F 2 ), Ar, and O 2.
  • CF 4 carbon tetrafluoride
  • CH 2 F 2 ethylene difluoride
  • Ar Ar
  • O 2 ethylene difluoride
  • ion implantation is performed on the first region 103 using the first gate electrode 134 and the first sidewall 138 as a mask, and the second gate electrode 144 and the second sidewall are performed. Ion implantation is performed on the second region 104 using 148 as a mask.
  • the first N-type source / drain diffusion layer 139 is formed in the first region 103
  • the second N-type source / drain diffusion layer 149 is formed in the second region 104.
  • arsenic (As) ions may be implanted at an acceleration voltage of 20 keV so that the dose amount is 4 ⁇ 10 14 / cm 2 .
  • heat treatment for activating the first N-type source / drain diffusion layer 139 and the second N-type source / drain diffusion layer 149 is performed.
  • the heat treatment may be a rapid heat treatment at 1000 ° C. for 10 seconds, for example.
  • a step of forming the silicide layer 107 on the first N-type source / drain diffusion layer 139, the second N-type source / drain diffusion layer 149, the first gate electrode 134, and the second gate electrode 144 is performed. Just do it.
  • a first transistor having a first sidewall 138 having a width of about 60 nm is formed in the first region 103
  • a second transistor 148 having a second sidewall 148 having a width of about 105 nm is formed in the second region 104. Two transistors are formed.
  • the width of the sidewall can be controlled by the thickness of the second insulating film 152 and the third insulating film 153 that are silicon oxide films, and the width of the sidewall can be freely set. It is possible to set.
  • the second insulating film 152 that is a silicon oxide film is removed by wet etching in the first region 103, the first gate insulating film 133 is covered with the first insulating film 151 made of a silicon nitride film. ing. Therefore, side etching is not generated in the first gate insulating film 133, and a highly reliable transistor can be formed.
  • the etching can be stopped in the first insulating film 151 by performing etching under a condition with a high etching selectivity. Therefore, the element isolation region 102 is not etched particularly in the first region 103, and there is no possibility that junction leakage occurs when the silicide layer 107 is formed.
  • the first outer sidewall 136 of the first transistor and the second outer sidewall 146 of the second transistor are formed in the same etching step.
  • an oxide film for forming the sidewall may remain on the element isolation region.
  • FIG. 5 when the sidewall 546 of the second transistor is formed, an end portion of the resist film 571 covering the first region 503 protrudes to the second region 504 side, and the first transistor
  • a thin columnar oxide film 511 remains on the element isolation region 502.
  • the oxide film 511 is easily broken, and when the oxide film 511 is broken and particles are generated, the yield of the product is lowered. In addition, the particles have an adverse effect on post-process equipment. However, in this embodiment, such an oxide film does not remain.
  • first outer side wall 136 and the second outer side wall 146 are formed in the same process.
  • first outer side wall 136 and the second outer side wall 146 may be formed sequentially.
  • the steps until the third insulating film 153 is formed are the same as the steps shown in the embodiment.
  • the second insulating film 152 and the third insulating film 153 are etched back until the first insulating film 151 is exposed in the first region 103.
  • the first outer side wall 136 is formed on the side surface of the first gate electrode 134, and in the second region 104, the second insulating film 152 and the third insulating film are formed.
  • the film 153 remains and the first insulating film 151 is not exposed.
  • a resist film 174 that covers the first region 103 and exposes the second region 104 is formed.
  • the second insulating film 152 and the third insulating film 153 are etched until the first insulating film 151 is exposed.
  • the second outer sidewall 146 is formed on the side surface of the second gate insulating film in the second region 104.
  • the second insulating film 152 and the third insulating film 153 may be etched under the same conditions as in the embodiment.
  • the exposed portion of the first insulating film 151 is removed as in the embodiment.
  • the first sidewall 138 having the first inner sidewall 137 and the first outer sidewall 136, and the second sidewall having the second inner sidewall 147 and the second outer sidewall 146. 148 is formed.
  • the first insulating film 151 may be etched under the same conditions as in the embodiment.
  • an N-type source / drain diffusion layer, a silicide layer, and the like may be formed in the same manner as in the embodiment.
  • the width of the sidewall can be freely set as in the embodiment. Further, side etching is not generated in the first gate insulating film 133, so that a highly reliable transistor can be formed. Furthermore, there is no possibility that junction leakage will occur when the silicide layer 107 is formed.
  • the first region 103 is covered with the resist film 174 when the second outer side wall 146 is formed. For this reason, the first outer side wall 136 is not over-etched excessively. In the case where the width of the first sidewall 138 is extremely narrower than the width of the second sidewall 148, the thickness of the third insulating film needs to be reduced. In this case, since the amount of overetching in the first region 103 increases, the etching cannot be stopped in the first insulating film 151, and the base may be etched. In this modification, since the second outer side wall 136 is formed after the first outer side wall 136 is formed, the etching amount of the first insulating film 151 in the first region 103 does not increase.
  • the first outer side wall 136 is not excessively etched, the height of the first side wall 138 does not become lower than the height of the first gate electrode 134. For this reason, when ion implantation for forming the N-type source / drain diffusion layer is performed, there is no possibility that ion species may penetrate the substrate.
  • the first N-type extension diffusion layer 135 and the second N-type extension diffusion layer 145 are formed using the first gate electrode 134 and the second gate electrode 144, respectively, as an implantation mask. .
  • ion implantation for forming an N-type extension diffusion layer is performed.
  • the steps until the first gate electrode 134 and the second gate electrode 144 are formed are the same as the steps shown in the embodiment.
  • a fourth insulating film 161 made of a silicon oxide film having a thickness of 10 nm is formed so as to cover the first gate electrode 134 and the second gate electrode 144.
  • the fourth insulating film 161 is etched until the substrate 101 is exposed by the entire surface etch back, and on the side surfaces of the first gate electrode 134 and the second gate electrode 144.
  • An offset spacer 162 is formed.
  • the fourth insulating film 161 is etched by using, for example, a lower one-frequency RIE etching apparatus, and supplying C 4 F 8 , Ar, and O 2 as etching gases into the chamber at flow rates of 22 sccm, 1500 sccm, and 4 sccm, respectively.
  • the pressure in the chamber may be 30 mTorr, the high-frequency power is 250 W, and the substrate temperature is 20 ° C.
  • a resist film 175 that covers the first region 103 and exposes the second region 104 is formed, and the second gate electrode 144 and the offset spacer 162 are used as an implantation mask. Ion implantation is performed on the second region 104. Thereby, the second N-type extension diffusion layer 145 is formed. The ion implantation may be performed under the same conditions as the steps shown in the embodiment.
  • a resist film 176 that covers the second region 104 and exposes the first region 103 is formed, and the first gate electrode 134 and Ions are implanted into the first region 103 using the offset spacer 162 as an implantation mask. Thereby, the first N-type extension diffusion layer 135 is formed.
  • the ion implantation may be performed under the same conditions as the steps shown in the embodiment.
  • a first insulating film 151 and a second insulating film 152 are sequentially formed as shown in FIG.
  • a third insulating film 153 is formed over the entire surface of the substrate 101.
  • the second insulating film 152 and the third insulating film 153 are entirely etched back to form the first outer side wall 136 and the second outer side wall 146.
  • the exposed portion of the first insulating film 151 is removed to form a first inner side wall 137 and a second inner side wall 147.
  • ion implantation is performed on the first region 103 using the first gate electrode 134, the offset spacer 162, and the first sidewall 138 as a mask, and the second gate electrode 144. Then, ion implantation is performed on the second region 104 using the offset spacer 162 and the second sidewall 148 as a mask. Thereby, an N-type source / drain diffusion layer is formed. After the N-type source / drain diffusion layer is formed, a silicide layer and the like are formed.
  • the first outer side wall 136 is first formed in the same manner as in the first modification, and then, FIG. A second outer sidewall 146 may be formed as shown in FIG.
  • the width of the sidewall can be freely set as in the embodiment. Further, side etching is not generated in the first gate insulating film 133, so that a highly reliable transistor can be formed. Furthermore, there is no possibility that junction leakage will occur when the silicide layer 107 is formed.
  • the extension diffusion layer is formed after the offset sidewall is formed, so that the short channel effect can be reduced. Further, since the extension diffusion layer is formed after removing the portion of the fourth insulating film formed on the semiconductor substrate, the implantation is performed when the process of forming the extension diffusion layer shallow from the semiconductor substrate is used. Profile control becomes easy.
  • An offset sidewall made of a silicon oxide film is formed between the first insulating film made of a silicon nitride film and the gate insulating film.
  • an interface state is formed in the vicinity of the interface between the gate insulating film and the first insulating film, and hot carriers and NBTI (Negative bias temperature instability) There is a possibility that a problem of lowering reliability may occur.
  • the offset spacer made of the silicon oxide film is formed between the first insulating film made of the silicon nitride film and the gate insulating film, so that such a problem does not occur.
  • the steps until the fourth insulating film 161 is formed are the same as the steps shown in the second modification.
  • ion implantation is performed on the second region 104, An N-type extension diffusion layer 145 is formed.
  • the ion implantation may be performed under the same conditions as the steps shown in the embodiment.
  • a resist film 179 that covers the second region 104 and exposes the first region 103 is formed, and then the first region 103 is formed.
  • Ion implantation is performed to form a first N-type extension diffusion layer 135. The ion implantation may be performed under the same conditions as the steps shown in the embodiment.
  • a first insulating film 151 and a second insulating film 152 are sequentially formed on the fourth insulating film 161 as shown in FIG.
  • a resist film 173 that exposes the first region 103 and covers the second region 104 is formed, and is formed in the first region 103 in the second insulating film 152. Remove the part. Etching of the second insulating film 152 may be performed under the same conditions as in the steps described in one embodiment.
  • a third insulating film 153 is formed in the first region 103 and the second region 104 as shown in FIG.
  • the second insulating film 152 and the third insulating film 153 are etched back to form the first outer side wall 136 and the second outer side wall 146. . Etching of the second insulating film 152 and the third insulating film 153 may be performed under the same conditions as in the steps described in one embodiment.
  • the exposed portion of the first insulating film 151 is etched, and then the exposed portion of the fourth insulating film 161 is etched. Accordingly, the first inner sidewall 137 having the first insulating film 151 and the fourth insulating film 161 and the second inner sidewall 147 having the first insulating film 151 and the fourth insulating film 161 are formed. Form.
  • the etching of the first insulating film 151 may be performed under the same conditions as in the process described in one embodiment.
  • the fourth insulating film 161 is etched by using, for example, a lower one-frequency RIE etching apparatus, and supplying C 4 F 8 , Ar, and O 2 as etching gases into the chamber at flow rates of 22 sccm, 1500 sccm, and 4 sccm, respectively.
  • the pressure in the chamber may be 30 mTorr, the high-frequency power is 250 W, and the substrate temperature is 20 ° C.
  • ion implantation is performed on the first region 103 using the first gate electrode 134 and the first sidewall 138 as a mask, and the second gate electrode 144 and the second gate electrode 138. Ions are implanted into the second region 104 using the sidewall 148 as a mask. As a result, a first N-type source / drain diffusion layer 139 and a second N-type source / drain diffusion layer 149 are formed.
  • the ion implantation may be performed under the same conditions as the steps shown in the embodiment. Thereafter, the silicide layer 107 may be formed on the first N-type source / drain diffusion layer 139, the second N-type source / drain diffusion layer 149, the first gate electrode 134, and the second gate electrode 144.
  • the first outer sidewall 136 is formed as shown in FIG. 13A, and then the second outer sidewall 146 is formed as shown in FIG. 13B. May be formed.
  • the width of the sidewall can be freely set as in the embodiment. Further, side etching is not generated in the first gate insulating film 133, so that a highly reliable transistor can be formed. Furthermore, there is no possibility that junction leakage will occur when the silicide layer 107 is formed.
  • the short channel effect can be reduced because the fourth insulating film is formed when the extension diffusion layer is formed.
  • a fourth insulating film made of a silicon oxide film is formed between the first insulating film made of the silicon nitride film and the gate insulating film.
  • the first insulating film made of a silicon nitride film and the gate insulating film are in direct contact, an interface state is formed in the vicinity of the interface between the gate insulating film and the first insulating film, and hot carriers and NBTI (Negative bias temperature instability) There is a possibility that a problem of lowering reliability may occur.
  • the offset spacer made of the silicon oxide film is formed between the first insulating film made of the silicon nitride film and the gate insulating film, so that such a problem does not occur.
  • the first transistor is a low breakdown voltage transistor and the second transistor is a high breakdown voltage transistor.
  • the size of the gate electrode, the width of the sidewall, and the like exemplified are suitable when the operating voltage of the first transistor is 1.8V and the operating voltage of the second transistor is 5V.
  • the operating voltages of the first transistor and the second transistor are not limited to this.
  • the operating voltages of the first transistor and the second transistor may be arbitrarily set as long as the second transistor is higher than the first transistor.
  • the operating voltage of the first transistor may be in the range of about 1.1V to 2V
  • the operating voltage of the second transistor may be in the range of about 3.3V to 7V.
  • the manufacturing method shown in the embodiment and its modification can be applied.
  • the gate length of the first transistor was 180 nm, and the gate length of the second transistor was 600 nm.
  • the gate lengths of the first transistor and the second transistor may be arbitrarily set.
  • the gate length of the first transistor may be in the range of about 30 nm to 180 nm, and the gate length of the second transistor may be in the range of about 200 nm to 700 nm.
  • an N-type MIS transistor is formed is shown in one embodiment and its modification, the manufacturing method shown in one embodiment and its modification can also be applied when forming a P-type MIS transistor. it can. Further, an N-type MIS transistor and a P-type MIS transistor may be mixed on the semiconductor substrate. In this case, an N-type MIS transistor and a P-type MIS transistor having different sidewall widths may be formed.
  • the first gate insulating film and the second gate insulating film are silicon oxide films, but other insulating films may be used. Further, although the first gate electrode and the second gate electrode are polysilicon gate electrodes, they may be gate electrodes made of other materials.
  • the first insulating film is a silicon nitride film
  • the second insulating film and the third insulating film are silicon oxide films.
  • the first insulating film and the second insulating film are used.
  • Other materials may be used as long as the second insulating film and the third insulating film are made of the same material.
  • the etching selectivity between the first insulating film, the second insulating film, and the third insulating film is set to about 5.
  • the etching selectivity is not limited to this value.
  • the film thickness of the first insulating film is such that the first insulating film remains in accordance with the etching selection ratio and the film thicknesses of the second insulating film and the third insulating film. Is set, there is no problem even if the etching selectivity is about 2.
  • the thickness of the second insulating film is 20 nm
  • the thickness of the third insulating film is 50 nm
  • the overetch amount is 20%
  • the etching amount is 84 nm.
  • the converted etching amount of the first insulating film is 64 nm. Therefore, when the etching selectivity is 2, it is sufficient that the thickness of the first insulating film is about 35 nm.
  • the method for manufacturing a semiconductor device according to the present disclosure can accurately form a plurality of transistors having different sidewall widths on a substrate without causing etching of an element isolation region, and particularly includes a plurality of transistors having different sidewall widths. This is useful as a method for manufacturing a semiconductor device.

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Abstract

La présente invention concerne un procédé de fabrication d'un dispositif à semi-conducteurs ; en premier lieu, un premier film isolant (151) et un deuxième film isolant (152) sont formés de manière séquentielle, de façon à ce qu'une première électrode grille (134) et une seconde électrode grille (144) soient recouvertes. Une partie du deuxième film isolant (152) formée sur une première région (103) est ensuite retirée. Un troisième film isolant (153) est ensuite formé sur un substrat (101). Puis, par le retrait sélectif du deuxième film isolant (152) et du troisième film isolant (153), une première paroi latérale externe (136), comprenant le troisième film isolant (153), est formée sur la surface latérale de la première électrode grille (134). Une seconde paroi latérale externe (146), comprenant le deuxième film isolant (152) et le troisième film isolant (153), est formée sur la surface latérale de la seconde électrode grille (144).
PCT/JP2011/003129 2010-10-08 2011-06-02 Dispositif à semi-conducteurs et son procédé de fabrication WO2012046365A1 (fr)

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EP3246948A1 (fr) * 2016-05-20 2017-11-22 Commissariat à l'Energie Atomique et aux Energies Alternatives Procédé de réalisation sur un même substrat de transistors présentant des caractéristiques différentes
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EP3246948A1 (fr) * 2016-05-20 2017-11-22 Commissariat à l'Energie Atomique et aux Energies Alternatives Procédé de réalisation sur un même substrat de transistors présentant des caractéristiques différentes
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