WO2012046365A1 - Semiconductor device and method for manufacturing same - Google Patents

Abstract

A method for manufacturing a semiconductor device, wherein first of all a first insulating film (151) and a second insulating film (152) are sequentially formed in such a way that a first gate electrode (134) and a second gate electrode (144) are covered. A portion of the second insulating film (152) formed on a first region (103) is then removed. A third insulating film (153) is then formed on a substrate (101). Then, by selectively removing the second insulating film (152) and the third insulating film (153), a first external side wall (136) comprising the third insulating film (153) is formed on the side surface of the first gate electrode (134). A second external side wall (146) comprising the second insulating film (152) and the third insulating film (153) is formed on the side surface of the second gate electrode (144).

Description

Semiconductor device and manufacturing method thereof

The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a plurality of transistors having different sidewall widths and a manufacturing method thereof.

In recent years, with the miniaturization of semiconductor devices, the difference in power supply voltage between an arithmetic circuit such as a microcomputer and a core circuit used for a built-in memory and an input / output circuit used as an interface with the outside has increased. In addition, the movement of mounting transistors with various power supply voltages on one chip for higher functionality is accelerating.

In a MIS (metal-insulating film-semiconductor) type field effect transistor used in a semiconductor device, a change in impurity concentration at a boundary between a source / drain and a channel is reduced, and deterioration of the transistor due to hot carriers is suppressed. LDD (Lightly Doped Drain) structure is often used. In the LDD structure, impurities having a concentration lower than that of the source / drain regions are implanted on both sides of the gate electrode of the transistor, sidewalls are then formed on the sidewalls of the gate electrode, and impurities having a high concentration are implanted through the sidewalls. Source / drain regions are formed.

In the case of the LDD structure, generally, the sidewall width of a transistor having a high power supply voltage needs to be larger than that of a transistor having a low power supply voltage. When the sidewall width of the transistor is smaller than the design value, the change in the impurity concentration in the boundary region between the source / drain and the channel becomes steep. As a result, carriers flowing through the channel obtain energy and become so-called hot carriers, which are injected into the gate insulating film. Hot carriers injected into the gate insulating film cause defects in the gate insulating film or are trapped in the gate insulating film. As a result, the threshold value of the transistor varies and the reliability decreases. Conversely, when the sidewall width becomes larger than the design, the resistance value of the diffusion layer increases and the driving capability of the transistor decreases. As described above, the width of the sidewall of the LDD structure has a great influence on the characteristics of the transistor, and thus control is important. Therefore, various techniques for controlling the sidewall width of each transistor have been reported (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 2-139965

However, in the conventional method for manufacturing a semiconductor device, a sidewall having a small width is formed by etching the oxide film for forming the sidewall for a long time. When etching is performed for a long time, not only the oxide film for forming the sidewall but also the element isolation region is etched in the vicinity of the boundary between the element isolation region and the active region, and the pn junction may be exposed on the side surface of the active region. . When the pn junction is exposed on the side surface of the active region, it causes a junction leak when the silicide layer is formed.

If the etching mask is overlapped on the element isolation region in order to avoid the etching of the element isolation region, the sidewall oxide film may not be etched at the portion where the etching mask overlaps, and may remain in a thin column shape. . If the oxide film remaining in a thin columnar shape is broken during the manufacturing process, particles are generated and the product yield is lowered. Further, the particles adversely affect the post-process equipment.

An object of the present disclosure is to solve the above-described problem and to accurately form a plurality of transistors having different sidewall widths on a substrate without causing etching of an element isolation region.

In order to achieve the above object, the present disclosure discloses a method for manufacturing a semiconductor device, in which a sidewall is formed from a plurality of stacked insulating films, and the sidewall width is changed by changing the number of stacked insulating films. The configuration is to be controlled.

Specifically, the semiconductor device manufacturing method of the first example includes a step (a) of forming a first region and a second region that are separated from each other by an element isolation region on a substrate, and a step above the first region. (B) forming a first gate electrode with a first gate insulating film interposed therebetween, and forming a second gate electrode with a second gate insulating film interposed on the second region; The step (c) of sequentially forming the first insulating film and the second insulating film so as to cover the first gate electrode and the second gate electrode, and the second insulating film after the step (c) A step (d) of removing a portion formed on the first region in step (d), a step (e) of forming a third insulating film on the substrate after the step (d), and a step (e ), The second insulating film and the third insulating film are etched back to form the first gate electrode on the side surface. Forming a first outer side wall made of three insulating films and forming a second outer side wall made of the second insulating film and the third insulating film on the side surface of the second gate electrode (f) And after the step (f), the portion of the first insulating film that is not covered by the first outer sidewall and the second outer sidewall is removed, so that the first gate electrode is exposed on the side surface of the first gate electrode. Forming a first inner side wall and forming a second inner side wall on the side surface of the second gate electrode, wherein the second gate electrode is formed from the first gate electrode. Also, the gate length is long, and the first insulating film and the second insulating film are made of different materials, and the second insulating film and the third insulating film are made of the same material.

In the method of manufacturing the semiconductor device of the first example, a step (d) of removing a portion formed on the first region in the second insulating film, and a step on the substrate after the step (d) are performed. The third insulating film is formed on the side surface of the first gate electrode by etching back the second insulating film and the third insulating film after the step (e) of forming the third insulating film and the step (e). Forming a first outer sidewall made of a second insulating film, and forming a second outer sidewall made of a second insulating film and a third insulating film on the side surface of the second gate electrode (f) And. For this reason, the width of the first outer sidewall and the width of the second outer sidewall can be accurately controlled. In addition, since the first insulating film is formed under the second insulating film, the element isolation region, the gate insulating film, and the like are etched when the second insulating film and the third insulating film are etched. There is no.

In the semiconductor device manufacturing method of the first example, in the step (d), the second insulating film may be removed by wet etching.

In the semiconductor device manufacturing method of the first example, the first outer side wall may be narrower than the second outer side wall.

In the semiconductor device manufacturing method of the first example, the first gate insulating film may be thinner than the second gate insulating film.

In the semiconductor device manufacturing method of the first example, the first region is a formation region of the first transistor, the second region is a formation region of the second transistor, and the first transistor is a power source. The voltage may be greater than or equal to 1.1 V and less than or equal to 2.0 V, and the second transistor may have a structure in which the power supply voltage is greater than or equal to 3.3 V and less than or equal to 7.0 V.

In the semiconductor device manufacturing method of the first example, the first gate electrode has a gate length of 30 nm to 180 nm, and the second gate electrode has a gate length of 200 nm to 700 nm. Good.

In the method of manufacturing the semiconductor device of the first example, in the step (f), the second insulating film and the third insulating film are formed until a portion of the first insulating film formed on the first gate electrode is exposed. And after the step (f1), the second insulating film and the third insulating film are exposed until a portion of the first insulating film formed on the second gate electrode is exposed. A step (f2) of removing a portion of the film formed on the second region.

The manufacturing method of the semiconductor device of the first example further includes a step (h) of forming a fourth insulating film on the substrate after the step (b) and before the step (c). In (g), after removing the exposed portion of the first insulating film, the exposed portion of the fourth insulating film may be removed.

The method of manufacturing the semiconductor device of the first example includes a step (h) of forming a fourth insulating film on the substrate after the step (b) and before the step (c), The method may further comprise a step (i) of forming an offset spacer on the side surfaces of the first gate electrode and the second gate electrode by selectively removing the insulating film.

In the semiconductor device manufacturing method of the first example, the fourth insulating film may be a silicon oxide film.

In the semiconductor device manufacturing method of the first example, the first insulating film may be a silicon nitride film, and the second insulating film and the third insulating film may be silicon oxide films.

The semiconductor device of the second example includes a first transistor formed in the first region of the substrate and a second transistor formed in the second region, and the first transistor is formed on the substrate over the first transistor. Formed on the side wall of the first gate electrode, a first inner side wall formed on the side surface of the first gate electrode, and a first inner side wall. A second transistor having a first outer sidewall and a second gate electrode formed on the substrate with a second gate insulating film interposed between the second gate electrode and a side surface of the second gate electrode; A second inner sidewall formed on the second inner sidewall; a second outer sidewall formed on the second inner sidewall; and the first inner sidewall, the second inner sidewall, and the first inner sidewall. Outside sidewalls and number The outer side wall, made of different materials, a first outer side wall is made of a single layer film, a second outer side wall is made of a laminated film.

According to the method for manufacturing a semiconductor device of the present disclosure, it is possible to accurately form a plurality of transistors having different sidewall widths on a substrate without causing etching of an element isolation region.

(A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment to process order. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment to process order. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment to process order. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on one Embodiment. It is sectional drawing which shows the problem of the manufacturing method of the conventional side wall. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st modification of one Embodiment in order of a process. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd modification of one Embodiment to process order. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd modification of one Embodiment to process order. (A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd modification of one Embodiment to process order. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd modification of one Embodiment to process order. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd modification of one Embodiment to process order. (A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd modification of one Embodiment to process order. (A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd modification of one Embodiment to process order.

(One embodiment)
First, as shown in FIG. 1A, an element isolation region 102 having a shallow trench (STI) structure made of a silicon oxide film having a thickness of 300 nm is formed on a substrate 101 such as a silicon substrate. An element region is formed. Subsequently, in the first region 103 that forms the first transistor that is a low breakdown voltage transistor, a first P well 131 is formed above the element region, and a second transistor that is a high breakdown voltage transistor is formed. In the region 104, a second P well 141 is formed above the element region.

Next, as shown in FIG. 1B, the first gate insulating film 133 and the first gate electrode 134 of the first transistor, and the second gate insulating film 143 and the second gate electrode of the second transistor are used. A gate electrode 144 is formed. Specifically, a silicon oxide film having a thickness of 2 nm is formed on the first region 103, a silicon oxide film having a thickness of 20 nm is formed on the second region 104, and then the first region is formed. A polysilicon film having a thickness of 200 nm is formed on the third region 104 and the second region 104. Subsequently, patterning using lithography is performed and etching is performed. Thus, the first gate insulating film 133 and the first gate electrode 134 are formed on the first region 103, and the second gate insulating film 143 and the second gate electrode are formed on the second region 104. 144 is formed. The first gate electrode 134 has a gate length of 180 nm, and the second gate electrode 144 has a gate length of 600 nm.

Next, as shown in FIG. 1C, a resist mask is patterned by lithography to form a resist film 171 that covers the first region 103 and exposes the second region 104. Phosphorus (P) ions are implanted into the second region 104 using the resist film 171 as an implantation mask. In the ion implantation, the acceleration voltage is set to 80 keV, and the dose amount is set to 2 × 10 ¹³ / cm ² . Thereby, the second N-type extension diffusion layer 145 for the second transistor is formed on the second region 104.

Next, after removing the resist film 171, as shown in FIG. 2A, a resist mask is patterned by a lithography method to cover the second region 104 and to expose the first region 103. Form. Phosphorus ions are implanted into the first region 103 using the resist film 172 as an implantation mask. In the ion implantation, the acceleration voltage is set to 12 keV, and the dose is set to 5 × 10 ¹⁴ cm ² . Thus, the first N-type extension diffusion layer 135 for the first transistor is formed on the first region 103.

Next, after removing the resist film 172, as shown in FIG. 2B, a first silicon nitride film having a thickness of 15 nm is formed so as to cover the first gate electrode 134 and the second gate electrode 144. Next, a second insulating film 152 made of a silicon oxide film having a thickness of 40 nm is deposited.

Next, as shown in FIG. 2C, a resist film 173 that covers the second region 104 and exposes the first region 103 is formed, and subsequently formed on the first region 103 by wet etching. The second insulating film 152 is removed. The second insulating film 152 made of a silicon oxide film may be etched using, for example, dilute hydrofluoric acid in which hydrofluoric acid (HF) and water are mixed at a ratio of 1:20. The first gate insulating film 133 and the element isolation region 102 are not etched because they are covered with the first insulating film 151 made of a silicon nitride film.

Next, after removing the resist film 173, a third insulating film 153 made of a silicon oxide film having a thickness of 50 nm is deposited as shown in FIG.

Next, as shown in FIG. 3B, the first outer side wall 136 is formed on the side surface of the first gate electrode 134 by the entire surface etch back, and the second side electrode 136 is formed on the side surface of the second gate electrode 144. Outer sidewalls 146 are formed. Etchback of the third insulating film 153 and the second insulating film 152 may be performed until part of the first insulating film 151 is exposed in the second region 104 by dry etching. For example, dry etching uses a lower one-frequency RIE etching apparatus that applies high-frequency power of a single frequency (for example, 13.56 MHz) only to the lower electrode, and uses perfluorocyclobutane (C ₄ F ₈ ) as an etching gas. Argon (Ar) and oxygen (O ₂ ) are supplied into the chamber at a flow rate of 22 sccm (standard state cm ³ / min), 1500 sccm and 4 sccm, respectively, and the pressure in the chamber is set to 30 mTorr (about 4 Pa). Is 250 W and the substrate temperature is 20 ° C. By using such etching conditions, the selection ratio between the silicon oxide film and the silicon nitride film can be about 5.

In the second region 104, the thickness of the silicon oxide film deposited on the first insulating film 151 is the sum of the thickness of the second insulating film 152 and the thickness of the third insulating film 153. It is 90 nm. On the other hand, since the second insulating film 152 is removed in the first region 103, the thickness of the silicon oxide film deposited on the first insulating film 151 is 50 nm. When the first insulating film 151 is exposed in the second region 104, an overetch amount of about 20% is added to the thickness of the silicon oxide film, and etching equivalent to 108 nm is performed as the silicon oxide film. There is a need. When the selection ratio between the silicon oxide film and the silicon nitride film is about 5, in the second region 104, the first insulating film 151 is etched by about 4 nm. On the other hand, in the first region 103, overetching corresponding to 58 nm occurs as a silicon oxide film, and the first insulating film 151 is etched by about 12 nm. As described above, when the thickness of the first insulating film 151 is 15 nm, in the etching for removing the second insulating film 152 and the third insulating film 153, the selectivity between the silicon oxide film and the silicon nitride film If the thickness is about 5, the etching can be stopped in the first insulating film 151 made of the silicon nitride film, and the substrate 101 and the element isolation region 102 are not etched.

Next, as shown in FIG. 3C, the first insulating film 151 is removed by etching the entire surface until the substrate 101 is exposed. At this time, the first insulating film 151 on the first gate electrode 134 and the second gate electrode 144 is also removed. As a result, a first sidewall 138 having a first inner sidewall 137 and a first outer sidewall 136 is formed on the side surface of the first gate electrode 134, and the second gate electrode 144 is disposed on the side surface. A second sidewall 148 having a second inner sidewall 147 and a second outer sidewall 146 is formed. The first insulating film is etched using, for example, a lower one-frequency RIE etching apparatus, and an etching gas of carbon tetrafluoride (CF ₄ ), ethylene difluoride (CH ₂ F ₂ ), Ar, and O _2. Are supplied into the chamber at flow rates of 50 sccm, 30 sccm, 1500 sccm, and 30 sccm, respectively, the pressure in the chamber is 60 mTorr (about 8 Pa), the high-frequency power is 250 W, and the substrate temperature is 20 ° C.

Next, as illustrated in FIG. 4, ion implantation is performed on the first region 103 using the first gate electrode 134 and the first sidewall 138 as a mask, and the second gate electrode 144 and the second sidewall are performed. Ion implantation is performed on the second region 104 using 148 as a mask. Thus, the first N-type source / drain diffusion layer 139 is formed in the first region 103, and the second N-type source / drain diffusion layer 149 is formed in the second region 104. For the ion implantation, for example, arsenic (As) ions may be implanted at an acceleration voltage of 20 keV so that the dose amount is 4 × 10 ¹⁴ / cm ² . Subsequently, heat treatment for activating the first N-type source / drain diffusion layer 139 and the second N-type source / drain diffusion layer 149 is performed. The heat treatment may be a rapid heat treatment at 1000 ° C. for 10 seconds, for example. Thereafter, a step of forming the silicide layer 107 on the first N-type source / drain diffusion layer 139, the second N-type source / drain diffusion layer 149, the first gate electrode 134, and the second gate electrode 144 is performed. Just do it. Thus, a first transistor having a first sidewall 138 having a width of about 60 nm is formed in the first region 103, and a second transistor 148 having a second sidewall 148 having a width of about 105 nm is formed in the second region 104. Two transistors are formed.

In the semiconductor device manufacturing method of this embodiment, the width of the sidewall can be controlled by the thickness of the second insulating film 152 and the third insulating film 153 that are silicon oxide films, and the width of the sidewall can be freely set. It is possible to set. When the second insulating film 152 that is a silicon oxide film is removed by wet etching in the first region 103, the first gate insulating film 133 is covered with the first insulating film 151 made of a silicon nitride film. ing. Therefore, side etching is not generated in the first gate insulating film 133, and a highly reliable transistor can be formed. Further, when the second insulating film 152 and the third insulating film 153 are etched, the etching can be stopped in the first insulating film 151 by performing etching under a condition with a high etching selectivity. Therefore, the element isolation region 102 is not etched particularly in the first region 103, and there is no possibility that junction leakage occurs when the silicide layer 107 is formed.

In the present embodiment, the first outer sidewall 136 of the first transistor and the second outer sidewall 146 of the second transistor are formed in the same etching step. When the sidewall of the first transistor and the sidewall of the second transistor are formed by separate processes, an oxide film for forming the sidewall may remain on the element isolation region. For example, as illustrated in FIG. 5, when the sidewall 546 of the second transistor is formed, an end portion of the resist film 571 covering the first region 503 protrudes to the second region 504 side, and the first transistor When an overlap with the region covered with the resist film occurs when forming the sidewall 536, a thin columnar oxide film 511 remains on the element isolation region 502. The oxide film 511 is easily broken, and when the oxide film 511 is broken and particles are generated, the yield of the product is lowered. In addition, the particles have an adverse effect on post-process equipment. However, in this embodiment, such an oxide film does not remain.

(First Modification of One Embodiment)
In the embodiment, the example in which the first outer side wall 136 and the second outer side wall 146 are formed in the same process is shown. However, the first outer side wall 136 and the second outer side wall 146 may be formed sequentially.

The steps until the third insulating film 153 is formed are the same as the steps shown in the embodiment.

Next, as shown in FIG. 6A, the second insulating film 152 and the third insulating film 153 are etched back until the first insulating film 151 is exposed in the first region 103. Thereby, in the first region 103, the first outer side wall 136 is formed on the side surface of the first gate electrode 134, and in the second region 104, the second insulating film 152 and the third insulating film are formed. The film 153 remains and the first insulating film 151 is not exposed.

Next, as shown in FIG. 6B, a resist film 174 that covers the first region 103 and exposes the second region 104 is formed. Subsequently, in the second region 104, the second insulating film 152 and the third insulating film 153 are etched until the first insulating film 151 is exposed. As a result, the second outer sidewall 146 is formed on the side surface of the second gate insulating film in the second region 104. The second insulating film 152 and the third insulating film 153 may be etched under the same conditions as in the embodiment.

Next, after removing the resist film 174, as shown in FIG. 6C, the exposed portion of the first insulating film 151 is removed as in the embodiment. Thus, the first sidewall 138 having the first inner sidewall 137 and the first outer sidewall 136, and the second sidewall having the second inner sidewall 147 and the second outer sidewall 146. 148 is formed. The first insulating film 151 may be etched under the same conditions as in the embodiment.

Thereafter, an N-type source / drain diffusion layer, a silicide layer, and the like may be formed in the same manner as in the embodiment.

In the manufacturing method of the semiconductor device according to this modification, the width of the sidewall can be freely set as in the embodiment. Further, side etching is not generated in the first gate insulating film 133, so that a highly reliable transistor can be formed. Furthermore, there is no possibility that junction leakage will occur when the silicide layer 107 is formed.

In this modification, the first region 103 is covered with the resist film 174 when the second outer side wall 146 is formed. For this reason, the first outer side wall 136 is not over-etched excessively. In the case where the width of the first sidewall 138 is extremely narrower than the width of the second sidewall 148, the thickness of the third insulating film needs to be reduced. In this case, since the amount of overetching in the first region 103 increases, the etching cannot be stopped in the first insulating film 151, and the base may be etched. In this modification, since the second outer side wall 136 is formed after the first outer side wall 136 is formed, the etching amount of the first insulating film 151 in the first region 103 does not increase. Further, since the first outer side wall 136 is not excessively etched, the height of the first side wall 138 does not become lower than the height of the first gate electrode 134. For this reason, when ion implantation for forming the N-type source / drain diffusion layer is performed, there is no possibility that ion species may penetrate the substrate.

(Second Modification of One Embodiment)
In one embodiment, the first N-type extension diffusion layer 135 and the second N-type extension diffusion layer 145 are formed using the first gate electrode 134 and the second gate electrode 144, respectively, as an implantation mask. . In this modification, after an offset spacer is formed on the side surface of the gate electrode, ion implantation for forming an N-type extension diffusion layer is performed.

The steps until the first gate electrode 134 and the second gate electrode 144 are formed are the same as the steps shown in the embodiment.

Next, as shown in FIG. 7A, a fourth insulating film 161 made of a silicon oxide film having a thickness of 10 nm is formed so as to cover the first gate electrode 134 and the second gate electrode 144.

Next, as shown in FIG. 7B, the fourth insulating film 161 is etched until the substrate 101 is exposed by the entire surface etch back, and on the side surfaces of the first gate electrode 134 and the second gate electrode 144. An offset spacer 162 is formed. The fourth insulating film 161 is etched by using, for example, a lower one-frequency RIE etching apparatus, and supplying C ₄ F ₈ , Ar, and O ₂ as etching gases into the chamber at flow rates of 22 sccm, 1500 sccm, and 4 sccm, respectively. The pressure in the chamber may be 30 mTorr, the high-frequency power is 250 W, and the substrate temperature is 20 ° C.

Next, as shown in FIG. 7C, a resist film 175 that covers the first region 103 and exposes the second region 104 is formed, and the second gate electrode 144 and the offset spacer 162 are used as an implantation mask. Ion implantation is performed on the second region 104. Thereby, the second N-type extension diffusion layer 145 is formed. The ion implantation may be performed under the same conditions as the steps shown in the embodiment.

Next, after removing the resist film 175, as shown in FIG. 8A, a resist film 176 that covers the second region 104 and exposes the first region 103 is formed, and the first gate electrode 134 and Ions are implanted into the first region 103 using the offset spacer 162 as an implantation mask. Thereby, the first N-type extension diffusion layer 135 is formed. The ion implantation may be performed under the same conditions as the steps shown in the embodiment.

Next, after removing the resist film 176, a first insulating film 151 and a second insulating film 152 are sequentially formed as shown in FIG. After removing the second insulating film 152 in the region 103, a third insulating film 153 is formed over the entire surface of the substrate 101. Thereafter, the second insulating film 152 and the third insulating film 153 are entirely etched back to form the first outer side wall 136 and the second outer side wall 146. Next, as shown in FIG. 8C, the exposed portion of the first insulating film 151 is removed to form a first inner side wall 137 and a second inner side wall 147. Further, although not shown, as in the embodiment, ion implantation is performed on the first region 103 using the first gate electrode 134, the offset spacer 162, and the first sidewall 138 as a mask, and the second gate electrode 144. Then, ion implantation is performed on the second region 104 using the offset spacer 162 and the second sidewall 148 as a mask. Thereby, an N-type source / drain diffusion layer is formed. After the N-type source / drain diffusion layer is formed, a silicide layer and the like are formed.

Further, after forming the third insulating film 153, as shown in FIG. 9A, the first outer side wall 136 is first formed in the same manner as in the first modification, and then, FIG. A second outer sidewall 146 may be formed as shown in FIG.

In the manufacturing method of the semiconductor device according to this modification, the width of the sidewall can be freely set as in the embodiment. Further, side etching is not generated in the first gate insulating film 133, so that a highly reliable transistor can be formed. Furthermore, there is no possibility that junction leakage will occur when the silicide layer 107 is formed.

In the manufacturing method of the semiconductor device of the present modification, the extension diffusion layer is formed after the offset sidewall is formed, so that the short channel effect can be reduced. Further, since the extension diffusion layer is formed after removing the portion of the fourth insulating film formed on the semiconductor substrate, the implantation is performed when the process of forming the extension diffusion layer shallow from the semiconductor substrate is used. Profile control becomes easy.

An offset sidewall made of a silicon oxide film is formed between the first insulating film made of a silicon nitride film and the gate insulating film. When the first insulating film made of a silicon nitride film and the gate insulating film are in direct contact, an interface state is formed in the vicinity of the interface between the gate insulating film and the first insulating film, and hot carriers and NBTI (Negative bias temperature instability) There is a possibility that a problem of lowering reliability may occur. In this modification, the offset spacer made of the silicon oxide film is formed between the first insulating film made of the silicon nitride film and the gate insulating film, so that such a problem does not occur.

(Third Modification of One Embodiment)
In the second modified example, an example is shown in which ion implantation of the extension diffusion layer is performed after an offset spacer is formed by etching back the fourth insulating film. However, the extension diffusion layer may be ion-implanted with the fourth insulating film remaining.

The steps until the fourth insulating film 161 is formed are the same as the steps shown in the second modification.

Next, as shown in FIG. 10A, after forming a resist film 178 that covers the first region 103 and exposes the second region 104, ion implantation is performed on the second region 104, An N-type extension diffusion layer 145 is formed. The ion implantation may be performed under the same conditions as the steps shown in the embodiment.

Next, after removing the resist film 178, as shown in FIG. 10B, a resist film 179 that covers the second region 104 and exposes the first region 103 is formed, and then the first region 103 is formed. Ion implantation is performed to form a first N-type extension diffusion layer 135. The ion implantation may be performed under the same conditions as the steps shown in the embodiment.

Next, after removing the resist film 179, a first insulating film 151 and a second insulating film 152 are sequentially formed on the fourth insulating film 161 as shown in FIG.

Next, as shown in FIG. 11A, a resist film 173 that exposes the first region 103 and covers the second region 104 is formed, and is formed in the first region 103 in the second insulating film 152. Remove the part. Etching of the second insulating film 152 may be performed under the same conditions as in the steps described in one embodiment.

Next, after removing the resist film 173, a third insulating film 153 is formed in the first region 103 and the second region 104 as shown in FIG.

Next, as shown in FIG. 11C, the second insulating film 152 and the third insulating film 153 are etched back to form the first outer side wall 136 and the second outer side wall 146. . Etching of the second insulating film 152 and the third insulating film 153 may be performed under the same conditions as in the steps described in one embodiment.

Next, as shown in FIG. 12A, the exposed portion of the first insulating film 151 is etched, and then the exposed portion of the fourth insulating film 161 is etched. Accordingly, the first inner sidewall 137 having the first insulating film 151 and the fourth insulating film 161 and the second inner sidewall 147 having the first insulating film 151 and the fourth insulating film 161 are formed. Form. The etching of the first insulating film 151 may be performed under the same conditions as in the process described in one embodiment. The fourth insulating film 161 is etched by using, for example, a lower one-frequency RIE etching apparatus, and supplying C ₄ F ₈ , Ar, and O ₂ as etching gases into the chamber at flow rates of 22 sccm, 1500 sccm, and 4 sccm, respectively. The pressure in the chamber may be 30 mTorr, the high-frequency power is 250 W, and the substrate temperature is 20 ° C.

Next, as illustrated in FIG. 12B, ion implantation is performed on the first region 103 using the first gate electrode 134 and the first sidewall 138 as a mask, and the second gate electrode 144 and the second gate electrode 138. Ions are implanted into the second region 104 using the sidewall 148 as a mask. As a result, a first N-type source / drain diffusion layer 139 and a second N-type source / drain diffusion layer 149 are formed. The ion implantation may be performed under the same conditions as the steps shown in the embodiment. Thereafter, the silicide layer 107 may be formed on the first N-type source / drain diffusion layer 139, the second N-type source / drain diffusion layer 149, the first gate electrode 134, and the second gate electrode 144.

As in the second modification, first, the first outer sidewall 136 is formed as shown in FIG. 13A, and then the second outer sidewall 146 is formed as shown in FIG. 13B. May be formed.

In the manufacturing method of the semiconductor device according to this modification, the width of the sidewall can be freely set as in the embodiment. Further, side etching is not generated in the first gate insulating film 133, so that a highly reliable transistor can be formed. Furthermore, there is no possibility that junction leakage will occur when the silicide layer 107 is formed.

In the manufacturing method of the semiconductor device of this modification, the short channel effect can be reduced because the fourth insulating film is formed when the extension diffusion layer is formed.

Further, a fourth insulating film made of a silicon oxide film is formed between the first insulating film made of the silicon nitride film and the gate insulating film. When the first insulating film made of a silicon nitride film and the gate insulating film are in direct contact, an interface state is formed in the vicinity of the interface between the gate insulating film and the first insulating film, and hot carriers and NBTI (Negative bias temperature instability) There is a possibility that a problem of lowering reliability may occur. In this modification, the offset spacer made of the silicon oxide film is formed between the first insulating film made of the silicon nitride film and the gate insulating film, so that such a problem does not occur.

In one embodiment and its modification, an example in which the first transistor is a low breakdown voltage transistor and the second transistor is a high breakdown voltage transistor is shown. The size of the gate electrode, the width of the sidewall, and the like exemplified are suitable when the operating voltage of the first transistor is 1.8V and the operating voltage of the second transistor is 5V. However, the operating voltages of the first transistor and the second transistor are not limited to this. The operating voltages of the first transistor and the second transistor may be arbitrarily set as long as the second transistor is higher than the first transistor. For example, the operating voltage of the first transistor may be in the range of about 1.1V to 2V, and the operating voltage of the second transistor may be in the range of about 3.3V to 7V. In addition, even when three or more types of transistors having different operating voltages are formed, the manufacturing method shown in the embodiment and its modification can be applied.

In one embodiment and its modification, the gate length of the first transistor was 180 nm, and the gate length of the second transistor was 600 nm. However, if the gate length of the second transistor is longer than the gate length of the first transistor, the gate lengths of the first transistor and the second transistor may be arbitrarily set. For example, the gate length of the first transistor may be in the range of about 30 nm to 180 nm, and the gate length of the second transistor may be in the range of about 200 nm to 700 nm.

Although an example in which an N-type MIS transistor is formed is shown in one embodiment and its modification, the manufacturing method shown in one embodiment and its modification can also be applied when forming a P-type MIS transistor. it can. Further, an N-type MIS transistor and a P-type MIS transistor may be mixed on the semiconductor substrate. In this case, an N-type MIS transistor and a P-type MIS transistor having different sidewall widths may be formed.

In one embodiment and its modification, the first gate insulating film and the second gate insulating film are silicon oxide films, but other insulating films may be used. Further, although the first gate electrode and the second gate electrode are polysilicon gate electrodes, they may be gate electrodes made of other materials.

In one embodiment and the modification thereof, the first insulating film is a silicon nitride film, and the second insulating film and the third insulating film are silicon oxide films. However, the first insulating film and the second insulating film are used. Other materials may be used as long as the second insulating film and the third insulating film are made of the same material.

In the step of forming the outer sidewall by removing the second insulating film and the third insulating film, the etching selectivity between the first insulating film, the second insulating film, and the third insulating film is set to about 5. Although an example of setting is shown, the etching selectivity is not limited to this value. Although it is preferable that the etching selection ratio is large, the film thickness of the first insulating film is such that the first insulating film remains in accordance with the etching selection ratio and the film thicknesses of the second insulating film and the third insulating film. Is set, there is no problem even if the etching selectivity is about 2. For example, when the thickness of the second insulating film is 20 nm, the thickness of the third insulating film is 50 nm, and the overetch amount is 20%, the etching amount is 84 nm. For this reason, in the low withstand voltage region, the converted etching amount of the first insulating film is 64 nm. Therefore, when the etching selectivity is 2, it is sufficient that the thickness of the first insulating film is about 35 nm.

The method for manufacturing a semiconductor device according to the present disclosure can accurately form a plurality of transistors having different sidewall widths on a substrate without causing etching of an element isolation region, and particularly includes a plurality of transistors having different sidewall widths. This is useful as a method for manufacturing a semiconductor device.

101 Substrate 102 Element isolation region 103 First region 104 Second region 107 Silicide layer 131 First P well 133 First gate insulating film 134 First gate electrode 135 First N-type extension diffusion layer 136 First Outer side wall 137 first inner side wall 138 first side wall 139 first N-type source / drain diffusion layer 141 second P well 143 second gate insulating film 144 second gate electrode 145 second gate electrode 145 N-type extension diffusion layer 146 Second outer side wall 147 Second inner side wall 148 Second side wall 149 Second N-type source / drain diffusion layer 151 First insulating film 152 Second insulating film 153 Third Insulating film 161 Fourth insulating film 162 Tosupesa 171 resist film 172 resist film 173 resist film 174 resist film 175 resist film 176 resist film 177 resist film 178 resist film 502 isolation regions 503 first region 504 second region 511 oxide film 536 sidewall 547 sidewall

Claims (12)

Forming a first region and a second region separated from each other by an element isolation region on the substrate;
A first gate insulating film is formed on the substrate in the first region to form a first gate electrode, and a second gate insulating film is formed on the substrate in the second region. Forming a second gate electrode (b),
A step (c) of sequentially forming a first insulating film and a second insulating film so as to cover the first gate electrode and the second gate electrode;
A step (d) of removing a portion of the second insulating film formed on the first region after the step (c);
A step (e) of forming a third insulating film on the substrate after the step (d);
After the step (e), by etching back the second insulating film and the third insulating film, the first outer side made of the third insulating film on the side surface of the first gate electrode. Forming a sidewall, and forming a second outer sidewall made of the second insulating film and the third insulating film on a side surface of the second gate electrode;
After the step (f), by removing a portion of the first insulating film that is not covered with the first outer sidewall and the second outer sidewall, the side surface of the first gate electrode is removed. Forming a first inner sidewall on the second gate electrode, and forming a second inner sidewall on the side surface of the second gate electrode;
The second gate electrode has a longer gate length than the first gate electrode,
The first insulating film and the second insulating film are made of different materials,
The method for manufacturing a semiconductor device, wherein the second insulating film and the third insulating film are made of the same material. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (d), the second insulating film is removed by wet etching. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first outer side wall is narrower than the second outer side wall. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the first gate insulating film is thinner than the second gate insulating film. The first region is a formation region of a first transistor;
The second region is a formation region of a second transistor,
The first transistor has a power supply voltage of 1.1 V or more and 2.0 V or less,
The method for manufacturing a semiconductor device according to claim 1, wherein the second transistor has a power supply voltage of 3.3 V or more and 7.0 V or less. The first gate electrode has a gate length of 30 nm or more and 180 nm or less,
6. The method for manufacturing a semiconductor device according to claim 1, wherein the second gate electrode has a gate length of not less than 200 nm and not more than 700 nm. The step (f)
Removing the second insulating film and the third insulating film until a portion of the first insulating film formed on the first gate electrode is exposed (f1);
After the step (f1), the first insulating film in the second insulating film and the third insulating film is exposed until a portion of the first insulating film formed on the second gate electrode is exposed. The method for manufacturing a semiconductor device according to claim 1, further comprising a step (f2) of removing a portion formed on the second region. A step (h) of forming a fourth insulating film on the substrate after the step (b) and before the step (c);
8. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (g), after the exposed portion of the first insulating film is removed, the exposed portion of the fourth insulating film is removed. Method. After step (b) and before step (c),
Forming a fourth insulating film on the substrate (h);
The method further comprises the step (i) of forming offset spacers on side surfaces of the first gate electrode and the second gate electrode by selectively removing the fourth insulating film. The method for manufacturing a semiconductor device according to any one of the above. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the fourth insulating film is a silicon oxide film. The first insulating film is a silicon nitride film;
11. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film and the third insulating film are silicon oxide films. A first transistor formed in a first region of the substrate and a second transistor formed in a second region;
The first transistor includes:
A first gate electrode formed on the substrate with a first gate insulating film interposed;
A first inner sidewall formed on a side surface of the first gate electrode;
A first outer sidewall formed on the first inner sidewall;
The second transistor is
A second gate electrode formed on the substrate with a second gate insulating film interposed therebetween;
A second inner sidewall formed on a side surface of the second gate electrode;
A second outer sidewall formed on the second inner sidewall,
The first inner side wall and the second inner side wall and the first outer side wall and the second outer side wall are made of different materials,
The first outer sidewall is a single layer film,
The second outer sidewall is a semiconductor device made of a laminated film.

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