WO2009060625A1 - Nonvolatile latch circuit and nonvolatile flip-flop circuit - Google Patents
Nonvolatile latch circuit and nonvolatile flip-flop circuit Download PDFInfo
- Publication number
- WO2009060625A1 WO2009060625A1 PCT/JP2008/003236 JP2008003236W WO2009060625A1 WO 2009060625 A1 WO2009060625 A1 WO 2009060625A1 JP 2008003236 W JP2008003236 W JP 2008003236W WO 2009060625 A1 WO2009060625 A1 WO 2009060625A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- potential
- operating current
- circuit
- nonvolatile
- latch circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/50—Resistive cell structure aspects
- G11C2213/52—Structure characterized by the electrode material, shape, etc.
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Static Random-Access Memory (AREA)
Abstract
A nonvolatile latch circuit comprises a latch circuit (6), output terminals (8, 9) of two inverters constituting the latch circuit, a first inverter (INV1) connected with one end of the operating current passage of one inverter, a second inverter (INV2) connected with one end of the operating current passage of the other inverter, a pair of resistance variation elements (1, 2) connected in series between a first node (n13) and a second node (n14) through a third node (n15) such that the conduction direction is reversed, a storage control terminal (STR) connected with one end of each operating current passage of the first and second inverters, a switching circuit (Trn1) having one I/O terminal connected with the third node, a data control circuit (15) connected with the first output terminal (8), and a potential control circuit (Trp10) for supplying the operating current to the other end of each operating current passage of the pair of inverters in the latch circuit and imparting a potential while varying from a first potential to a second potential wherein the other end of each operating current passage of the first and second inverters and the other I/O terminal of the switching circuit are connected with a potential imparting terminal for imparting the first potential.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007-290892 | 2007-11-08 | ||
JP2007290892 | 2007-11-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009060625A1 true WO2009060625A1 (en) | 2009-05-14 |
Family
ID=40625532
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2008/003236 WO2009060625A1 (en) | 2007-11-08 | 2008-11-07 | Nonvolatile latch circuit and nonvolatile flip-flop circuit |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2009060625A1 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7961005B1 (en) | 2009-12-09 | 2011-06-14 | Samsung Electronics Co., Ltd. | Non-volatile logic circuits, integrated circuits including the non-volatile logic circuits, and methods of operating the integrated circuits |
JP4995360B1 (en) * | 2011-01-20 | 2012-08-08 | パナソニック株式会社 | Nonvolatile latch circuit and nonvolatile flip-flop circuit |
JP2013218778A (en) * | 2012-03-13 | 2013-10-24 | Semiconductor Energy Lab Co Ltd | Memory device and driving method thereof |
US8604827B2 (en) | 2011-02-21 | 2013-12-10 | Samsung Electronics Co., Ltd. | Logic circuit, integrated circuit including the logic circuit, and method of operating the integrated circuit |
US8619466B2 (en) | 2011-02-07 | 2013-12-31 | Panasonic Corporation | Nonvolatile latch circuit, nonvolatile flip-flop circuit, and nonvolatile signal processing device |
US8792268B2 (en) | 2011-11-22 | 2014-07-29 | Panasonic Corporation | Nonvolatile latch circuit, nonvolatile flip-flop circuit, and nonvolatile signal processing device |
WO2019203019A1 (en) * | 2018-04-19 | 2019-10-24 | ソニーセミコンダクタソリューションズ株式会社 | Non-volatile storage circuit |
CN117789795A (en) * | 2023-12-27 | 2024-03-29 | 无锡中微亿芯有限公司 | Non-volatile DFF for FPGA based on variable resistance resistor |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003016773A (en) * | 2001-04-27 | 2003-01-17 | Internatl Business Mach Corp <Ibm> | Register, data storing method, and data read-out method |
WO2004040582A1 (en) * | 2002-11-01 | 2004-05-13 | Matsushita Electric Industrial Co., Ltd. | Method for driving non-volatile flip-flop circuit using resistance change element |
JP2005166170A (en) * | 2003-12-03 | 2005-06-23 | Internatl Business Mach Corp <Ibm> | Magnetic storage device |
JP2008085770A (en) * | 2006-09-28 | 2008-04-10 | Toshiba Corp | Nonvolatile latch circuit, and nonvolatile flip-flop circuit |
-
2008
- 2008-11-07 WO PCT/JP2008/003236 patent/WO2009060625A1/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003016773A (en) * | 2001-04-27 | 2003-01-17 | Internatl Business Mach Corp <Ibm> | Register, data storing method, and data read-out method |
WO2004040582A1 (en) * | 2002-11-01 | 2004-05-13 | Matsushita Electric Industrial Co., Ltd. | Method for driving non-volatile flip-flop circuit using resistance change element |
JP2005166170A (en) * | 2003-12-03 | 2005-06-23 | Internatl Business Mach Corp <Ibm> | Magnetic storage device |
JP2008085770A (en) * | 2006-09-28 | 2008-04-10 | Toshiba Corp | Nonvolatile latch circuit, and nonvolatile flip-flop circuit |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7961005B1 (en) | 2009-12-09 | 2011-06-14 | Samsung Electronics Co., Ltd. | Non-volatile logic circuits, integrated circuits including the non-volatile logic circuits, and methods of operating the integrated circuits |
JP4995360B1 (en) * | 2011-01-20 | 2012-08-08 | パナソニック株式会社 | Nonvolatile latch circuit and nonvolatile flip-flop circuit |
US8437177B2 (en) | 2011-01-20 | 2013-05-07 | Panasonic Corporation | Nonvolatile latch circuit and nonvolatile flip-flop circuit |
US8619466B2 (en) | 2011-02-07 | 2013-12-31 | Panasonic Corporation | Nonvolatile latch circuit, nonvolatile flip-flop circuit, and nonvolatile signal processing device |
US8604827B2 (en) | 2011-02-21 | 2013-12-10 | Samsung Electronics Co., Ltd. | Logic circuit, integrated circuit including the logic circuit, and method of operating the integrated circuit |
US8792268B2 (en) | 2011-11-22 | 2014-07-29 | Panasonic Corporation | Nonvolatile latch circuit, nonvolatile flip-flop circuit, and nonvolatile signal processing device |
JP2013218778A (en) * | 2012-03-13 | 2013-10-24 | Semiconductor Energy Lab Co Ltd | Memory device and driving method thereof |
WO2019203019A1 (en) * | 2018-04-19 | 2019-10-24 | ソニーセミコンダクタソリューションズ株式会社 | Non-volatile storage circuit |
CN112020744A (en) * | 2018-04-19 | 2020-12-01 | 索尼半导体解决方案公司 | Nonvolatile memory circuit |
CN112020744B (en) * | 2018-04-19 | 2024-09-17 | 索尼半导体解决方案公司 | Non-volatile storage circuit |
TWI863904B (en) * | 2018-04-19 | 2024-12-01 | 日商索尼半導體解決方案公司 | Non-volatile memory circuit |
CN117789795A (en) * | 2023-12-27 | 2024-03-29 | 无锡中微亿芯有限公司 | Non-volatile DFF for FPGA based on variable resistance resistor |
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