WO2008133167A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents
Semiconductor device and method for manufacturing semiconductor device Download PDFInfo
- Publication number
- WO2008133167A1 WO2008133167A1 PCT/JP2008/057487 JP2008057487W WO2008133167A1 WO 2008133167 A1 WO2008133167 A1 WO 2008133167A1 JP 2008057487 W JP2008057487 W JP 2008057487W WO 2008133167 A1 WO2008133167 A1 WO 2008133167A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- power supply
- supply voltage
- rom
- semiconductor device
- substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 4
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
To provide a mechanism for controlling a substrate voltage and a power supply voltage for suppressing MOS transistor device fluctuation by a simple means and to simplify a testing step. Combinations of a plurality of power supply voltage values (VDD) and substrate voltage values (VBP, VBN) are set in ROMs (ROM1- ROM 7). At the time of performing chip test, drain current and operation speed tests are performed at first to MOS transistors (PT, NT) to be controlled, while the transistors are turned off, and device fluctuation is confirmed. Fuse circuits (FU0-FU1) program to select an ROM having an optimum combination of the power supply voltage value (VDD) and the substrate voltage values (VBP, VBN), corresponding to the status of device fluctuation. In the subsequent chip tests, optimum substrate voltages are determined by looking up an ROM table corresponding to a power supply voltage value inputted from the external.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009511840A JP5090440B2 (en) | 2007-04-23 | 2008-04-17 | Semiconductor device |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007112767 | 2007-04-23 | ||
| JP2007-112767 | 2007-04-23 | ||
| JP2007336241 | 2007-12-27 | ||
| JP2007-336241 | 2007-12-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2008133167A1 true WO2008133167A1 (en) | 2008-11-06 |
Family
ID=39925623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2008/057487 WO2008133167A1 (en) | 2007-04-23 | 2008-04-17 | Semiconductor device and method for manufacturing semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP5090440B2 (en) |
| WO (1) | WO2008133167A1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001345693A (en) * | 2000-05-30 | 2001-12-14 | Hitachi Ltd | Semiconductor integrated circuit device |
| JP2002041160A (en) * | 2000-07-24 | 2002-02-08 | Univ Tokyo | Power control apparatus and method, and recording medium storing power control program |
| JP2003142598A (en) * | 2001-11-01 | 2003-05-16 | Hitachi Ltd | Semiconductor integrated circuit device |
| JP2004228417A (en) * | 2003-01-24 | 2004-08-12 | Renesas Technology Corp | Semiconductor integrated circuit apparatus |
| JP2005136322A (en) * | 2003-10-31 | 2005-05-26 | Toshiba Corp | Semiconductor integrated circuit and power supply voltage / substrate bias control circuit |
-
2008
- 2008-04-17 WO PCT/JP2008/057487 patent/WO2008133167A1/en active Application Filing
- 2008-04-17 JP JP2009511840A patent/JP5090440B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001345693A (en) * | 2000-05-30 | 2001-12-14 | Hitachi Ltd | Semiconductor integrated circuit device |
| JP2002041160A (en) * | 2000-07-24 | 2002-02-08 | Univ Tokyo | Power control apparatus and method, and recording medium storing power control program |
| JP2003142598A (en) * | 2001-11-01 | 2003-05-16 | Hitachi Ltd | Semiconductor integrated circuit device |
| JP2004228417A (en) * | 2003-01-24 | 2004-08-12 | Renesas Technology Corp | Semiconductor integrated circuit apparatus |
| JP2005136322A (en) * | 2003-10-31 | 2005-05-26 | Toshiba Corp | Semiconductor integrated circuit and power supply voltage / substrate bias control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5090440B2 (en) | 2012-12-05 |
| JPWO2008133167A1 (en) | 2010-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6630857B2 (en) | Semiconductor integrated circuit apparatus | |
| JP5806853B2 (en) | Voltage regulator | |
| US8610421B2 (en) | Current generator and method of operating | |
| CN103825601A (en) | Fuse trimming and adjusting circuit | |
| KR20090089795A (en) | Power circuit | |
| KR20020077035A (en) | Address generating circuit | |
| JP2013055102A (en) | Semiconductor integrated circuit and protection circuit | |
| US8018197B2 (en) | Voltage reference device and methods thereof | |
| US8476966B2 (en) | On-die voltage regulation using p-FET header devices with a feedback control loop | |
| JP2004111959A (en) | Programmable fuse device | |
| US20080205115A1 (en) | Apparatus and method for trimming integrated circuit | |
| TW201027711A (en) | Transitioning digital integrated circuit from standby mode to active mode via backgate charge transfer | |
| CN102622027B (en) | Voltage recognition device and clock control device | |
| US7913141B2 (en) | Power gating in integrated circuits for leakage reduction | |
| CA2679364A1 (en) | Circuit device and method of controlling a voltage swing | |
| US20160196880A1 (en) | Fuse element programming circuit and method | |
| WO2008133167A1 (en) | Semiconductor device and method for manufacturing semiconductor device | |
| US10263622B2 (en) | Semiconductor apparatus and method of controlling MOS transistor | |
| WO2013161483A1 (en) | Output driver circuit | |
| US8405432B2 (en) | Output buffer circuit, input buffer circuit, and input/output buffer circuit | |
| WO2008114342A1 (en) | Power switch circuit and semiconductor integrated circuit device | |
| CN109213246B (en) | Power supply circuit, generation method and control method | |
| US8779804B2 (en) | Gate-stress test circuit without test pad | |
| CN103312313A (en) | rail to rail enable signal and level conversion circuit | |
| JP2006073553A (en) | Fuse trimming circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 08740557 Country of ref document: EP Kind code of ref document: A1 |
|
| ENP | Entry into the national phase |
Ref document number: 2009511840 Country of ref document: JP Kind code of ref document: A |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 08740557 Country of ref document: EP Kind code of ref document: A1 |