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WO2008066030A1 - Film d'alliage d'al pour un dispositf d'affichage, dispositf d'affichage, et cible de pulvérisation cathodique - Google Patents

Film d'alliage d'al pour un dispositf d'affichage, dispositf d'affichage, et cible de pulvérisation cathodique Download PDF

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Publication number
WO2008066030A1
WO2008066030A1 PCT/JP2007/072832 JP2007072832W WO2008066030A1 WO 2008066030 A1 WO2008066030 A1 WO 2008066030A1 JP 2007072832 W JP2007072832 W JP 2007072832W WO 2008066030 A1 WO2008066030 A1 WO 2008066030A1
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Prior art keywords
film
alloy
alloy film
atomic
display device
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PCT/JP2007/072832
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English (en)
Japanese (ja)
Inventor
Hiroshi Gotou
Katsufumi Tomihisa
Aya Hino
Hiroyuki Okuno
Junichi Nakai
Nobuyuki Kawakami
Mototaka Ochi
Original Assignee
Kabushiki Kaisha Kobe Seiko Sho
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Priority claimed from JP2007168298A external-priority patent/JP4170367B2/ja
Application filed by Kabushiki Kaisha Kobe Seiko Sho filed Critical Kabushiki Kaisha Kobe Seiko Sho
Priority to US12/312,907 priority Critical patent/US8786090B2/en
Priority to KR1020097011088A priority patent/KR101085271B1/ko
Priority to CN2007800442895A priority patent/CN101542696B/zh
Publication of WO2008066030A1 publication Critical patent/WO2008066030A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53219—Aluminium alloys
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/18—Metallic material, boron or silicon on other inorganic substrates
    • C23C14/185—Metallic material, boron or silicon on other inorganic substrates by cathodic sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to an A1 alloy film for display devices used for liquid crystal displays, semiconductors, optical components, and the like, a display device, and a sputtering target for display devices.
  • the present invention relates to a wiring material.
  • Liquid crystal display devices used in a variety of fields, from small mobile phones to large televisions exceeding 30 inches, are active with simple matrix type liquid crystal display devices depending on the pixel driving method. It is divided into a matrix type liquid crystal display device. Among them, an active matrix liquid crystal display device having a thin film transistor (hereinafter referred to as TFT) as a switching element is widely used because it can realize high-precision image quality and can cope with high-speed images. Yes.
  • TFT thin film transistor
  • a representative example of a TFT substrate using hydrogenated amorphous silicon as an active semiconductor layer (hereinafter sometimes referred to as an amorphous silicon TFT substrate) is not limited to this, and polysilicon is used. V, or even a TFT substrate!
  • a liquid crystal display is disposed between a TFT substrate 1, a counter substrate 2 disposed opposite the TFT substrate 1, and between the TFT substrate 1 and the counter substrate 2, and performs light modulation. And a liquid crystal layer 3 that functions as a layer.
  • the TFT substrate 1 includes a TFT 4 disposed on an insulating glass substrate la, a transparent pixel electrode 5, and a wiring portion 6 including a scanning line and a signal line.
  • the transparent pixel electrode 5 is an oxide film containing about 10% by mass of tin oxide (SnO) in indium oxide (In 2 O 3).
  • the TFT substrate 1 is driven by a driver circuit 13 and a control circuit 14 connected via a TAB tape 12.
  • the counter substrate 2 includes a common electrode 7 formed on the entire surface of the insulating glass substrate lb on the TFT substrate 1 side, a color filter 8 disposed at a position facing the transparent pixel electrode 5, and a TFT substrate. It has a light-shielding film 9 arranged at a position facing the TFT 4 on the board 1 and the wiring part 6
  • the counter substrate 2 further includes an alignment film 11 for aligning liquid crystal molecules (not shown) included in the liquid crystal layer 3 in a predetermined direction.
  • a polarizing plate 10 is disposed on the outside of the TFT substrate 1 and the counter substrate 2 (on the side opposite to the liquid crystal layer 3 side).
  • the alignment direction of liquid crystal molecules in the liquid crystal layer 3 is controlled by an electric field formed between a counter electrode (not shown) and the transparent pixel electrode 5, and light passing through the liquid crystal layer 3 is modulated.
  • a counter electrode not shown
  • the transparent pixel electrode 5 the amount of light transmitted through the counter substrate 2 is controlled and an image is displayed.
  • FIG. 2 is an enlarged view of the main part A in FIG.
  • a scanning line (gate wiring) 25 is formed on a glass substrate (not shown), and a part of the scanning line 25 is a gate electrode 26 that controls on / off of the TFT. Function as.
  • a gate insulating film (silicon nitride film) 27 is formed so as to cover the gate electrode 26.
  • a signal line (source-drain wiring) 34 is formed so as to cross the scanning line 25 via the gate insulating film 27, and a part of the signal line 34 functions as a source electrode 28 of the TFT.
  • an amorphous silicon channel film active semiconductor film, not shown
  • a signal line source-drain wiring
  • an interlayer insulating silicon nitride film protection film
  • the amorphous silicon channel film is an intrinsic layer that is not doped with P (phosphorus).
  • a transparent pixel electrode 5 formed of an O film is disposed.
  • the drain electrode 29 of the TFT is electrically connected to the transparent pixel electrode 5.
  • the TFT 4 When a gate voltage is supplied to the gate electrode 26 through the scanning line 25, the TFT 4 is turned on, and the drive voltage supplied to the signal line 34 in advance from the source electrode 28 through the drain electrode 29. And supplied to the transparent pixel electrode 5. Then, the transparent pixel electrode 5 is driven to a predetermined level.
  • the voltage is supplied, as described in FIG. 1, as a result of the potential difference between the transparent pixel electrode 5 and the counter electrode, the liquid crystal molecules contained in the liquid crystal layer 3 are aligned and light modulation is performed. .
  • a signal line (pixel electrode signal line) electrically connected to the transparent pixel electrode 5, a source-drain wiring 34 electrically connected to the source electrode 28 -drain electrode 29, and a gate
  • the scanning lines 25 that are electrically connected to the electrodes 26 are all made of pure Al or a thin film of an A1 alloy such as Al_Nd (below, for reasons such as low electrical resistivity and easy fine application). In the background art column, it is referred to as an A1-based thin film.)
  • a barrier methanole made of a refractory metal such as Mo, Cr, Ti, or W. Layers 51, 52, 53, and 54 are formed.
  • the reason for connecting the A1-based thin film to the transparent pixel electrode 5 via the rare metal layer 54 is that the connection resistance (contact resistance) increases when the A1-based thin film is directly connected to the transparent pixel electrode 5. This is because the display quality of the screen is lowered.
  • A1 which constitutes the wiring directly connected to the transparent pixel electrode, is easily oxidized and oxygen generated in the liquid crystal display film formation process or oxygen added at the time of film formation. This is because an A1 oxide insulating layer is formed at the interface.
  • ITO that constitutes the transparent pixel electrode is a conductive metal oxide, but cannot be electrically connected electrically by the A1 oxide layer generated as described above.
  • a film-forming chamber for forming a barrier metal is provided. I have to equip extra. As the cost of production increases with the mass production of liquid crystal displays, the increase in manufacturing cost and the decrease in productivity associated with the formation of the barrier metal layer cannot be neglected!
  • Patent Document 1 discloses a technique in which an indium zinc oxide (IZO) film containing about 10% by mass of zinc oxide in indium oxide is used as a material for a transparent pixel electrode.
  • IZO indium zinc oxide
  • Patent Document 2 discloses a method of modifying the surface of the drain electrode by performing plasma treatment or ion implantation on the drain electrode. However, according to this method, a process for surface treatment is added, and thus productivity is lowered.
  • Patent Document 3 discloses a first layer of pure A1 or A1 as a gate electrode, a source electrode, and a drain electrode, and a first layer containing impurities such as N, O, Si, and C in pure A1 or A1.
  • a method using two layers is disclosed. According to this method, although there is an advantage that the thin films constituting the gate electrode, the source electrode, and the drain electrode can be continuously formed using the same film formation chamber, the second layer containing the impurity described above is formed. Extra steps are added.
  • the source wall is exposed from the wall surface of the chamber due to the difference in thermal expansion coefficient between the film mixed with the impurity!
  • the drain wiring deposits often flake off as flakes. In order to prevent this phenomenon, it is necessary to frequently stop the film forming process and perform maintenance, and the productivity is significantly reduced.
  • Patent Document 4 there is a method capable of omitting the near metal layer, simplifying without increasing the number of steps, and connecting the A1 alloy film directly and securely to the transparent pixel electrode.
  • Patent Document 4 A1 alloy containing at least one selected from the group consisting of Au, Ag, Zn, Cu, Ni, Sr, Ge, Sm, and B is used as an alloy component. The above problems are solved by allowing at least a part of these alloy components to exist as precipitates or concentrated layers at the interface between the A1 alloy film and the transparent pixel electrode.
  • Patent Document 4 for example, in the case of an Al-Ni alloy, the electrical resistivity after heat treatment at 250 ° C for 30 minutes is 8 1-2 atoms ° / ( ⁇ ⁇ 3 ⁇ 8 ⁇ ⁇ « ⁇ , 8 1-4 atomic% ⁇ is 5 ⁇ 8 ⁇ -cm, A 1-6 atomic% ⁇ is 6 ⁇ 5 ⁇ 'cm, and the A1 alloy film with low electrical resistivity is used.
  • This is very useful because the power consumption of the display device can be reduced, and the time constant determined by the product of the electrical resistance and the capacitance is reduced when the electrical resistivity of the electrode portion is reduced. Even when the size is increased, it is possible to maintain a high degree of display quality, but the heat resistance temperature of the above Al-Ni alloys is generally as low as 150 to 200 C.
  • Patent Document 5 includes a thin film transistor and a transparent pixel electrode, and an A1 alloy film and a conductive layer.
  • a thin film transistor substrate is disclosed in which a conductive oxide film is directly connected without a refractory metal and a part or all of the A1 alloy component is precipitated or concentrated at the direct connection interface.
  • the A1 alloy film contains, as an alloy component, an element belonging to group ⁇ in the range of 0.1 atomic% to 6 atomic% and an element belonging to group X in the range of 0.1 atomic% to 2.0 atomic%.
  • group ⁇ is at least one element selected from the group consisting of Ni, Ag, Zn, Cu, and Ge
  • group X is Mg, Cr, Mn, Ru, Rh
  • a thin film transistor substrate that is at least one element selected from the group consisting of Pd, Ir, Pt, La, Ce, Pr, Gd, Tb, Sm, Eu, Ho, Er, Tm, Yb, Lu, and Dy. is there.
  • this thin film transistor substrate When this thin film transistor substrate is used, it is possible to omit the near metal layer, and to connect the A1 alloy film directly and reliably to the pixel electrode having the conductive oxide film force without increasing the number of steps. It is supposed to be possible. In addition, even when a low heat treatment temperature of, for example, about 100 ° C. or more and 300 ° C. or less is applied to the A1 alloy film, it is said that reduction in electrical resistivity between pixel electrodes and excellent heat resistance can be achieved. Yes. Specifically, even when heat treatment at a low temperature such as 250 ° CX for 30 minutes is adopted, the electrical resistivity of the A1 alloy thin film can achieve 7 ⁇ 'cm or less without causing defects such as hillocks. It is stated that it can be done.
  • Patent Document 6 includes, as an additive element, Ge in an amount of 0.2 to 1.5 atom%, further containing Ni in an amount of 0.2 to 2.5 atom%, and the balance being A1 for a wiring film A1. Although an alloy film is described, according to Table 1 of Patent Document 6, it is difficult to satisfy both a low electrical resistivity and a good surface state.
  • the A1 alloy film electrode wiring has been made finer (line width has been reduced). Is shifting from the widely used wet etching method (a method of performing wiring patterning by chemical etching) to a dry etching method (a method of performing wiring patterning by reactive plasma etching). .
  • a phenomenon called “side etching” occurs in which the chemical solution wraps around the underside of the resist, which is a patterning mask, and etches the hot spring side walls. It ’s difficult.
  • the dry etching method is excellent in fine processing of wiring because precise etching can be performed. By dry etching, fine wiring with a line width of 2 m or less can be formed. In addition, if all etching processes in TFT fabrication can be dry-etched, productivity can be expected to improve.
  • Patent Document 7 discloses an Al-Nd alloy thin film containing Nd in A1 in an amount of more than 0.1 atomic% to 1.0 atomic%. It is disclosed. However, this A1 alloy thin film cannot be directly connected to the transparent pixel electrode.
  • Patent Document 1 Japanese Patent Laid-Open Publication No. U-337976
  • Patent Document 2 JP-A-5-283934
  • Patent Document 3 Japanese Patent Laid-Open Publication No. U-284195
  • Patent Document 4 Japanese Patent Laid-Open No. 2004-214606
  • Patent Document 5 Japanese Unexamined Patent Publication No. 2006-261636
  • Patent Document 6 JP-A-2005-171378
  • Patent Document 7 Japanese Patent Application Laid-Open No. 2004-55842
  • the process temperature for manufacturing a display device tends to be lower.
  • source / drain electrode materials for amorphous silicon TFTs are required to have low electrical resistivity and high heat resistance, and the required specifications have been about 7 ⁇ 'cm or less in terms of electrical resistivity.
  • the temperature is about 250 ° C.
  • This heat-resistant temperature is determined by the maximum temperature that is applied to the source-drain electrode in the manufacturing process, and this maximum temperature is the formation temperature of the insulating film formed as a protective film on the electrode.
  • the protective film on the source-drain electrode can be formed at about 220 ° C.
  • the heat resistance temperature is 220 ° C level and the electrical resistivity is about 4.5 ⁇ 'cm or less.
  • the electrical resistivity is preferably sufficiently low, and preferably excellent in dry etching property. It is.
  • an A1-based wiring material that combines such a low electrical resistivity and high heat resistance and is preferably excellent in dry etching and can be directly connected to a transparent pixel electrode is disclosed. Not.
  • the A1 alloy film disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 2004-214606 has a low electrical resistivity but a low heat resistance temperature.
  • the A1 alloy film generally has a force S formed by a sputtering method, and according to this method, an alloy component added to the A1 beyond the solid solubility limit exists in a forced solid solution state.
  • the electrical resistivity of A1 alloys containing solid solution alloy elements is generally higher than pure A1.
  • the alloy component precipitates at the grain boundary as an intermetallic compound when heated, and when further heated, the recrystallization of A1 proceeds, and A1 crystal growth happenss.
  • the precipitation temperature of the intermetallic compound and the temperature of crystal growth are different forces S depending on the alloy element.
  • the A1 alloy film depends on the precipitation of the alloy component (intermetallic compound) and the crystal growth. The electrical resistivity of the liquid crystal is lowered.
  • the liquid crystal display device is representatively described.
  • the above-described problem is not limited to the liquid crystal display device, and can be commonly seen in the amorphous silicon TFT substrate.
  • the above problems are also observed when polycrystalline silicon is used in addition to amorphous silicon as the TFT semiconductor layer.
  • the A1 alloy film is also required to have excellent dry etching properties in addition to the above-mentioned characteristics.
  • An A1 alloy thin film having all these characteristics is still provided. It has not been.
  • the present invention has been made paying attention to such a situation, and the object thereof is to make it possible to omit the rare metal layer, simplify the process without increasing the number of steps, and conduct the A1 alloy film. Even when a lower heat treatment temperature is applied in a shorter time to an A1 alloy film that can be connected directly and securely to a transparent pixel electrode made of a conductive oxide film, the electrical resistivity between the transparent pixel electrodes can be reduced. It is an object of the present invention to provide a technique capable of achieving reduction and excellent heat resistance, and preferably excellent in dry etching property.
  • the A1 system that does not cause defects such as hillocks even when heat treatment at a lower temperature, such as 220 ° CX for 20 minutes, is used in a shorter time.
  • a lower temperature such as 220 ° CX for 20 minutes.
  • the A1 alloy film for a display device of the present invention that has solved the above problems is an A1 alloy film for a display device that is directly connected to a conductive oxide film on a substrate, and the A1 alloy film is , Containing 0.5 to 0.5 atomic% of Ge, and containing 0.05 to 0.45 atomic% of Gd and / or La in total. Gd and La may be contained alone in an amount of 0.05-0.45 atomic%, or in total, 0.05 to 0.45 atomic%.
  • Another display device A1 alloy film of the present invention that has solved the above problems is an A1 alloy film for display devices that is directly connected to an amorphous Si layer or a polycrystalline Si layer on a substrate.
  • the Al alloy film contains 0.05 to 0.5 atomic percent of Ge and 0.05 to 0.45 atomic percent of Gd and / or La in total. Gd and La are each independently 0.0.
  • It may be contained in an amount of 5 to 0.45% by atom, or it may be contained in a total amount of 0.05-0.45% by atom.
  • the A1 alloy film for display device described above is further adjusted to contain 0.05 to 0.5 to 35 atomic% of Ni and the total content of Ge and Ni to 0.45 atomic% or less. It is recommended that
  • a display device of the present invention that has solved the above-described problems includes the above-described A1 alloy film and a thin film transistor.
  • Another display device of the present invention that has solved the above-described problem is one in which the above-described A1 alloy film is used for a gate electrode and a scanning line of a thin film transistor and is directly connected to a conductive oxide film. .
  • Another display device of the present invention capable of solving the above-described problems is used for the source electrode and / or drain electrode and signal line of the above-described A1 alloy film force thin film transistor, and a conductive oxide film and / or It is directly connected to an amorphous Si layer or a polycrystalline Si layer.
  • a configuration in which the source electrode and / or the drain electrode and the signal line of the thin film transistor are formed of the same material as the gate electrode and the scanning line of the thin film transistor is recommended.
  • the conductive oxide film is preferably formed of a composite oxide containing at least one selected from the group consisting of indium oxide, zinc oxide, tin oxide, and titanium oxide.
  • the electrical resistivity of the A1 alloy film for display devices is preferably 4.5 ⁇ 'cm or less.
  • the sputtering target of the present invention that has solved the above-mentioned problems contains Ge in a range of 0.05 to 0.5 atomic%, and Gd and / or La in a total amount of 0.05 to 0.45 atomic%. It is something. Gd and La may be contained alone in an amount of 0.05-0.45 atomic percent, or a total of 0.05 to 0.45 atomic percent may be contained.
  • the above sputtering target is further a 0-05-0. 35 atoms 0/0 containing Ni, and, Ge It is recommended that the content of Ni and Ni be adjusted to 0.45 atomic% or less.
  • the A1 alloy film can be directly connected to the transparent pixel electrode made of a conductive oxide film without interposing a barrier metal layer, and is relatively low at about 220 ° C. Even when the heat treatment temperature is applied, an A1 alloy film for display devices in which sufficiently low electrical resistivity and excellent heat resistance are ensured, and a display device using the same can be provided.
  • the above heat treatment temperature refers to the highest heat treatment temperature in a TFT (thin film transistor) array manufacturing process, for example, and in a general display device manufacturing process, a CVD film for forming various thin films is formed. It means the heating temperature of the substrate and the temperature of the heat treatment furnace when the protective film is thermally cured.
  • the barrier metal layer 54 shown in FIG. 2 can be omitted. Further, if the A1 alloy film used in the present invention is applied to the gate electrode and its wiring material, it is possible to omit the barrier metal layers 51 and 52 shown in FIG.
  • A1 alloy film for display devices of the present invention is used, a display device having excellent productivity, low cost and high performance can be obtained.
  • FIG. 1 is an enlarged schematic cross-sectional explanatory view showing a configuration of a typical liquid crystal display to which an amorphous silicon TFT substrate is applied.
  • FIG. 2 is a schematic cross-sectional explanatory view showing a configuration of a conventional typical amorphous silicon TFT substrate.
  • FIG. 3 is a schematic cross-sectional explanatory view showing the configuration of the TFT substrate according to the first embodiment of the present invention.
  • FIG. 4 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.
  • FIG. 5 is an explanatory view showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 3.
  • FIG. 6 is an explanatory view showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 3.
  • FIG. 7 is an explanatory view showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 3.
  • FIG. 8 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.
  • FIG. 9 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.
  • FIG. 10 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.
  • FIG. 11 is an explanatory diagram showing an example of the manufacturing process of the TFT substrate shown in FIG. 3 in order.
  • FIG. 12 is a schematic cross-sectional explanatory view showing the configuration of the TFT substrate according to the second embodiment of the present invention.
  • FIG. 13 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG.
  • FIG. 14 is an explanatory diagram showing an example of the manufacturing process of the TFT substrate shown in FIG. 12 in order.
  • FIG. 15 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 12.
  • FIG. 16 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG.
  • FIG. 17 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 12.
  • FIG. 18 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 12.
  • FIG. 19 is an explanatory diagram showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 12.
  • FIG. 20 is a diagram showing a Kelvin pattern (TEG pattern) used for measurement of contact resistivity (connection resistivity) between an Al alloy film and a transparent conductive film.
  • TEG pattern Kelvin pattern
  • FIG. 21 is a view showing a contact resistivity between an A1 alloy film and a transparent conductive film.
  • FIG. 22 is a diagram showing the correlation between the heat treatment time of the A1 alloy film and the electrical resistivity.
  • FIG. 23 is a diagram showing a TEG for evaluation of Si direct contact characteristics.
  • FIG. 24 is a graph showing the drain current-gate voltage switching characteristics of a TFT.
  • FIG. 25 is a schematic view of a dry etching apparatus used in Examples.
  • FIG. 26 shows the etching time and the pure A1 film after etching in Example 6
  • FIG. 27 is a graph showing the relationship between the Ge amount in the A1 alloy film and the etching rate ratio in Example 7.
  • FIG. 28 is a graph showing the relationship between the amount of Gd / La in the A1 alloy film and the etching rate ratio in Example 7.
  • FIG. 29 is a graph showing the relationship between the amount of Ni in the A1 alloy film and the etching rate ratio in Example 7.
  • TFT Thin film transistor
  • Amorphous silicon channel film active semiconductor film
  • Signal line source-drain wiring
  • Non-doped hydrogenated amorphous silicon film (aS to H) n + type hydrogenated amorphous silicon film (n + aS to H) Chamber
  • antenna 64 high frequency power (antenna side)
  • the present inventor can directly connect to a transparent pixel electrode made of a conductive oxide film and each electrode such as a source, drain, and gate of a thin film transistor, and has a relatively low force of about 220 ° C. ! /, Low enough even when heat treatment temperature is applied! /, which has both electrical resistivity and excellent heat resistance, and preferably eagerly to provide a new wiring material with excellent dry etching properties I have been considering it.
  • the inventor further reduces the electrical resistivity in the A1-based alloy thin film even under conditions of lower temperature and shorter time than the heat treatment conditions described in the above-mentioned JP-A-2006-261636. Based on the viewpoint of further improving the heat resistance, studies have been repeated.
  • the heat treatment in the process after the formation of the A1 alloy film is performed at a relatively low temperature for a short time.
  • the contact resistance between the A1 alloy film and the transparent pixel electrode and the source “drain” gate of the thin film transistor and each electrode can be kept low.
  • the A1 alloy film to which Ge is added is compared with the A1 alloy film to which Ni, Ag, Zn, and Cu are added, which is included in the group ⁇ described in JP-A-2006-261636. There is little variation in contact resistance.
  • the present invention since a predetermined amount of Gd and / or La is contained in the A1 alloy film as a heat resistance improving element, hillocks and the like can be obtained even by heat treatment at 220 ° C to 300 ° C. Excellent heat resistance can be ensured without generating heat.
  • the Gd and / or La content and the Ni content are appropriately controlled, the dry etching property can be improved.
  • the transparent pixel electrode having both sufficiently low! /, Electrical resistivity and sufficiently high // heat resistance, and preferably excellent in dry etching property. It is possible to provide a wiring material that can be directly connected to the wiring.
  • dry etching means removal of an object to be etched (interlayer insulating film), and the purpose of cleaning the surface of the A1 alloy film even after the contact hole reaches the A1 alloy film. This also means that the surface of the A1 alloy film is exposed to an etching gas.
  • excellent in dry etching property means (a) a small amount of residue generated after etching and (i) a high etching rate ratio. . Specifically, when the above characteristics (a) and (i) were evaluated by the method described in the examples described later, (a) no residue was generated after etching, and (i) the etching rate ratio was 0. Those that satisfy 3 or more are called “excellent dry etching”. Those satisfying these characteristics are excellent in dry etching properties, so the precise control of the wiring dimensions' shape can be achieved with the force S.
  • the “etching rate ratio” is an index of the ease of etching of the A1 alloy thin film by plasma irradiation.
  • the etching rate ratio is the ratio of the etching rate of the A1 alloy film based on the etching rate of pure A1 with a good etching rate (that is, the etching rate of the A1 alloy film is Nl, When the etching rate is N2, the ratio is expressed as the ratio of N1 / N2. The higher the etching rate ratio, the shorter the dry etching processing time and the higher the productivity.
  • Ge is particularly useful for reducing the contact resistance between the A1 alloy film and the transparent pixel electrode.
  • Ge is added in the range of 0.05 to 0.5 atomic%.
  • it is 0.07 atomic% or more, More preferably, it is 0.1 atomic% or more.
  • the Ge content is 0.5
  • the reason for not more than atomic% is to prevent the electrical resistivity of the Al alloy film from becoming too high.
  • it is 0.4 atomic% or less, more preferably 0.3 atomic% or less.
  • the electrical resistivity when heat-treated at 220 ° C. for 10 minutes can be reduced to approximately 4.5 ⁇ ′cm or less.
  • the "Ge-containing precipitate” means a precipitate in which Ge is precipitated, for example, an Al-Ge-Gd alloy, an A Ge-La alloy, or an Al-Ge-Gd-La alloy.
  • Examples include Ge alone, an intermetallic compound of A1, Ge, and Gd, an intermetallic compound of A1, Ge, and La, or an intermetallic compound of A1, Ge, Gd, and La.
  • the "Ge-containing concentrated layer” means that the average concentration of Ge in the Ge concentrated layer is Al-Ge-Gd alloy, A Ge-La alloy or Al-Ge-Gd- This means that the average concentration of Ge in the La alloy is 2 times or more, preferably 2.5 times or more.
  • Ge exceeding the solid solubility limit (0.1 atomic%) of Ge in the A1 alloy film is precipitated at the grain boundary of the A1 alloy film by heat treatment or the like.
  • the Ge may be diffused and concentrated on the surface of the A1 alloy film to form a Ge-enriched layer.
  • Such a Ge enriched layer is also included in the “Ge-containing enriched layer”.
  • the Ge halogen compound remains on the surface of the A1 alloy film, where the vapor pressure is lower than that of the A1, and it is difficult to volatilize. It is in a higher concentration state than the Ge concentration of A1 alloy bulk material.
  • Such an embodiment is also included in the “Ge-containing concentrated layer”.
  • the Ge concentration of the A1 alloy thin film surface layer and the thickness of the Ge-containing concentrated layer change.
  • part of the force may be concentrated on the surface layer side.
  • Such a mode is also included in the above-mentioned “Ge-containing concentrated layer”. included.
  • the thickness of the Ge-containing concentrated layer is preferably 0.5 nm or more and 10 nm or less. More preferably, it is not less than Onm and not more than 5 nm.
  • the electrical resistivity of the Al-Ge alloy binary alloy after heat treatment at 220 ° C for 10 minutes is very low.
  • the third component is contained in the Al-Ge alloy.
  • the electrical resistivity tends to increase. Therefore, when the purpose is only to reduce the electrical resistivity, an Al_Ge alloy binary alloy may be used, but as mentioned above, the heat resistance is reduced to about 150 ° C. Therefore, for the purpose of providing a wiring material having both low electrical resistivity and high heat resistance as in the present invention, a binary alloy of Al-Ge alloy is insufficient, and will be described below.
  • the ternary alloy of Al-Ge-Gd alloy or Al-Ge-La alloy or the quaternary alloy of Al-Ge-Gd-La alloy was used.
  • the heat resistance of the A1 alloy film is significantly improved. It is possible to effectively prevent hillocks from forming on the surface of the A1 alloy film.
  • the content of Gd and La must be 0.05 atomic% or more. Preferably, it is 0.1 atomic% or more.
  • the electrical resistivity of the A1 alloy film will increase, so the upper limit of the content is 0.45 atomic%, more preferably 0.4 atomic percent. 0/0, more preferably from 0.3 atomic%.
  • These elements may be added alone or in combination of two or more. When adding two or more elements, the total content of each element only needs to satisfy the above range.
  • the upper limit of the content of Gd and / or La is preferably set to 0.35 atomic%. This is because, as shown in the examples described later, if it exceeds 0.35 atomic%, the etching rate ratio is lowered, and residues may be generated after dry etching. If only dry etching properties are considered, the upper limit of the content of Gd and / or La is better. If you want to reduce the electrical resistivity, improve the heat resistance, and improve the dry etching properties of the A1 alloy film, the Gd and / or La content should be approximately 0.1 atomic% or more. It is more preferable to make it atomic% or less.
  • the A1 alloy film and transparent pixel Electrode or A1 alloy film And the contact resistance between each electrode of the source 'drain' gate can be reduced.
  • the upper limit of the Ni content is preferably 0.35 atomic%, more preferably 0.3 atomic%. More preferably, it is 0.25 atomic%, and still more preferably 0.20 atomic%.
  • each of the ternary alloy of AH ⁇ e-Gd alloy or AH ⁇ e-La alloy or the quaternary alloy of Al-Ge-Gd-La alloy contains Ni, Ge and Ni
  • the total content of is preferably in the range of 0.;! To 0.45 atomic%.
  • the contact electrical resistance between the A1 alloy film and the transparent pixel electrode cannot be kept low, and the above-described action of Ge and Ni becomes effective. It is not demonstrated.
  • the etching rate ratio decreases when the total amount of Ge and Ni exceeds 0.6 atomic% (described later). See Examples).
  • the upper limit of the total amount of Ge and Ni is more preferably 0.35 atomic%, even more preferably 0.30 atomic% or less.
  • a liquid crystal display device including an amorphous silicon TFT substrate or a polysilicon TFT substrate will be described as a representative example, but the present invention is not limited to this, and is suitable within a range that can meet the purpose described above. It is also possible to carry out with modifications, and both of them are included in the technical scope of the present invention.
  • the A1 alloy film used in the present invention is also applied to, for example, a reflective electrode such as a reflective liquid crystal display device and a TAB (tab) connecting electrode used for signal input / output to the outside. It is confirmed by.
  • FIG. 3 is a schematic diagram illustrating a preferred embodiment of a bottom-gate TFT substrate according to the present invention.
  • the metal layers 51, 52, 54, and 53 are formed, respectively, whereas the metal layers 51, 52, and 54 can be omitted in the TFT substrate of the present embodiment. That is, according to the present embodiment, the wiring material used for the TFT source-drain electrode 29 without the barrier metal layer interposed as in the prior art can be directly connected to the transparent pixel electrode 5, thereby However, it can achieve good TFT characteristics equivalent to or better than those of conventional TFT substrates (see the examples below).
  • the wiring material used in the present invention is applied to the wiring material of the source-drain electrode and the gate electrode as in this embodiment.
  • the wiring material of the present invention is applied to a wiring material for a gate electrode, the noor metal layers 51 and 52 can be omitted. Even in these embodiments !, we are confident that we can achieve good TFT characteristics comparable to or better than conventional TFT substrates.
  • FIG. 11 has the same reference numerals as FIG.
  • a sputtering method is used to form an A1-0.2 atomic% 06_0.35 atomic% 0 (one alloy film having a thickness of about 200 nm.
  • the temperature was set to 150 ° C.
  • the gate electrode 26 and the scanning line 25 were formed (see FIG. 4), in which case the coverage of the gate insulating film 27 in FIG. It is preferable to etch the peripheral edge of the laminated thin film into a taper of about 30 ° to 40 ° so that the die is improved.
  • a gate insulating film 27 is formed with a silicon oxide film (SiOx) having a thickness of about 30 Onm by using a method such as a plasma CVD method.
  • the deposition temperature for the plasma CVD method was about 350 ° C.
  • a hydrogenated amorphous silicon film (aS to H) 55 having a thickness of about 50 nm and a silicon nitride film (SiNx) having a thickness of about 300 nm are formed on the gate insulating film 27. Is deposited.
  • a silicon nitride film (SiNx) is patterned as shown in FIG. 6 to form a channel protective film. Further, an n + type hydrogenated amorphous silicon film (n + aS to H) 56 having a thickness of about 50 nm doped with phosphorus is formed thereon, and then a hydrogenated amorphous silicon film (n aS to H) 55 and n + type hydrogenated amorphous silicon film (n + a_S to H) 56 are patterned.
  • the Mo film 53 and the thickness of about 300 nm thickness of about 50 nm are sequentially stacked.
  • the deposition temperature for sputtering was 150 ° C.
  • the source electrode 28 integrated with the signal line and the drain electrode 29 directly connected to the pixel electrode 5 are formed.
  • the n + type hydrogenated silicon silicon film (n + aS to H) 56 on the channel protective film (SiNx) is removed by dry etching.
  • a silicon nitride film 30 having a thickness of about 300 nm is formed using a plasma CVD apparatus, for example, to form a protective film.
  • the film formation temperature at this time is, for example, about 220 ° C.
  • the silicon nitride film 30 is patterned, and contact holes 32 are formed in the silicon nitride film 30 by, for example, dry etching.
  • a contact hole (not shown) is formed in a portion corresponding to the connection with TAB on the gate electrode at the end of the panel.
  • the photoresist layer 31 is stripped using, for example, an amine-based stripping solution.
  • an ITO film having a thickness of, for example, about 40 nm is formed and patterned by wet etching to form the transparent pixel electrode 5.
  • the TFT array substrate 1 is completed by patterning the ITO film for indexing.
  • the drain electrode 29 and the transparent pixel electrode 5 are in direct contact, and the gate electrode 26 and the ITO film for TAB connection are also in direct contact.
  • a composite oxide containing at least one of a force using an ITO (indium tin oxide) film, indium oxide, zinc oxide, tin oxide, and titanium oxide may be used.
  • ITO indium tin oxide
  • IZO film ⁇ - ⁇ -based conductive oxide film
  • polysilicon may be used as the active semiconductor layer instead of amorphous silicon V (see Embodiment 2 described later).
  • the liquid crystal display device shown in FIG. 1 is completed by the method described below.
  • polyimide is applied to the surface of the TFT substrate 1 manufactured as described above, and after drying, a rubbing treatment is performed to form an alignment film.
  • the counter substrate 2 forms the light shielding film 9 on a glass substrate by patterning, for example, chromium (Cr) in a matrix.
  • resin red, green and blue color filters 8 are formed in the gaps between the light shielding films 9.
  • a counter electrode is formed by disposing a transparent conductive film such as an ITO film as the common electrode 7 on the light shielding film 9 and the color filter 8. Then, for example, polyimide is applied to the uppermost layer of the counter electrode, and after drying, a rubbing process is performed to form the alignment film 11.
  • the TFT substrate 1 and the surface of the counter substrate 2 on which the alignment film 11 is formed are arranged so as to face each other, and the TFT is removed by a sealing material 16 made of resin, excluding the liquid crystal sealing port. Bond substrate 1 and 22 counter substrates. At this time, the gap between the two substrates is kept substantially constant by interposing a spacer 15 between the TFT substrate 1 and the counter substrate 2.
  • the empty cell obtained in this way is placed in a vacuum, and gradually returned to atmospheric pressure with the sealing port immersed in liquid crystal, whereby a liquid crystal material containing liquid crystal molecules is injected into the empty cell. A liquid crystal layer is formed and the sealing port is sealed. Finally, a polarizing plate 10 is attached to both sides of the empty cell to complete the liquid crystal display.
  • the driver circuit 13 for driving the liquid crystal display device is connected to the liquid crystal display. Electrically connected to the lay and placed on the side or back of the liquid crystal display. Then, the liquid crystal display is held by the holding frame 23 including the opening serving as the display surface of the liquid crystal display, the backlight 22 that forms the surface light source, the light guide plate 20, and the holding frame 23, thereby completing the liquid crystal display device.
  • FIG. 12 is a schematic cross-sectional explanatory view for explaining a preferred embodiment of a top gate type TFT substrate according to the present invention.
  • the same reference numerals as those in FIG. 2 described above showing the conventional TFT substrate are attached.
  • polysilicon is used instead of amorphous silicon as an active semiconductor layer
  • a top gate type TFT substrate is used instead of a bottom gate type
  • source-drain electrodes and gate electrodes are used.
  • A1-0. 2 atomic% 06_0.2 atomic% 0 one alloy is used in the point that the alloy is used as the wiring material of the source-drain electrode instead of the wiring material, which satisfies the requirements of the present invention.
  • the active semiconductor film is composed of a polysilicon film (poly-Si) that is not doped with phosphorus and phosphorus or arsenic. This is different from the amorphous silicon TFT substrate shown in Fig. 3 described above in that (As) is formed from a polysilicon film ( ⁇ + poly-Si) into which ions are implanted. Run through (SiOx) It is formed in so that to intersect the line.
  • the near metal layer 54 can be omitted. That is, the wiring material used for the TFT source-drain electrode 29 without the barrier metal layer interposed can be directly connected to the transparent pixel electrode 5 as in the prior art. Experiments have confirmed that good TFT characteristics equivalent to or higher than those of the substrate can be achieved.
  • the force S for omitting the rare metal layers 51 and 52 can be achieved.
  • the above alloy is applied to the wiring material of the source-drain electrode and the gate electrode, the rare metal layers 51, 52, and 54 can be omitted. Even in these cases, good TFT characteristics equivalent to or better than those of conventional TFT substrates were achieved. Be patient with what you are doing!
  • FIG. 12 An example of a method for manufacturing the polysilicon TFT substrate according to the present invention shown in FIG. 12 will be described with reference to FIGS.
  • A1-0.2 atom% 06_0.2 atom% 0 (1 alloy is used as the source-drain electrode and its wiring material.
  • the thin film transistor is made of a polysilicon film (poly-Si). This is a polysilicon TFT used as a semiconductor layer, and the same reference numerals as those in FIG.
  • heat treatment about 470 ° C for about 1 hour
  • laser annealing are performed to convert the hydrogenated amorphous silicon film (a-Si-H) to polysilicon.
  • the hydrogenated amorphous silicon film (aS to H) is irradiated with a laser having an energy of about 230 mj / cm 2 to obtain a thickness of about 0.
  • a polysilicon film (poly-Si) of about 3 mm is obtained (Fig. 13).
  • the polysilicon film (poly-Si) is patterned by plasma etching or the like.
  • a silicon oxide film (SiOx) having a thickness of about lOOnm is formed, and a gate insulating film 27 is formed.
  • the gate insulating film 27 by sputtering, etc., 8 1-2 atoms / ( ⁇ (1 alloy thin film and approximately 50 nm thick Mo thin film 52 approximately 50 nm thick) are stacked and then plasma etching is performed.
  • the gate electrode 26 integrated with the scanning line is formed.
  • a mask is formed with a photoresist 31, and, for example, phosphorus is doped with, for example, about 1 ⁇ 10 15 pieces / cm 2 at about 50 keV by using an ion implantation apparatus or the like to form a polysilicon film.
  • An n + type polysilicon film ( ⁇ + poly-Si) is formed on a part of (poly-Si).
  • the photoresist 31 is peeled off, and phosphorus is diffused by heat treatment at about 500 ° C., for example.
  • a silicon oxide film (SiOx) having a thickness of about 500 nm is formed at a substrate temperature of about 250 ° C. to form an interlayer insulating film.
  • the interlayer insulating film (SiOx) and the silicon oxide film of the gate insulating film 27 are dry-etched to form contact holes.
  • the Mo film 53 with a thickness of about 50 nm and the 0.2 atomic% 06_0.2 atomic% 0 with a thickness of about 450 nm are formed into a signal line by patterning after forming an alloy thin film.
  • An integrated source electrode 28 and drain electrode 29 are formed, and as a result, the source electrode 28 and the drain electrode 29 are contacted with the n + type polysilicon film (n + poly-Si) through the contact holes, respectively. .
  • a silicon nitride film (SiNx) having a thickness of about 500 nm is formed at a substrate temperature of about 220 ° C. by using a plasma CVD apparatus or the like to form an interlayer insulating film.
  • a photoresist layer 31 is formed on the interlayer insulating film, a silicon nitride film (SiNx) is patterned, and contact holes 32 are formed in the silicon nitride film (SiNx), for example, by dry etching.
  • the photoresist is stripped using an amin-based stripping solution in the same manner as in the first embodiment, and then An ITO film is formed and patterned by wet etching to form the pixel electrode 5.
  • the drain electrode 29 is in direct contact with the transparent pixel electrode 5. Constructing the drain electrode 29 ⁇ 0 ⁇ 2 atomic% 0 6 -0. 2 atomic% 0 (A Ge-concentrated layer is formed at the interface between the alloy thin film and the pixel electrode 5 to reduce the contact resistance. At the same time, since Ge diffuses and precipitates as a single substance, the recrystallization of A1 is promoted, and the electrical resistivity of the A1 alloy film itself is greatly reduced.
  • heat treatment is performed at about 220 ° C. for about 1 hour to complete a polysilicon TFT array substrate.
  • the same effects as those of the TFT substrate according to the first embodiment described above can be obtained.
  • the A1 alloy in the second embodiment can also be used as a reflective electrode for reflective liquid crystals.
  • the A1 alloy film of the present invention is also excellent in dry etching property. Less than, The dry etching process will be described.
  • a halo such as C1 is formed on a substrate placed in a vacuum vessel.
  • the source gas containing the source gas is turned into plasma by high-frequency power, and on the other hand, by applying another high-frequency power to the susceptor on which the substrate (etching material) is placed, ions in the plasma are drawn onto the substrate, Anisotropy by ion-assisted reaction with reactive plasma.
  • This C1 radical is adsorbed on the A1 alloy thin film, which is a highly reactive material to be etched, and generates chloride on the surface of the A1 alloy thin film. Since a high-frequency bias is applied to the substrate on which the A1 alloy thin film is formed, ions in the plasma are accelerated and incident on the surface of the A1 alloy thin film, and chloride is evaporated by this ion bombardment effect. Is exhausted out of the vacuum container!
  • the vapor pressure of the generated chloride is preferably relatively high. If the vapor pressure is high, chloride can be evaporated by the physical assistance of the surface temperature of the A1 alloy thin film and ion bombardment. On the other hand, when the vapor pressure of chloride is low, chloride remains on the surface without evaporation and etching residue (residual etching generated during dry etching) occurs.
  • the present invention is not limited to a dry etching method or an apparatus used for the dry etching process.
  • a general dry etching process can be performed using a general-purpose dry etching apparatus as shown in FIG.
  • a single (inductively coupled plasma) type dry etching apparatus shown in FIG. 25 was used.
  • a one-turn antenna 63 is placed.
  • the plasma generator shown in FIG. 25 is a so-called TCP (Transfer Coupled Plasma) in which the dielectric window 62 is a flat plate type.
  • a high frequency power 64 of 13.56 MHz is introduced into the antenna 63 through a matching unit 65.
  • a process gas inlet 66 in the chamber 61 where a halogen gas such as C1, C1, etc. An etching gas is introduced.
  • a substrate (material to be etched) 67 is placed on a susceptor 68.
  • the susceptor 68 is an electrostatic chuck 69, and can be chucked by an electrostatic force due to the electric charge flowing into the substrate from the plasma.
  • a member called a quartz glass collar 70 is placed around the susceptor 68.
  • the halogen gas introduced into the chamber 61 is turned into plasma in an excited state by a dielectric magnetic field generated by applying high frequency power to the antenna 63 on the dielectric window 62.
  • high frequency power 72 of 400 kHz is introduced into the susceptor 68 via the matching unit 71, and a high frequency bias is applied to the substrate (material to be etched) 67 placed on the susceptor 68.
  • a high frequency bias is applied to the substrate (material to be etched) 67 placed on the susceptor 68.
  • the etching gas (process gas) used in the dry etching step typically includes a mixed gas of a halogen gas, a boride of a halogen gas, and a rare gas.
  • the composition of the mixed gas is not limited to this, and for example, hydrogen bromide or carbon tetrafluoride may be further added.
  • the flow ratio of the mixed gas is not particularly limited.
  • a mixed gas of Ar, C1, and BC1 is used.
  • dry etching can be used in all steps of etching an A1 alloy thin film or Si semiconductor layer and forming contact holes, thereby improving productivity.
  • the present invention is not intended to be limited to this.
  • wet etching is performed until the bottom of the contact hole reaches the A1 alloy film, and switching to dry etching is performed at the final stage of the contact hole formation process.
  • wet etching most of the contact hole formation process, it is possible to process multiple TFT substrates at once.
  • productivity can be improved if dry etching is performed in all steps of contact hole formation.
  • the electrical resistivity of the A1 alloy film itself and the A1 alloy film are transparent pixel electrodes or non- The contact resistivity when directly connected to the crystalline Si layer or the polycrystalline Si layer was measured, and the heat resistance when the A1 alloy film was heated was examined.
  • Transparent pixel electrode configuration Indium tin oxide (ITO) with 10% by weight tin oxide added to indium oxide, or Indium zinc oxide (IZO) with 10% by weight zinc oxide added to indium oxide
  • the content of each alloy element in the various A1 alloys used in the experiments was determined by ICP emission analysis (inductively coupled plasma emission analysis).
  • the contact resistance is measured by preparing the Kelvin pattern (contact hole size: 10 ⁇ m square) shown in Fig. 20 and measuring it at 4 terminals (by applying current to ITO-A1 alloy or IZO-A1 alloy and using another terminal).
  • FIG. 21 shows the results when ITO is used as the transparent pixel electrode.
  • IZO was used instead of ITO, the same trend as in Fig. 21 was observed.
  • the Ge-added A1 alloy film has the best stability with the smallest variation in contact resistance (in Fig. 21, the contact resistivity is indicated by ⁇ , and the upper and lower sides of the ⁇ are shown below. Each bar-shaped mark on the side One bar).
  • FIG. 22 shows the correlation between the heat treatment time and the electrical resistivity of the A1 alloy film.
  • the electric resistivity of the A1 alloy film decreases smoothly when the heat treatment time is increased.
  • the amount of Gd La added is large, the electric resistivity does not decrease much.
  • the amount of Gd La added alone or in total is 0.45 atomic% or less. It is considered to be 0.4 atomic% or less, more preferably 0.3 atomic% or less.
  • the Al—Ge—Gd film and A1—Ge—La film having various compositions shown in Table 3 were heat-treated at 220 ° C., and the hillock density and electrical resistivity of the A1 alloy film were measured.
  • the hillock density was measured by counting the number of hillocks formed on the surface of the A1 alloy film after heating the sample at 220 ° C for 30 minutes instead of examining the hillock generation temperature as in Experimental Example 2. This is what is done. That is, only the A1 alloy film was formed on the glass substrate under the conditions described in (2) above.
  • the contact resistivity and Si direct contact characteristics of various A1-Ge-X films and ITO films shown in Table 4 were measured.
  • the method shown in Experimental Example 1 was used to measure the contact resistivity with the ITO film.
  • 2. 00 X 10- 4 ⁇ - cm 2 or less of a low contact resistivity is obtained.
  • Ni and Cu of sample numbers 10, 11, 14, and 15 are added in combination with Ge, the effect of reducing the contact resistivity is particularly great.
  • Si direct contact characteristics ON current and OFF current of evaluation TEG described later.
  • L is 10 ⁇ m and gate width W is 10 ⁇ m.
  • the prepared TEG for evaluation was subjected to heat treatment at 300 ° C for 30 minutes.
  • a heating process is started after the formation of the A1 alloy film, and when the interdiffusion and interfacial reaction between the Si layer and the A1 alloy film proceed, the on-current decreases and / or the off-current increases. It is because it will produce.
  • the off current is the current value when the gate voltage is -3V, and the on current is 20
  • the A1 alloy film of the present invention has a high etching rate ratio comparable to that of pure A1.
  • A1-0. 2 atomic% 0 6 _0.10 atomic% 0 (1 was used.
  • A1 ⁇ 2. 0 atomic% ⁇ was used.
  • a non-alkali glass substrate having a diameter of 6 inches and a thickness of 0.5 mm manufactured by Cowing Co., Ltd.
  • a silicon oxide (SiOx) film with a thickness of 200 nm is deposited at a substrate temperature of about 250 ° C, and then the pure A1 film or A1 alloy film is formed under the conditions described in (2) above. Filmed .
  • a positive photoresist nopolac resin; TSMR8900 manufactured by Tokyo Ohka Kogyo Co., Ltd., thickness 1 ⁇ O ⁇ m
  • TSMR8900 manufactured by Tokyo Ohka Kogyo Co., Ltd., thickness 1 ⁇ O ⁇ m
  • Substrate temperature Susceptor temperature (20 ° C)
  • Etching was performed by changing the etching time in the range where the etching depth was 100 to 300 nm, and samples with different etching depths were produced.
  • etching time in the range where the etching depth was 100 to 300 nm, and samples with different etching depths were produced.
  • Etching was performed in the same manner as in Example 6, and the thickness (etching thickness) of the pure A1 film and each A1 alloy film after the etching was measured. These results are statistically processed by the least squares method to calculate the etching rate of pure A1 film (N2) and the etching rate of A1 alloy film (N1), respectively. " In this example, an etching rate ratio of 0.3 or higher was determined to be acceptable ( ⁇ ).
  • an etching rate ratio that passed and no residue after dry etching was determined to be “excellent in dry etching”.
  • Table 5 provides a column for comprehensive evaluation, where “O” is marked for those satisfying both of the above characteristics, and “X” is marked for those with V or one of the characteristics rejected (X).
  • Fig. 27 shows the relationship between the Ge amount in the A1 alloy film and the etching rate ratio
  • Fig. 28 shows the relationship between the Gd amount and La amount in the A1 alloy film, and the etching rate ratio
  • Fig. 29 shows the A1 alloy film. The relationship between the amount of Ni in the steel and the etching rate ratio is shown below.
  • the etching rate ratio is approximately 0.6, which is substantially constant.
  • the etching rate ratio is approximately 0.6, which is substantially constant.
  • the etching rate ratio increases as the content of Gd or La decreases.
  • the upper limit of the total amount of Gd and / or La needs to be 0.35 atomic%, and the upper limit is 0.4 atomic%. As a result, desired characteristics could not be obtained.
  • Ni also showed the same tendency as Gd / La described above, and as shown in FIG. 29, the etching rate ratio increased as the Ni content decreased.
  • the upper limit of the Ni amount needs to be 0.3 atomic%, and when the upper limit is 0.4 atomic%, desired characteristics are obtained. Was not obtained.
  • the A1 alloy film can be directly connected to the transparent pixel electrode made of a conductive oxide film without interposing a barrier metal layer, and a relatively low heat treatment temperature of about 220 ° C.
  • A1 alloy film for display devices that can secure a sufficiently low electrical resistivity and excellent heat resistance even when applying the above, and a display device using the same can be provided.

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Abstract

L'invention concerne un film d'alliage d'Al pour des dispositifs d'affichage, qui est directement relié à un fil d'oxyde conducteur sur un substrat. Ce film d'alliage d'Al pour des dispositifs d'affichage contient 0,05-0,5 % atomique de Ge et 0,05-0,45 % atomique de Gd et/ou La au total. L'invention concerne également un dispositif d'affichage utilisant un tel film d'alliage d'Al, et une cible de pulvérisation cathodique pour des dispositifs d'affichage. Le film d'alliage d'Al pour des dispositifs d'affichage présente une haute adhésion à un film d'oxyde conducteur et une faible résistivité de contact même lorsque le film d'alliage d'Al est directement relié au film d'oxyde conducteur sans utiliser un métal de barrière. De préférence, le film d'alliage d'Al pour des dispositifs d'affichage a d'excellentes propriétés de gravure à sec.
PCT/JP2007/072832 2006-11-30 2007-11-27 Film d'alliage d'al pour un dispositf d'affichage, dispositf d'affichage, et cible de pulvérisation cathodique WO2008066030A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/312,907 US8786090B2 (en) 2006-11-30 2007-11-27 Al alloy film for display device, display device, and sputtering target
KR1020097011088A KR101085271B1 (ko) 2006-11-30 2007-11-27 표시 디바이스용 Ａｌ 합금막, 표시 디바이스 및 스퍼터링 타깃
CN2007800442895A CN101542696B (zh) 2006-11-30 2007-11-27 显示装置用Al合金膜、显示装置以及溅射靶材

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2006324494 2006-11-30
JP2006-324494 2006-11-30
JP2007-168298 2007-06-26
JP2007168298A JP4170367B2 (ja) 2006-11-30 2007-06-26 表示デバイス用Ａｌ合金膜、表示デバイス、及びスパッタリングターゲット

Publications (1)

Publication Number Publication Date
WO2008066030A1 true WO2008066030A1 (fr) 2008-06-05

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Application Number Title Priority Date Filing Date
PCT/JP2007/072832 WO2008066030A1 (fr) 2006-11-30 2007-11-27 Film d'alliage d'al pour un dispositf d'affichage, dispositf d'affichage, et cible de pulvérisation cathodique

Country Status (1)

Country Link
WO (1) WO2008066030A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090224256A1 (en) * 2008-03-05 2009-09-10 Hyun-Eok Shin Organic light emitting display
US20110248272A1 (en) * 2008-11-10 2011-10-13 Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd) Organic el display device reflective anode and method for manufacturing the same
CN102473730A (zh) * 2009-07-27 2012-05-23 株式会社神户制钢所 布线构造及其制造方法、以及具备布线构造的显示装置
CN113529018A (zh) * 2020-04-16 2021-10-22 株式会社神户制钢所 Al合金蒸镀膜、显示器用配线膜、显示器装置及溅射靶材

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997013885A1 (fr) * 1995-10-12 1997-04-17 Kabushiki Kaisha Toshiba Film de cablage, cible de pulverisation par bombardement ionique destinee a la formation de ce film et composant electronique comportant ce film
JPH09186238A (ja) * 1995-12-29 1997-07-15 Internatl Business Mach Corp <Ibm> 導電構造およびその形成

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997013885A1 (fr) * 1995-10-12 1997-04-17 Kabushiki Kaisha Toshiba Film de cablage, cible de pulverisation par bombardement ionique destinee a la formation de ce film et composant electronique comportant ce film
JPH09186238A (ja) * 1995-12-29 1997-07-15 Internatl Business Mach Corp <Ibm> 導電構造およびその形成

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090224256A1 (en) * 2008-03-05 2009-09-10 Hyun-Eok Shin Organic light emitting display
US8227845B2 (en) * 2008-03-05 2012-07-24 Samsung Mobile Display Co., Ltd. Organic light emitting display
US20110248272A1 (en) * 2008-11-10 2011-10-13 Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd) Organic el display device reflective anode and method for manufacturing the same
CN102473730A (zh) * 2009-07-27 2012-05-23 株式会社神户制钢所 布线构造及其制造方法、以及具备布线构造的显示装置
CN102473730B (zh) * 2009-07-27 2015-09-16 株式会社神户制钢所 布线构造及其制造方法、以及具备布线构造的显示装置
CN113529018A (zh) * 2020-04-16 2021-10-22 株式会社神户制钢所 Al合金蒸镀膜、显示器用配线膜、显示器装置及溅射靶材
CN113529018B (zh) * 2020-04-16 2023-07-28 株式会社神户制钢所 Al合金蒸镀膜、显示器用配线膜及显示器装置

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