WO2008066030A1 - Al ALLOY FILM FOR DISPLAY DEVICE, DISPLAY DEVICE, AND SPUTTERING TARGET - Google Patents
Al ALLOY FILM FOR DISPLAY DEVICE, DISPLAY DEVICE, AND SPUTTERING TARGET Download PDFInfo
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- WO2008066030A1 WO2008066030A1 PCT/JP2007/072832 JP2007072832W WO2008066030A1 WO 2008066030 A1 WO2008066030 A1 WO 2008066030A1 JP 2007072832 W JP2007072832 W JP 2007072832W WO 2008066030 A1 WO2008066030 A1 WO 2008066030A1
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- Prior art keywords
- film
- alloy
- alloy film
- atomic
- display device
- Prior art date
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- 229910000838 Al alloy Inorganic materials 0.000 title claims abstract description 11
- 238000005477 sputtering target Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 118
- 238000001312 dry etching Methods 0.000 claims abstract description 57
- 239000010408 film Substances 0.000 claims description 291
- 229910045601 alloy Inorganic materials 0.000 claims description 185
- 239000000956 alloy Substances 0.000 claims description 185
- 239000010409 thin film Substances 0.000 claims description 48
- 239000000463 material Substances 0.000 claims description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 34
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 33
- 229910052759 nickel Inorganic materials 0.000 claims description 17
- 229910052732 germanium Inorganic materials 0.000 claims description 13
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 10
- 229910003437 indium oxide Inorganic materials 0.000 claims description 7
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 7
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 5
- 229910001887 tin oxide Inorganic materials 0.000 claims description 5
- 239000011787 zinc oxide Substances 0.000 claims description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 20
- 239000002184 metal Substances 0.000 abstract description 20
- 230000004888 barrier function Effects 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 72
- 238000005530 etching Methods 0.000 description 71
- 238000000034 method Methods 0.000 description 55
- 239000004973 liquid crystal related substance Substances 0.000 description 46
- 238000010438 heat treatment Methods 0.000 description 34
- 238000004519 manufacturing process Methods 0.000 description 28
- 230000008569 process Effects 0.000 description 27
- 239000007789 gas Substances 0.000 description 22
- 229920005591 polysilicon Polymers 0.000 description 19
- 229910052688 Gadolinium Inorganic materials 0.000 description 15
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 230000000694 effects Effects 0.000 description 14
- 229910052746 lanthanum Inorganic materials 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- 125000004429 atom Chemical group 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 13
- 229910052814 silicon oxide Inorganic materials 0.000 description 13
- 229910000858 La alloy Inorganic materials 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 12
- 239000011521 glass Substances 0.000 description 11
- 239000013078 crystal Substances 0.000 description 9
- 229910000765 intermetallic Inorganic materials 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 230000001681 protective effect Effects 0.000 description 9
- 229910004205 SiNX Inorganic materials 0.000 description 8
- 238000000059 patterning Methods 0.000 description 8
- 239000002244 precipitate Substances 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 8
- 229910000748 Gd alloy Inorganic materials 0.000 description 7
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 7
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 230000007423 decrease Effects 0.000 description 6
- 238000002474 experimental method Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 239000011701 zinc Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000011156 evaluation Methods 0.000 description 5
- 230000006872 improvement Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 238000001556 precipitation Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910002056 binary alloy Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 229910052736 halogen Inorganic materials 0.000 description 4
- 150000002367 halogens Chemical class 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910002059 quaternary alloy Inorganic materials 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 229910002058 ternary alloy Inorganic materials 0.000 description 4
- 229910052725 zinc Inorganic materials 0.000 description 4
- 229910018459 Al—Ge Inorganic materials 0.000 description 3
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- 239000000654 additive Substances 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910018507 Al—Ni Inorganic materials 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052692 Dysprosium Inorganic materials 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- 229910000583 Nd alloy Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 239000006104 solid solution Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910052720 vanadium Inorganic materials 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910052693 Europium Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 229910052689 Holmium Inorganic materials 0.000 description 1
- -1 L a Inorganic materials 0.000 description 1
- 229910020794 La-Ni Inorganic materials 0.000 description 1
- 229910052765 Lutetium Inorganic materials 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910052777 Praseodymium Inorganic materials 0.000 description 1
- 229910052772 Samarium Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 229910052771 Terbium Inorganic materials 0.000 description 1
- 229910052775 Thulium Inorganic materials 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000006356 dehydrogenation reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000005281 excited state Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002366 halogen compounds Chemical class 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010406 interfacial reaction Methods 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical class [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53219—Aluminium alloys
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/18—Metallic material, boron or silicon on other inorganic substrates
- C23C14/185—Metallic material, boron or silicon on other inorganic substrates by cathodic sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/441—Interconnections, e.g. scanning lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to an A1 alloy film for display devices used for liquid crystal displays, semiconductors, optical components, and the like, a display device, and a sputtering target for display devices.
- the present invention relates to a wiring material.
- Liquid crystal display devices used in a variety of fields, from small mobile phones to large televisions exceeding 30 inches, are active with simple matrix type liquid crystal display devices depending on the pixel driving method. It is divided into a matrix type liquid crystal display device. Among them, an active matrix liquid crystal display device having a thin film transistor (hereinafter referred to as TFT) as a switching element is widely used because it can realize high-precision image quality and can cope with high-speed images. Yes.
- TFT thin film transistor
- a representative example of a TFT substrate using hydrogenated amorphous silicon as an active semiconductor layer (hereinafter sometimes referred to as an amorphous silicon TFT substrate) is not limited to this, and polysilicon is used. V, or even a TFT substrate!
- a liquid crystal display is disposed between a TFT substrate 1, a counter substrate 2 disposed opposite the TFT substrate 1, and between the TFT substrate 1 and the counter substrate 2, and performs light modulation. And a liquid crystal layer 3 that functions as a layer.
- the TFT substrate 1 includes a TFT 4 disposed on an insulating glass substrate la, a transparent pixel electrode 5, and a wiring portion 6 including a scanning line and a signal line.
- the transparent pixel electrode 5 is an oxide film containing about 10% by mass of tin oxide (SnO) in indium oxide (In 2 O 3).
- the TFT substrate 1 is driven by a driver circuit 13 and a control circuit 14 connected via a TAB tape 12.
- the counter substrate 2 includes a common electrode 7 formed on the entire surface of the insulating glass substrate lb on the TFT substrate 1 side, a color filter 8 disposed at a position facing the transparent pixel electrode 5, and a TFT substrate. It has a light-shielding film 9 arranged at a position facing the TFT 4 on the board 1 and the wiring part 6
- the counter substrate 2 further includes an alignment film 11 for aligning liquid crystal molecules (not shown) included in the liquid crystal layer 3 in a predetermined direction.
- a polarizing plate 10 is disposed on the outside of the TFT substrate 1 and the counter substrate 2 (on the side opposite to the liquid crystal layer 3 side).
- the alignment direction of liquid crystal molecules in the liquid crystal layer 3 is controlled by an electric field formed between a counter electrode (not shown) and the transparent pixel electrode 5, and light passing through the liquid crystal layer 3 is modulated.
- a counter electrode not shown
- the transparent pixel electrode 5 the amount of light transmitted through the counter substrate 2 is controlled and an image is displayed.
- FIG. 2 is an enlarged view of the main part A in FIG.
- a scanning line (gate wiring) 25 is formed on a glass substrate (not shown), and a part of the scanning line 25 is a gate electrode 26 that controls on / off of the TFT. Function as.
- a gate insulating film (silicon nitride film) 27 is formed so as to cover the gate electrode 26.
- a signal line (source-drain wiring) 34 is formed so as to cross the scanning line 25 via the gate insulating film 27, and a part of the signal line 34 functions as a source electrode 28 of the TFT.
- an amorphous silicon channel film active semiconductor film, not shown
- a signal line source-drain wiring
- an interlayer insulating silicon nitride film protection film
- the amorphous silicon channel film is an intrinsic layer that is not doped with P (phosphorus).
- a transparent pixel electrode 5 formed of an O film is disposed.
- the drain electrode 29 of the TFT is electrically connected to the transparent pixel electrode 5.
- the TFT 4 When a gate voltage is supplied to the gate electrode 26 through the scanning line 25, the TFT 4 is turned on, and the drive voltage supplied to the signal line 34 in advance from the source electrode 28 through the drain electrode 29. And supplied to the transparent pixel electrode 5. Then, the transparent pixel electrode 5 is driven to a predetermined level.
- the voltage is supplied, as described in FIG. 1, as a result of the potential difference between the transparent pixel electrode 5 and the counter electrode, the liquid crystal molecules contained in the liquid crystal layer 3 are aligned and light modulation is performed. .
- a signal line (pixel electrode signal line) electrically connected to the transparent pixel electrode 5, a source-drain wiring 34 electrically connected to the source electrode 28 -drain electrode 29, and a gate
- the scanning lines 25 that are electrically connected to the electrodes 26 are all made of pure Al or a thin film of an A1 alloy such as Al_Nd (below, for reasons such as low electrical resistivity and easy fine application). In the background art column, it is referred to as an A1-based thin film.)
- a barrier methanole made of a refractory metal such as Mo, Cr, Ti, or W. Layers 51, 52, 53, and 54 are formed.
- the reason for connecting the A1-based thin film to the transparent pixel electrode 5 via the rare metal layer 54 is that the connection resistance (contact resistance) increases when the A1-based thin film is directly connected to the transparent pixel electrode 5. This is because the display quality of the screen is lowered.
- A1 which constitutes the wiring directly connected to the transparent pixel electrode, is easily oxidized and oxygen generated in the liquid crystal display film formation process or oxygen added at the time of film formation. This is because an A1 oxide insulating layer is formed at the interface.
- ITO that constitutes the transparent pixel electrode is a conductive metal oxide, but cannot be electrically connected electrically by the A1 oxide layer generated as described above.
- a film-forming chamber for forming a barrier metal is provided. I have to equip extra. As the cost of production increases with the mass production of liquid crystal displays, the increase in manufacturing cost and the decrease in productivity associated with the formation of the barrier metal layer cannot be neglected!
- Patent Document 1 discloses a technique in which an indium zinc oxide (IZO) film containing about 10% by mass of zinc oxide in indium oxide is used as a material for a transparent pixel electrode.
- IZO indium zinc oxide
- Patent Document 2 discloses a method of modifying the surface of the drain electrode by performing plasma treatment or ion implantation on the drain electrode. However, according to this method, a process for surface treatment is added, and thus productivity is lowered.
- Patent Document 3 discloses a first layer of pure A1 or A1 as a gate electrode, a source electrode, and a drain electrode, and a first layer containing impurities such as N, O, Si, and C in pure A1 or A1.
- a method using two layers is disclosed. According to this method, although there is an advantage that the thin films constituting the gate electrode, the source electrode, and the drain electrode can be continuously formed using the same film formation chamber, the second layer containing the impurity described above is formed. Extra steps are added.
- the source wall is exposed from the wall surface of the chamber due to the difference in thermal expansion coefficient between the film mixed with the impurity!
- the drain wiring deposits often flake off as flakes. In order to prevent this phenomenon, it is necessary to frequently stop the film forming process and perform maintenance, and the productivity is significantly reduced.
- Patent Document 4 there is a method capable of omitting the near metal layer, simplifying without increasing the number of steps, and connecting the A1 alloy film directly and securely to the transparent pixel electrode.
- Patent Document 4 A1 alloy containing at least one selected from the group consisting of Au, Ag, Zn, Cu, Ni, Sr, Ge, Sm, and B is used as an alloy component. The above problems are solved by allowing at least a part of these alloy components to exist as precipitates or concentrated layers at the interface between the A1 alloy film and the transparent pixel electrode.
- Patent Document 4 for example, in the case of an Al-Ni alloy, the electrical resistivity after heat treatment at 250 ° C for 30 minutes is 8 1-2 atoms ° / ( ⁇ ⁇ 3 ⁇ 8 ⁇ ⁇ « ⁇ , 8 1-4 atomic% ⁇ is 5 ⁇ 8 ⁇ -cm, A 1-6 atomic% ⁇ is 6 ⁇ 5 ⁇ 'cm, and the A1 alloy film with low electrical resistivity is used.
- This is very useful because the power consumption of the display device can be reduced, and the time constant determined by the product of the electrical resistance and the capacitance is reduced when the electrical resistivity of the electrode portion is reduced. Even when the size is increased, it is possible to maintain a high degree of display quality, but the heat resistance temperature of the above Al-Ni alloys is generally as low as 150 to 200 C.
- Patent Document 5 includes a thin film transistor and a transparent pixel electrode, and an A1 alloy film and a conductive layer.
- a thin film transistor substrate is disclosed in which a conductive oxide film is directly connected without a refractory metal and a part or all of the A1 alloy component is precipitated or concentrated at the direct connection interface.
- the A1 alloy film contains, as an alloy component, an element belonging to group ⁇ in the range of 0.1 atomic% to 6 atomic% and an element belonging to group X in the range of 0.1 atomic% to 2.0 atomic%.
- group ⁇ is at least one element selected from the group consisting of Ni, Ag, Zn, Cu, and Ge
- group X is Mg, Cr, Mn, Ru, Rh
- a thin film transistor substrate that is at least one element selected from the group consisting of Pd, Ir, Pt, La, Ce, Pr, Gd, Tb, Sm, Eu, Ho, Er, Tm, Yb, Lu, and Dy. is there.
- this thin film transistor substrate When this thin film transistor substrate is used, it is possible to omit the near metal layer, and to connect the A1 alloy film directly and reliably to the pixel electrode having the conductive oxide film force without increasing the number of steps. It is supposed to be possible. In addition, even when a low heat treatment temperature of, for example, about 100 ° C. or more and 300 ° C. or less is applied to the A1 alloy film, it is said that reduction in electrical resistivity between pixel electrodes and excellent heat resistance can be achieved. Yes. Specifically, even when heat treatment at a low temperature such as 250 ° CX for 30 minutes is adopted, the electrical resistivity of the A1 alloy thin film can achieve 7 ⁇ 'cm or less without causing defects such as hillocks. It is stated that it can be done.
- Patent Document 6 includes, as an additive element, Ge in an amount of 0.2 to 1.5 atom%, further containing Ni in an amount of 0.2 to 2.5 atom%, and the balance being A1 for a wiring film A1. Although an alloy film is described, according to Table 1 of Patent Document 6, it is difficult to satisfy both a low electrical resistivity and a good surface state.
- the A1 alloy film electrode wiring has been made finer (line width has been reduced). Is shifting from the widely used wet etching method (a method of performing wiring patterning by chemical etching) to a dry etching method (a method of performing wiring patterning by reactive plasma etching). .
- a phenomenon called “side etching” occurs in which the chemical solution wraps around the underside of the resist, which is a patterning mask, and etches the hot spring side walls. It ’s difficult.
- the dry etching method is excellent in fine processing of wiring because precise etching can be performed. By dry etching, fine wiring with a line width of 2 m or less can be formed. In addition, if all etching processes in TFT fabrication can be dry-etched, productivity can be expected to improve.
- Patent Document 7 discloses an Al-Nd alloy thin film containing Nd in A1 in an amount of more than 0.1 atomic% to 1.0 atomic%. It is disclosed. However, this A1 alloy thin film cannot be directly connected to the transparent pixel electrode.
- Patent Document 1 Japanese Patent Laid-Open Publication No. U-337976
- Patent Document 2 JP-A-5-283934
- Patent Document 3 Japanese Patent Laid-Open Publication No. U-284195
- Patent Document 4 Japanese Patent Laid-Open No. 2004-214606
- Patent Document 5 Japanese Unexamined Patent Publication No. 2006-261636
- Patent Document 6 JP-A-2005-171378
- Patent Document 7 Japanese Patent Application Laid-Open No. 2004-55842
- the process temperature for manufacturing a display device tends to be lower.
- source / drain electrode materials for amorphous silicon TFTs are required to have low electrical resistivity and high heat resistance, and the required specifications have been about 7 ⁇ 'cm or less in terms of electrical resistivity.
- the temperature is about 250 ° C.
- This heat-resistant temperature is determined by the maximum temperature that is applied to the source-drain electrode in the manufacturing process, and this maximum temperature is the formation temperature of the insulating film formed as a protective film on the electrode.
- the protective film on the source-drain electrode can be formed at about 220 ° C.
- the heat resistance temperature is 220 ° C level and the electrical resistivity is about 4.5 ⁇ 'cm or less.
- the electrical resistivity is preferably sufficiently low, and preferably excellent in dry etching property. It is.
- an A1-based wiring material that combines such a low electrical resistivity and high heat resistance and is preferably excellent in dry etching and can be directly connected to a transparent pixel electrode is disclosed. Not.
- the A1 alloy film disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 2004-214606 has a low electrical resistivity but a low heat resistance temperature.
- the A1 alloy film generally has a force S formed by a sputtering method, and according to this method, an alloy component added to the A1 beyond the solid solubility limit exists in a forced solid solution state.
- the electrical resistivity of A1 alloys containing solid solution alloy elements is generally higher than pure A1.
- the alloy component precipitates at the grain boundary as an intermetallic compound when heated, and when further heated, the recrystallization of A1 proceeds, and A1 crystal growth happenss.
- the precipitation temperature of the intermetallic compound and the temperature of crystal growth are different forces S depending on the alloy element.
- the A1 alloy film depends on the precipitation of the alloy component (intermetallic compound) and the crystal growth. The electrical resistivity of the liquid crystal is lowered.
- the liquid crystal display device is representatively described.
- the above-described problem is not limited to the liquid crystal display device, and can be commonly seen in the amorphous silicon TFT substrate.
- the above problems are also observed when polycrystalline silicon is used in addition to amorphous silicon as the TFT semiconductor layer.
- the A1 alloy film is also required to have excellent dry etching properties in addition to the above-mentioned characteristics.
- An A1 alloy thin film having all these characteristics is still provided. It has not been.
- the present invention has been made paying attention to such a situation, and the object thereof is to make it possible to omit the rare metal layer, simplify the process without increasing the number of steps, and conduct the A1 alloy film. Even when a lower heat treatment temperature is applied in a shorter time to an A1 alloy film that can be connected directly and securely to a transparent pixel electrode made of a conductive oxide film, the electrical resistivity between the transparent pixel electrodes can be reduced. It is an object of the present invention to provide a technique capable of achieving reduction and excellent heat resistance, and preferably excellent in dry etching property.
- the A1 system that does not cause defects such as hillocks even when heat treatment at a lower temperature, such as 220 ° CX for 20 minutes, is used in a shorter time.
- a lower temperature such as 220 ° CX for 20 minutes.
- the A1 alloy film for a display device of the present invention that has solved the above problems is an A1 alloy film for a display device that is directly connected to a conductive oxide film on a substrate, and the A1 alloy film is , Containing 0.5 to 0.5 atomic% of Ge, and containing 0.05 to 0.45 atomic% of Gd and / or La in total. Gd and La may be contained alone in an amount of 0.05-0.45 atomic%, or in total, 0.05 to 0.45 atomic%.
- Another display device A1 alloy film of the present invention that has solved the above problems is an A1 alloy film for display devices that is directly connected to an amorphous Si layer or a polycrystalline Si layer on a substrate.
- the Al alloy film contains 0.05 to 0.5 atomic percent of Ge and 0.05 to 0.45 atomic percent of Gd and / or La in total. Gd and La are each independently 0.0.
- It may be contained in an amount of 5 to 0.45% by atom, or it may be contained in a total amount of 0.05-0.45% by atom.
- the A1 alloy film for display device described above is further adjusted to contain 0.05 to 0.5 to 35 atomic% of Ni and the total content of Ge and Ni to 0.45 atomic% or less. It is recommended that
- a display device of the present invention that has solved the above-described problems includes the above-described A1 alloy film and a thin film transistor.
- Another display device of the present invention that has solved the above-described problem is one in which the above-described A1 alloy film is used for a gate electrode and a scanning line of a thin film transistor and is directly connected to a conductive oxide film. .
- Another display device of the present invention capable of solving the above-described problems is used for the source electrode and / or drain electrode and signal line of the above-described A1 alloy film force thin film transistor, and a conductive oxide film and / or It is directly connected to an amorphous Si layer or a polycrystalline Si layer.
- a configuration in which the source electrode and / or the drain electrode and the signal line of the thin film transistor are formed of the same material as the gate electrode and the scanning line of the thin film transistor is recommended.
- the conductive oxide film is preferably formed of a composite oxide containing at least one selected from the group consisting of indium oxide, zinc oxide, tin oxide, and titanium oxide.
- the electrical resistivity of the A1 alloy film for display devices is preferably 4.5 ⁇ 'cm or less.
- the sputtering target of the present invention that has solved the above-mentioned problems contains Ge in a range of 0.05 to 0.5 atomic%, and Gd and / or La in a total amount of 0.05 to 0.45 atomic%. It is something. Gd and La may be contained alone in an amount of 0.05-0.45 atomic percent, or a total of 0.05 to 0.45 atomic percent may be contained.
- the above sputtering target is further a 0-05-0. 35 atoms 0/0 containing Ni, and, Ge It is recommended that the content of Ni and Ni be adjusted to 0.45 atomic% or less.
- the A1 alloy film can be directly connected to the transparent pixel electrode made of a conductive oxide film without interposing a barrier metal layer, and is relatively low at about 220 ° C. Even when the heat treatment temperature is applied, an A1 alloy film for display devices in which sufficiently low electrical resistivity and excellent heat resistance are ensured, and a display device using the same can be provided.
- the above heat treatment temperature refers to the highest heat treatment temperature in a TFT (thin film transistor) array manufacturing process, for example, and in a general display device manufacturing process, a CVD film for forming various thin films is formed. It means the heating temperature of the substrate and the temperature of the heat treatment furnace when the protective film is thermally cured.
- the barrier metal layer 54 shown in FIG. 2 can be omitted. Further, if the A1 alloy film used in the present invention is applied to the gate electrode and its wiring material, it is possible to omit the barrier metal layers 51 and 52 shown in FIG.
- A1 alloy film for display devices of the present invention is used, a display device having excellent productivity, low cost and high performance can be obtained.
- FIG. 1 is an enlarged schematic cross-sectional explanatory view showing a configuration of a typical liquid crystal display to which an amorphous silicon TFT substrate is applied.
- FIG. 2 is a schematic cross-sectional explanatory view showing a configuration of a conventional typical amorphous silicon TFT substrate.
- FIG. 3 is a schematic cross-sectional explanatory view showing the configuration of the TFT substrate according to the first embodiment of the present invention.
- FIG. 4 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.
- FIG. 5 is an explanatory view showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 3.
- FIG. 6 is an explanatory view showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 3.
- FIG. 7 is an explanatory view showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 3.
- FIG. 8 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.
- FIG. 9 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.
- FIG. 10 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.
- FIG. 11 is an explanatory diagram showing an example of the manufacturing process of the TFT substrate shown in FIG. 3 in order.
- FIG. 12 is a schematic cross-sectional explanatory view showing the configuration of the TFT substrate according to the second embodiment of the present invention.
- FIG. 13 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG.
- FIG. 14 is an explanatory diagram showing an example of the manufacturing process of the TFT substrate shown in FIG. 12 in order.
- FIG. 15 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 12.
- FIG. 16 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG.
- FIG. 17 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 12.
- FIG. 18 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 12.
- FIG. 19 is an explanatory diagram showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 12.
- FIG. 20 is a diagram showing a Kelvin pattern (TEG pattern) used for measurement of contact resistivity (connection resistivity) between an Al alloy film and a transparent conductive film.
- TEG pattern Kelvin pattern
- FIG. 21 is a view showing a contact resistivity between an A1 alloy film and a transparent conductive film.
- FIG. 22 is a diagram showing the correlation between the heat treatment time of the A1 alloy film and the electrical resistivity.
- FIG. 23 is a diagram showing a TEG for evaluation of Si direct contact characteristics.
- FIG. 24 is a graph showing the drain current-gate voltage switching characteristics of a TFT.
- FIG. 25 is a schematic view of a dry etching apparatus used in Examples.
- FIG. 26 shows the etching time and the pure A1 film after etching in Example 6
- FIG. 27 is a graph showing the relationship between the Ge amount in the A1 alloy film and the etching rate ratio in Example 7.
- FIG. 28 is a graph showing the relationship between the amount of Gd / La in the A1 alloy film and the etching rate ratio in Example 7.
- FIG. 29 is a graph showing the relationship between the amount of Ni in the A1 alloy film and the etching rate ratio in Example 7.
- TFT Thin film transistor
- Amorphous silicon channel film active semiconductor film
- Signal line source-drain wiring
- Non-doped hydrogenated amorphous silicon film (aS to H) n + type hydrogenated amorphous silicon film (n + aS to H) Chamber
- antenna 64 high frequency power (antenna side)
- the present inventor can directly connect to a transparent pixel electrode made of a conductive oxide film and each electrode such as a source, drain, and gate of a thin film transistor, and has a relatively low force of about 220 ° C. ! /, Low enough even when heat treatment temperature is applied! /, which has both electrical resistivity and excellent heat resistance, and preferably eagerly to provide a new wiring material with excellent dry etching properties I have been considering it.
- the inventor further reduces the electrical resistivity in the A1-based alloy thin film even under conditions of lower temperature and shorter time than the heat treatment conditions described in the above-mentioned JP-A-2006-261636. Based on the viewpoint of further improving the heat resistance, studies have been repeated.
- the heat treatment in the process after the formation of the A1 alloy film is performed at a relatively low temperature for a short time.
- the contact resistance between the A1 alloy film and the transparent pixel electrode and the source “drain” gate of the thin film transistor and each electrode can be kept low.
- the A1 alloy film to which Ge is added is compared with the A1 alloy film to which Ni, Ag, Zn, and Cu are added, which is included in the group ⁇ described in JP-A-2006-261636. There is little variation in contact resistance.
- the present invention since a predetermined amount of Gd and / or La is contained in the A1 alloy film as a heat resistance improving element, hillocks and the like can be obtained even by heat treatment at 220 ° C to 300 ° C. Excellent heat resistance can be ensured without generating heat.
- the Gd and / or La content and the Ni content are appropriately controlled, the dry etching property can be improved.
- the transparent pixel electrode having both sufficiently low! /, Electrical resistivity and sufficiently high // heat resistance, and preferably excellent in dry etching property. It is possible to provide a wiring material that can be directly connected to the wiring.
- dry etching means removal of an object to be etched (interlayer insulating film), and the purpose of cleaning the surface of the A1 alloy film even after the contact hole reaches the A1 alloy film. This also means that the surface of the A1 alloy film is exposed to an etching gas.
- excellent in dry etching property means (a) a small amount of residue generated after etching and (i) a high etching rate ratio. . Specifically, when the above characteristics (a) and (i) were evaluated by the method described in the examples described later, (a) no residue was generated after etching, and (i) the etching rate ratio was 0. Those that satisfy 3 or more are called “excellent dry etching”. Those satisfying these characteristics are excellent in dry etching properties, so the precise control of the wiring dimensions' shape can be achieved with the force S.
- the “etching rate ratio” is an index of the ease of etching of the A1 alloy thin film by plasma irradiation.
- the etching rate ratio is the ratio of the etching rate of the A1 alloy film based on the etching rate of pure A1 with a good etching rate (that is, the etching rate of the A1 alloy film is Nl, When the etching rate is N2, the ratio is expressed as the ratio of N1 / N2. The higher the etching rate ratio, the shorter the dry etching processing time and the higher the productivity.
- Ge is particularly useful for reducing the contact resistance between the A1 alloy film and the transparent pixel electrode.
- Ge is added in the range of 0.05 to 0.5 atomic%.
- it is 0.07 atomic% or more, More preferably, it is 0.1 atomic% or more.
- the Ge content is 0.5
- the reason for not more than atomic% is to prevent the electrical resistivity of the Al alloy film from becoming too high.
- it is 0.4 atomic% or less, more preferably 0.3 atomic% or less.
- the electrical resistivity when heat-treated at 220 ° C. for 10 minutes can be reduced to approximately 4.5 ⁇ ′cm or less.
- the "Ge-containing precipitate” means a precipitate in which Ge is precipitated, for example, an Al-Ge-Gd alloy, an A Ge-La alloy, or an Al-Ge-Gd-La alloy.
- Examples include Ge alone, an intermetallic compound of A1, Ge, and Gd, an intermetallic compound of A1, Ge, and La, or an intermetallic compound of A1, Ge, Gd, and La.
- the "Ge-containing concentrated layer” means that the average concentration of Ge in the Ge concentrated layer is Al-Ge-Gd alloy, A Ge-La alloy or Al-Ge-Gd- This means that the average concentration of Ge in the La alloy is 2 times or more, preferably 2.5 times or more.
- Ge exceeding the solid solubility limit (0.1 atomic%) of Ge in the A1 alloy film is precipitated at the grain boundary of the A1 alloy film by heat treatment or the like.
- the Ge may be diffused and concentrated on the surface of the A1 alloy film to form a Ge-enriched layer.
- Such a Ge enriched layer is also included in the “Ge-containing enriched layer”.
- the Ge halogen compound remains on the surface of the A1 alloy film, where the vapor pressure is lower than that of the A1, and it is difficult to volatilize. It is in a higher concentration state than the Ge concentration of A1 alloy bulk material.
- Such an embodiment is also included in the “Ge-containing concentrated layer”.
- the Ge concentration of the A1 alloy thin film surface layer and the thickness of the Ge-containing concentrated layer change.
- part of the force may be concentrated on the surface layer side.
- Such a mode is also included in the above-mentioned “Ge-containing concentrated layer”. included.
- the thickness of the Ge-containing concentrated layer is preferably 0.5 nm or more and 10 nm or less. More preferably, it is not less than Onm and not more than 5 nm.
- the electrical resistivity of the Al-Ge alloy binary alloy after heat treatment at 220 ° C for 10 minutes is very low.
- the third component is contained in the Al-Ge alloy.
- the electrical resistivity tends to increase. Therefore, when the purpose is only to reduce the electrical resistivity, an Al_Ge alloy binary alloy may be used, but as mentioned above, the heat resistance is reduced to about 150 ° C. Therefore, for the purpose of providing a wiring material having both low electrical resistivity and high heat resistance as in the present invention, a binary alloy of Al-Ge alloy is insufficient, and will be described below.
- the ternary alloy of Al-Ge-Gd alloy or Al-Ge-La alloy or the quaternary alloy of Al-Ge-Gd-La alloy was used.
- the heat resistance of the A1 alloy film is significantly improved. It is possible to effectively prevent hillocks from forming on the surface of the A1 alloy film.
- the content of Gd and La must be 0.05 atomic% or more. Preferably, it is 0.1 atomic% or more.
- the electrical resistivity of the A1 alloy film will increase, so the upper limit of the content is 0.45 atomic%, more preferably 0.4 atomic percent. 0/0, more preferably from 0.3 atomic%.
- These elements may be added alone or in combination of two or more. When adding two or more elements, the total content of each element only needs to satisfy the above range.
- the upper limit of the content of Gd and / or La is preferably set to 0.35 atomic%. This is because, as shown in the examples described later, if it exceeds 0.35 atomic%, the etching rate ratio is lowered, and residues may be generated after dry etching. If only dry etching properties are considered, the upper limit of the content of Gd and / or La is better. If you want to reduce the electrical resistivity, improve the heat resistance, and improve the dry etching properties of the A1 alloy film, the Gd and / or La content should be approximately 0.1 atomic% or more. It is more preferable to make it atomic% or less.
- the A1 alloy film and transparent pixel Electrode or A1 alloy film And the contact resistance between each electrode of the source 'drain' gate can be reduced.
- the upper limit of the Ni content is preferably 0.35 atomic%, more preferably 0.3 atomic%. More preferably, it is 0.25 atomic%, and still more preferably 0.20 atomic%.
- each of the ternary alloy of AH ⁇ e-Gd alloy or AH ⁇ e-La alloy or the quaternary alloy of Al-Ge-Gd-La alloy contains Ni, Ge and Ni
- the total content of is preferably in the range of 0.;! To 0.45 atomic%.
- the contact electrical resistance between the A1 alloy film and the transparent pixel electrode cannot be kept low, and the above-described action of Ge and Ni becomes effective. It is not demonstrated.
- the etching rate ratio decreases when the total amount of Ge and Ni exceeds 0.6 atomic% (described later). See Examples).
- the upper limit of the total amount of Ge and Ni is more preferably 0.35 atomic%, even more preferably 0.30 atomic% or less.
- a liquid crystal display device including an amorphous silicon TFT substrate or a polysilicon TFT substrate will be described as a representative example, but the present invention is not limited to this, and is suitable within a range that can meet the purpose described above. It is also possible to carry out with modifications, and both of them are included in the technical scope of the present invention.
- the A1 alloy film used in the present invention is also applied to, for example, a reflective electrode such as a reflective liquid crystal display device and a TAB (tab) connecting electrode used for signal input / output to the outside. It is confirmed by.
- FIG. 3 is a schematic diagram illustrating a preferred embodiment of a bottom-gate TFT substrate according to the present invention.
- the metal layers 51, 52, 54, and 53 are formed, respectively, whereas the metal layers 51, 52, and 54 can be omitted in the TFT substrate of the present embodiment. That is, according to the present embodiment, the wiring material used for the TFT source-drain electrode 29 without the barrier metal layer interposed as in the prior art can be directly connected to the transparent pixel electrode 5, thereby However, it can achieve good TFT characteristics equivalent to or better than those of conventional TFT substrates (see the examples below).
- the wiring material used in the present invention is applied to the wiring material of the source-drain electrode and the gate electrode as in this embodiment.
- the wiring material of the present invention is applied to a wiring material for a gate electrode, the noor metal layers 51 and 52 can be omitted. Even in these embodiments !, we are confident that we can achieve good TFT characteristics comparable to or better than conventional TFT substrates.
- FIG. 11 has the same reference numerals as FIG.
- a sputtering method is used to form an A1-0.2 atomic% 06_0.35 atomic% 0 (one alloy film having a thickness of about 200 nm.
- the temperature was set to 150 ° C.
- the gate electrode 26 and the scanning line 25 were formed (see FIG. 4), in which case the coverage of the gate insulating film 27 in FIG. It is preferable to etch the peripheral edge of the laminated thin film into a taper of about 30 ° to 40 ° so that the die is improved.
- a gate insulating film 27 is formed with a silicon oxide film (SiOx) having a thickness of about 30 Onm by using a method such as a plasma CVD method.
- the deposition temperature for the plasma CVD method was about 350 ° C.
- a hydrogenated amorphous silicon film (aS to H) 55 having a thickness of about 50 nm and a silicon nitride film (SiNx) having a thickness of about 300 nm are formed on the gate insulating film 27. Is deposited.
- a silicon nitride film (SiNx) is patterned as shown in FIG. 6 to form a channel protective film. Further, an n + type hydrogenated amorphous silicon film (n + aS to H) 56 having a thickness of about 50 nm doped with phosphorus is formed thereon, and then a hydrogenated amorphous silicon film (n aS to H) 55 and n + type hydrogenated amorphous silicon film (n + a_S to H) 56 are patterned.
- the Mo film 53 and the thickness of about 300 nm thickness of about 50 nm are sequentially stacked.
- the deposition temperature for sputtering was 150 ° C.
- the source electrode 28 integrated with the signal line and the drain electrode 29 directly connected to the pixel electrode 5 are formed.
- the n + type hydrogenated silicon silicon film (n + aS to H) 56 on the channel protective film (SiNx) is removed by dry etching.
- a silicon nitride film 30 having a thickness of about 300 nm is formed using a plasma CVD apparatus, for example, to form a protective film.
- the film formation temperature at this time is, for example, about 220 ° C.
- the silicon nitride film 30 is patterned, and contact holes 32 are formed in the silicon nitride film 30 by, for example, dry etching.
- a contact hole (not shown) is formed in a portion corresponding to the connection with TAB on the gate electrode at the end of the panel.
- the photoresist layer 31 is stripped using, for example, an amine-based stripping solution.
- an ITO film having a thickness of, for example, about 40 nm is formed and patterned by wet etching to form the transparent pixel electrode 5.
- the TFT array substrate 1 is completed by patterning the ITO film for indexing.
- the drain electrode 29 and the transparent pixel electrode 5 are in direct contact, and the gate electrode 26 and the ITO film for TAB connection are also in direct contact.
- a composite oxide containing at least one of a force using an ITO (indium tin oxide) film, indium oxide, zinc oxide, tin oxide, and titanium oxide may be used.
- ITO indium tin oxide
- IZO film ⁇ - ⁇ -based conductive oxide film
- polysilicon may be used as the active semiconductor layer instead of amorphous silicon V (see Embodiment 2 described later).
- the liquid crystal display device shown in FIG. 1 is completed by the method described below.
- polyimide is applied to the surface of the TFT substrate 1 manufactured as described above, and after drying, a rubbing treatment is performed to form an alignment film.
- the counter substrate 2 forms the light shielding film 9 on a glass substrate by patterning, for example, chromium (Cr) in a matrix.
- resin red, green and blue color filters 8 are formed in the gaps between the light shielding films 9.
- a counter electrode is formed by disposing a transparent conductive film such as an ITO film as the common electrode 7 on the light shielding film 9 and the color filter 8. Then, for example, polyimide is applied to the uppermost layer of the counter electrode, and after drying, a rubbing process is performed to form the alignment film 11.
- the TFT substrate 1 and the surface of the counter substrate 2 on which the alignment film 11 is formed are arranged so as to face each other, and the TFT is removed by a sealing material 16 made of resin, excluding the liquid crystal sealing port. Bond substrate 1 and 22 counter substrates. At this time, the gap between the two substrates is kept substantially constant by interposing a spacer 15 between the TFT substrate 1 and the counter substrate 2.
- the empty cell obtained in this way is placed in a vacuum, and gradually returned to atmospheric pressure with the sealing port immersed in liquid crystal, whereby a liquid crystal material containing liquid crystal molecules is injected into the empty cell. A liquid crystal layer is formed and the sealing port is sealed. Finally, a polarizing plate 10 is attached to both sides of the empty cell to complete the liquid crystal display.
- the driver circuit 13 for driving the liquid crystal display device is connected to the liquid crystal display. Electrically connected to the lay and placed on the side or back of the liquid crystal display. Then, the liquid crystal display is held by the holding frame 23 including the opening serving as the display surface of the liquid crystal display, the backlight 22 that forms the surface light source, the light guide plate 20, and the holding frame 23, thereby completing the liquid crystal display device.
- FIG. 12 is a schematic cross-sectional explanatory view for explaining a preferred embodiment of a top gate type TFT substrate according to the present invention.
- the same reference numerals as those in FIG. 2 described above showing the conventional TFT substrate are attached.
- polysilicon is used instead of amorphous silicon as an active semiconductor layer
- a top gate type TFT substrate is used instead of a bottom gate type
- source-drain electrodes and gate electrodes are used.
- A1-0. 2 atomic% 06_0.2 atomic% 0 one alloy is used in the point that the alloy is used as the wiring material of the source-drain electrode instead of the wiring material, which satisfies the requirements of the present invention.
- the active semiconductor film is composed of a polysilicon film (poly-Si) that is not doped with phosphorus and phosphorus or arsenic. This is different from the amorphous silicon TFT substrate shown in Fig. 3 described above in that (As) is formed from a polysilicon film ( ⁇ + poly-Si) into which ions are implanted. Run through (SiOx) It is formed in so that to intersect the line.
- the near metal layer 54 can be omitted. That is, the wiring material used for the TFT source-drain electrode 29 without the barrier metal layer interposed can be directly connected to the transparent pixel electrode 5 as in the prior art. Experiments have confirmed that good TFT characteristics equivalent to or higher than those of the substrate can be achieved.
- the force S for omitting the rare metal layers 51 and 52 can be achieved.
- the above alloy is applied to the wiring material of the source-drain electrode and the gate electrode, the rare metal layers 51, 52, and 54 can be omitted. Even in these cases, good TFT characteristics equivalent to or better than those of conventional TFT substrates were achieved. Be patient with what you are doing!
- FIG. 12 An example of a method for manufacturing the polysilicon TFT substrate according to the present invention shown in FIG. 12 will be described with reference to FIGS.
- A1-0.2 atom% 06_0.2 atom% 0 (1 alloy is used as the source-drain electrode and its wiring material.
- the thin film transistor is made of a polysilicon film (poly-Si). This is a polysilicon TFT used as a semiconductor layer, and the same reference numerals as those in FIG.
- heat treatment about 470 ° C for about 1 hour
- laser annealing are performed to convert the hydrogenated amorphous silicon film (a-Si-H) to polysilicon.
- the hydrogenated amorphous silicon film (aS to H) is irradiated with a laser having an energy of about 230 mj / cm 2 to obtain a thickness of about 0.
- a polysilicon film (poly-Si) of about 3 mm is obtained (Fig. 13).
- the polysilicon film (poly-Si) is patterned by plasma etching or the like.
- a silicon oxide film (SiOx) having a thickness of about lOOnm is formed, and a gate insulating film 27 is formed.
- the gate insulating film 27 by sputtering, etc., 8 1-2 atoms / ( ⁇ (1 alloy thin film and approximately 50 nm thick Mo thin film 52 approximately 50 nm thick) are stacked and then plasma etching is performed.
- the gate electrode 26 integrated with the scanning line is formed.
- a mask is formed with a photoresist 31, and, for example, phosphorus is doped with, for example, about 1 ⁇ 10 15 pieces / cm 2 at about 50 keV by using an ion implantation apparatus or the like to form a polysilicon film.
- An n + type polysilicon film ( ⁇ + poly-Si) is formed on a part of (poly-Si).
- the photoresist 31 is peeled off, and phosphorus is diffused by heat treatment at about 500 ° C., for example.
- a silicon oxide film (SiOx) having a thickness of about 500 nm is formed at a substrate temperature of about 250 ° C. to form an interlayer insulating film.
- the interlayer insulating film (SiOx) and the silicon oxide film of the gate insulating film 27 are dry-etched to form contact holes.
- the Mo film 53 with a thickness of about 50 nm and the 0.2 atomic% 06_0.2 atomic% 0 with a thickness of about 450 nm are formed into a signal line by patterning after forming an alloy thin film.
- An integrated source electrode 28 and drain electrode 29 are formed, and as a result, the source electrode 28 and the drain electrode 29 are contacted with the n + type polysilicon film (n + poly-Si) through the contact holes, respectively. .
- a silicon nitride film (SiNx) having a thickness of about 500 nm is formed at a substrate temperature of about 220 ° C. by using a plasma CVD apparatus or the like to form an interlayer insulating film.
- a photoresist layer 31 is formed on the interlayer insulating film, a silicon nitride film (SiNx) is patterned, and contact holes 32 are formed in the silicon nitride film (SiNx), for example, by dry etching.
- the photoresist is stripped using an amin-based stripping solution in the same manner as in the first embodiment, and then An ITO film is formed and patterned by wet etching to form the pixel electrode 5.
- the drain electrode 29 is in direct contact with the transparent pixel electrode 5. Constructing the drain electrode 29 ⁇ 0 ⁇ 2 atomic% 0 6 -0. 2 atomic% 0 (A Ge-concentrated layer is formed at the interface between the alloy thin film and the pixel electrode 5 to reduce the contact resistance. At the same time, since Ge diffuses and precipitates as a single substance, the recrystallization of A1 is promoted, and the electrical resistivity of the A1 alloy film itself is greatly reduced.
- heat treatment is performed at about 220 ° C. for about 1 hour to complete a polysilicon TFT array substrate.
- the same effects as those of the TFT substrate according to the first embodiment described above can be obtained.
- the A1 alloy in the second embodiment can also be used as a reflective electrode for reflective liquid crystals.
- the A1 alloy film of the present invention is also excellent in dry etching property. Less than, The dry etching process will be described.
- a halo such as C1 is formed on a substrate placed in a vacuum vessel.
- the source gas containing the source gas is turned into plasma by high-frequency power, and on the other hand, by applying another high-frequency power to the susceptor on which the substrate (etching material) is placed, ions in the plasma are drawn onto the substrate, Anisotropy by ion-assisted reaction with reactive plasma.
- This C1 radical is adsorbed on the A1 alloy thin film, which is a highly reactive material to be etched, and generates chloride on the surface of the A1 alloy thin film. Since a high-frequency bias is applied to the substrate on which the A1 alloy thin film is formed, ions in the plasma are accelerated and incident on the surface of the A1 alloy thin film, and chloride is evaporated by this ion bombardment effect. Is exhausted out of the vacuum container!
- the vapor pressure of the generated chloride is preferably relatively high. If the vapor pressure is high, chloride can be evaporated by the physical assistance of the surface temperature of the A1 alloy thin film and ion bombardment. On the other hand, when the vapor pressure of chloride is low, chloride remains on the surface without evaporation and etching residue (residual etching generated during dry etching) occurs.
- the present invention is not limited to a dry etching method or an apparatus used for the dry etching process.
- a general dry etching process can be performed using a general-purpose dry etching apparatus as shown in FIG.
- a single (inductively coupled plasma) type dry etching apparatus shown in FIG. 25 was used.
- a one-turn antenna 63 is placed.
- the plasma generator shown in FIG. 25 is a so-called TCP (Transfer Coupled Plasma) in which the dielectric window 62 is a flat plate type.
- a high frequency power 64 of 13.56 MHz is introduced into the antenna 63 through a matching unit 65.
- a process gas inlet 66 in the chamber 61 where a halogen gas such as C1, C1, etc. An etching gas is introduced.
- a substrate (material to be etched) 67 is placed on a susceptor 68.
- the susceptor 68 is an electrostatic chuck 69, and can be chucked by an electrostatic force due to the electric charge flowing into the substrate from the plasma.
- a member called a quartz glass collar 70 is placed around the susceptor 68.
- the halogen gas introduced into the chamber 61 is turned into plasma in an excited state by a dielectric magnetic field generated by applying high frequency power to the antenna 63 on the dielectric window 62.
- high frequency power 72 of 400 kHz is introduced into the susceptor 68 via the matching unit 71, and a high frequency bias is applied to the substrate (material to be etched) 67 placed on the susceptor 68.
- a high frequency bias is applied to the substrate (material to be etched) 67 placed on the susceptor 68.
- the etching gas (process gas) used in the dry etching step typically includes a mixed gas of a halogen gas, a boride of a halogen gas, and a rare gas.
- the composition of the mixed gas is not limited to this, and for example, hydrogen bromide or carbon tetrafluoride may be further added.
- the flow ratio of the mixed gas is not particularly limited.
- a mixed gas of Ar, C1, and BC1 is used.
- dry etching can be used in all steps of etching an A1 alloy thin film or Si semiconductor layer and forming contact holes, thereby improving productivity.
- the present invention is not intended to be limited to this.
- wet etching is performed until the bottom of the contact hole reaches the A1 alloy film, and switching to dry etching is performed at the final stage of the contact hole formation process.
- wet etching most of the contact hole formation process, it is possible to process multiple TFT substrates at once.
- productivity can be improved if dry etching is performed in all steps of contact hole formation.
- the electrical resistivity of the A1 alloy film itself and the A1 alloy film are transparent pixel electrodes or non- The contact resistivity when directly connected to the crystalline Si layer or the polycrystalline Si layer was measured, and the heat resistance when the A1 alloy film was heated was examined.
- Transparent pixel electrode configuration Indium tin oxide (ITO) with 10% by weight tin oxide added to indium oxide, or Indium zinc oxide (IZO) with 10% by weight zinc oxide added to indium oxide
- the content of each alloy element in the various A1 alloys used in the experiments was determined by ICP emission analysis (inductively coupled plasma emission analysis).
- the contact resistance is measured by preparing the Kelvin pattern (contact hole size: 10 ⁇ m square) shown in Fig. 20 and measuring it at 4 terminals (by applying current to ITO-A1 alloy or IZO-A1 alloy and using another terminal).
- FIG. 21 shows the results when ITO is used as the transparent pixel electrode.
- IZO was used instead of ITO, the same trend as in Fig. 21 was observed.
- the Ge-added A1 alloy film has the best stability with the smallest variation in contact resistance (in Fig. 21, the contact resistivity is indicated by ⁇ , and the upper and lower sides of the ⁇ are shown below. Each bar-shaped mark on the side One bar).
- FIG. 22 shows the correlation between the heat treatment time and the electrical resistivity of the A1 alloy film.
- the electric resistivity of the A1 alloy film decreases smoothly when the heat treatment time is increased.
- the amount of Gd La added is large, the electric resistivity does not decrease much.
- the amount of Gd La added alone or in total is 0.45 atomic% or less. It is considered to be 0.4 atomic% or less, more preferably 0.3 atomic% or less.
- the Al—Ge—Gd film and A1—Ge—La film having various compositions shown in Table 3 were heat-treated at 220 ° C., and the hillock density and electrical resistivity of the A1 alloy film were measured.
- the hillock density was measured by counting the number of hillocks formed on the surface of the A1 alloy film after heating the sample at 220 ° C for 30 minutes instead of examining the hillock generation temperature as in Experimental Example 2. This is what is done. That is, only the A1 alloy film was formed on the glass substrate under the conditions described in (2) above.
- the contact resistivity and Si direct contact characteristics of various A1-Ge-X films and ITO films shown in Table 4 were measured.
- the method shown in Experimental Example 1 was used to measure the contact resistivity with the ITO film.
- 2. 00 X 10- 4 ⁇ - cm 2 or less of a low contact resistivity is obtained.
- Ni and Cu of sample numbers 10, 11, 14, and 15 are added in combination with Ge, the effect of reducing the contact resistivity is particularly great.
- Si direct contact characteristics ON current and OFF current of evaluation TEG described later.
- L is 10 ⁇ m and gate width W is 10 ⁇ m.
- the prepared TEG for evaluation was subjected to heat treatment at 300 ° C for 30 minutes.
- a heating process is started after the formation of the A1 alloy film, and when the interdiffusion and interfacial reaction between the Si layer and the A1 alloy film proceed, the on-current decreases and / or the off-current increases. It is because it will produce.
- the off current is the current value when the gate voltage is -3V, and the on current is 20
- the A1 alloy film of the present invention has a high etching rate ratio comparable to that of pure A1.
- A1-0. 2 atomic% 0 6 _0.10 atomic% 0 (1 was used.
- A1 ⁇ 2. 0 atomic% ⁇ was used.
- a non-alkali glass substrate having a diameter of 6 inches and a thickness of 0.5 mm manufactured by Cowing Co., Ltd.
- a silicon oxide (SiOx) film with a thickness of 200 nm is deposited at a substrate temperature of about 250 ° C, and then the pure A1 film or A1 alloy film is formed under the conditions described in (2) above. Filmed .
- a positive photoresist nopolac resin; TSMR8900 manufactured by Tokyo Ohka Kogyo Co., Ltd., thickness 1 ⁇ O ⁇ m
- TSMR8900 manufactured by Tokyo Ohka Kogyo Co., Ltd., thickness 1 ⁇ O ⁇ m
- Substrate temperature Susceptor temperature (20 ° C)
- Etching was performed by changing the etching time in the range where the etching depth was 100 to 300 nm, and samples with different etching depths were produced.
- etching time in the range where the etching depth was 100 to 300 nm, and samples with different etching depths were produced.
- Etching was performed in the same manner as in Example 6, and the thickness (etching thickness) of the pure A1 film and each A1 alloy film after the etching was measured. These results are statistically processed by the least squares method to calculate the etching rate of pure A1 film (N2) and the etching rate of A1 alloy film (N1), respectively. " In this example, an etching rate ratio of 0.3 or higher was determined to be acceptable ( ⁇ ).
- an etching rate ratio that passed and no residue after dry etching was determined to be “excellent in dry etching”.
- Table 5 provides a column for comprehensive evaluation, where “O” is marked for those satisfying both of the above characteristics, and “X” is marked for those with V or one of the characteristics rejected (X).
- Fig. 27 shows the relationship between the Ge amount in the A1 alloy film and the etching rate ratio
- Fig. 28 shows the relationship between the Gd amount and La amount in the A1 alloy film, and the etching rate ratio
- Fig. 29 shows the A1 alloy film. The relationship between the amount of Ni in the steel and the etching rate ratio is shown below.
- the etching rate ratio is approximately 0.6, which is substantially constant.
- the etching rate ratio is approximately 0.6, which is substantially constant.
- the etching rate ratio increases as the content of Gd or La decreases.
- the upper limit of the total amount of Gd and / or La needs to be 0.35 atomic%, and the upper limit is 0.4 atomic%. As a result, desired characteristics could not be obtained.
- Ni also showed the same tendency as Gd / La described above, and as shown in FIG. 29, the etching rate ratio increased as the Ni content decreased.
- the upper limit of the Ni amount needs to be 0.3 atomic%, and when the upper limit is 0.4 atomic%, desired characteristics are obtained. Was not obtained.
- the A1 alloy film can be directly connected to the transparent pixel electrode made of a conductive oxide film without interposing a barrier metal layer, and a relatively low heat treatment temperature of about 220 ° C.
- A1 alloy film for display devices that can secure a sufficiently low electrical resistivity and excellent heat resistance even when applying the above, and a display device using the same can be provided.
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Abstract
Description
明 細 書 Specification
表示デバイス用 A1合金膜、表示デバイス、及びスパッタリングターゲット 技術分野 A1 alloy film for display device, display device, and sputtering target
[0001] 本発明は、液晶ディスプレイ、半導体、光学部品などに使用される表示デバイス用 A1合金膜、表示デバイス、および表示デバイス用のスパッタリングターゲットに関し、 特に、 A1合金膜を構成要素として含む新規な配線材料に関するものである。 TECHNICAL FIELD [0001] The present invention relates to an A1 alloy film for display devices used for liquid crystal displays, semiconductors, optical components, and the like, a display device, and a sputtering target for display devices. The present invention relates to a wiring material.
背景技術 Background art
[0002] 小型の携帯電話から、 30インチを超す大型のテレビに至るまで様々な分野に用い られる液晶表示装置 (液晶表示デバイス)は、画素の駆動方法によって、単純マトリク ス型液晶表示装置とアクティブマトリクス型液晶表示装置とに分けられる。このうちスィ ツチング素子として薄膜トランジスタ(Thin Film Transistor,以下、 TFTと呼ぶ。 ) を有するアクティブマトリクス型液晶表示装置は、高精度の画質を実現でき、高速の 画像などにも対応できるため、汎用されている。 [0002] Liquid crystal display devices (liquid crystal display devices) used in a variety of fields, from small mobile phones to large televisions exceeding 30 inches, are active with simple matrix type liquid crystal display devices depending on the pixel driving method. It is divided into a matrix type liquid crystal display device. Among them, an active matrix liquid crystal display device having a thin film transistor (hereinafter referred to as TFT) as a switching element is widely used because it can realize high-precision image quality and can cope with high-speed images. Yes.
[0003] 図 1を参照しながら、アクティブマトリクス型液晶表示装置に適用される代表的な液 晶ディスプレイの構成および動作原理を説明する。ここでは、活性半導体層として水 素化アモルファスシリコンを用いた TFT基板(以下、アモルファスシリコン TFT基板と 呼ぶ場合がある。)の例を代表的に説明する力 これに限定されず、ポリシリコンを用 V、た TFT基板であっても良!/、。 With reference to FIG. 1, the configuration and operating principle of a typical liquid crystal display applied to an active matrix liquid crystal display device will be described. Here, a representative example of a TFT substrate using hydrogenated amorphous silicon as an active semiconductor layer (hereinafter sometimes referred to as an amorphous silicon TFT substrate) is not limited to this, and polysilicon is used. V, or even a TFT substrate!
[0004] 図 1に示すように、液晶ディスプレイは、 TFT基板 1と、 TFT基板 1に対向して配置 された対向基板 2と、 TFT基板 1と対向基板 2との間に配置され、光変調層として機 能する液晶層 3とを備えている。 TFT基板 1は、絶縁性のガラス基板 la上に配置され た TFT4、透明画素電極 5、走査線や信号線を含む配線部 6を有している。透明画 素電極 5は、酸化インジウム(In O )中に酸化錫(SnO)を 10質量%程度含む酸化ィ As shown in FIG. 1, a liquid crystal display is disposed between a TFT substrate 1, a counter substrate 2 disposed opposite the TFT substrate 1, and between the TFT substrate 1 and the counter substrate 2, and performs light modulation. And a liquid crystal layer 3 that functions as a layer. The TFT substrate 1 includes a TFT 4 disposed on an insulating glass substrate la, a transparent pixel electrode 5, and a wiring portion 6 including a scanning line and a signal line. The transparent pixel electrode 5 is an oxide film containing about 10% by mass of tin oxide (SnO) in indium oxide (In 2 O 3).
2 3 twenty three
ンジゥム '錫 (ITO)膜などの導電性酸化膜から形成されている。 TFT基板 1は、 TAB テープ 12を介して連結されたドライバ回路 13及び制御回路 14によって駆動される。 It is made of conductive oxide film such as Ngum 'Tin (ITO) film. The TFT substrate 1 is driven by a driver circuit 13 and a control circuit 14 connected via a TAB tape 12.
[0005] 対向基板 2は、 TFT基板 1側に、絶縁性のガラス基板 lbの全面に形成された共通 電極 7と、透明画素電極 5に対向する位置に配置されたカラーフィルタ 8と、 TFT基 板 1上の TFT4および配線部 6に対向する位置に配置された遮光膜 9とを有している[0005] The counter substrate 2 includes a common electrode 7 formed on the entire surface of the insulating glass substrate lb on the TFT substrate 1 side, a color filter 8 disposed at a position facing the transparent pixel electrode 5, and a TFT substrate. It has a light-shielding film 9 arranged at a position facing the TFT 4 on the board 1 and the wiring part 6
。対向基板 2は、液晶層 3に含まれる液晶分子(不図示)を所定の向きに配向させる ための配向膜 11を更に有している。 . The counter substrate 2 further includes an alignment film 11 for aligning liquid crystal molecules (not shown) included in the liquid crystal layer 3 in a predetermined direction.
[0006] TFT基板 1および対向基板 2の外側(液晶層 3側とは反対側)には、それぞれ、偏 光板 10が配置されている。 [0006] On the outside of the TFT substrate 1 and the counter substrate 2 (on the side opposite to the liquid crystal layer 3 side), a polarizing plate 10 is disposed.
[0007] 液晶ディスプレイは、対向電極(不図示)と透明画素電極 5との間に形成される電界 によって液晶層 3における液晶分子の配向方向が制御され、液晶層 3を通過する光 が変調される。これにより、対向基板 2を透過する光の透過量が制御されて画像が表 示される。 In the liquid crystal display, the alignment direction of liquid crystal molecules in the liquid crystal layer 3 is controlled by an electric field formed between a counter electrode (not shown) and the transparent pixel electrode 5, and light passing through the liquid crystal layer 3 is modulated. The As a result, the amount of light transmitted through the counter substrate 2 is controlled and an image is displayed.
[0008] 次に、図 2を参照しながら、液晶ディスプレイに好適に用いられる従来のァモルファ スシリコン TFT基板の構成および動作原理を詳しく説明する。図 2は、図 1中、 Aの要 部拡大図である。 Next, the configuration and operation principle of a conventional amorphous silicon TFT substrate suitably used for a liquid crystal display will be described in detail with reference to FIG. FIG. 2 is an enlarged view of the main part A in FIG.
[0009] 図 2に示すように、ガラス基板(不図示)上には、走査線 (ゲート配線) 25が形成され 、走査線 25の一部は、 TFTのオン ·オフを制御するゲート電極 26として機能する。ゲ ート電極 26を覆うようにしてゲート絶縁膜 (シリコン窒化膜) 27が形成されている。ゲ ート絶縁膜 27を介して走査線 25と交差するように信号線 (ソース-ドレイン配線) 34が 形成され、信号線 34の一部は、 TFTのソース電極 28として機能する。ゲート絶縁膜 27上に、アモルファスシリコンチャネル膜 (活性半導体膜、不図示)、信号線 (ソース- ドレイン配線) 34、層間絶縁シリコン窒化膜 (保護膜) 30が順次形成されている。この タイプは一般にボトムゲート型とも呼ばれる。 As shown in FIG. 2, a scanning line (gate wiring) 25 is formed on a glass substrate (not shown), and a part of the scanning line 25 is a gate electrode 26 that controls on / off of the TFT. Function as. A gate insulating film (silicon nitride film) 27 is formed so as to cover the gate electrode 26. A signal line (source-drain wiring) 34 is formed so as to cross the scanning line 25 via the gate insulating film 27, and a part of the signal line 34 functions as a source electrode 28 of the TFT. On the gate insulating film 27, an amorphous silicon channel film (active semiconductor film, not shown), a signal line (source-drain wiring) 34, and an interlayer insulating silicon nitride film (protective film) 30 are sequentially formed. This type is generally called a bottom gate type.
[0010] アモルファスシリコンチャネル膜は、 P (リン)がドープされていないイントリンシック層 [0010] The amorphous silicon channel film is an intrinsic layer that is not doped with P (phosphorus).
(i層、ノンドーピング層とも呼ばれる。)と、 Pがドープされたドーブト層(n層)とから構 成されている。ゲート絶縁膜 27上の画素領域には、例えば In O中に SnOを含む IT (also referred to as the i layer or non-doping layer) and a doped layer doped with P (n layer). In the pixel region on the gate insulating film 27, for example, IT containing SnO in InO
2 3 twenty three
O膜によって形成された透明画素電極 5が配置されている。 TFTのドレイン電極 29 は、透明画素電極 5に電気的に接続されている。 A transparent pixel electrode 5 formed of an O film is disposed. The drain electrode 29 of the TFT is electrically connected to the transparent pixel electrode 5.
[0011] 走査線 25を介してゲート電極 26にゲート電圧が供給されると、 TFT4はオン状態と なり、予め信号線 34に供給された駆動電圧は、ソース電極 28から、ドレイン電極 29 を介して透明画素電極 5へ供給される。そして、透明画素電極 5に所定レベルの駆動 電圧が供給されると、図 1で説明したように、透明画素電極 5と対向電極との間に電 位差が生じる結果、液晶層 3に含まれる液晶分子が配向して光変調が行われる。 When a gate voltage is supplied to the gate electrode 26 through the scanning line 25, the TFT 4 is turned on, and the drive voltage supplied to the signal line 34 in advance from the source electrode 28 through the drain electrode 29. And supplied to the transparent pixel electrode 5. Then, the transparent pixel electrode 5 is driven to a predetermined level. When the voltage is supplied, as described in FIG. 1, as a result of the potential difference between the transparent pixel electrode 5 and the counter electrode, the liquid crystal molecules contained in the liquid crystal layer 3 are aligned and light modulation is performed. .
[0012] TFT基板 1において、透明画素電極 5に電気的に接続される信号線 (画素電極用 信号線)、ソース電極 28-ドレイン電極 29に電気的に接続されるソース-ドレイン配線 34、ゲート電極 26に電気的に接続される走査線 25は、電気抵抗率が低ぐ微細加 ェが容易であるなどの理由により、いずれも、純 Al、又は Al_Ndなどの A1合金の薄 膜 (以下、背景技術の欄において A1系薄膜と呼ぶ。)から形成されており、その上お よびその下には、図 2に示すように、 Mo, Cr, Ti, W等の高融点金属からなるバリア メタノレ層 51、 52、 53、 54カ形成されている。 In the TFT substrate 1, a signal line (pixel electrode signal line) electrically connected to the transparent pixel electrode 5, a source-drain wiring 34 electrically connected to the source electrode 28 -drain electrode 29, and a gate The scanning lines 25 that are electrically connected to the electrodes 26 are all made of pure Al or a thin film of an A1 alloy such as Al_Nd (below, for reasons such as low electrical resistivity and easy fine application). In the background art column, it is referred to as an A1-based thin film.) As shown in Fig. 2, there is a barrier methanole made of a refractory metal such as Mo, Cr, Ti, or W. Layers 51, 52, 53, and 54 are formed.
[0013] ここで、透明画素電極 5に対し、ノ リアメタル層 54を介して A1系薄膜を接続する理 由は、 A1系薄膜を透明画素電極 5と直接接続すると接続抵抗 (コンタクト抵抗)が上 昇し、画面の表示品位が低下するからである。すなわち、透明画素電極に直接接続 する配線を構成する A1は非常に酸化され易ぐ液晶ディスプレイの成膜過程で生じ る酸素や成膜時に添加する酸素などにより、 A1系薄膜と透明画素電極との界面に A1 酸化物の絶縁層が生成するためである。また、透明画素電極を構成する ITOは導電 性の金属酸化物であるが、上記のようにして生成した A1酸化物層により、電気的なォ 一ミック接続を行うことができなレ、。 Here, the reason for connecting the A1-based thin film to the transparent pixel electrode 5 via the rare metal layer 54 is that the connection resistance (contact resistance) increases when the A1-based thin film is directly connected to the transparent pixel electrode 5. This is because the display quality of the screen is lowered. In other words, A1, which constitutes the wiring directly connected to the transparent pixel electrode, is easily oxidized and oxygen generated in the liquid crystal display film formation process or oxygen added at the time of film formation. This is because an A1 oxide insulating layer is formed at the interface. In addition, ITO that constitutes the transparent pixel electrode is a conductive metal oxide, but cannot be electrically connected electrically by the A1 oxide layer generated as described above.
[0014] ところ力 ノ リアメタル層を形成するためには、ゲート電極やソース電極、更にはドレ イン電極の形成に必要な成膜用スパッタ装置に加えて、バリアメタル形成用の成膜 チャンバ一を余分に装備しなければならなレ、。液晶ディスプレイの大量生産に伴って 低コスト化が進むにつれて、バリアメタル層の形成に伴う製造コストの上昇や生産性 の低下は軽視できなくなって!/、る。 [0014] However, in order to form a force-free metal layer, in addition to a film-forming sputtering apparatus necessary for forming a gate electrode, a source electrode, and further a drain electrode, a film-forming chamber for forming a barrier metal is provided. I have to equip extra. As the cost of production increases with the mass production of liquid crystal displays, the increase in manufacturing cost and the decrease in productivity associated with the formation of the barrier metal layer cannot be neglected!
[0015] そこで、ノ リアメタル層の形成を省略でき、 A1系薄膜を透明画素電極に直接接続す ることが可能な電極などの配線材料や製造方法が提案されている。 [0015] In view of this, wiring materials such as electrodes and manufacturing methods capable of directly connecting the A1-based thin film to the transparent pixel electrode have been proposed.
[0016] 例えば、特許文献 1には、透明画素電極の材料として、酸化インジウムに酸化亜鉛 を 10質量%程度含む酸化インジウム亜鉛 (IZO)膜を用いた技術が開示されている。 しかし、この技術によれば、現在、最も普及している ITO膜を IZO膜に変更しなけれ ばならないため、材料コストが上昇する。 [0017] 特許文献 2には、ドレイン電極にプラズマ処理やイオン注入を行い、ドレイン電極の 表面を改質する方法が開示されている。しかし、この方法によれば、表面処理のため の工程が付加されるため、生産性が低下する。 For example, Patent Document 1 discloses a technique in which an indium zinc oxide (IZO) film containing about 10% by mass of zinc oxide in indium oxide is used as a material for a transparent pixel electrode. However, this technology increases the material cost because the most popular ITO film must be changed to an IZO film. Patent Document 2 discloses a method of modifying the surface of the drain electrode by performing plasma treatment or ion implantation on the drain electrode. However, according to this method, a process for surface treatment is added, and thus productivity is lowered.
[0018] また、特許文献 3には、ゲート電極、ソース電極およびドレイン電極として、純 A1また は A1の第 1層と、純 A1または A1に N, O, Si, C等の不純物を含む第 2層とを用いる 方法が開示されている。この方法によれば、ゲート電極、ソース電極、およびドレイン 電極を構成する薄膜を同じ成膜チャンバ一を用いて連続して形成できるという利点 はあるが、上述した不純物を含む第 2層を形成する工程が余分に増える。しかも、ソ ース-ドレイン配線に不純物を導入する過程で、不純物が混入した膜と混入して!/、な い膜との熱膨張係数の差に起因して、チャンバ一の壁面からソース-ドレイン配線の 堆積物がフレークとして剥がれ落ちる現象が頻発する。この現象を防ぐため、成膜ェ 程を頻繁に停止してメンテナンスを行う必要があり、生産性が著しく低下する。 [0018] Further, Patent Document 3 discloses a first layer of pure A1 or A1 as a gate electrode, a source electrode, and a drain electrode, and a first layer containing impurities such as N, O, Si, and C in pure A1 or A1. A method using two layers is disclosed. According to this method, although there is an advantage that the thin films constituting the gate electrode, the source electrode, and the drain electrode can be continuously formed using the same film formation chamber, the second layer containing the impurity described above is formed. Extra steps are added. In addition, in the process of introducing impurities into the source-drain wiring, the source wall is exposed from the wall surface of the chamber due to the difference in thermal expansion coefficient between the film mixed with the impurity! The drain wiring deposits often flake off as flakes. In order to prevent this phenomenon, it is necessary to frequently stop the film forming process and perform maintenance, and the productivity is significantly reduced.
[0019] このような事情に鑑み、ノ リアメタル層の省略を可能にすると共に、工程数を増やす ことなく簡略化し、 A1合金膜を透明画素電極に対して直接かつ確実に接続し得る方 法が開示されている(特許文献 4)。特許文献 4では、合金成分として、 Au、 Ag、 Zn、 Cu、 Ni、 Sr、 Ge、 Sm、および Bはりなる群から選ばれる少なくとも一種を 0· ;!〜 6原 子%含む A1合金を使用しており、これら合金成分の少なくとも一部を当該 A1合金膜 と透明画素電極との界面で析出物または濃化層として存在させることによって上記課 題を解決している。 In view of such circumstances, there is a method capable of omitting the near metal layer, simplifying without increasing the number of steps, and connecting the A1 alloy film directly and securely to the transparent pixel electrode. (Patent Document 4). In Patent Document 4, A1 alloy containing at least one selected from the group consisting of Au, Ag, Zn, Cu, Ni, Sr, Ge, Sm, and B is used as an alloy component. The above problems are solved by allowing at least a part of these alloy components to exist as precipitates or concentrated layers at the interface between the A1 alloy film and the transparent pixel electrode.
[0020] 特許文献 4において、例えば Al-Ni系合金の場合、 250°Cで 30分熱処理した後の 電気抵抗率は、八1-2原子°/(^1で 3· 8 Ω · «η、八1-4原子%^で 5· 8 Ω - cm, A 1-6原子%^で 6 · 5 μ Ω ' cmと低い。このように電気抵抗率が低く抑えられた A1合金 膜を用いれば、表示デバイスの消費電力を少なくできるため、非常に有用である。ま た、電極部分の電気抵抗率が下がると、電気抵抗と電気容量の積によって決まる時 定数も小さくなるので、表示パネルを大型化する場合でも高度の表示品位を保つこと が可能となる。し力もながら、上記 Al-Ni系合金の耐熱温度は、いずれも、おおむね 、 150〜200。Cと低い。 [0020] In Patent Document 4, for example, in the case of an Al-Ni alloy, the electrical resistivity after heat treatment at 250 ° C for 30 minutes is 8 1-2 atoms ° / (^ · 3 · 8Ω · «η , 8 1-4 atomic% ^ is 5 · 8 Ω-cm, A 1-6 atomic% ^ is 6 · 5 μΩ 'cm, and the A1 alloy film with low electrical resistivity is used. This is very useful because the power consumption of the display device can be reduced, and the time constant determined by the product of the electrical resistance and the capacitance is reduced when the electrical resistivity of the electrode portion is reduced. Even when the size is increased, it is possible to maintain a high degree of display quality, but the heat resistance temperature of the above Al-Ni alloys is generally as low as 150 to 200 C.
[0021] そこで、特許文献 5には、薄膜トランジスタと透明画素電極を有し、 A1合金膜と導電 性酸化膜が、高融点金属を介さずに直接接続し、その直接接続界面に A1合金成分 の一部または全部が析出もしくは濃化して存在する薄膜トランジスタ基板が開示され ている。 A1合金膜は、合金成分として、グループ αに属する元素を 0. 1原子%以上 6原子%以下、およびグループ Xに属する元素を 0. 1原子%以上 2. 0原子%以下 の範囲で含有する Α^ α -Χ合金からなり、グループ αは、 Ni, Ag, Zn, Cu,および Geよりなる群から選択される少なくとも一種の元素であり、グループ Xは、 Mg, Cr, Mn, Ru, Rh, Pd, Ir, Pt, La, Ce, Pr, Gd, Tb, Sm, Eu, Ho, Er, Tm, Yb, Lu ,および Dyよりなる群から選択される少なくとも一種の元素である薄膜トランジスタ基 板である。 Therefore, Patent Document 5 includes a thin film transistor and a transparent pixel electrode, and an A1 alloy film and a conductive layer. A thin film transistor substrate is disclosed in which a conductive oxide film is directly connected without a refractory metal and a part or all of the A1 alloy component is precipitated or concentrated at the direct connection interface. The A1 alloy film contains, as an alloy component, an element belonging to group α in the range of 0.1 atomic% to 6 atomic% and an element belonging to group X in the range of 0.1 atomic% to 2.0 atomic%. Α ^ α -Χ alloy, group α is at least one element selected from the group consisting of Ni, Ag, Zn, Cu, and Ge, and group X is Mg, Cr, Mn, Ru, Rh A thin film transistor substrate that is at least one element selected from the group consisting of Pd, Ir, Pt, La, Ce, Pr, Gd, Tb, Sm, Eu, Ho, Er, Tm, Yb, Lu, and Dy. is there.
[0022] この薄膜トランジスタ基板を用いると、ノ リアメタル層の省略が可能になると共に、ェ 程数を増やすことなぐ A1合金膜を導電性酸化膜力 なる画素電極に対し直接的且 つ確実に接続することができるとされている。また、 A1合金膜に対し、例えば、約 100 °C以上 300°C以下の低い熱処理温度を適用した場合でも、画素電極間の電気抵抗 率の低減と優れた耐熱性とを達成できるとされている。具体的には、例えば 250°C X 30分といった低温の熱処理を採用した場合でも、ヒロックなどの欠陥を生じることなく 、当該 A1系合金薄膜の電気抵抗率で 7 Ω 'cm以下を達成することができると記載 されている。 [0022] When this thin film transistor substrate is used, it is possible to omit the near metal layer, and to connect the A1 alloy film directly and reliably to the pixel electrode having the conductive oxide film force without increasing the number of steps. It is supposed to be possible. In addition, even when a low heat treatment temperature of, for example, about 100 ° C. or more and 300 ° C. or less is applied to the A1 alloy film, it is said that reduction in electrical resistivity between pixel electrodes and excellent heat resistance can be achieved. Yes. Specifically, even when heat treatment at a low temperature such as 250 ° CX for 30 minutes is adopted, the electrical resistivity of the A1 alloy thin film can achieve 7 Ω'cm or less without causing defects such as hillocks. It is stated that it can be done.
また、特許文献 6には、添加元素として Geを 0. 2〜; 1. 5原子%含有し、更に Niを 0 . 2〜2. 5原子%含有し、残部が A1からなる配線膜用 A1合金膜が記載されているが 、特許文献 6の表 1によると、低い電気抵抗率と良好な表面状態の両方を満足するこ とは難しい。 Further, Patent Document 6 includes, as an additive element, Ge in an amount of 0.2 to 1.5 atom%, further containing Ni in an amount of 0.2 to 2.5 atom%, and the balance being A1 for a wiring film A1. Although an alloy film is described, according to Table 1 of Patent Document 6, it is difficult to satisfy both a low electrical resistivity and a good surface state.
[0023] 一方、近年では、液晶ディスプレイの高画質化、高精細化とともに、 A1合金膜電極 用配線の微細化(線幅の微細化)が進められており、これに伴い、配線形成の方法 は、従来汎用されてきたウエットエッチング法 (薬液によるエッチングによって配線バタ 一ユングを行う方法)から、ドライエッチング法 (反応性プラズマによるエッチングによ つて配線パターユングを行う方法)へと移行しつつある。ウエットエッチング法では、薬 液がパターユングのマスクであるレジストの下側に回り込んで配泉側壁をエッチング する「サイドエッチング」と呼ばれる現象が発生するので、配線寸法 ·形状の精密な制 御が難しい。これに対し、ドライエッチング法では、精密なエッチングを行うことができ るので、配線の微細加工に優れている。ドライエッチングによれば、線幅が 2 m以 下の微細配線を形成することができる。また、 TFT作製における全てのエッチングェ 程をドライエッチングすることができれば、生産性の向上も期待される。 [0023] On the other hand, in recent years, along with the improvement in image quality and resolution of liquid crystal displays, the A1 alloy film electrode wiring has been made finer (line width has been reduced). Is shifting from the widely used wet etching method (a method of performing wiring patterning by chemical etching) to a dry etching method (a method of performing wiring patterning by reactive plasma etching). . In the wet etching method, a phenomenon called “side etching” occurs in which the chemical solution wraps around the underside of the resist, which is a patterning mask, and etches the hot spring side walls. It ’s difficult. On the other hand, the dry etching method is excellent in fine processing of wiring because precise etching can be performed. By dry etching, fine wiring with a line width of 2 m or less can be formed. In addition, if all etching processes in TFT fabrication can be dry-etched, productivity can be expected to improve.
[0024] そこで、ドライエッチング処理に好適な電極用膜/配線用膜として、特許文献 7に、 A1に Ndを 0. 1原子%超〜 1. 0原子%含有する Al-Nd系合金薄膜が開示されてい る。ただし、この A1合金薄膜は、透明画素電極に対して直接接続し得るものではない 特許文献 1:特開平; U -337976号公報 [0024] Therefore, as an electrode film / wiring film suitable for dry etching, Patent Document 7 discloses an Al-Nd alloy thin film containing Nd in A1 in an amount of more than 0.1 atomic% to 1.0 atomic%. It is disclosed. However, this A1 alloy thin film cannot be directly connected to the transparent pixel electrode. Patent Document 1: Japanese Patent Laid-Open Publication No. U-337976
特許文献 2:特開平; U -283934号公報 Patent Document 2: JP-A-5-283934
特許文献 3:特開平; U -284195号公報 Patent Document 3: Japanese Patent Laid-Open Publication No. U-284195
特許文献 4:特開 2004-214606号公報 Patent Document 4: Japanese Patent Laid-Open No. 2004-214606
特許文献 5:特開 2006-261636号公報 Patent Document 5: Japanese Unexamined Patent Publication No. 2006-261636
特許文献 6 :特開 2005-171378号公報 Patent Document 6: JP-A-2005-171378
特許文献 7:特開 2004-55842号公報 Patent Document 7: Japanese Patent Application Laid-Open No. 2004-55842
発明の開示 Disclosure of the invention
[0025] 近年、歩留りの改善および生産性向上の観点から、表示デバイスを製造する際の プロセス温度がますます低温化する傾向にある。例えば、アモルファスシリコン TFT のソース-ドレイン電極材料には、低い電気抵抗率と高い耐熱性とが求められており、 その要求スペックは、これまでは、電気抵抗率で 7 Ω ' cm程度以下、耐熱温度で 2 50°C程度とされている。この耐熱温度は、ソース-ドレイン電極に対し製造工程で加 わる最高温度によって決まり、この最高温度は、電極上に保護膜として形成する絶縁 膜の形成温度とされている。最近では、成膜技術の向上によって低温でも所望の絶 縁膜を得ることが可能となり、特にソース-ドレイン電極上の保護膜では、 220°C程度 での成膜も可能になってきている。 [0025] In recent years, from the viewpoint of yield improvement and productivity improvement, the process temperature for manufacturing a display device tends to be lower. For example, source / drain electrode materials for amorphous silicon TFTs are required to have low electrical resistivity and high heat resistance, and the required specifications have been about 7 Ω'cm or less in terms of electrical resistivity. The temperature is about 250 ° C. This heat-resistant temperature is determined by the maximum temperature that is applied to the source-drain electrode in the manufacturing process, and this maximum temperature is the formation temperature of the insulating film formed as a protective film on the electrode. Recently, it has become possible to obtain a desired insulating film even at a low temperature by improving the film forming technique. In particular, the protective film on the source-drain electrode can be formed at about 220 ° C.
[0026] そのため、ドレイン電極と透明画素電極とを直接接続し得る配線材料であることに 加えて、耐熱温度は 220°Cレベルで、且つ、電気抵抗率は 4. 5 μ Ω ' cm程度以下と 、電気抵抗率の充分に低ぐ好ましくは、ドライエッチング性にも優れたものが求めら れている。 [0026] Therefore, in addition to being a wiring material that can directly connect the drain electrode and the transparent pixel electrode, the heat resistance temperature is 220 ° C level and the electrical resistivity is about 4.5 μΩ 'cm or less. In addition, the electrical resistivity is preferably sufficiently low, and preferably excellent in dry etching property. It is.
[0027] しかしながら、このような低い電気抵抗率と高い耐熱性とを兼ね備えており、好まし くはドライエッチング性にも優れた、透明画素電極と直接接続し得る A1系の配線材料 は開示されていない。 [0027] However, an A1-based wiring material that combines such a low electrical resistivity and high heat resistance and is preferably excellent in dry etching and can be directly connected to a transparent pixel electrode is disclosed. Not.
[0028] 例えば、前述した特開 2004-214606号公報に開示された A1合金膜は、低い電気 抵抗率を備えているが、耐熱温度は低い。 [0028] For example, the A1 alloy film disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 2004-214606 has a low electrical resistivity but a low heat resistance temperature.
[0029] また、前述した特開 2006-261636号公報に開示された A1合金膜でも、 250°Cで の加熱で 7 Ω ' cm程度と十分とは言えない。 [0029] Further, even the A1 alloy film disclosed in the above-mentioned JP-A-2006-261636 cannot be said to be sufficient at about 7 Ω'cm when heated at 250 ° C.
[0030] このように従来の Al_Nd合金などの A1合金膜では、プロセス温度が低くなると、以 下に示すように、金属間化合物の析出および結晶成長が十分進まないため、低い電 気抵抗率が得られず、 Ndの添加量を減らすとプロセス温度が低くなつても低!/、電気 抵抗率は得られるが、析出物が少なぐ結晶成長が進み、ヒロックが発生しやすぐ耐 熱温度が下がると考えられる。 [0030] Thus, in the conventional A1 alloy film such as Al_Nd alloy, when the process temperature is lowered, the precipitation of the intermetallic compound and the crystal growth do not sufficiently proceed as shown below. If the amount of Nd added is reduced, the process temperature will be low even if the process temperature is low! /, But electrical resistivity will be obtained, but crystal growth will progress with less precipitates, hillocks will occur, and the heat resistance temperature will soon increase. It is thought to go down.
[0031] 以下、この点について、詳しく説明する。 Hereinafter, this point will be described in detail.
[0032] A1合金膜は、一般に、スパッタリング法によって形成される力 S、この方法によれば、 A1中に固溶限を超えて添加された合金成分は強制固溶状態で存在する。固溶状態 の合金元素を含む A1合金の電気抵抗率は、一般に純 A1よりも高い。これに対し、固 溶限を超えて合金元素を含む A1合金膜は、加熱すると合金成分が金属間化合物と して粒界に析出し、更に加熱すると A1の再結晶が進み、 A1の結晶成長が起こる。こ のときの金属間化合物の析出温度および結晶成長の温度は、合金元素によって異 なる力 S、いずれにしても、合金成分 (金属間化合物)の析出と結晶成長とによって、当 該 A1合金膜の電気抵抗率は低下するようになる。 [0032] The A1 alloy film generally has a force S formed by a sputtering method, and according to this method, an alloy component added to the A1 beyond the solid solubility limit exists in a forced solid solution state. The electrical resistivity of A1 alloys containing solid solution alloy elements is generally higher than pure A1. In contrast, when the A1 alloy film containing the alloy element exceeds the solid solubility limit, the alloy component precipitates at the grain boundary as an intermetallic compound when heated, and when further heated, the recrystallization of A1 proceeds, and A1 crystal growth Happens. At this time, the precipitation temperature of the intermetallic compound and the temperature of crystal growth are different forces S depending on the alloy element. In any case, the A1 alloy film depends on the precipitation of the alloy component (intermetallic compound) and the crystal growth. The electrical resistivity of the liquid crystal is lowered.
[0033] 加熱によって結晶成長が進むと膜内部の圧縮応力は大きくなる力 更に加熱して 結晶成長が進むと、ついには耐え切れなくなり、応力緩和のため、 A1が膜表面に拡 散してヒロック (コブ状の突起物)が生じる。合金化は、粒界に析出した金属間化合物 によって A1の拡散を抑えてヒロックの発生を防止し、耐熱性を高めるという作用を有し ている。従来は、こうした現象を利用して合金成分の析出と結晶成長の進行を図り、 A1合金膜の電気抵抗率の低減と高耐熱性との両立を図ってきた。 [0034] ところ力 上記の様にプロセス温度が低くなると、従来の合金成分では、金属間化 合物の析出が十分に起こらず、その結果、結晶成長も進まなくなり、電気抵抗率が低 減し難くなると考免られる。 [0033] The force that increases the compressive stress inside the film as the crystal growth progresses due to heating. When the crystal growth progresses further by heating, it finally becomes unbearable, and A1 diffuses on the film surface to relax the stress and hillocks. (Hump-like projections) are generated. Alloying has the effect of preventing the generation of hillocks by suppressing the diffusion of A1 by the intermetallic compounds precipitated at the grain boundaries, and improving the heat resistance. Conventionally, precipitation of alloy components and progress of crystal growth have been promoted by utilizing these phenomena, and both reduction of the electrical resistivity of the A1 alloy film and high heat resistance have been achieved. [0034] However, when the process temperature is lowered as described above, in the conventional alloy components, the precipitation of intermetallic compounds does not occur sufficiently, and as a result, the crystal growth does not progress and the electrical resistivity is reduced. When it becomes difficult, it is ignored.
[0035] 上記では、液晶表示装置を代表的に取上げて説明したが、前述した課題は液晶表 示装置に限定されず、アモルファスシリコン TFT基板に共通して見られる。また、上 記課題は、 TFTの半導体層として、アモルファスシリコンのほか、多結晶シリコンを用 いた場合にも見られる。 In the above description, the liquid crystal display device is representatively described. However, the above-described problem is not limited to the liquid crystal display device, and can be commonly seen in the amorphous silicon TFT substrate. The above problems are also observed when polycrystalline silicon is used in addition to amorphous silicon as the TFT semiconductor layer.
[0036] 一方、前述したように、 A1合金膜は、上記特性のほか、ドライエッチング性に優れて いることも要求されている力 これらの特性をすベて兼ね備えた A1合金薄膜は、未だ 提供されていない。 [0036] On the other hand, as described above, the A1 alloy film is also required to have excellent dry etching properties in addition to the above-mentioned characteristics. An A1 alloy thin film having all these characteristics is still provided. It has not been.
[0037] 本発明はこの様な事情に着目してなされたものであって、その目的は、ノ リアメタル 層の省略を可能にすると共に、工程数を増やすことなく簡略化し、 A1合金膜を導電 性酸化膜からなる透明画素電極に対し直接且つ確実に接続することだけでなぐ A1 合金膜に対し、より低い熱処理温度をより短時間で適用した場合でも、透明画素電 極間の電気抵抗率の低減と優れた耐熱性とを達成することができ、好ましくは、ドライ エッチング性にも優れている技術を提供することにある。具体的には、電気抵抗率と 耐熱性の目安として、例えば 220°C X 20分といった、より短時間でかつより低温の熱 処理を採用した場合でも、ヒロックなどの欠陥を生じることなぐ当該 A1系合金薄膜の 電気抵抗率を一層低くすることができ、処理温度の低温化に適合し得る TFT基板お よび表示デバイスを提供すること、および当該表示デバイスの製造に有用な A1系合 金薄膜形成用のスパッタリングターゲットを提供することにある。 [0037] The present invention has been made paying attention to such a situation, and the object thereof is to make it possible to omit the rare metal layer, simplify the process without increasing the number of steps, and conduct the A1 alloy film. Even when a lower heat treatment temperature is applied in a shorter time to an A1 alloy film that can be connected directly and securely to a transparent pixel electrode made of a conductive oxide film, the electrical resistivity between the transparent pixel electrodes can be reduced. It is an object of the present invention to provide a technique capable of achieving reduction and excellent heat resistance, and preferably excellent in dry etching property. Specifically, as a measure of electrical resistivity and heat resistance, the A1 system that does not cause defects such as hillocks even when heat treatment at a lower temperature, such as 220 ° CX for 20 minutes, is used in a shorter time. To provide TFT substrates and display devices that can further reduce the electrical resistivity of alloy thin films and can be adapted to lower processing temperatures, and for the formation of A1-based alloy thin films that are useful for the production of such display devices. It is providing the sputtering target of this.
[0038] 上記課題を解決することのできた本発明の表示デバイス用 A1合金膜は、基板上に て、導電性酸化膜に直接接続する表示デバイス用 A1合金膜であって、該 A1合金膜 は、 Geを 0. 05—0. 5原子%含有し、 Gdおよび/または Laを合計で 0. 05—0. 45 原子%含有するものである。 Gd、 Laは、それぞれ単独で 0. 05-0. 45原子%含有 されても良ぐ合計で 0. 05〜0. 45原子%含有されても良い。 [0038] The A1 alloy film for a display device of the present invention that has solved the above problems is an A1 alloy film for a display device that is directly connected to a conductive oxide film on a substrate, and the A1 alloy film is , Containing 0.5 to 0.5 atomic% of Ge, and containing 0.05 to 0.45 atomic% of Gd and / or La in total. Gd and La may be contained alone in an amount of 0.05-0.45 atomic%, or in total, 0.05 to 0.45 atomic%.
[0039] 上記課題を解決することのできた本発明の他の表示デバイス用 A1合金膜は、基板 上にて、非晶質 Si層または多結晶 Si層に直接接続する表示デバイス用 A1合金膜で あって、該 Al合金膜は、 Geを 0. 05-0. 5原子%含有し、 Gdおよび/または Laを 合計で 0. 05-0. 45原子%含有するものである。 Gd、 Laは、それぞれ単独で 0. 0[0039] Another display device A1 alloy film of the present invention that has solved the above problems is an A1 alloy film for display devices that is directly connected to an amorphous Si layer or a polycrystalline Si layer on a substrate. The Al alloy film contains 0.05 to 0.5 atomic percent of Ge and 0.05 to 0.45 atomic percent of Gd and / or La in total. Gd and La are each independently 0.0.
5〜0. 45原子%含有されても良ぐ合計で 0. 05-0. 45原子%含有されても良い。 It may be contained in an amount of 5 to 0.45% by atom, or it may be contained in a total amount of 0.05-0.45% by atom.
[0040] ここで、 Gdおよび/または Laを合計で 0. 05-0. 35原子0 /0含有する表示デバィ ス用 A1合金膜とすれば、ドライエッチング特性もさらに高められるようになる。 [0040] Here, if Gd and / or La 0. The total 05-0. 35 atoms 0/0 containing display Debai A1 alloy film for a scan, so that dry etching characteristics is further enhanced.
[0041] 上記表示デバイス用 A1合金膜は、更に Niを 0. 05-0. 35原子%含有し、かつ、 G eと Niの含有量の合計が 0. 45原子%以下となるように調整されることが推奨される。 [0041] The A1 alloy film for display device described above is further adjusted to contain 0.05 to 0.5 to 35 atomic% of Ni and the total content of Ge and Ni to 0.45 atomic% or less. It is recommended that
[0042] 上記課題を解決することのできた本発明の表示デバイスは、上記した A1合金膜と、 薄膜トランジスタとを有するものである。 [0042] A display device of the present invention that has solved the above-described problems includes the above-described A1 alloy film and a thin film transistor.
[0043] 上記課題を解決することのできた本発明の他の表示デバイスは、上記した A1合金 膜が、薄膜トランジスタのゲート電極および走査線に用いられ、導電性酸化膜に直接 接続されたものである。 [0043] Another display device of the present invention that has solved the above-described problem is one in which the above-described A1 alloy film is used for a gate electrode and a scanning line of a thin film transistor and is directly connected to a conductive oxide film. .
[0044] 上記課題を解決することのできた本発明の他の表示デバイスは、上記した A1合金 膜力 薄膜トランジスタのソース電極および/またはドレイン電極および信号線に用 いられ、導電性酸化膜および/または非晶質 Si層もしくは多結晶 Si層に直接接続さ れたものである。 [0044] Another display device of the present invention capable of solving the above-described problems is used for the source electrode and / or drain electrode and signal line of the above-described A1 alloy film force thin film transistor, and a conductive oxide film and / or It is directly connected to an amorphous Si layer or a polycrystalline Si layer.
[0045] 前記薄膜トランジスタのソース電極および/またはドレイン電極および信号線が、 前記薄膜トランジスタのゲート電極および走査線と同一の材料で形成される構成が 推奨される。 A configuration in which the source electrode and / or the drain electrode and the signal line of the thin film transistor are formed of the same material as the gate electrode and the scanning line of the thin film transistor is recommended.
[0046] 前記導電性酸化膜は、酸化インジウム、酸化亜鉛、酸化スズ及び酸化チタンからな る群から選ばれる少なくとも一種を含む複合酸化物で形成されることが好ましい。 [0046] The conductive oxide film is preferably formed of a composite oxide containing at least one selected from the group consisting of indium oxide, zinc oxide, tin oxide, and titanium oxide.
[0047] 表示デバイス用 A1合金膜の電気抵抗率が 4. 5 μ Ω ' cm以下であることが好ましい[0047] The electrical resistivity of the A1 alloy film for display devices is preferably 4.5 μΩ 'cm or less.
〇 Yes
[0048] 上記課題を解決することのできた本発明のスパッタリングターゲットは、 Geを 0. 05 〜0. 5原子%含有し、 Gdおよび/または Laを合計で 0. 05-0. 45原子%含有す るものである。 Gd、 Laは、それぞれ単独で 0. 05-0. 45原子%含有されても良ぐ 合計で 0. 05〜0. 45原子%含有されても良い。 [0048] The sputtering target of the present invention that has solved the above-mentioned problems contains Ge in a range of 0.05 to 0.5 atomic%, and Gd and / or La in a total amount of 0.05 to 0.45 atomic%. It is something. Gd and La may be contained alone in an amount of 0.05-0.45 atomic percent, or a total of 0.05 to 0.45 atomic percent may be contained.
[0049] 上記スパッタリングターゲットは、更に Niを 0· 05—0. 35原子0 /0含有し、かつ、 Ge と Niの含有量が合計で 0. 45原子%以下となるように調整されることが推奨される。 [0049] The above sputtering target is further a 0-05-0. 35 atoms 0/0 containing Ni, and, Ge It is recommended that the content of Ni and Ni be adjusted to 0.45 atomic% or less.
[0050] 本発明によれば、バリアメタル層を介在させずに、 A1合金膜を導電性酸化膜からな る透明画素電極と直接接続することができ、且つ、約 220°Cといった比較的低い熱 処理温度を適用した場合でも十分に低い電気抵抗率と優れた耐熱性とが確保され た表示デバイス用 A1合金膜や、これを用いた表示デバイスを提供することができる。 上記の熱処理温度とは、例えば TFT (薄膜トランジスタ)アレイの製造工程で最も高 温となる熱処理温度を指し、一般的な表示デバイスの製造工程においては、各種薄 膜形成のための CVD成膜時の基板の加熱温度や、保護膜を熱硬化させる際の熱 処理炉の温度などを意味する。 [0050] According to the present invention, the A1 alloy film can be directly connected to the transparent pixel electrode made of a conductive oxide film without interposing a barrier metal layer, and is relatively low at about 220 ° C. Even when the heat treatment temperature is applied, an A1 alloy film for display devices in which sufficiently low electrical resistivity and excellent heat resistance are ensured, and a display device using the same can be provided. The above heat treatment temperature refers to the highest heat treatment temperature in a TFT (thin film transistor) array manufacturing process, for example, and in a general display device manufacturing process, a CVD film for forming various thin films is formed. It means the heating temperature of the substrate and the temperature of the heat treatment furnace when the protective film is thermally cured.
[0051] 例えば、本発明に用いられる A1合金膜をソース-ドレイン電極の配線材料に適用す れば、図 2に示すバリアメタル層 54を省略することができる。また、本発明に用いられ る A1合金膜をゲート電極ならびにその配線材料に適用すれば、図 2に示すバリアメタ ル層 51、 52を省略すること力 Sできる。 For example, if the A1 alloy film used in the present invention is applied to the wiring material of the source-drain electrode, the barrier metal layer 54 shown in FIG. 2 can be omitted. Further, if the A1 alloy film used in the present invention is applied to the gate electrode and its wiring material, it is possible to omit the barrier metal layers 51 and 52 shown in FIG.
[0052] 更に、 Gdおよび/または Laの含有量を制御することにより、上記特性に加えて、ド ライエッチング生も更に高められるようになる。 [0052] Further, by controlling the content of Gd and / or La, in addition to the above characteristics, dry etching can be further enhanced.
[0053] 本発明の表示デバイス用 A1合金膜を用いれば、生産性に優れ、安価で且つ高性 能の表示デバイスが得られる。 [0053] If the A1 alloy film for display devices of the present invention is used, a display device having excellent productivity, low cost and high performance can be obtained.
図面の簡単な説明 Brief Description of Drawings
[0054] [図 1]図 1は、アモルファスシリコン TFT基板が適用される代表的な液晶ディスプレイ の構成を示す概略断面拡大説明図である。 [0054] FIG. 1 is an enlarged schematic cross-sectional explanatory view showing a configuration of a typical liquid crystal display to which an amorphous silicon TFT substrate is applied.
[図 2]図 2は、従来の代表的なアモルファスシリコン TFT基板の構成を示す概略断面 説明図である。 [FIG. 2] FIG. 2 is a schematic cross-sectional explanatory view showing a configuration of a conventional typical amorphous silicon TFT substrate.
[図 3]図 3は、本発明の第 1の実施形態に係る TFT基板の構成を示す概略断面説明 図である。 FIG. 3 is a schematic cross-sectional explanatory view showing the configuration of the TFT substrate according to the first embodiment of the present invention.
[図 4]図 4は、図 3に示した TFT基板の製造工程の一例を、順番を追って示す説明図 である。 FIG. 4 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.
[図 5]図 5は、図 3に示した TFT基板の製造工程の一例を、順番を追って示す説明図 である。 [図 6]図 6は、図 3に示した TFT基板の製造工程の一例を、順番を追って示す説明図 である。 FIG. 5 is an explanatory view showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 3. FIG. 6 is an explanatory view showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 3.
[図 7]図 7は、図 3に示した TFT基板の製造工程の一例を、順番を追って示す説明図 である。 FIG. 7 is an explanatory view showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 3.
[図 8]図 8は、図 3に示した TFT基板の製造工程の一例を、順番を追って示す説明図 である。 FIG. 8 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.
[図 9]図 9は、図 3に示した TFT基板の製造工程の一例を、順番を追って示す説明図 である。 FIG. 9 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.
[図 10]図 10は、図 3に示した TFT基板の製造工程の一例を、順番を追って示す説明 図である。 FIG. 10 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.
園 11]図 11は、図 3に示した TFT基板の製造工程の一例を、順番を追って示す説明 図である。 11] FIG. 11 is an explanatory diagram showing an example of the manufacturing process of the TFT substrate shown in FIG. 3 in order.
園 12]図 12は、本発明の第 2の実施形態に係る TFT基板の構成を示す概略断面説 明図である。 12] FIG. 12 is a schematic cross-sectional explanatory view showing the configuration of the TFT substrate according to the second embodiment of the present invention.
[図 13]図 13は、図 12に示した TFT基板の製造工程の一例を、順番を追って示す説 明図である。 FIG. 13 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG.
[図 14]図 14は、図 12に示した TFT基板の製造工程の一例を、順番を追って示す説 明図である。 FIG. 14 is an explanatory diagram showing an example of the manufacturing process of the TFT substrate shown in FIG. 12 in order.
[図 15]図 15は、図 12に示した TFT基板の製造工程の一例を、順番を追って示す説 明図である。 FIG. 15 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 12.
[図 16]図 16は、図 12に示した TFT基板の製造工程の一例を、順番を追って示す説 明図である。 FIG. 16 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG.
[図 17]図 17は、図 12に示した TFT基板の製造工程の一例を、順番を追って示す説 明図である。 FIG. 17 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 12.
[図 18]図 18は、図 12に示した TFT基板の製造工程の一例を、順番を追って示す説 明図である。 FIG. 18 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 12.
[図 19]図 19は、図 12に示した TFT基板の製造工程の一例を、順番を追って示す説 明図である。 [図 20]図 20は、 Al合金膜と透明導電膜との間のコンタクト抵抗率 (接続抵抗率)の測 定に用いたケルビンパターン (TEGパターン)を示す図である。 FIG. 19 is an explanatory diagram showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 12. FIG. 20 is a diagram showing a Kelvin pattern (TEG pattern) used for measurement of contact resistivity (connection resistivity) between an Al alloy film and a transparent conductive film.
[図 21]図 21は、 A1合金膜と透明導電膜との間のコンタクト抵抗率を示す図である。 FIG. 21 is a view showing a contact resistivity between an A1 alloy film and a transparent conductive film.
[図 22]図 22は、 A1合金膜の加熱処理時間と電気抵抗率との相関を示す図である。 FIG. 22 is a diagram showing the correlation between the heat treatment time of the A1 alloy film and the electrical resistivity.
[図 23]図 23は、 Siダイレクトコンタクト特性の評価用 TEGを示す図である。 FIG. 23 is a diagram showing a TEG for evaluation of Si direct contact characteristics.
[図 24]図 24は、 TFTのドレイン電流-ゲート電圧スイッチング特性を示す図である。 FIG. 24 is a graph showing the drain current-gate voltage switching characteristics of a TFT.
[図 25]図 25は、実施例で用いたドライエッチング用装置の概略図である。 FIG. 25 is a schematic view of a dry etching apparatus used in Examples.
[図 26]図 26は、実施例 6において、エッチング時間と、エッチング後の純 A1膜または FIG. 26 shows the etching time and the pure A1 film after etching in Example 6
A1合金膜の厚さとの関係をグラフ化したものである。 This is a graph of the relationship with the thickness of the A1 alloy film.
[図 27]図 27は、実施例 7において、 A1合金膜中の Ge量とエッチングレート比との関 係をグラフ化したものである。 FIG. 27 is a graph showing the relationship between the Ge amount in the A1 alloy film and the etching rate ratio in Example 7.
[図 28]図 28は、実施例 7において、 A1合金膜中の Gd量 /La量とエッチングレート比 との関係をグラフ化したものである。 FIG. 28 is a graph showing the relationship between the amount of Gd / La in the A1 alloy film and the etching rate ratio in Example 7.
[図 29]図 29は、実施例 7において、 A1合金膜中の Ni量とエッチングレート比との関係 をグラフ化したものである。 FIG. 29 is a graph showing the relationship between the amount of Ni in the A1 alloy film and the etching rate ratio in Example 7.
符号の説明 Explanation of symbols
1 TFT基板 1 TFT substrate
2対向基板 2 Counter substrate
3液晶層 3 liquid crystal layer
4薄膜トランジスタ (TFT) 4 Thin film transistor (TFT)
5透明画素電極 5 Transparent pixel electrode
6配線部 6 Wiring section
7共通電極 7 Common electrode
8カラーフィノレタ 8 color finoleta
9遮光膜 9 Shading film
10a, 10b偏光板 10a, 10b polarizing plate
11配向膜 11 Alignment film
12 TABテープ ドライバ回路 12 TAB tape Driver circuit
制御回路 Control circuit
スぺーサー Spacer
シール材 Sealing material
保護膜 Protective film
拡散板 Diffusion plate
プリズムシート Prism sheet
導光板 Light guide plate
反射板 a reflector
ノ ックライト Knock light
保持フレーム Holding frame
プリント基板 Printed board
走査線 Scan line
ゲート電極 Gate electrode
ゲート絶縁膜 Gate insulation film
ソース電極 Source electrode
ドレイン電極 Drain electrode
保護膜 (シリコン窒化膜) Protective film (silicon nitride film)
フォトレジスト Photoresist
コンタクトホーノレ Contact Honoré
アモルファスシリコンチャネル膜 (活性半導体膜) 信号線(ソース-ドレイン配線) Amorphous silicon channel film (active semiconductor film) Signal line (source-drain wiring)
、 52、 53、 54 ノ リアメタノレ層 52, 53, 54 Nolia methanol layer
ノンドーピング水素化アモルファスシリコン膜(a-Sト H) n+型水素化アモルファスシリコン膜 (n+a-Sト H) チャンバ Non-doped hydrogenated amorphous silicon film (aS to H) n + type hydrogenated amorphous silicon film (n + aS to H) Chamber
誘電窓 Dielectric window
アンテナ 64高周波電力(アンテナ側) antenna 64 high frequency power (antenna side)
65整合器 (アンテナ側) 65 matcher (antenna side)
66プロセスガス導入口 66 Process gas inlet
67基板(被エッチング材) 67 substrate (material to be etched)
68サセプタ 68 Susceptor
69誘電チャック 69 dielectric chuck
70カラー 70 colors
71整合器 (基板側) 71 Matching device (board side)
72高周波電力(基板側) 72 high frequency power (board side)
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
[0056] 本発明者は、導電性酸化膜からなる透明画素電極や、薄膜トランジスタのソース、 ドレイン、ゲートといった各電極と直接接続することができ、し力、も、約 220°Cといった 比較的低!/、熱処理温度を施した場合でも十分に低!/、電気抵抗率と優れた耐熱性と を兼ね備えており、好ましくは、ドライエッチング性にも優れた新規な配線材料を提供 するため、鋭意検討してきた。特に、本発明者は、前述した特開 2006-261636号 公報に記載された熱処理条件よりも一層低温、短時間の条件であっても、 A1系合金 薄膜における電気抵抗率をより一層低減させると共に、耐熱性をより一層改善すると いう観点に基づき、検討を重ねてきた。その結果、特開 2006-261636号公報に記 載されたグループ αに属する合金成分の中でも特に Geを特定の範囲で含有し、か つ、第 3成分として Gdおよび/または Laを所定量用いれば、所期の目的を達成でき ることを見出し、本発明を完成した。 [0056] The present inventor can directly connect to a transparent pixel electrode made of a conductive oxide film and each electrode such as a source, drain, and gate of a thin film transistor, and has a relatively low force of about 220 ° C. ! /, Low enough even when heat treatment temperature is applied! /, Which has both electrical resistivity and excellent heat resistance, and preferably eagerly to provide a new wiring material with excellent dry etching properties I have been considering it. In particular, the inventor further reduces the electrical resistivity in the A1-based alloy thin film even under conditions of lower temperature and shorter time than the heat treatment conditions described in the above-mentioned JP-A-2006-261636. Based on the viewpoint of further improving the heat resistance, studies have been repeated. As a result, among the alloy components belonging to group α described in JP-A-2006-261636, in particular, Ge is contained in a specific range, and a predetermined amount of Gd and / or La is used as the third component. The inventors have found that the intended purpose can be achieved and completed the present invention.
[0057] 本発明によれば、 A1合金膜中に合金成分として Geを所定量含有しているため、 A1 合金膜を形成した後のプロセスにおける熱処理が比較的低温でかつ短時間であつ ても、 A1合金膜と透明画素電極や、薄膜トランジスタのソース'ドレイン 'ゲートといつ た各電極との間のコンタクト抵抗を低く抑えることができる。また、後述するように、 Ge を添加した A1合金膜は、特開 2006-261636号公報に記載されたグループ αに含 まれる、 Ni, Ag, Zn, Cuを添加した A1合金膜に比べてコンタクト抵抗のばらつきが 少ない。 [0058] 更に、本発明によれば、 A1合金膜中に耐熱性向上元素として、 Gdおよび/または Laを所定量含有しているため、 220°C〜300°Cの加熱処理によってもヒロック等を生 じることのない優れた耐熱性を確保できる。また、 Gdおよび/または Laの含有量や、 Niの含有量を適切に制御すれば、ドライエッチング性も高められるようになる。 [0057] According to the present invention, since a predetermined amount of Ge is contained as an alloy component in the A1 alloy film, the heat treatment in the process after the formation of the A1 alloy film is performed at a relatively low temperature for a short time. The contact resistance between the A1 alloy film and the transparent pixel electrode and the source “drain” gate of the thin film transistor and each electrode can be kept low. Further, as will be described later, the A1 alloy film to which Ge is added is compared with the A1 alloy film to which Ni, Ag, Zn, and Cu are added, which is included in the group α described in JP-A-2006-261636. There is little variation in contact resistance. [0058] Further, according to the present invention, since a predetermined amount of Gd and / or La is contained in the A1 alloy film as a heat resistance improving element, hillocks and the like can be obtained even by heat treatment at 220 ° C to 300 ° C. Excellent heat resistance can be ensured without generating heat. In addition, if the Gd and / or La content and the Ni content are appropriately controlled, the dry etching property can be improved.
[0059] 従って、本発明によれば、充分に低!/、電気抵抗率と十分に高!/、耐熱性とを兼ね備 えており、好ましくは、ドライエッチング性にも優れた、透明画素電極と直接接続し得 る配線材料を提供することができる。 Therefore, according to the present invention, the transparent pixel electrode having both sufficiently low! /, Electrical resistivity and sufficiently high // heat resistance, and preferably excellent in dry etching property. It is possible to provide a wiring material that can be directly connected to the wiring.
[0060] 本明細書における「ドライエッチング」とは、エッチング対象物(層間絶縁膜)の除去 を意味するほか、コンタクトホールが A1合金膜に達した後でも、 A1合金膜の表面清浄 化の目的で、 A1合金膜の表面をエッチングガスに曝すことも意味している。 [0060] In this specification, "dry etching" means removal of an object to be etched (interlayer insulating film), and the purpose of cleaning the surface of the A1 alloy film even after the contact hole reaches the A1 alloy film. This also means that the surface of the A1 alloy film is exposed to an etching gas.
[0061] 本明細書において、「ドライエッチング性に優れている」とは、(ァ)エッチング後の残 渣の発生量が少なぐ且つ、(ィ)エッチングレート比が高いことを意味している。具体 的には、後記する実施例に記載の方法によって上記(ァ)および (ィ)の特性を評価し たとき、(ァ)エッチング後の残渣が発生せず、(ィ)エッチングレート比が 0. 3以上を 満足するものを、「ドライエッチング性に優れる」と呼ぶ。これらの特性を満足するもの は、ドライエッチング性に優れているため、配線寸法'形状の緻密な制御を精度良く fiうこと力 Sでさる。 In the present specification, “excellent in dry etching property” means (a) a small amount of residue generated after etching and (i) a high etching rate ratio. . Specifically, when the above characteristics (a) and (i) were evaluated by the method described in the examples described later, (a) no residue was generated after etching, and (i) the etching rate ratio was 0. Those that satisfy 3 or more are called “excellent dry etching”. Those satisfying these characteristics are excellent in dry etching properties, so the precise control of the wiring dimensions' shape can be achieved with the force S.
[0062] ここで、「エッチングレート比」は、プラズマ照射による A1合金薄膜のエッチングされ 易さの指標である。本明細書において、エッチングレート比は、エッチングレートが良 好な純 A1のエッチングレートを基準にしたときの A1合金膜のエッチングレートの比( すなわち、 A1合金膜のエッチングレートを Nl、純 A1のエッチングレートを N2としたと き、 N1/N2の比)で表される。エッチングレート比が高いほど、ドライエッチング処理 時間が短縮され、生産性が高められる。 Here, the “etching rate ratio” is an index of the ease of etching of the A1 alloy thin film by plasma irradiation. In this specification, the etching rate ratio is the ratio of the etching rate of the A1 alloy film based on the etching rate of pure A1 with a good etching rate (that is, the etching rate of the A1 alloy film is Nl, When the etching rate is N2, the ratio is expressed as the ratio of N1 / N2. The higher the etching rate ratio, the shorter the dry etching processing time and the higher the productivity.
[0063] まず、本発明の A1合金膜中に用いられる Geの作用について説明する。 [0063] First, the action of Ge used in the A1 alloy film of the present invention will be described.
[0064] Geは、特に、 A1合金膜と透明画素電極とのコンタクト抵抗を低減するのに有用であ る。具体的には、 Geを、 0. 05-0. 5原子%の範囲で添加する。 Geの含有量を 0. 0 5原子%以上としたのは、コンタクト抵抗低減効果を発揮するためである。好ましくは 0. 07原子%以上、より好ましくは 0. 1原子%以上である。一方、 Geの含有量を 0. 5 原子%以下としたのは、 Al合金膜の電気抵抗率が高くなり過ぎないようにするためで ある。好ましくは 0. 4原子%以下、より好ましくは 0. 3原子%以下である。 [0064] Ge is particularly useful for reducing the contact resistance between the A1 alloy film and the transparent pixel electrode. Specifically, Ge is added in the range of 0.05 to 0.5 atomic%. The reason why the Ge content is 0.05 atomic% or more is to exhibit the effect of reducing contact resistance. Preferably it is 0.07 atomic% or more, More preferably, it is 0.1 atomic% or more. On the other hand, the Ge content is 0.5 The reason for not more than atomic% is to prevent the electrical resistivity of the Al alloy film from becoming too high. Preferably it is 0.4 atomic% or less, more preferably 0.3 atomic% or less.
[0065] ここで、 Geが A1合金膜の電気抵抗に及ぼす影響についてもう少し詳しく述べる。 [0065] Here, the effect of Ge on the electrical resistance of the A1 alloy film will be described in a little more detail.
A1合金膜に Geを添加すると、比較的低い熱処理温度で、 A1合金膜と透明画素電 極との接続界面に、 Geを含む析出物 (Ge含有析出物)もしくは濃化層(Ge含有濃化 層)が形成されるため、後記する実施例に示すように、 220°Cで 10分間熱処理したと きの電気抵抗率を、おおむね、 4. 5 Ω 'cm以下に低減することができる。 When Ge is added to the A1 alloy film, a Ge-containing precipitate (Ge-containing precipitate) or a concentrated layer (Ge-containing concentrated) is formed at the connection interface between the A1 alloy film and the transparent pixel electrode at a relatively low heat treatment temperature. Therefore, as shown in the examples described later, the electrical resistivity when heat-treated at 220 ° C. for 10 minutes can be reduced to approximately 4.5 Ω′cm or less.
[0066] また、後記する実施例に示すように、 Geが上記範囲内であれば、ドライエッチング 十生も良好である。 [0066] Further, as shown in the examples described later, if Ge is within the above range, dry etching can be performed well.
[0067] ここで、「Ge含有析出物」とは、 Geが析出した析出物を意味し、例えば、 Al-Ge-G d合金もしくは A Ge-La合金もしくは Al-Ge-Gd-La合金に含まれる Ge単体、また は A1と Geと Gdとの金属間化合物もしくは A1と Geと Laとの金属間化合物、もしくは A1 と Geと Gdと Laとの金属間化合物が挙げられる。 [0067] Here, the "Ge-containing precipitate" means a precipitate in which Ge is precipitated, for example, an Al-Ge-Gd alloy, an A Ge-La alloy, or an Al-Ge-Gd-La alloy. Examples include Ge alone, an intermetallic compound of A1, Ge, and Gd, an intermetallic compound of A1, Ge, and La, or an intermetallic compound of A1, Ge, Gd, and La.
[0068] また、「Ge含有濃化層」とは、当該 Ge濃化層中の Geの平均濃度が、 Al-Ge-Gd合 金中または A Ge-La合金中もしくは Al-Ge-Gd-La合金中の Geの平均濃度の 2倍 以上はり好ましくは 2. 5倍以上)であるものを意味する。 [0068] In addition, the "Ge-containing concentrated layer" means that the average concentration of Ge in the Ge concentrated layer is Al-Ge-Gd alloy, A Ge-La alloy or Al-Ge-Gd- This means that the average concentration of Ge in the La alloy is 2 times or more, preferably 2.5 times or more.
[0069] なお、 Geを含有する A1合金膜では、熱処理などによって A1合金膜中の Geの固溶 限(0. 1原子%)を超える Geが A1合金膜の粒界に析出し、その一部が A1合金膜の 表面に拡散 ·濃縮して Ge濃化層が形成されることがある。このような Ge濃化層も、上 記「Ge含有濃化層」のなかに含まれる。また、例えば、コンタクトホールのエッチング を行う際、 Geのハロゲン化合物は A1よりも蒸気圧が低いため揮発し難ぐ A1合金膜 の表面に残留した状態となり、当該合金膜表層部の Geの濃度は A1系合金バルク材 の Geの濃度よりも高濃度状態となる。このような態様も、上記「Ge含有濃化層」のな かに含まれる。なお、エッチング条件を適切に制御することにより、 A1系合金薄膜表 層部の Geの濃度や Ge含有濃化層の厚さは変化する。このとき、第三成分として用い る Gd、或いは、 Laによっては、その一部が表層側に濃化されることがある力 その様 な態様も、上記の「Ge含有濃化層」のなかに含まれる。 [0069] In the A1 alloy film containing Ge, Ge exceeding the solid solubility limit (0.1 atomic%) of Ge in the A1 alloy film is precipitated at the grain boundary of the A1 alloy film by heat treatment or the like. The Ge may be diffused and concentrated on the surface of the A1 alloy film to form a Ge-enriched layer. Such a Ge enriched layer is also included in the “Ge-containing enriched layer”. Also, for example, when etching contact holes, the Ge halogen compound remains on the surface of the A1 alloy film, where the vapor pressure is lower than that of the A1, and it is difficult to volatilize. It is in a higher concentration state than the Ge concentration of A1 alloy bulk material. Such an embodiment is also included in the “Ge-containing concentrated layer”. By appropriately controlling the etching conditions, the Ge concentration of the A1 alloy thin film surface layer and the thickness of the Ge-containing concentrated layer change. At this time, depending on Gd or La used as the third component, part of the force may be concentrated on the surface layer side. Such a mode is also included in the above-mentioned “Ge-containing concentrated layer”. included.
[0070] 上記の Ge含有濃化層の厚さは、 0. 5nm以上、 10nm以下であることが好ましぐ 1 . Onm以上、 5nm以下であることがより好ましい。 [0070] The thickness of the Ge-containing concentrated layer is preferably 0.5 nm or more and 10 nm or less. More preferably, it is not less than Onm and not more than 5 nm.
[0071] なお、以下に示すように、 220°Cで 10分熱処理した後の Al-Ge合金の 2元系合金 の電気抵抗率は非常に低ぐ当該 Al-Ge合金中に第 3成分を更に添加すると、電気 抵抗率は、上昇する傾向にある。従って、電気抵抗率の低減のみを目的とする場合 は、 Al_Ge合金の 2元系合金を利用すればよいが、前述したとおり、耐熱性は、約 15 0°C程度と低くなる。従って、本発明のように低い電気抵抗率と高い耐熱性とを兼ね 備えた配線材料の提供を目的とする場合は、 Al-Ge合金の 2元系合金では不十分 であり、以下に説明するように、 Al-Ge-Gd合金または Al-Ge-La合金の 3元系合金 、若しくは Al-Ge-Gd-La合金の 4元系合金を用いることにした。 [0071] As shown below, the electrical resistivity of the Al-Ge alloy binary alloy after heat treatment at 220 ° C for 10 minutes is very low. The third component is contained in the Al-Ge alloy. When further added, the electrical resistivity tends to increase. Therefore, when the purpose is only to reduce the electrical resistivity, an Al_Ge alloy binary alloy may be used, but as mentioned above, the heat resistance is reduced to about 150 ° C. Therefore, for the purpose of providing a wiring material having both low electrical resistivity and high heat resistance as in the present invention, a binary alloy of Al-Ge alloy is insufficient, and will be described below. Thus, the ternary alloy of Al-Ge-Gd alloy or Al-Ge-La alloy or the quaternary alloy of Al-Ge-Gd-La alloy was used.
[0072] Al-Ge-Gd合金または Al-Ge-La合金の 3元系合金もしくは Al-Ge-Gd-La合金 の 4元系合金を用いることによって A1合金膜の耐熱性が著しく高められ、 A1合金膜の 表面にヒロックが形成されるのを有効に防止できる。耐熱性の効果を実効的に得るた めには、 Gd、 Laの含有量は、 0. 05原子%以上必要である。好ましくは、 0. 1原子% 以上である。一方、 Gd、 Laの含有量を多くしすぎると、 A1合金膜の電気抵抗率が上 力 Sつてしまうため、含有量の上限は、 0. 45原子%であり、より好ましくは 0. 4原子0 /0、 更に好ましくは 0. 3原子%である。これらの元素は、単独で添加しても良ぐ 2種以上 を併用してもよい。 2種以上の元素を添加するときは、各元素の合計の含有量が上記 範囲を満足すればよい。 [0072] By using an Al-Ge-Gd alloy, an Al-Ge-La alloy ternary alloy, or an Al-Ge-Gd-La alloy quaternary alloy, the heat resistance of the A1 alloy film is significantly improved. It is possible to effectively prevent hillocks from forming on the surface of the A1 alloy film. In order to effectively obtain the heat resistance effect, the content of Gd and La must be 0.05 atomic% or more. Preferably, it is 0.1 atomic% or more. On the other hand, if the content of Gd and La is excessively increased, the electrical resistivity of the A1 alloy film will increase, so the upper limit of the content is 0.45 atomic%, more preferably 0.4 atomic percent. 0/0, more preferably from 0.3 atomic%. These elements may be added alone or in combination of two or more. When adding two or more elements, the total content of each element only needs to satisfy the above range.
[0073] なお、ドライエッチング性の向上を考慮すると、 Gdおよび/または Laの含有量の上 限を 0. 35原子%とすることが好ましい。後記する実施例に示すように、 0. 35原子% を超えると、エッチングレート比が低下するほか、ドライエッチング後に残渣が発生す る恐れがあるからである。ドライエッチング性のみを考慮した場合には、 Gdおよび/ または Laの含有量の上限は少ない方が良い。 A1合金膜の電気抵抗率の低減、耐熱 性向上、ドライエッチング性向上をすベて実現させたい場合は、 Gdおよび/または L aの含有量を、おおむね、 0. 1原子%以上 0. 30原子%以下とすることがより好まし い。 [0073] In consideration of improvement in dry etching property, the upper limit of the content of Gd and / or La is preferably set to 0.35 atomic%. This is because, as shown in the examples described later, if it exceeds 0.35 atomic%, the etching rate ratio is lowered, and residues may be generated after dry etching. If only dry etching properties are considered, the upper limit of the content of Gd and / or La is better. If you want to reduce the electrical resistivity, improve the heat resistance, and improve the dry etching properties of the A1 alloy film, the Gd and / or La content should be approximately 0.1 atomic% or more. It is more preferable to make it atomic% or less.
[0074] さらに、 A Ge-Gd合金または AH^e-La合金の 3元系合金もしくは AH^e-Gd-L a合金の 4元系合金に、 Niを添加すると、 A1合金膜と透明画素電極、又は A1合金膜 とソース'ドレイン 'ゲートの各電極とのコンタクト抵抗を低減することができる。このよう な効果を発揮するためには、 Niを 0. 05原子%以上含有させることが好ましい。より 好ましくは、 0. 07原子%以上、さらに好ましくは、 0. 1原子%以上である。一方、 Ni の含有量が多くなりすぎると、 A1合金膜の電気抵抗率が増加してしまうため、 Ni含有 量の上限は、好ましくは 0. 35原子%、より好ましくは、 0. 3原子%、更に好ましくは、 0. 25原子%、更により好ましくは、 0. 20原子%である。 [0074] Furthermore, when Ni is added to the ternary alloy of A Ge-Gd alloy or AH ^ e-La alloy or the quaternary alloy of AH ^ e-Gd-La alloy, the A1 alloy film and transparent pixel Electrode or A1 alloy film And the contact resistance between each electrode of the source 'drain' gate can be reduced. In order to exert such an effect, it is preferable to contain 0.05 atomic% or more of Ni. More preferably, it is 0.07 atomic% or more, and still more preferably 0.1 atomic% or more. On the other hand, if the Ni content increases too much, the electrical resistivity of the A1 alloy film increases, so the upper limit of the Ni content is preferably 0.35 atomic%, more preferably 0.3 atomic%. More preferably, it is 0.25 atomic%, and still more preferably 0.20 atomic%.
[0075] また、 Ni量が上記範囲内であれば、エッチング後の残渣が発生せず、高いエッチ ングレート比が得られるため、優れたドライエッチング性が発揮される(後記する実施 例を参照)。 [0075] If the amount of Ni is within the above range, residues after etching are not generated, and a high etching rate ratio is obtained, so that excellent dry etching properties are exhibited (see Examples described later). .
[0076] また、 AH^e-Gd合金若しくは AH^e-La合金の 3元系合金、または Al-Ge-Gd-L a合金の 4元系合金のそれぞれが Niを含む場合、 Geと Niの含有量は合計で 0. ;!〜 0. 45原子%の範囲内であることが好ましい。 Geと Niの合計量が 0. 1原子%を下回 る場合、 A1合金膜と透明画素電極との間の接触電気抵抗を低く抑えることができず、 前述した Geおよび Niの作用が有効に発揮されない。一方、 Ge、 Niの単独の含有量 が前述した範囲を満足していても、 Geと Niの合計量が 0. 6原子%を超えると、エツ チングレート比が低下するようになる(後記する実施例を参照)。 Geと Niの合計量の 上限は 0. 35原子%であることがより好ましぐ 0. 30原子%以下であることが更に好 ましい。 [0076] Further, when each of the ternary alloy of AH ^ e-Gd alloy or AH ^ e-La alloy or the quaternary alloy of Al-Ge-Gd-La alloy contains Ni, Ge and Ni The total content of is preferably in the range of 0.;! To 0.45 atomic%. When the total amount of Ge and Ni is less than 0.1 atomic%, the contact electrical resistance between the A1 alloy film and the transparent pixel electrode cannot be kept low, and the above-described action of Ge and Ni becomes effective. It is not demonstrated. On the other hand, even if the single content of Ge and Ni satisfies the above-mentioned range, the etching rate ratio decreases when the total amount of Ge and Ni exceeds 0.6 atomic% (described later). See Examples). The upper limit of the total amount of Ge and Ni is more preferably 0.35 atomic%, even more preferably 0.30 atomic% or less.
[0077] 以下、図面を参照しながら、本発明に係る TFT基板の好ましい実施形態を説明す る。以下では、アモルファスシリコン TFT基板またはポリシリコン TFT基板を備えた液 晶表示装置を代表的に挙げて説明するが、本発明はこれに限定されず、前'後記の 趣旨に適合し得る範囲で適当に変更を加えて実施することも可能であり、それらはい ずれも本発明の技術的範囲に包含される。本発明に用いられる A1系合金膜は、例え ば、反射型液晶表示装置等の反射電極、外部への信号入出力のために使用される TAB (タブ)接続電極にも同様に適用できることを実験により確認している。 Hereinafter, preferred embodiments of the TFT substrate according to the present invention will be described with reference to the drawings. In the following, a liquid crystal display device including an amorphous silicon TFT substrate or a polysilicon TFT substrate will be described as a representative example, but the present invention is not limited to this, and is suitable within a range that can meet the purpose described above. It is also possible to carry out with modifications, and both of them are included in the technical scope of the present invention. The A1 alloy film used in the present invention is also applied to, for example, a reflective electrode such as a reflective liquid crystal display device and a TAB (tab) connecting electrode used for signal input / output to the outside. It is confirmed by.
[0078] (実施形態 1) (Embodiment 1)
図 3を参照しながら、アモルファスシリコン TFT基板の実施形態を詳細に説明する。 図 3は、本発明に係るボトムゲート型の TFT基板の好ましい実施形態を説明する概 略断面説明図である。図 3には、従来の TFT基板を示す前述した図 2と同じ参照番 号を付している。 An embodiment of an amorphous silicon TFT substrate will be described in detail with reference to FIG. FIG. 3 is a schematic diagram illustrating a preferred embodiment of a bottom-gate TFT substrate according to the present invention. FIG. In Fig. 3, the same reference numerals as those in Fig. 2 are given to indicate a conventional TFT substrate.
[0079] 図 2と図 3とを対比すると明らかなように、従来の TFT基板では、図 2に示すように、 走査線 25の上、ゲート電極 26の上、ソース一ドレイン配線 34の上または下に、それ ぞれ、ノ リアメタル層 51、 52、 54、 53が形成されているのに対し、本実施形態の TF T基板では、ノ リアメタル層 51、 52、 54を省略することができる。すなわち、本実施形 態によれば、従来のようにバリアメタル層を介在させることなぐ TFTのソース-ドレイ ン電極 29に用いられる配線材料を透明画素電極 5と直接接続することができ、これ によっても、従来の TFT基板と同程度以上の良好な TFT特性を実現できる(後記す る実施例を参照)。 [0079] As is apparent from the comparison between FIG. 2 and FIG. 3, in the conventional TFT substrate, as shown in FIG. 2, the top of the scanning line 25, the top of the gate electrode 26, the top of the source-drain wiring 34, or Below, the metal layers 51, 52, 54, and 53 are formed, respectively, whereas the metal layers 51, 52, and 54 can be omitted in the TFT substrate of the present embodiment. That is, according to the present embodiment, the wiring material used for the TFT source-drain electrode 29 without the barrier metal layer interposed as in the prior art can be directly connected to the transparent pixel electrode 5, thereby However, it can achieve good TFT characteristics equivalent to or better than those of conventional TFT substrates (see the examples below).
[0080] なお、本発明に用いられる配線材料は、本実施形態のように、ソース-ドレイン電極 およびゲート電極の配線材料に適用される。例えば、本発明の配線材料をゲート電 極の配線材料に適用すれば、ノ リアメタル層 51、 52を省略することができる。これら の実施形態にお!/、ても、従来の TFT基板と同程度以上の良好な TFT特性を実現で さることを確言忍している。 Note that the wiring material used in the present invention is applied to the wiring material of the source-drain electrode and the gate electrode as in this embodiment. For example, if the wiring material of the present invention is applied to a wiring material for a gate electrode, the noor metal layers 51 and 52 can be omitted. Even in these embodiments !, we are confident that we can achieve good TFT characteristics comparable to or better than conventional TFT substrates.
[0081] 次に、図 4から図 11を参照しながら、図 3に示す本発明に係るアモルファスシリコン TFT基板の製造方法の一例を説明する。ここでは、ソース-ドレイン電極およびその 配線に用いられる材料として、 A1-0. 2原子%06_0. 2原子%0(1合金を使用してい る。また、ゲート電極およびその配線に用いられる材料として、 A1-0. 2原子%06-0 . 35原子%0(1合金を使用している。薄膜トランジスタは、水素化アモルファスシリコ ンを半導体層として用いたアモルファスシリコン TFTである。図 4力、ら図 11には、図 3 と同じ参照符号を付している。 Next, an example of a method for manufacturing the amorphous silicon TFT substrate according to the present invention shown in FIG. 3 will be described with reference to FIGS. 4 to 11. Here, A1-0. 2 atomic% 06_0.2 atomic% 0 (1 alloy is used as the material used for the source-drain electrode and its wiring. Also, as the material used for the gate electrode and its wiring. A1-0. 2 atomic% 06- 0.35 atomic% 0 (1 alloy is used. The thin film transistor is an amorphous silicon TFT using hydrogenated amorphous silicon as the semiconductor layer. FIG. 11 has the same reference numerals as FIG.
[0082] まず、ガラス基板 (透明基板) laに、スパッタリング法を用いて、厚さ 200nm程度の A1-0. 2原子%06_0. 35原子%0(1合金を成膜する。スパッタリングの成膜温度は、 150°Cとした。この膜をパターユングすることにより、ゲート電極 26および走査線 25を 形成する(図 4を参照)。このとき、後記する図 5において、ゲート絶縁膜 27のカバレツ ジが良くなる様に、上記積層薄膜の周縁を約 30° 〜40° のテーパー状にエツチン グしておくのがよい。 [0083] 次いで、図 5に示すように、例えばプラズマ CVD法などの方法を用いて、厚さ約 30 Onm程度の酸化シリコン膜(SiOx)でゲート絶縁膜 27を形成する。プラズマ CVD法 の成膜温度は、約 350°Cとした。続いて、例えばプラズマ CVD法などの方法を用い て、ゲート絶縁膜 27の上に、厚さ 50nm程度の水素化アモルファスシリコン膜(a-Sト H) 55および厚さ 300nm程度の窒化シリコン膜(SiNx)を成膜する。 [0082] First, on a glass substrate (transparent substrate) la, a sputtering method is used to form an A1-0.2 atomic% 06_0.35 atomic% 0 (one alloy film having a thickness of about 200 nm. The temperature was set to 150 ° C. By patterning this film, the gate electrode 26 and the scanning line 25 were formed (see FIG. 4), in which case the coverage of the gate insulating film 27 in FIG. It is preferable to etch the peripheral edge of the laminated thin film into a taper of about 30 ° to 40 ° so that the die is improved. Next, as shown in FIG. 5, a gate insulating film 27 is formed with a silicon oxide film (SiOx) having a thickness of about 30 Onm by using a method such as a plasma CVD method. The deposition temperature for the plasma CVD method was about 350 ° C. Subsequently, using a method such as plasma CVD, a hydrogenated amorphous silicon film (aS to H) 55 having a thickness of about 50 nm and a silicon nitride film (SiNx) having a thickness of about 300 nm are formed on the gate insulating film 27. Is deposited.
[0084] 続いて、ゲート電極 26をマスクとする裏面露光により、図 6に示すように窒化シリコン 膜(SiNx)をパターユングし、チャネル保護膜を形成する。更にその上に、リンをドー ビングした厚さ 50nm程度の n+型水素化アモルファスシリコン膜(n+a-Sト H) 56を成 膜した後、図 7に示すように、水素化アモルファスシリコン膜(a-Sト H) 55および n+型 水素化アモルファスシリコン膜(n+a_Sト H) 56をパターユングする。 Subsequently, by backside exposure using the gate electrode 26 as a mask, a silicon nitride film (SiNx) is patterned as shown in FIG. 6 to form a channel protective film. Further, an n + type hydrogenated amorphous silicon film (n + aS to H) 56 having a thickness of about 50 nm doped with phosphorus is formed thereon, and then a hydrogenated amorphous silicon film (n aS to H) 55 and n + type hydrogenated amorphous silicon film (n + a_S to H) 56 are patterned.
[0085] 次に、その上に、スパッタリング法を用いて、厚さ 50nm程度の Mo膜 53と厚さ 300 nm程度の A O. 2原子0 /oGe_0. 2原子0 /0Gd合金膜 28, 29と厚さ 50nm程度の Mo 膜 (不図示)とを順次積層する。スパッタリングの成膜温度は、 150°Cとした。次いで、 図 8に示す様にパターユングすることにより、信号線と一体のソース電極 28と、画素 電極 5に直接接続されるドレイン電極 29とが形成される。更に、ソース電極 28および ドレイン電極 29をマスクとして、チャネル保護膜(SiNx)上の n+型水素化ァモルファ スシリコン膜 (n+a-Sト H) 56をドライエッチングして除去する。 [0085] Next, thereon by sputtering, the Mo film 53 and the thickness of about 300 nm thickness of about 50 nm A O. 2 atoms 0 / o Ge_0. 2 atoms 0/0 Gd alloy film 28 , 29 and a Mo film (not shown) having a thickness of about 50 nm are sequentially stacked. The deposition temperature for sputtering was 150 ° C. Next, by patterning as shown in FIG. 8, the source electrode 28 integrated with the signal line and the drain electrode 29 directly connected to the pixel electrode 5 are formed. Further, using the source electrode 28 and the drain electrode 29 as a mask, the n + type hydrogenated silicon silicon film (n + aS to H) 56 on the channel protective film (SiNx) is removed by dry etching.
[0086] 次に、図 9に示すように、例えばプラズマ CVD装置などを用いて、厚さ 300nm程度 の窒化シリコン膜 30を成膜し、保護膜を形成する。このときの成膜温度は、例えば 22 0°C程度で行なわれる。次いで、窒化シリコン膜 30上にフォトレジスト層 31を形成した 後、窒化シリコン膜 30をパターユングし、例えばドライエッチング等によって窒化シリ コン膜 30にコンタクトホール 32を形成する。同時に、パネル端部のゲート電極上の T ABとの接続に当たる部分にコンタクトホール (不図示)を形成する。 Next, as shown in FIG. 9, a silicon nitride film 30 having a thickness of about 300 nm is formed using a plasma CVD apparatus, for example, to form a protective film. The film formation temperature at this time is, for example, about 220 ° C. Next, after a photoresist layer 31 is formed on the silicon nitride film 30, the silicon nitride film 30 is patterned, and contact holes 32 are formed in the silicon nitride film 30 by, for example, dry etching. At the same time, a contact hole (not shown) is formed in a portion corresponding to the connection with TAB on the gate electrode at the end of the panel.
[0087] 次に、例えば酸素プラズマによるアツシング工程を経た後、図 10に示すように、例 えばアミン系等の剥離液を用いてフォトレジスト層 31を剥離する。最後に、例えば保 管時間(8時間程度)の範囲内で、図 11に示すように、例えば厚さ 40nm程度の ITO 膜を成膜し、ウエットエッチングによるパターユングを行うことによって透明画素電極 5 を形成する。同時に、パネル端部のゲート電極の TABとの接続部分に、 TABとのボ ンデイングのため ITO膜をパターユングすると、 TFTアレイ基板 1が完成する。 Next, after an ashing process using, for example, oxygen plasma, as shown in FIG. 10, the photoresist layer 31 is stripped using, for example, an amine-based stripping solution. Finally, for example, within the range of the storage time (about 8 hours), as shown in FIG. 11, an ITO film having a thickness of, for example, about 40 nm is formed and patterned by wet etching to form the transparent pixel electrode 5. Form. At the same time, connect the TAB to the TAB connection part of the gate electrode at the panel edge. The TFT array substrate 1 is completed by patterning the ITO film for indexing.
[0088] このようにして作製された TFT基板は、ドレイン電極 29と透明画素電極 5とが直接 コンタクトされており、またゲート電極 26と TAB接続用の ITO膜も直接コンタクトされ ている。 In the TFT substrate manufactured in this way, the drain electrode 29 and the transparent pixel electrode 5 are in direct contact, and the gate electrode 26 and the ITO film for TAB connection are also in direct contact.
[0089] 上記では、透明画素電極 5として、 ITO (酸化インジウムスズ)膜を用いた力、酸化ィ ンジゥム、酸化亜鉛、酸化スズ、酸化チタンの少なくとも一種を含む複合酸化物を用 いても良い。例えば、 IZO膜 (Ιηθχ-Ζηθχ系導電性酸化膜)を用いることもできる。 また、活性半導体層として、アモルファスシリコンの代わりにポリシリコンを用いてもよ V、(後記する実施形態 2を参照)。 In the above, as the transparent pixel electrode 5, a composite oxide containing at least one of a force using an ITO (indium tin oxide) film, indium oxide, zinc oxide, tin oxide, and titanium oxide may be used. For example, an IZO film (Ιηθχ-Ζηθχ-based conductive oxide film) can be used. Further, polysilicon may be used as the active semiconductor layer instead of amorphous silicon V (see Embodiment 2 described later).
[0090] このようにして得られる TFT基板を使用し、例えば、以下に記載の方法によって、 前述した図 1に示す液晶表示装置を完成させる。 Using the TFT substrate thus obtained, for example, the liquid crystal display device shown in FIG. 1 is completed by the method described below.
[0091] まず、上記のようにして作製した TFT基板 1の表面に、例えばポリイミドを塗布し、乾 燥してからラビング処理を行って配向膜を形成する。 First, for example, polyimide is applied to the surface of the TFT substrate 1 manufactured as described above, and after drying, a rubbing treatment is performed to form an alignment film.
[0092] 一方、対向基板 2は、ガラス基板上に、例えばクロム(Cr)をマトリックス状にパター ユングすることによって遮光膜 9を形成する。次に、遮光膜 9の間隙に、樹脂製の赤、 緑、青のカラーフィルタ 8を形成する。遮光膜 9とカラーフィルタ 8上に、 ITO膜のよう な透明導電性膜を共通電極 7として配置することによって対向電極を形成する。そし て、対向電極の最上層に例えばポリイミドを塗布し、乾燥した後、ラビング処理を行つ て配向膜 11を形成する。 On the other hand, the counter substrate 2 forms the light shielding film 9 on a glass substrate by patterning, for example, chromium (Cr) in a matrix. Next, resin red, green and blue color filters 8 are formed in the gaps between the light shielding films 9. A counter electrode is formed by disposing a transparent conductive film such as an ITO film as the common electrode 7 on the light shielding film 9 and the color filter 8. Then, for example, polyimide is applied to the uppermost layer of the counter electrode, and after drying, a rubbing process is performed to form the alignment film 11.
[0093] 次いで、 TFT基板 1と対向基板 2の配向膜 11が形成されている面とを夫々対向す るように配置し、樹脂製などのシール材 16により、液晶の封入口を除いて TFT基板 1 と対向基板 22枚とを貼り合わせる。このとき、 TFT基板 1と対向基板 2との間には、ス ぺーサ一 15を介在させるなどして 2枚の基板間のギャップを略一定に保つ。 [0093] Next, the TFT substrate 1 and the surface of the counter substrate 2 on which the alignment film 11 is formed are arranged so as to face each other, and the TFT is removed by a sealing material 16 made of resin, excluding the liquid crystal sealing port. Bond substrate 1 and 22 counter substrates. At this time, the gap between the two substrates is kept substantially constant by interposing a spacer 15 between the TFT substrate 1 and the counter substrate 2.
[0094] このようにして得られる空セルを真空中に置き、封入口を液晶に浸した状態で徐々 に大気圧に戻していくことにより、空セルに液晶分子を含む液晶材料を注入して液晶 層を形成し、封入口を封止する。最後に、空セルの外側の両面に偏光板 10を貼り付 けて液晶ディスプレイを完成させる。 [0094] The empty cell obtained in this way is placed in a vacuum, and gradually returned to atmospheric pressure with the sealing port immersed in liquid crystal, whereby a liquid crystal material containing liquid crystal molecules is injected into the empty cell. A liquid crystal layer is formed and the sealing port is sealed. Finally, a polarizing plate 10 is attached to both sides of the empty cell to complete the liquid crystal display.
[0095] 次に、図 1に示したように、液晶表示装置を駆動するドライバ回路 13を液晶ディスプ レイに電気的に接続し、液晶ディスプレイの側部あるいは裏面部に配置する。そして 、液晶ディスプレイの表示面となる開口を含む保持フレーム 23と、面光源をなすバッ クライト 22と導光板 20と保持フレーム 23によって液晶ディスプレイを保持し、液晶表 示装置を完成させる。 Next, as shown in FIG. 1, the driver circuit 13 for driving the liquid crystal display device is connected to the liquid crystal display. Electrically connected to the lay and placed on the side or back of the liquid crystal display. Then, the liquid crystal display is held by the holding frame 23 including the opening serving as the display surface of the liquid crystal display, the backlight 22 that forms the surface light source, the light guide plate 20, and the holding frame 23, thereby completing the liquid crystal display device.
[0096] (実施形態 2) [0096] (Embodiment 2)
図 12を参照しながら、ポリシリコン TFT基板の実施形態を詳細に説明する。 An embodiment of a polysilicon TFT substrate will be described in detail with reference to FIG.
図 12は、本発明に係るトップゲート型の TFT基板の好ましい実施形態を説明する 概略断面説明図である。図 12では、従来の TFT基板を示す前述した図 2と同じ参照 番号を付している。 FIG. 12 is a schematic cross-sectional explanatory view for explaining a preferred embodiment of a top gate type TFT substrate according to the present invention. In FIG. 12, the same reference numerals as those in FIG. 2 described above showing the conventional TFT substrate are attached.
[0097] 本実施形態は、活性半導体層として、アモルファスシリコンの代わりにポリシリコンを 用いた点、ボトムゲート型ではなくトップゲート型の TFT基板を用いた点、及びソース -ドレイン電極およびゲート電極の配線材料としてではなくソース-ドレイン電極の配 線材料として、本発明の要件を満足する A1-0. 2原子%06_0. 2原子%0(1合金を 用いた点において、前述した実施形態 1と、主に相違している。詳細には、図 12に示 す本実施形態のポリシリコン TFT基板では、活性半導体膜は、リンがドープされてい ないポリシリコン膜(poly-Si)とリンもしくはヒ素(As)がイオン注入されたポリシリコン 膜 (η+poly-Si)とから形成されている点で、前述した図 3に示すアモルファスシリコン TFT基板と相違する。また、信号線は、層間絶縁膜 (SiOx)を介して走査線と交差す るように形成されている。 In this embodiment, polysilicon is used instead of amorphous silicon as an active semiconductor layer, a top gate type TFT substrate is used instead of a bottom gate type, and source-drain electrodes and gate electrodes are used. A1-0. 2 atomic% 06_0.2 atomic% 0 (one alloy is used in the point that the alloy is used as the wiring material of the source-drain electrode instead of the wiring material, which satisfies the requirements of the present invention. Specifically, in the polysilicon TFT substrate of this embodiment shown in FIG. 12, the active semiconductor film is composed of a polysilicon film (poly-Si) that is not doped with phosphorus and phosphorus or arsenic. This is different from the amorphous silicon TFT substrate shown in Fig. 3 described above in that (As) is formed from a polysilicon film (η + poly-Si) into which ions are implanted. Run through (SiOx) It is formed in so that to intersect the line.
[0098] 本実施形態によれば、ノ リアメタル層 54を省略することができる。すなわち、従来の ようにバリアメタル層を介在させることなぐ TFTのソース-ドレイン電極 29に用いられ る配線材料を透明画素電極 5と直接接続することができ、これによつても、従来の TF T基板と同程度以上の良好な TFT特性を実現できることを実験によって確認してい According to the present embodiment, the near metal layer 54 can be omitted. That is, the wiring material used for the TFT source-drain electrode 29 without the barrier metal layer interposed can be directly connected to the transparent pixel electrode 5 as in the prior art. Experiments have confirmed that good TFT characteristics equivalent to or higher than those of the substrate can be achieved.
[0099] 本実施形態において、上記の合金をゲート電極の配線材料に適用すれば、ノ リア メタル層 51、 52を省略すること力 Sできる。また、上記の合金をソース-ドレイン電極お よびゲート電極の配線材料に適用すれば、ノ リアメタル層 51、 52、 54を省略すること ができる。これらにおいても、従来の TFT基板と同程度以上の良好な TFT特性を実 現でさることを確言忍して!/、る。 In the present embodiment, if the above alloy is applied to the wiring material of the gate electrode, the force S for omitting the rare metal layers 51 and 52 can be achieved. In addition, if the above alloy is applied to the wiring material of the source-drain electrode and the gate electrode, the rare metal layers 51, 52, and 54 can be omitted. Even in these cases, good TFT characteristics equivalent to or better than those of conventional TFT substrates were achieved. Be patient with what you are doing!
[0100] 次に、図 13から図 19を参照しながら、図 12に示す本発明に係るポリシリコン TFT 基板の製造方法の一例を説明する。ここでは、ソース-ドレイン電極ならびにその配 線材料として、 A1-0. 2原子%06_0. 2原子%0(1合金を使用している。薄膜トランジ スタは、ポリシリコン膜 (poly-Si)を半導体層として用いたポリシリコン TFTである。図 13から図 19には、図 12と同じ参照符号を付している。 [0100] Next, an example of a method for manufacturing the polysilicon TFT substrate according to the present invention shown in FIG. 12 will be described with reference to FIGS. Here, A1-0.2 atom% 06_0.2 atom% 0 (1 alloy is used as the source-drain electrode and its wiring material. The thin film transistor is made of a polysilicon film (poly-Si). This is a polysilicon TFT used as a semiconductor layer, and the same reference numerals as those in FIG.
[0101] まず、ガラス基板 la上に、例えばプラズマ CVD法などにより、基板温度約 300°C程 度で、厚さ 50nm程度の窒化シリコン膜(SiNx)、厚さ lOOnm程度の酸化シリコン膜 (SiOx)、および厚さ約 50nm程度の水素化アモルファスシリコン膜(a-Si-H)を成膜 する。次に、水素化アモルファスシリコン膜(a-Si-H)をポリシリコン化するため、熱処 理 (約 470°Cで 1時間程度)およびレーザーァニールを行う。脱水素処理を行った後 、例えばエキシマレーザァニール装置を用いて、エネルギー約 230mj/cm2程度の レーザーを水素化アモルファスシリコン膜 (a-Sト H)に照射することにより、厚さが約 0. 3〃 m程度のポリシリコン膜 (poly-Si)を得る(図 13)。 [0101] First, a silicon nitride film (SiNx) having a thickness of about 50 nm and a silicon oxide film having a thickness of about lOOnm (SiOx) on a glass substrate la by a plasma CVD method or the like, for example, at a substrate temperature of about 300 ° C. ), And a hydrogenated amorphous silicon film (a-Si-H) with a thickness of about 50 nm. Next, heat treatment (about 470 ° C for about 1 hour) and laser annealing are performed to convert the hydrogenated amorphous silicon film (a-Si-H) to polysilicon. After dehydrogenation treatment, for example, using an excimer laser annealing apparatus, the hydrogenated amorphous silicon film (aS to H) is irradiated with a laser having an energy of about 230 mj / cm 2 to obtain a thickness of about 0. A polysilicon film (poly-Si) of about 3 mm is obtained (Fig. 13).
[0102] 次いで、図 14に示すように、プラズマエッチング等によってポリシリコン膜(poly-Si )をパターユングする。次に、図 15に示すように、厚さが約 lOOnm程度の酸化シリコ ン膜 (SiOx)を成膜し、ゲート絶縁膜 27を形成する。ゲート絶縁膜 27の上に、スパッ タリング等によって、厚さ約 200nm程度の八1-2原子°/(^(1合金薄膜および厚さ約 50 nm程度の Mo薄膜 52を積層した後、プラズマエッチング等の方法でパターユングす る。これにより、走査線と一体のゲート電極 26が形成される。 Next, as shown in FIG. 14, the polysilicon film (poly-Si) is patterned by plasma etching or the like. Next, as shown in FIG. 15, a silicon oxide film (SiOx) having a thickness of about lOOnm is formed, and a gate insulating film 27 is formed. On the gate insulating film 27, by sputtering, etc., 8 1-2 atoms / (^ (1 alloy thin film and approximately 50 nm thick Mo thin film 52 approximately 50 nm thick) are stacked and then plasma etching is performed. Thus, the gate electrode 26 integrated with the scanning line is formed.
[0103] 続いて、図 16に示すように、フォトレジスト 31でマスクを形成し、例えばイオン注入 装置などにより、例えばリンを 50keV程度で 1 X 1015個/ cm2程度ドーピングし、ポリ シリコン膜 (poly-Si)の一部に n+型ポリシリコン膜 (η+poly-Si)を形成する。次に、フ オトレジスト 31を剥離し、例えば 500°C程度で熱処理することによってリンを拡散させ Subsequently, as shown in FIG. 16, a mask is formed with a photoresist 31, and, for example, phosphorus is doped with, for example, about 1 × 10 15 pieces / cm 2 at about 50 keV by using an ion implantation apparatus or the like to form a polysilicon film. An n + type polysilicon film (η + poly-Si) is formed on a part of (poly-Si). Next, the photoresist 31 is peeled off, and phosphorus is diffused by heat treatment at about 500 ° C., for example.
[0104] 次いで、図 17に示すように、例えばプラズマ CVD装置などを用いて、厚さ 500nm 程度の酸化シリコン膜 (SiOx)を基板温度約 250°C程度で成膜し、層間絶縁膜を形 成した後、同様にフォトレジストによってパターユングしたマスクを用いて層間絶縁膜 (SiOx)とゲート絶縁膜 27の酸化シリコン膜をドライエッチングし、コンタクトホールを 形成する。スパッタリングにより、厚さ 50nm程度の Mo膜 53と厚さ 450nm程度の 0. 2原子%06_0. 2原子%0(1合金薄膜を成膜した後、パターユングすることによつ て、信号線に一体のソース電極 28およびドレイン電極 29を形成する。その結果、ソ ース電極 28とドレイン電極 29は、各々コンタクトホールを介して n+型ポリシリコン膜( n+poly-Si)にコンタクトされる。 Next, as shown in FIG. 17, using a plasma CVD apparatus or the like, a silicon oxide film (SiOx) having a thickness of about 500 nm is formed at a substrate temperature of about 250 ° C. to form an interlayer insulating film. In the same way, using a mask patterned with photoresist, the interlayer insulating film (SiOx) and the silicon oxide film of the gate insulating film 27 are dry-etched to form contact holes. By sputtering, the Mo film 53 with a thickness of about 50 nm and the 0.2 atomic% 06_0.2 atomic% 0 with a thickness of about 450 nm are formed into a signal line by patterning after forming an alloy thin film. An integrated source electrode 28 and drain electrode 29 are formed, and as a result, the source electrode 28 and the drain electrode 29 are contacted with the n + type polysilicon film (n + poly-Si) through the contact holes, respectively. .
[0105] 次いで、図 18に示すように、プラズマ CVD装置などにより、厚さ 500nm程度の窒 化シリコン膜 (SiNx)を基板温度 220°C程度で成膜し、層間絶縁膜を形成する。層 間絶縁膜の上にフォトレジスト層 31を形成した後、窒化シリコン膜(SiNx)をパター二 ングし、例えばドライエッチングによって窒化シリコン膜(SiNx)にコンタクトホール 32 を形成する。 Next, as shown in FIG. 18, a silicon nitride film (SiNx) having a thickness of about 500 nm is formed at a substrate temperature of about 220 ° C. by using a plasma CVD apparatus or the like to form an interlayer insulating film. After a photoresist layer 31 is formed on the interlayer insulating film, a silicon nitride film (SiNx) is patterned, and contact holes 32 are formed in the silicon nitride film (SiNx), for example, by dry etching.
[0106] 次に、図 19に示すように、例えば酸素プラズマによるアツシング工程を経た後、前 述した実施形態 1と同様にしてァミン系の剥離液などを用いてフォトレジストを剥離し てから、 ITO膜を成膜し、ウエットエッチングによるパターユングを行って画素電極 5を 形成する。 Next, as shown in FIG. 19, after undergoing an ashing process using, for example, oxygen plasma, the photoresist is stripped using an amin-based stripping solution in the same manner as in the first embodiment, and then An ITO film is formed and patterned by wet etching to form the pixel electrode 5.
[0107] このようにして作製されたポリシリコン TFT基板では、ドレイン電極 29は透明画素電 極 5に直接コンタクトされている。ドレイン電極 29を構成する Α 0· 2原子%06-0. 2 原子%0(1合金薄膜と画素電極 5との界面には Ge濃化層が形成されており、コンタク ト抵抗が低減されると共に、 Geが拡散し、単体で析出しているため、 A1の再結晶が 促進され、 A1合金膜自体の電気抵抗率も大幅に低減されるようになる。 In the polysilicon TFT substrate manufactured in this way, the drain electrode 29 is in direct contact with the transparent pixel electrode 5. Constructing the drain electrode 29 Α 0 · 2 atomic% 0 6 -0. 2 atomic% 0 (A Ge-concentrated layer is formed at the interface between the alloy thin film and the pixel electrode 5 to reduce the contact resistance. At the same time, since Ge diffuses and precipitates as a single substance, the recrystallization of A1 is promoted, and the electrical resistivity of the A1 alloy film itself is greatly reduced.
[0108] 次に、トランジスタの特性を安定させるため、例えば 220°C程度で 1時間程度熱処 理すると、ポリシリコン TFTアレイ基板が完成する。 Next, in order to stabilize the characteristics of the transistor, for example, heat treatment is performed at about 220 ° C. for about 1 hour to complete a polysilicon TFT array substrate.
[0109] 第 2の実施形態に係る TFT基板、および該 TFT基板を備えた液晶表示装置によ れば、前述した第 1の実施形態に係る TFT基板と同様の効果が得られる。また、第 2 の実施形態における A1合金は、反射型液晶の反射電極として用いることもできる。 [0109] According to the TFT substrate according to the second embodiment and the liquid crystal display device including the TFT substrate, the same effects as those of the TFT substrate according to the first embodiment described above can be obtained. The A1 alloy in the second embodiment can also be used as a reflective electrode for reflective liquid crystals.
[0110] このようにして得られる TFTアレイ基板を用い、前述した実施形態 1の TFT基板と 同様にして液晶表示装置を完成させる。 [0110] Using the TFT array substrate thus obtained, a liquid crystal display device is completed in the same manner as the TFT substrate of Embodiment 1 described above.
[0111] 前述したように、本発明の A1合金膜は、ドライエッチング性にも優れている。以下、 ドライエッチング工程にっレ、て説明する。 [0111] As described above, the A1 alloy film of the present invention is also excellent in dry etching property. Less than, The dry etching process will be described.
[0112] ドライエッチング工程では、一般に、真空容器内に載置した基板上に C1等のハロ [0112] In the dry etching process, generally, a halo such as C1 is formed on a substrate placed in a vacuum vessel.
2 ゲンガスを含む原料ガスを高周波電力によってプラズマ化し、他方で、基板 (被エツ チング材)を載置しているサセプタに別の高周波電力を印加することによって基板上 にプラズマ中のイオンを引き込み、反応性プラズマとのイオンアシスト反応による異方 十生のパターユングを fiつて!/、る。 2 The source gas containing the source gas is turned into plasma by high-frequency power, and on the other hand, by applying another high-frequency power to the susceptor on which the substrate (etching material) is placed, ions in the plasma are drawn onto the substrate, Anisotropy by ion-assisted reaction with reactive plasma.
[0113] 例えば、エッチングガスとして代表的な C1ガスを用いた場合、 C1ガスがプラズマに [0113] For example, when a typical C1 gas is used as an etching gas, the C1 gas is converted into plasma.
2 2
よって解離されて C1ラジカルを生成する。この C1ラジカルは反応性が高ぐ被エッチ ング物である A1合金薄膜に吸着し、該 A1合金薄膜表面に塩化物を生成する。 A1合 金薄膜が形成された基板には、高周波バイアスが印加されるので、プラズマ中のィォ ンが加速されて A1合金薄膜表面に入射し、このイオンボンバード効果によって塩化 物が蒸発し、基板が載置されて!/、る真空容器外へと排気される。 Thus, it is dissociated to produce C1 radical. This C1 radical is adsorbed on the A1 alloy thin film, which is a highly reactive material to be etched, and generates chloride on the surface of the A1 alloy thin film. Since a high-frequency bias is applied to the substrate on which the A1 alloy thin film is formed, ions in the plasma are accelerated and incident on the surface of the A1 alloy thin film, and chloride is evaporated by this ion bombardment effect. Is exhausted out of the vacuum container!
[0114] ドライエッチングを効率良く行うには、生成された塩化物の蒸気圧が比較的高いこと が好ましい。蒸気圧が高ければ、 A1合金薄膜の表面温度やイオンボンバードの物理 的なアシストによって、塩化物を蒸発させることができる。これに対し、塩化物の蒸気 圧が低い場合は、表面に塩化物が生成したまま蒸発せずに残留するため、エツチン グ残渣(ドライエッチング中に発生するエッチングの残り)が発生する。 [0114] In order to perform dry etching efficiently, the vapor pressure of the generated chloride is preferably relatively high. If the vapor pressure is high, chloride can be evaporated by the physical assistance of the surface temperature of the A1 alloy thin film and ion bombardment. On the other hand, when the vapor pressure of chloride is low, chloride remains on the surface without evaporation and etching residue (residual etching generated during dry etching) occurs.
[0115] 本発明は、ドライエッチング処理の方法やドライエッチング処理に用いられる装置な どを限定するものではない。例えば、図 25に示すような汎用のドライエッチング用装 置を用いて通常のドライエッチング工程を行うことができる。後記する実施例では、図 25に示す1じ (誘導結合プラズマ)式ドライエッチング装置を用いた。 [0115] The present invention is not limited to a dry etching method or an apparatus used for the dry etching process. For example, a general dry etching process can be performed using a general-purpose dry etching apparatus as shown in FIG. In the examples described later, a single (inductively coupled plasma) type dry etching apparatus shown in FIG. 25 was used.
[0116] 以下、図 25のドライエッチング用装置を用いた代表的なドライエッチング処理を説 明する力 これに限定する趣旨では決してない。 Hereinafter, the power to explain a typical dry etching process using the dry etching apparatus of FIG. 25 is not intended to be limited to this.
[0117] 図 25の装置において、チャンバ 61上部には誘電窓 62があり、誘電窓 62の上には [0117] In the apparatus of FIG. 25, there is a dielectric window 62 above the chamber 61, and above the dielectric window 62,
1ターンのアンテナ 63が載置されている。図 25のプラズマ発生装置は、誘電窓 62が 平板タイプのいわゆる TCP (Transfer Coupled Plasma)と呼ばれるものである。ァ ンテナ 63には、 13. 56MHzの高周波電力 64が整合器 65を介して導入される。 A one-turn antenna 63 is placed. The plasma generator shown in FIG. 25 is a so-called TCP (Transfer Coupled Plasma) in which the dielectric window 62 is a flat plate type. A high frequency power 64 of 13.56 MHz is introduced into the antenna 63 through a matching unit 65.
[0118] チャンバ 61にはプロセスガス導入口 66があり、ここ力、ら、 C1などのハロゲンガスを 含むエッチングガスが導入される。基板 (被エッチング材) 67はサセプタ 68上に載置 される。サセプタ 68は静電チャック 69となっており、プラズマから基板に流入した電 荷によって静電力でチヤッキング可能となっている。サセプタ 68の周辺は、石英ガラ スのカラー 70と呼ばれる部材が載置されている。 [0118] There is a process gas inlet 66 in the chamber 61, where a halogen gas such as C1, C1, etc. An etching gas is introduced. A substrate (material to be etched) 67 is placed on a susceptor 68. The susceptor 68 is an electrostatic chuck 69, and can be chucked by an electrostatic force due to the electric charge flowing into the substrate from the plasma. A member called a quartz glass collar 70 is placed around the susceptor 68.
[0119] チャンバ 61内に導入されたハロゲンガスは、誘電窓 62上にあるアンテナ 63に高周 波電力を印加して生じた誘電磁場により、励起状態となってプラズマ化される。 [0119] The halogen gas introduced into the chamber 61 is turned into plasma in an excited state by a dielectric magnetic field generated by applying high frequency power to the antenna 63 on the dielectric window 62.
[0120] 更に、サセプタ 68には整合器 71を介して 400kHzの高周波電力 72が導入され、 サセプタ 68に載置された基板 (被エッチング材) 67に高周波バイアスが印加される。 この高周波バイアスによってプラズマ中のイオンが基板に異方性をもって引き込まれ 、垂直エッチングなどの異方性エッチングが可能となる。 Furthermore, high frequency power 72 of 400 kHz is introduced into the susceptor 68 via the matching unit 71, and a high frequency bias is applied to the substrate (material to be etched) 67 placed on the susceptor 68. By this high frequency bias, ions in the plasma are attracted to the substrate with anisotropy, and anisotropic etching such as vertical etching becomes possible.
[0121] ドライエッチング工程に用いられるエッチングガス(プロセスガス)は、代表的には、 ハロゲンガス、ハロゲンガスの硼化物、及び希ガスの混合ガスが挙げられる。混合ガ スの組成はこれに限定されず、例えば、更に臭化水素や四フッ化炭素などを添加し てもよい。 [0121] The etching gas (process gas) used in the dry etching step typically includes a mixed gas of a halogen gas, a boride of a halogen gas, and a rare gas. The composition of the mixed gas is not limited to this, and for example, hydrogen bromide or carbon tetrafluoride may be further added.
[0122] 混合ガスの流量比は特に限定されないが、例えば、 Arと C1と BC1の混合ガスを使 [0122] The flow ratio of the mixed gas is not particularly limited. For example, a mixed gas of Ar, C1, and BC1 is used.
2 3 twenty three
用する場合、おおむね、 Ar : Cl : BC1 = 300sccm : 120sccm : 60sccmの付近に When using, generally, Ar: Cl: BC1 = 300sccm: 120sccm: around 60sccm
2 3 twenty three
調整することが好ましい。 It is preferable to adjust.
[0123] 本発明において、ドライエッチングは、 A1合金薄膜や Si半導体層のエッチング、及 びコンタクトホールを形成する全工程で用いることができ、これにより、生産性が高め られる。ただし、本発明はこれに限定する趣旨では決してない。例えば、コンタクトホ 一ルの底部が A1合金膜に到達する直前までは、ウエットエッチングを行い、コンタクト ホール形成工程の最終段階でドライエッチングに切り替えてもょレ、。コンタクトホール 形成工程の殆どをウエットエッチングにより行うことにより、複数の TFT基板を一括処 理すること力 Sできる。ただし、コンタクトホール形成の全工程でドライエッチングを行な えば、生産性が高められる。 [0123] In the present invention, dry etching can be used in all steps of etching an A1 alloy thin film or Si semiconductor layer and forming contact holes, thereby improving productivity. However, the present invention is not intended to be limited to this. For example, wet etching is performed until the bottom of the contact hole reaches the A1 alloy film, and switching to dry etching is performed at the final stage of the contact hole formation process. By performing wet etching most of the contact hole formation process, it is possible to process multiple TFT substrates at once. However, productivity can be improved if dry etching is performed in all steps of contact hole formation.
実施例 Example
[0124] 以下、実施例を挙げて本発明をより具体的に説明するが、本発明はもとより下記実 施例によって制限を受けるものではなぐ前、後記の趣旨に適合し得る範囲で適当に 変更を加えて実施することも可能であり、それらはいずれも本発明の技術的範囲に p¾よれ 。 [0124] Hereinafter, the present invention will be described in more detail with reference to examples. However, before the present invention is not limited by the following examples, the present invention is suitably applied within a range that can be adapted to the purpose described below. It is also possible to carry out with modifications, and all of them depend on the technical scope of the present invention.
[0125] 表 1、表 2、および表 3に示す種々の合金組成の A1合金膜について、以下に示すよ うに、 A1合金膜自体の電気抵抗率、および A1合金膜を透明画素電極、または非晶 質 Si層、または多結晶 Si層に直接接続したときのコンタクト抵抗率を測定するとともに 、 A1合金膜を加熱したときの耐熱性を調べた。 [0125] For the A1 alloy films having various alloy compositions shown in Table 1, Table 2, and Table 3, as shown below, the electrical resistivity of the A1 alloy film itself and the A1 alloy film are transparent pixel electrodes or non- The contact resistivity when directly connected to the crystalline Si layer or the polycrystalline Si layer was measured, and the heat resistance when the A1 alloy film was heated was examined.
[0126] A1合金膜の上記した諸特性は、次のような条件の下で行なった。 [0126] The various properties described above of the A1 alloy film were performed under the following conditions.
( 1 )透明画素電極の構成:酸化インジウムに 10質量%の酸化スズを加えた酸化ィ ンジゥムスズ (ITO)、若しくは酸化インジウムに 10質量%の酸化亜鉛を加えた酸化ィ ンジゥム亜鉛(IZO) (1) Transparent pixel electrode configuration: Indium tin oxide (ITO) with 10% by weight tin oxide added to indium oxide, or Indium zinc oxide (IZO) with 10% by weight zinc oxide added to indium oxide
(2) A1合金膜の形成条件: (2) A1 alloy film formation conditions:
雰囲気ガス =アルゴン、圧力 = 3mTorr、厚さ = 200nm Atmosphere gas = argon, pressure = 3mTorr, thickness = 200nm
(3) A1合金膜における各合金元素の含有量: (3) Content of each alloy element in A1 alloy film:
実験に供した種々の A1合金における各合金元素の含有量は、 ICP発光分析 (誘導 結合プラズマ発光分析)法によって求めた。 The content of each alloy element in the various A1 alloys used in the experiments was determined by ICP emission analysis (inductively coupled plasma emission analysis).
[0127] (実験例 1) [0127] (Experiment 1)
A1合金膜として、 A1— 0· 3原子% α— 0· 35Gd原子% ( a =Ni、 Ge、 Ag、 Zn、 C u)の 5種類の試料を準備し、それぞれ、 ITO膜とのコンタクト抵抗率を測定した。コン タクト抵抗の測定法は、図 20に示すケルビンパターン(コンタクトホールサイズ: 10 μ m角)を作製し、 4端子測定 (ITO-A1合金若しくは IZO-A1合金に電流を流し、別の 端子で ITO-A1合金間若しくは IZO-A1合金の電圧降下を測定する方法)を行なった 。具体的には、図 20の I -I間に電流 Iを流し、 V -V間の電圧 Vをモニターすることに As A1 alloy films, five types of samples of A1— 0 · 3 atomic% α— 0 · 35Gd atomic% (a = Ni, Ge, Ag, Zn, Cu) were prepared, and each contact resistance with ITO film The rate was measured. The contact resistance is measured by preparing the Kelvin pattern (contact hole size: 10 μm square) shown in Fig. 20 and measuring it at 4 terminals (by applying current to ITO-A1 alloy or IZO-A1 alloy and using another terminal). A method of measuring the voltage drop between ITO-A1 alloys or between IZO-A1 alloys). Specifically, the current I flows between I and I in Fig. 20, and the voltage V between V and V is monitored.
1 2 1 2 1 2 1 2
より、接続部 Cのコンタクト抵抗 Rを [R= (V -V ) /I ]として求めた。 Thus, the contact resistance R of the connection C was obtained as [R = (V−V) / I].
[0128] 図 21に、透明画素電極として ITOを用いたときの結果を示す。 ITOの代わりに IZO を用いたときも、図 21と同じような傾向が見られた。図 21より、 a =Geの場合が最も コンタクト抵抗率が低いことが分かる。しかも、 Ge添加の A1合金膜が最もコンタクト抵 抗率のばらつきも少なぐ安定性に優れていることが分かる(図 21において、コンタク ト抵抗率は♦印で示され、♦印の上側と下側にそれぞれ表れている棒状の印はエラ 一バーを示す)。 FIG. 21 shows the results when ITO is used as the transparent pixel electrode. When IZO was used instead of ITO, the same trend as in Fig. 21 was observed. From Fig. 21, it can be seen that the contact resistivity is lowest when a = Ge. In addition, it can be seen that the Ge-added A1 alloy film has the best stability with the smallest variation in contact resistance (in Fig. 21, the contact resistivity is indicated by ♦, and the upper and lower sides of the ♦ are shown below. Each bar-shaped mark on the side One bar).
[0129] (実験例 2) [0129] (Experiment 2)
A1合金膜として、 A1— 0. l原子%Ge—/3原子%X(X = Nd、 Gd、 La、Dy、Y、 β は表 1参照)の 10種類の試料を準備し、 A1合金膜の耐熱性を測定した。測定方法に ついて説明する。前述した(2)に示す条件でガラス基板上に A1合金膜のみを形成し た。次に、 10 幅のラインアンドスペースパターンを形成し、不活性ガス雰囲気中 で、 50°CZ分の速度で徐々に加熱しながら、光学顕微鏡による試料表面の観察を 行ない、ヒロックの発生が確認された時点での温度(以下、「ヒロック発生温度」と記す )を記録した。 5回測定したヒロック発生温度の平均値を表 1に示す。 As A1 alloy film, A1- 0. l atomic% G e - Prepare / 3 atomic% X 10 different samples (X = Nd, Gd, L a, Dy, Y, β see Table 1), A1 The heat resistance of the alloy film was measured. The measurement method is explained. Only the A1 alloy film was formed on the glass substrate under the conditions described in (2) above. Next, a 10-width line and space pattern was formed, and the sample surface was observed with an optical microscope while gradually heating at a rate of 50 ° CZ in an inert gas atmosphere, confirming the occurrence of hillocks. Temperature (hereinafter referred to as “hillock generation temperature”) was recorded. Table 1 shows the average hillock temperature measured five times.
[0130] [表 1] [0130] [Table 1]
[0131] 表 1から、何れの添加元素(X)の場合も 0. 5原子%程度の組成域では,約 430°C 〜460°Cと、ほぼ同等のヒロック発生温度を示すのに対し、 0. 1原子0 /。程度の低添 加組成域では,ヒロック発生温度に差が見られ、 Gd、 Laの順で耐熱性向上の効果が 高いことが明らかである。 [0131] From Table 1, in the case of any additive element (X), in the composition range of about 0.5 atomic%, about 430 ° C to 460 ° C, which shows almost the same hillock generation temperature, 0. 1 atom 0 /. In the low additive composition region, there is a difference in the hillock generation temperature, and it is clear that the effect of improving heat resistance is higher in the order of Gd and La.
[0132] (実験例 3) [0132] (Experiment 3)
表 2に示す種々の組成の A1合金膜を、 220°Cで加熱処理し、 A1合金膜の電気抵 抗率を測定した。図 22に、加熱処理時間と A1合金膜の電気抵抗率との相関を示す 。図 22から明らかなように、加熱処理時間を長くとれば A1合金膜の電気抵抗率は順 調に下がってくる力 Gd Laの添加量が多い場合には電気抵抗率はあまり下ってい ない。加熱時間 8分程度の条件で 4. δ μ Ω · cm程度の低い電気抵抗率を得るため には、 Gd Laの添加量は、それぞれ単独で、或いは、合計で 0. 45原子%以下、好 ましくは 0. 4原子%以下、更に好ましくは 0. 3原子%以下とするのが良いと考えられ A1 alloy films with various compositions shown in Table 2 were heat treated at 220 ° C, and the electrical resistance of the A1 alloy film was The drag rate was measured. FIG. 22 shows the correlation between the heat treatment time and the electrical resistivity of the A1 alloy film. As is clear from FIG. 22, the electric resistivity of the A1 alloy film decreases smoothly when the heat treatment time is increased. When the amount of Gd La added is large, the electric resistivity does not decrease much. In order to obtain a low electrical resistivity of about 4. δ μΩ · cm under a heating time of about 8 minutes, the amount of Gd La added alone or in total is 0.45 atomic% or less. It is considered to be 0.4 atomic% or less, more preferably 0.3 atomic% or less.
[表 2] [Table 2]
[0134] (実験例 4) [0134] (Experimental example 4)
表 3に示した種々の組成の Al— Ge— Gd系膜、 A1— Ge— La系膜において、 220 °Cで加熱処理し、 A1合金膜のヒロック密度と電気抵抗率を測定した。ヒロック密度の 測定は、実験例 2のようにヒロック発生温度を調べたのではなぐ試料を 220°Cで 30 分間加熱した後の、 A1合金膜の表面に形成されたヒロックの数をカウントすることによ り行なうものである。すなわち、前述した(2)に示す条件でガラス基板上に A1合金膜 のみを形成した。次に、 10 m幅のラインアンドスペースパターンを形成し、 220°C X 30分の真空加熱処理を行った後、 SEMで配線表面を観察し、直径 0. ; m以上 のヒロックの個数をカウントした。この結果を表 3に示す。 The Al—Ge—Gd film and A1—Ge—La film having various compositions shown in Table 3 were heat-treated at 220 ° C., and the hillock density and electrical resistivity of the A1 alloy film were measured. The hillock density was measured by counting the number of hillocks formed on the surface of the A1 alloy film after heating the sample at 220 ° C for 30 minutes instead of examining the hillock generation temperature as in Experimental Example 2. This is what is done. That is, only the A1 alloy film was formed on the glass substrate under the conditions described in (2) above. Next, a line and space pattern with a width of 10 m was formed, vacuum heat treatment was performed at 220 ° C for 30 minutes, the surface of the wiring was observed with SEM, and the number of hillocks with a diameter of 0; m or more was counted. . The results are shown in Table 3.
[0135] 一方、電気抵抗率は、試料を 220°Cで 10分間加熱した後、ケルビンパターンを用 い、 4端子法にて測定した。この結果も表 3に示す。 [0135] On the other hand, the electrical resistivity was measured by the 4-terminal method using a Kelvin pattern after heating the sample at 220 ° C for 10 minutes. The results are also shown in Table 3.
[0136] [表 3] [0136] [Table 3]
[0137] 表 3力、ら、 A1— Ge— Gd系材料、及び A1— Ge— La系材料にお!/、ては、 Gd、 Laの 含有量が 0. 1原子%以上の場合にヒロック密度が小さく抑えられて!/、ることが分かる 。 A1合金膜に更に Niを添加すると耐熱性を向上させる効果がある力 S、電気抵抗率の 増加を伴うことから、 Niの添加量は制限される。比較のため、 AL— Ge系材料(2元系 )のヒロック密度及び電気抵抗率を示すが、 Gdも Laも含有しない場合は耐熱性が著 しく低い。また、 A1— Ge— Gd— Zn系材料では Znの添加による更なる耐熱性改善効 果は認められなかった。 [0137] Table 3 Force, et al., A1—Ge—Gd and A1—Ge—La materials! /, If the content of Gd and La is 0.1 atomic% or more, hillock You can see that the density is kept small! Addition of Ni to the A1 alloy film has the effect of improving the heat resistance S and increases the electrical resistivity, so the amount of Ni added is limited. For comparison, the hillock density and electrical resistivity of the AL-Ge material (binary system) are shown. However, when neither Gd nor La is contained, the heat resistance is remarkably low. In addition, in the A1-Ge-Gd-Zn-based material, no further heat resistance improvement effect due to the addition of Zn was observed.
[0138] (実験例 5) [0138] (Experimental example 5)
表 4に示す各種の A1— Ge— X膜と ITO膜とのコンタクト抵抗率、及び Siダイレクトコ ンタクト特性をそれぞれ測定した。 ITO膜とのコンタクト抵抗率の測定には、実験例 1 に示した方法を用いた。表 4に示したいずれの試料についても、 2. 00 X 10— 4 Ω - cm 2以下の低いコンタクト抵抗率が得られている。試料番号 10、 11、 14及び 15の Niと C uを Geと複合的に添加した場合には、コンタクト抵抗率が低減される効果が特に大き い。 The contact resistivity and Si direct contact characteristics of various A1-Ge-X films and ITO films shown in Table 4 were measured. The method shown in Experimental Example 1 was used to measure the contact resistivity with the ITO film. For any of the samples shown in Table 4, 2. 00 X 10- 4 Ω - cm 2 or less of a low contact resistivity is obtained. When Ni and Cu of sample numbers 10, 11, 14, and 15 are added in combination with Ge, the effect of reducing the contact resistivity is particularly great.
[0139] [表 4] [0139] [Table 4]
[OHO] 一方、 Siダイレクトコンタクト特性(後述する評価用 TEGのオン電流、オフ電流)は それぞれ次のように測定した。まず、 Siウェハ上に、スパッタリング法及びプラズマ C[OHO] On the other hand, the Si direct contact characteristics (ON current and OFF current of evaluation TEG described later) are Each was measured as follows. First, sputtering method and plasma C on Si wafer
VD法を用いて、図 23に示す TFTを有する評価用 TEGを作製した。 TFTのゲート長Using the VD method, an evaluation TEG having the TFT shown in FIG. 23 was produced. TFT gate length
Lは 10 μ m、ゲート幅 Wは 10 μ mである。 L is 10 μm and gate width W is 10 μm.
[0141] 作製した評価用 TEGを、 300°Cで 30分間、加熱処理を施した。実際の TFTの製 造プロセスでは、 A1合金膜の形成時以降に加熱プロセスが入り、 Si層- A1合金膜間 での相互拡散や界面反応が進行するとオン電流の低下および/またはオフ電流の 増加を生じてしまうからである。 [0141] The prepared TEG for evaluation was subjected to heat treatment at 300 ° C for 30 minutes. In the actual TFT manufacturing process, a heating process is started after the formation of the A1 alloy film, and when the interdiffusion and interfacial reaction between the Si layer and the A1 alloy film proceed, the on-current decreases and / or the off-current increases. It is because it will produce.
[0142] 加熱処理後、 TFTのドレイン電流-ゲート電圧スイッチング特性を測定し、そのオン 電流及びオフ電流を特定した。この結果を図 24に示す。測定時のドレイン電圧は 10[0142] After the heat treatment, the drain current-gate voltage switching characteristics of the TFT were measured, and the on-current and off-current were identified. The results are shown in FIG. The drain voltage during measurement is 10
Vとした。オフ電流は、ゲート電圧が- 3Vの時の電流値、オン電流はゲート電圧が 20V. The off current is the current value when the gate voltage is -3V, and the on current is 20
Vのときの電圧と定義した。 It was defined as the voltage at V.
[0143] オン電流に関しては、表 4に示したいずれの A1合金膜でも、 2. 0 X 10— 6[A]以上で あり、良好である。 With respect to [0143] on-current, in any of the A1 alloy film shown in Table 4, 2. and a 0 X 10- 6 [A] or higher, the better.
[0144] 一方、オフ電流に関しては、試験番号 1〜3の A1— Ge2元系の A1合金膜、及び試 料番号 14及び試料番号 15の Cuを含有した A1合金膜において、 1. 0 X 10— U [A]を 超えており、著しくオフ電流が増加していることが分かる。 [0144] On the other hand, with regard to the off-state current, in the A1—Ge2 system A1 alloy film of test numbers 1 to 3 and the A1 alloy film containing Cu of sample number 14 and sample number 15, 1.0 X 10 — U [A] is exceeded, and it can be seen that the off-state current increases remarkably.
[0145] なお、 TFTの半導体層として、アモルファスシリコンのほ力、、多結晶シリコンを用い た場合も同様である。 Note that the same applies to the case where amorphous silicon or polycrystalline silicon is used as the TFT semiconductor layer.
[0146] (実験例 6) [0146] (Experiment 6)
本実験例および後記する実験例 7では、本発明の A1合金膜が優れたドライエッチ ング性を有することを調べた。 In this Experimental Example and Experimental Example 7 described later, it was investigated that the A1 alloy film of the present invention has excellent dry etching properties.
[0147] まず、実験例 6では、本発明の A1合金膜が、純 A1と同程度の高いエッチングレート 比を有していることを調べた。ここでは、本発明例として、 A1-0. 2原子%06_0. 10 原子%0(1を用いた。比較のため、純 A1のほか、従来の代表的な A1合金膜である A1 -2. 0原子%^を用いた。 First, in Experimental Example 6, it was examined that the A1 alloy film of the present invention has a high etching rate ratio comparable to that of pure A1. Here, as an example of the present invention, A1-0. 2 atomic% 0 6 _0.10 atomic% 0 (1 was used. For comparison, in addition to pure A1, A1 − 2. 0 atomic% ^ was used.
[0148] 具体的には、直径 6インチ、厚さ 0. 5mmの無アルカリガラス基板(コーユング社製 [0148] Specifically, a non-alkali glass substrate having a diameter of 6 inches and a thickness of 0.5 mm (manufactured by Cowing Co., Ltd.)
# 1737ガラス)上に、厚さ 200nmの酸化シリコン(SiOx)膜を基板温度 250°C程度 で成膜した後、上記の純 A1膜または A1合金膜を前述した(2)に示す条件で成膜した 。次いで、 g線のフォトリソグラフィ一によつてポジ型フォトレジスト(ノポラック系樹脂; 東京応化工業(株)製の TSMR8900、厚さは 1 · O ^ m)を線幅 2. 0 mのストライプ 状に形成した。 # 1737 glass), a silicon oxide (SiOx) film with a thickness of 200 nm is deposited at a substrate temperature of about 250 ° C, and then the pure A1 film or A1 alloy film is formed under the conditions described in (2) above. Filmed . Next, a positive photoresist (nopolac resin; TSMR8900 manufactured by Tokyo Ohka Kogyo Co., Ltd., thickness 1 · O ^ m) is formed into a stripe with a line width of 2.0 m by g-line photolithography. Formed.
[0149] 次に、前述した図 25に示すドライエッチング装置を用い、下記のエッチング条件で ドライエッチングを行なった。 Next, dry etching was performed under the following etching conditions using the dry etching apparatus shown in FIG.
[0150] (エッチング条件) [0150] (Etching condition)
Ar/Cl /BC1 : 300sccm/120sccm/60sccm Ar / Cl / BC1: 300sccm / 120sccm / 60sccm
2 3 twenty three
アンテナに印加した電力(ソース RF): 500W Power applied to antenna (source RF): 500W
基板バイアス: 60W、 Substrate bias: 60W
プロセス圧力(ガス圧): 14mTorr Process pressure (gas pressure): 14mTorr
基板温度:サセプタの温度(20°C) Substrate temperature: Susceptor temperature (20 ° C)
[0151] エッチングは、エッチング深さが 100〜300nmとなる範囲において、エッチング時 間を変えて行い、エッチング深さの異なるサンプルを作製した。次いで、窒化シリコン (SiNx)膜のエッチングと同様の方法でレジストを剥離した後、触針式膜厚計 (Vecc o社製の「Dektak II」)を用いて、純 Aほたは A1合金膜のエッチング厚さを測定した[0151] Etching was performed by changing the etching time in the range where the etching depth was 100 to 300 nm, and samples with different etching depths were produced. Next, after removing the resist in the same way as the etching of the silicon nitride (SiNx) film, using a stylus type film thickness meter ("Dektak II" manufactured by Vecco), pure A or A1 alloy film Measured the etching thickness of
〇 Yes
[0152] これらの結果を図 26に示す。 [0152] These results are shown in FIG.
[0153] 図 26に示すように、本発明の A Ge-Gd膜によるエッチングレート比は、従来の A1 _Ni膜に比べて高ぐ純 A1とほぼ同程度であることが確認された。 As shown in FIG. 26, it was confirmed that the etching rate ratio of the A Ge—Gd film of the present invention was almost the same as that of pure A1, which is higher than that of the conventional A1_Ni film.
[0154] (実験例 7) [0154] (Experimental example 7)
本実験例では、表 5に示す種々の A1合金膜の元素(Ge、 Gdおよび/または La, N i)がドライエッチング性に及ぼす影響を調べた。ドライエッチング条件は、前述した実 施例 6と同じである。ドライエッチング性は、以下のようにして評価した。 In this experimental example, the effects of various elements (Ge, Gd and / or La, Ni) of the A1 alloy film shown in Table 5 on dry etching properties were examined. The dry etching conditions are the same as in Example 6 described above. The dry etching property was evaluated as follows.
[0155] (エッチングレート比) [0155] (etching rate ratio)
実施例 6と同様にしてエッチングを行ない、エッチング後における純 A1膜および各 A1合金膜の厚さ (エッチング厚さ)を測定した。これらの結果を最小二乗法で統計処 理して純 A1膜のエッチングレート(N2)および A1合金膜のエッチングレート(N1)をそ れぞれ算出し、 N1/N2の比を「エッチングレート比」とした。 本実施例では、エッチングレート比が 0. 3以上を合格(〇)とした。 Etching was performed in the same manner as in Example 6, and the thickness (etching thickness) of the pure A1 film and each A1 alloy film after the etching was measured. These results are statistically processed by the least squares method to calculate the etching rate of pure A1 film (N2) and the etching rate of A1 alloy film (N1), respectively. " In this example, an etching rate ratio of 0.3 or higher was determined to be acceptable (◯).
[0156] (ドライエッチング後の残渣の有無) [0156] (Presence or absence of residue after dry etching)
種々の A1合金膜に対し、膜厚分のエッチング深さまで必要と考えられるエッチング 時間の 1. 2倍の時間エッチングを行なった試料について、レジストを剥離した後のガ ラス基板の表面を SEM観察 (倍率 3000倍)し、直径(円相当直径)が 0· 5 ^ 111以上 の残渣の有無を調べた。測定視野は 5視野とし、上記の基板表面を数箇所測定した とき、いずれの測定箇所でも上記の残渣が全く観察されない (残渣ゼロ)ものを合格( 〇)とした。 SEM observation of the surface of the glass substrate after the resist was peeled off for various A1 alloy films etched for 1.2 times the etching time considered to be necessary up to the etching depth equivalent to the film thickness ( Magnification 3000 times), and the presence or absence of a residue with a diameter (equivalent circle diameter) of 0.5 · 5 ^ 111 or more was examined. The measurement field of view was 5 fields of view, and when the above substrate surface was measured at several points, the above residue was not observed at any measurement point (no residue) and passed (O).
[0157] 本実施例では、エッチングレート比が合格で、且つ、ドライエッチング後の残渣が無 いものを「ドライエッチング性に優れる」と判定した。 In this example, an etching rate ratio that passed and no residue after dry etching was determined to be “excellent in dry etching”.
[0158] これらの結果を表 5にまとめて記載する。表 5には、総合評価の欄を設け、上記の両 特性を満足するものに〇を付け、 V、ずれか一方の特性が不合格( X )のものに Xを 付した。 [0158] These results are summarized in Table 5. Table 5 provides a column for comprehensive evaluation, where “O” is marked for those satisfying both of the above characteristics, and “X” is marked for those with V or one of the characteristics rejected (X).
[0159] また、図 27に A1合金膜中の Ge量とエッチングレート比の関係を、図 28に A1合金膜 中の Gd量、 La量とエッチングレート比の関係を、図 29に A1合金膜中の Ni量とエッチ ングレート比の関係を、それぞれ示す。 [0159] Fig. 27 shows the relationship between the Ge amount in the A1 alloy film and the etching rate ratio, Fig. 28 shows the relationship between the Gd amount and La amount in the A1 alloy film, and the etching rate ratio, and Fig. 29 shows the A1 alloy film. The relationship between the amount of Ni in the steel and the etching rate ratio is shown below.
[0160] [表 5] [0160] [Table 5]
[0161] 表 5に示すように、本発明の要件を満足する No.;!〜 4の Al-Ge-Gd膜、 No. 6〜9 の A Ge- La膜、 No. 11の Al- Ge- Gd- Ni膜、および No. 13の八1-06-1^-^膜は 、いずれも、ドライエッチング性に優れている。 [0161] As shown in Table 5, No. satisfying the requirements of the present invention! ~ 4 Al-Ge-Gd film, No.6 ~ 9 A Ge-La film, No.11 Al-Ge-Gd-Ni film, and No.13 8 1-06-1 ^-^ film Both are excellent in dry etching property.
[0162] これに対し、 Gd量が多い No. 5の A Ge- Gd膜、 La量が多い No. 10の Al- Ge- L a膜は、いずれも、エッチング後の残渣が観察され、且つ、エッチングレート比も低下 した。また、 No. 12のA Ge-Gd-Ni膜、および No. 14の A Ge- La- Ni膜は、い ずれも、 Ni量が多ぐ且つ Geと Niの合計量が多い例である力 エッチング後の残渣 は観察されなかったものの、エッチングレート比が低下した。 [0162] In contrast, No. 5 A Ge-Gd film with high Gd content, No. 10 Al- Ge- L with high La content In all the films, residues after etching were observed, and the etching rate ratio also decreased. In addition, the No. 12 A Ge-Gd-Ni film and the No. 14 A Ge-La-Ni film are both examples of a large amount of Ni and a large amount of Ge and Ni. Although no residue was observed after etching, the etching rate ratio decreased.
[0163] 上記の実験結果に基づき、エッチングレート比に及ぼす各元素の影響を考察する と、以下のとおりである。 [0163] Based on the above experimental results, the influence of each element on the etching rate ratio is as follows.
[0164] まず、 Al-Ge-Gd膜および Al-Ge-La膜に及ぼす Geの影響について考察する。 [0164] First, the influence of Ge on the Al-Ge-Gd film and the Al-Ge-La film will be considered.
[0165] 図 27に示すように、 Ge量が本発明で規定する範囲内(0. 05-0. 5原子%)の場 合、エッチングレート比は約 0. 6と、ほぼ一定である。また、表 5に示すように、上記範 囲内であれば、エッチング後の残渣も観察されない。従って、本発明の A1合金膜は、 Geの含有量にかかわらず、良好なドライエッチング性を示すことが確認された。 [0165] As shown in FIG. 27, when the Ge amount is within the range defined by the present invention (0.05-0.0.5 atomic%), the etching rate ratio is approximately 0.6, which is substantially constant. In addition, as shown in Table 5, within the above range, no residue after etching is observed. Therefore, it was confirmed that the A1 alloy film of the present invention showed good dry etching properties regardless of the Ge content.
[0166] 次に、 Al-Ge-Gd膜および Al-Ge-La膜に及ぼす Gd/Laの影響について考察す [0166] Next, the effect of Gd / La on Al-Ge-Gd and Al-Ge-La films will be discussed.
[0167] 図 28に示すように、 Gdまたは Laの含有量が減少するにつれて、エッチングレート 比が上昇することが分かる。本発明で規定するエッチングレート比 0. 3以上を満足す るためには、 Gdおよび/または Laの合計量の上限を 0. 35原子%とする必要があり 、上限が 0. 4原子%になると、所望の特性が得られなかった。 As shown in FIG. 28, it can be seen that the etching rate ratio increases as the content of Gd or La decreases. In order to satisfy the etching rate ratio of 0.3 or more specified in the present invention, the upper limit of the total amount of Gd and / or La needs to be 0.35 atomic%, and the upper limit is 0.4 atomic%. As a result, desired characteristics could not be obtained.
[0168] 次に、 Al-Ge-Gd膜および Al-Ge-La膜に及ぼす Niの影響について考察する。 [0168] Next, the effect of Ni on the Al-Ge-Gd film and the Al-Ge-La film will be considered.
[0169] Niも、前述した Gd/Laと同様の傾向が見られ、図 29に示すように、 Niの含有量が 減少するにつれて、エッチングレート比が上昇した。本発明で規定するエッチングレ ート比 0. 3以上を満足するためには、 Ni量の上限を 0. 35原子%とする必要があり、 上限が 0. 4原子%になると、所望の特性が得られなかった。 [0169] Ni also showed the same tendency as Gd / La described above, and as shown in FIG. 29, the etching rate ratio increased as the Ni content decreased. In order to satisfy the etching rate ratio of 0.3 or more specified in the present invention, the upper limit of the Ni amount needs to be 0.3 atomic%, and when the upper limit is 0.4 atomic%, desired characteristics are obtained. Was not obtained.
[0170] 本発明を特定の態様を参照して詳細に説明したが、本発明の精神と範囲を離れる ことなく様々な変更および修正が可能であることは、当業者にとって明らかである。 なお、本出願は、 2006年 11月 30日付けで出願された日本特許出願(特願 2006 — 324494)、及び 2007年 6月 26日付けで出願された日本特許出願(特願 2007— 168298)に基づいており、その全体が引用により援用される。 [0170] Although the invention has been described in detail with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. This application consists of a Japanese patent application filed on November 30, 2006 (Japanese Patent Application 2006-324494) and a Japanese patent application filed on June 26, 2007 (Japanese Patent Application 2007-168298). Which is incorporated by reference in its entirety.
また、ここに引用されるすべての参照は全体として取り込まれる。 産業上の利用可能性 Also, all references cited herein are incorporated as a whole. Industrial applicability
本発明によれば、バリアメタル層を介在させずに、 A1合金膜を導電性酸化膜からな る透明画素電極と直接接続することができ、且つ、約 220°Cといった比較的低い熱 処理温度を適用した場合でも十分に低い電気抵抗率と優れた耐熱性とが確保され た表示デバイス用 A1合金膜や、これを用いた表示デバイスを提供することができる。 According to the present invention, the A1 alloy film can be directly connected to the transparent pixel electrode made of a conductive oxide film without interposing a barrier metal layer, and a relatively low heat treatment temperature of about 220 ° C. A1 alloy film for display devices that can secure a sufficiently low electrical resistivity and excellent heat resistance even when applying the above, and a display device using the same can be provided.
Claims
Priority Applications (3)
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US12/312,907 US8786090B2 (en) | 2006-11-30 | 2007-11-27 | Al alloy film for display device, display device, and sputtering target |
CN2007800442895A CN101542696B (en) | 2006-11-30 | 2007-11-27 | Al alloy film for display device, display device, and sputtering target |
KR1020097011088A KR101085271B1 (en) | 2006-11-30 | 2007-11-27 | Alloy alloy film, display device and sputtering target for display device |
Applications Claiming Priority (4)
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JP2006-324494 | 2006-11-30 | ||
JP2006324494 | 2006-11-30 | ||
JP2007168298A JP4170367B2 (en) | 2006-11-30 | 2007-06-26 | Al alloy film for display device, display device, and sputtering target |
JP2007-168298 | 2007-06-26 |
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WO2008066030A1 true WO2008066030A1 (en) | 2008-06-05 |
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PCT/JP2007/072832 WO2008066030A1 (en) | 2006-11-30 | 2007-11-27 | Al ALLOY FILM FOR DISPLAY DEVICE, DISPLAY DEVICE, AND SPUTTERING TARGET |
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CN102473730A (en) * | 2009-07-27 | 2012-05-23 | 株式会社神户制钢所 | Wiring structure, method for manufacturing wiring structure, and display device provided with wiring structure |
CN113529018A (en) * | 2020-04-16 | 2021-10-22 | 株式会社神户制钢所 | Al alloy vapor-deposited film, wiring film for display, display device, and sputtering target |
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WO1997013885A1 (en) * | 1995-10-12 | 1997-04-17 | Kabushiki Kaisha Toshiba | Wiring film, sputter target for forming the wiring film and electronic component using the same |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US20090224256A1 (en) * | 2008-03-05 | 2009-09-10 | Hyun-Eok Shin | Organic light emitting display |
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US20110248272A1 (en) * | 2008-11-10 | 2011-10-13 | Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd) | Organic el display device reflective anode and method for manufacturing the same |
CN102473730A (en) * | 2009-07-27 | 2012-05-23 | 株式会社神户制钢所 | Wiring structure, method for manufacturing wiring structure, and display device provided with wiring structure |
CN102473730B (en) * | 2009-07-27 | 2015-09-16 | 株式会社神户制钢所 | Wiring structure and manufacture method thereof and possess the display unit of Wiring structure |
CN113529018A (en) * | 2020-04-16 | 2021-10-22 | 株式会社神户制钢所 | Al alloy vapor-deposited film, wiring film for display, display device, and sputtering target |
CN113529018B (en) * | 2020-04-16 | 2023-07-28 | 株式会社神户制钢所 | Al alloy vapor deposition film, wiring film for display, and display device |
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