WO2008066030A1 - Al ALLOY FILM FOR DISPLAY DEVICE, DISPLAY DEVICE, AND SPUTTERING TARGET - Google Patents

Abstract

Disclosed is an Al alloy film for display devices, which is directly connected with a conductive oxide film on a substrate. This Al alloy film for display devices contains 0.05-0.5 atom% of Ge and 0.05-0.45 atom% of Gd and/or La in total. Also disclosed are a display device using such an Al alloy film, and a sputtering target for display devices. The Al alloy film for display devices has high adhesion to a conductive oxide film and low contact resistivity even when the Al alloy film is directly connected with the conductive oxide film without using a barrier metal. Preferably, the Al alloy film for display devices is excellent in dry etching properties.

Description

 Specification

 A1 alloy film for display device, display device, and sputtering target

 TECHNICAL FIELD [0001] The present invention relates to an A1 alloy film for display devices used for liquid crystal displays, semiconductors, optical components, and the like, a display device, and a sputtering target for display devices. The present invention relates to a wiring material.

 Background art

 [0002] Liquid crystal display devices (liquid crystal display devices) used in a variety of fields, from small mobile phones to large televisions exceeding 30 inches, are active with simple matrix type liquid crystal display devices depending on the pixel driving method. It is divided into a matrix type liquid crystal display device. Among them, an active matrix liquid crystal display device having a thin film transistor (hereinafter referred to as TFT) as a switching element is widely used because it can realize high-precision image quality and can cope with high-speed images. Yes.

 With reference to FIG. 1, the configuration and operating principle of a typical liquid crystal display applied to an active matrix liquid crystal display device will be described. Here, a representative example of a TFT substrate using hydrogenated amorphous silicon as an active semiconductor layer (hereinafter sometimes referred to as an amorphous silicon TFT substrate) is not limited to this, and polysilicon is used. V, or even a TFT substrate!

 As shown in FIG. 1, a liquid crystal display is disposed between a TFT substrate 1, a counter substrate 2 disposed opposite the TFT substrate 1, and between the TFT substrate 1 and the counter substrate 2, and performs light modulation. And a liquid crystal layer 3 that functions as a layer. The TFT substrate 1 includes a TFT 4 disposed on an insulating glass substrate la, a transparent pixel electrode 5, and a wiring portion 6 including a scanning line and a signal line. The transparent pixel electrode 5 is an oxide film containing about 10% by mass of tin oxide (SnO) in indium oxide (In 2 O 3).

 twenty three

 It is made of conductive oxide film such as Ngum 'Tin (ITO) film. The TFT substrate 1 is driven by a driver circuit 13 and a control circuit 14 connected via a TAB tape 12.

[0005] The counter substrate 2 includes a common electrode 7 formed on the entire surface of the insulating glass substrate lb on the TFT substrate 1 side, a color filter 8 disposed at a position facing the transparent pixel electrode 5, and a TFT substrate. It has a light-shielding film 9 arranged at a position facing the TFT 4 on the board 1 and the wiring part 6

. The counter substrate 2 further includes an alignment film 11 for aligning liquid crystal molecules (not shown) included in the liquid crystal layer 3 in a predetermined direction.

[0006] On the outside of the TFT substrate 1 and the counter substrate 2 (on the side opposite to the liquid crystal layer 3 side), a polarizing plate 10 is disposed.

In the liquid crystal display, the alignment direction of liquid crystal molecules in the liquid crystal layer 3 is controlled by an electric field formed between a counter electrode (not shown) and the transparent pixel electrode 5, and light passing through the liquid crystal layer 3 is modulated. The As a result, the amount of light transmitted through the counter substrate 2 is controlled and an image is displayed.

 Next, the configuration and operation principle of a conventional amorphous silicon TFT substrate suitably used for a liquid crystal display will be described in detail with reference to FIG. FIG. 2 is an enlarged view of the main part A in FIG.

 As shown in FIG. 2, a scanning line (gate wiring) 25 is formed on a glass substrate (not shown), and a part of the scanning line 25 is a gate electrode 26 that controls on / off of the TFT. Function as. A gate insulating film (silicon nitride film) 27 is formed so as to cover the gate electrode 26. A signal line (source-drain wiring) 34 is formed so as to cross the scanning line 25 via the gate insulating film 27, and a part of the signal line 34 functions as a source electrode 28 of the TFT. On the gate insulating film 27, an amorphous silicon channel film (active semiconductor film, not shown), a signal line (source-drain wiring) 34, and an interlayer insulating silicon nitride film (protective film) 30 are sequentially formed. This type is generally called a bottom gate type.

 [0010] The amorphous silicon channel film is an intrinsic layer that is not doped with P (phosphorus).

 (also referred to as the i layer or non-doping layer) and a doped layer doped with P (n layer). In the pixel region on the gate insulating film 27, for example, IT containing SnO in InO

 twenty three

 A transparent pixel electrode 5 formed of an O film is disposed. The drain electrode 29 of the TFT is electrically connected to the transparent pixel electrode 5.

When a gate voltage is supplied to the gate electrode 26 through the scanning line 25, the TFT 4 is turned on, and the drive voltage supplied to the signal line 34 in advance from the source electrode 28 through the drain electrode 29. And supplied to the transparent pixel electrode 5. Then, the transparent pixel electrode 5 is driven to a predetermined level. When the voltage is supplied, as described in FIG. 1, as a result of the potential difference between the transparent pixel electrode 5 and the counter electrode, the liquid crystal molecules contained in the liquid crystal layer 3 are aligned and light modulation is performed. .

 In the TFT substrate 1, a signal line (pixel electrode signal line) electrically connected to the transparent pixel electrode 5, a source-drain wiring 34 electrically connected to the source electrode 28 -drain electrode 29, and a gate The scanning lines 25 that are electrically connected to the electrodes 26 are all made of pure Al or a thin film of an A1 alloy such as Al_Nd (below, for reasons such as low electrical resistivity and easy fine application). In the background art column, it is referred to as an A1-based thin film.) As shown in Fig. 2, there is a barrier methanole made of a refractory metal such as Mo, Cr, Ti, or W. Layers 51, 52, 53, and 54 are formed.

 Here, the reason for connecting the A1-based thin film to the transparent pixel electrode 5 via the rare metal layer 54 is that the connection resistance (contact resistance) increases when the A1-based thin film is directly connected to the transparent pixel electrode 5. This is because the display quality of the screen is lowered. In other words, A1, which constitutes the wiring directly connected to the transparent pixel electrode, is easily oxidized and oxygen generated in the liquid crystal display film formation process or oxygen added at the time of film formation. This is because an A1 oxide insulating layer is formed at the interface. In addition, ITO that constitutes the transparent pixel electrode is a conductive metal oxide, but cannot be electrically connected electrically by the A1 oxide layer generated as described above.

 [0014] However, in order to form a force-free metal layer, in addition to a film-forming sputtering apparatus necessary for forming a gate electrode, a source electrode, and further a drain electrode, a film-forming chamber for forming a barrier metal is provided. I have to equip extra. As the cost of production increases with the mass production of liquid crystal displays, the increase in manufacturing cost and the decrease in productivity associated with the formation of the barrier metal layer cannot be neglected!

 [0015] In view of this, wiring materials such as electrodes and manufacturing methods capable of directly connecting the A1-based thin film to the transparent pixel electrode have been proposed.

For example, Patent Document 1 discloses a technique in which an indium zinc oxide (IZO) film containing about 10% by mass of zinc oxide in indium oxide is used as a material for a transparent pixel electrode. However, this technology increases the material cost because the most popular ITO film must be changed to an IZO film. Patent Document 2 discloses a method of modifying the surface of the drain electrode by performing plasma treatment or ion implantation on the drain electrode. However, according to this method, a process for surface treatment is added, and thus productivity is lowered.

 [0018] Further, Patent Document 3 discloses a first layer of pure A1 or A1 as a gate electrode, a source electrode, and a drain electrode, and a first layer containing impurities such as N, O, Si, and C in pure A1 or A1. A method using two layers is disclosed. According to this method, although there is an advantage that the thin films constituting the gate electrode, the source electrode, and the drain electrode can be continuously formed using the same film formation chamber, the second layer containing the impurity described above is formed. Extra steps are added. In addition, in the process of introducing impurities into the source-drain wiring, the source wall is exposed from the wall surface of the chamber due to the difference in thermal expansion coefficient between the film mixed with the impurity! The drain wiring deposits often flake off as flakes. In order to prevent this phenomenon, it is necessary to frequently stop the film forming process and perform maintenance, and the productivity is significantly reduced.

 In view of such circumstances, there is a method capable of omitting the near metal layer, simplifying without increasing the number of steps, and connecting the A1 alloy film directly and securely to the transparent pixel electrode. (Patent Document 4). In Patent Document 4, A1 alloy containing at least one selected from the group consisting of Au, Ag, Zn, Cu, Ni, Sr, Ge, Sm, and B is used as an alloy component. The above problems are solved by allowing at least a part of these alloy components to exist as precipitates or concentrated layers at the interface between the A1 alloy film and the transparent pixel electrode.

 [0020] In Patent Document 4, for example, in the case of an Al-Ni alloy, the electrical resistivity after heat treatment at 250 ° C for 30 minutes is 8 1-2 atoms ° / (^ · 3 · 8Ω · «η , 8 1-4 atomic% ^ is 5 · 8 Ω-cm, A 1-6 atomic% ^ is 6 · 5 μΩ 'cm, and the A1 alloy film with low electrical resistivity is used. This is very useful because the power consumption of the display device can be reduced, and the time constant determined by the product of the electrical resistance and the capacitance is reduced when the electrical resistivity of the electrode portion is reduced. Even when the size is increased, it is possible to maintain a high degree of display quality, but the heat resistance temperature of the above Al-Ni alloys is generally as low as 150 to 200 C.

Therefore, Patent Document 5 includes a thin film transistor and a transparent pixel electrode, and an A1 alloy film and a conductive layer. A thin film transistor substrate is disclosed in which a conductive oxide film is directly connected without a refractory metal and a part or all of the A1 alloy component is precipitated or concentrated at the direct connection interface. The A1 alloy film contains, as an alloy component, an element belonging to group α in the range of 0.1 atomic% to 6 atomic% and an element belonging to group X in the range of 0.1 atomic% to 2.0 atomic%. Α ^ α -Χ alloy, group α is at least one element selected from the group consisting of Ni, Ag, Zn, Cu, and Ge, and group X is Mg, Cr, Mn, Ru, Rh A thin film transistor substrate that is at least one element selected from the group consisting of Pd, Ir, Pt, La, Ce, Pr, Gd, Tb, Sm, Eu, Ho, Er, Tm, Yb, Lu, and Dy. is there.

 [0022] When this thin film transistor substrate is used, it is possible to omit the near metal layer, and to connect the A1 alloy film directly and reliably to the pixel electrode having the conductive oxide film force without increasing the number of steps. It is supposed to be possible. In addition, even when a low heat treatment temperature of, for example, about 100 ° C. or more and 300 ° C. or less is applied to the A1 alloy film, it is said that reduction in electrical resistivity between pixel electrodes and excellent heat resistance can be achieved. Yes. Specifically, even when heat treatment at a low temperature such as 250 ° CX for 30 minutes is adopted, the electrical resistivity of the A1 alloy thin film can achieve 7 Ω'cm or less without causing defects such as hillocks. It is stated that it can be done.

 Further, Patent Document 6 includes, as an additive element, Ge in an amount of 0.2 to 1.5 atom%, further containing Ni in an amount of 0.2 to 2.5 atom%, and the balance being A1 for a wiring film A1. Although an alloy film is described, according to Table 1 of Patent Document 6, it is difficult to satisfy both a low electrical resistivity and a good surface state.

[0023] On the other hand, in recent years, along with the improvement in image quality and resolution of liquid crystal displays, the A1 alloy film electrode wiring has been made finer (line width has been reduced). Is shifting from the widely used wet etching method (a method of performing wiring patterning by chemical etching) to a dry etching method (a method of performing wiring patterning by reactive plasma etching). . In the wet etching method, a phenomenon called “side etching” occurs in which the chemical solution wraps around the underside of the resist, which is a patterning mask, and etches the hot spring side walls. It ’s difficult. On the other hand, the dry etching method is excellent in fine processing of wiring because precise etching can be performed. By dry etching, fine wiring with a line width of 2 m or less can be formed. In addition, if all etching processes in TFT fabrication can be dry-etched, productivity can be expected to improve.

[0024] Therefore, as an electrode film / wiring film suitable for dry etching, Patent Document 7 discloses an Al-Nd alloy thin film containing Nd in A1 in an amount of more than 0.1 atomic% to 1.0 atomic%. It is disclosed. However, this A1 alloy thin film cannot be directly connected to the transparent pixel electrode. Patent Document 1: Japanese Patent Laid-Open Publication No. U-337976

 Patent Document 2: JP-A-5-283934

 Patent Document 3: Japanese Patent Laid-Open Publication No. U-284195

 Patent Document 4: Japanese Patent Laid-Open No. 2004-214606

 Patent Document 5: Japanese Unexamined Patent Publication No. 2006-261636

 Patent Document 6: JP-A-2005-171378

 Patent Document 7: Japanese Patent Application Laid-Open No. 2004-55842

 Disclosure of the invention

 [0025] In recent years, from the viewpoint of yield improvement and productivity improvement, the process temperature for manufacturing a display device tends to be lower. For example, source / drain electrode materials for amorphous silicon TFTs are required to have low electrical resistivity and high heat resistance, and the required specifications have been about 7 Ω'cm or less in terms of electrical resistivity. The temperature is about 250 ° C. This heat-resistant temperature is determined by the maximum temperature that is applied to the source-drain electrode in the manufacturing process, and this maximum temperature is the formation temperature of the insulating film formed as a protective film on the electrode. Recently, it has become possible to obtain a desired insulating film even at a low temperature by improving the film forming technique. In particular, the protective film on the source-drain electrode can be formed at about 220 ° C.

[0026] Therefore, in addition to being a wiring material that can directly connect the drain electrode and the transparent pixel electrode, the heat resistance temperature is 220 ° C level and the electrical resistivity is about 4.5 μΩ 'cm or less. In addition, the electrical resistivity is preferably sufficiently low, and preferably excellent in dry etching property. It is.

 [0027] However, an A1-based wiring material that combines such a low electrical resistivity and high heat resistance and is preferably excellent in dry etching and can be directly connected to a transparent pixel electrode is disclosed. Not.

 [0028] For example, the A1 alloy film disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 2004-214606 has a low electrical resistivity but a low heat resistance temperature.

 [0029] Further, even the A1 alloy film disclosed in the above-mentioned JP-A-2006-261636 cannot be said to be sufficient at about 7 Ω'cm when heated at 250 ° C.

 [0030] Thus, in the conventional A1 alloy film such as Al_Nd alloy, when the process temperature is lowered, the precipitation of the intermetallic compound and the crystal growth do not sufficiently proceed as shown below. If the amount of Nd added is reduced, the process temperature will be low even if the process temperature is low! /, But electrical resistivity will be obtained, but crystal growth will progress with less precipitates, hillocks will occur, and the heat resistance temperature will soon increase. It is thought to go down.

 Hereinafter, this point will be described in detail.

 [0032] The A1 alloy film generally has a force S formed by a sputtering method, and according to this method, an alloy component added to the A1 beyond the solid solubility limit exists in a forced solid solution state. The electrical resistivity of A1 alloys containing solid solution alloy elements is generally higher than pure A1. In contrast, when the A1 alloy film containing the alloy element exceeds the solid solubility limit, the alloy component precipitates at the grain boundary as an intermetallic compound when heated, and when further heated, the recrystallization of A1 proceeds, and A1 crystal growth Happens. At this time, the precipitation temperature of the intermetallic compound and the temperature of crystal growth are different forces S depending on the alloy element. In any case, the A1 alloy film depends on the precipitation of the alloy component (intermetallic compound) and the crystal growth. The electrical resistivity of the liquid crystal is lowered.

[0033] The force that increases the compressive stress inside the film as the crystal growth progresses due to heating. When the crystal growth progresses further by heating, it finally becomes unbearable, and A1 diffuses on the film surface to relax the stress and hillocks. (Hump-like projections) are generated. Alloying has the effect of preventing the generation of hillocks by suppressing the diffusion of A1 by the intermetallic compounds precipitated at the grain boundaries, and improving the heat resistance. Conventionally, precipitation of alloy components and progress of crystal growth have been promoted by utilizing these phenomena, and both reduction of the electrical resistivity of the A1 alloy film and high heat resistance have been achieved. [0034] However, when the process temperature is lowered as described above, in the conventional alloy components, the precipitation of intermetallic compounds does not occur sufficiently, and as a result, the crystal growth does not progress and the electrical resistivity is reduced. When it becomes difficult, it is ignored.

 In the above description, the liquid crystal display device is representatively described. However, the above-described problem is not limited to the liquid crystal display device, and can be commonly seen in the amorphous silicon TFT substrate. The above problems are also observed when polycrystalline silicon is used in addition to amorphous silicon as the TFT semiconductor layer.

 [0036] On the other hand, as described above, the A1 alloy film is also required to have excellent dry etching properties in addition to the above-mentioned characteristics. An A1 alloy thin film having all these characteristics is still provided. It has not been.

 [0037] The present invention has been made paying attention to such a situation, and the object thereof is to make it possible to omit the rare metal layer, simplify the process without increasing the number of steps, and conduct the A1 alloy film. Even when a lower heat treatment temperature is applied in a shorter time to an A1 alloy film that can be connected directly and securely to a transparent pixel electrode made of a conductive oxide film, the electrical resistivity between the transparent pixel electrodes can be reduced. It is an object of the present invention to provide a technique capable of achieving reduction and excellent heat resistance, and preferably excellent in dry etching property. Specifically, as a measure of electrical resistivity and heat resistance, the A1 system that does not cause defects such as hillocks even when heat treatment at a lower temperature, such as 220 ° CX for 20 minutes, is used in a shorter time. To provide TFT substrates and display devices that can further reduce the electrical resistivity of alloy thin films and can be adapted to lower processing temperatures, and for the formation of A1-based alloy thin films that are useful for the production of such display devices. It is providing the sputtering target of this.

 [0038] The A1 alloy film for a display device of the present invention that has solved the above problems is an A1 alloy film for a display device that is directly connected to a conductive oxide film on a substrate, and the A1 alloy film is , Containing 0.5 to 0.5 atomic% of Ge, and containing 0.05 to 0.45 atomic% of Gd and / or La in total. Gd and La may be contained alone in an amount of 0.05-0.45 atomic%, or in total, 0.05 to 0.45 atomic%.

[0039] Another display device A1 alloy film of the present invention that has solved the above problems is an A1 alloy film for display devices that is directly connected to an amorphous Si layer or a polycrystalline Si layer on a substrate. The Al alloy film contains 0.05 to 0.5 atomic percent of Ge and 0.05 to 0.45 atomic percent of Gd and / or La in total. Gd and La are each independently 0.0.

It may be contained in an amount of 5 to 0.45% by atom, or it may be contained in a total amount of 0.05-0.45% by atom.

[0040] Here, if Gd and / or La 0. The total 05-0. 35 atoms _^0/0 containing display Debai A1 alloy film for a scan, so that dry etching characteristics is further enhanced.

[0041] The A1 alloy film for display device described above is further adjusted to contain 0.05 to 0.5 to 35 atomic% of Ni and the total content of Ge and Ni to 0.45 atomic% or less. It is recommended that

[0042] A display device of the present invention that has solved the above-described problems includes the above-described A1 alloy film and a thin film transistor.

[0043] Another display device of the present invention that has solved the above-described problem is one in which the above-described A1 alloy film is used for a gate electrode and a scanning line of a thin film transistor and is directly connected to a conductive oxide film. .

 [0044] Another display device of the present invention capable of solving the above-described problems is used for the source electrode and / or drain electrode and signal line of the above-described A1 alloy film force thin film transistor, and a conductive oxide film and / or It is directly connected to an amorphous Si layer or a polycrystalline Si layer.

 A configuration in which the source electrode and / or the drain electrode and the signal line of the thin film transistor are formed of the same material as the gate electrode and the scanning line of the thin film transistor is recommended.

 [0046] The conductive oxide film is preferably formed of a composite oxide containing at least one selected from the group consisting of indium oxide, zinc oxide, tin oxide, and titanium oxide.

[0047] The electrical resistivity of the A1 alloy film for display devices is preferably 4.5 μΩ 'cm or less.

Yes

 [0048] The sputtering target of the present invention that has solved the above-mentioned problems contains Ge in a range of 0.05 to 0.5 atomic%, and Gd and / or La in a total amount of 0.05 to 0.45 atomic%. It is something. Gd and La may be contained alone in an amount of 0.05-0.45 atomic percent, or a total of 0.05 to 0.45 atomic percent may be contained.

[0049] The above sputtering target is further a 0-05-0. 35 atoms _^0/0 containing Ni, and, Ge It is recommended that the content of Ni and Ni be adjusted to 0.45 atomic% or less.

[0050] According to the present invention, the A1 alloy film can be directly connected to the transparent pixel electrode made of a conductive oxide film without interposing a barrier metal layer, and is relatively low at about 220 ° C. Even when the heat treatment temperature is applied, an A1 alloy film for display devices in which sufficiently low electrical resistivity and excellent heat resistance are ensured, and a display device using the same can be provided. The above heat treatment temperature refers to the highest heat treatment temperature in a TFT (thin film transistor) array manufacturing process, for example, and in a general display device manufacturing process, a CVD film for forming various thin films is formed. It means the heating temperature of the substrate and the temperature of the heat treatment furnace when the protective film is thermally cured.

For example, if the A1 alloy film used in the present invention is applied to the wiring material of the source-drain electrode, the barrier metal layer 54 shown in FIG. 2 can be omitted. Further, if the A1 alloy film used in the present invention is applied to the gate electrode and its wiring material, it is possible to omit the barrier metal layers 51 and 52 shown in FIG.

[0052] Further, by controlling the content of Gd and / or La, in addition to the above characteristics, dry etching can be further enhanced.

 [0053] If the A1 alloy film for display devices of the present invention is used, a display device having excellent productivity, low cost and high performance can be obtained.

 Brief Description of Drawings

 [0054] FIG. 1 is an enlarged schematic cross-sectional explanatory view showing a configuration of a typical liquid crystal display to which an amorphous silicon TFT substrate is applied.

 [FIG. 2] FIG. 2 is a schematic cross-sectional explanatory view showing a configuration of a conventional typical amorphous silicon TFT substrate.

 FIG. 3 is a schematic cross-sectional explanatory view showing the configuration of the TFT substrate according to the first embodiment of the present invention.

 FIG. 4 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.

FIG. 5 is an explanatory view showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 3. FIG. 6 is an explanatory view showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 3.

 FIG. 7 is an explanatory view showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 3.

 FIG. 8 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.

 FIG. 9 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.

 FIG. 10 is an explanatory view showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 3.

11] FIG. 11 is an explanatory diagram showing an example of the manufacturing process of the TFT substrate shown in FIG. 3 in order.

12] FIG. 12 is a schematic cross-sectional explanatory view showing the configuration of the TFT substrate according to the second embodiment of the present invention.

 FIG. 13 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG.

 FIG. 14 is an explanatory diagram showing an example of the manufacturing process of the TFT substrate shown in FIG. 12 in order.

 FIG. 15 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 12.

 FIG. 16 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG.

 FIG. 17 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 12.

 FIG. 18 is an explanatory diagram showing, in order, an example of the manufacturing process of the TFT substrate shown in FIG. 12.

FIG. 19 is an explanatory diagram showing, in order, an example of a manufacturing process of the TFT substrate shown in FIG. 12. FIG. 20 is a diagram showing a Kelvin pattern (TEG pattern) used for measurement of contact resistivity (connection resistivity) between an Al alloy film and a transparent conductive film.

 FIG. 21 is a view showing a contact resistivity between an A1 alloy film and a transparent conductive film.

 FIG. 22 is a diagram showing the correlation between the heat treatment time of the A1 alloy film and the electrical resistivity.

 FIG. 23 is a diagram showing a TEG for evaluation of Si direct contact characteristics.

 FIG. 24 is a graph showing the drain current-gate voltage switching characteristics of a TFT.

 FIG. 25 is a schematic view of a dry etching apparatus used in Examples.

 FIG. 26 shows the etching time and the pure A1 film after etching in Example 6

This is a graph of the relationship with the thickness of the A1 alloy film.

 FIG. 27 is a graph showing the relationship between the Ge amount in the A1 alloy film and the etching rate ratio in Example 7.

 FIG. 28 is a graph showing the relationship between the amount of Gd / La in the A1 alloy film and the etching rate ratio in Example 7.

 FIG. 29 is a graph showing the relationship between the amount of Ni in the A1 alloy film and the etching rate ratio in Example 7.

Explanation of symbols

1 TFT substrate

2 Counter substrate

3 liquid crystal layer

 4 Thin film transistor (TFT)

 5 Transparent pixel electrode

 6 Wiring section

 7 Common electrode

 8 color finoleta

 9 Shading film

 10a, 10b polarizing plate

 11 Alignment film

12 TAB tape Driver circuit

Control circuit

Spacer

Sealing material

Protective film

Diffusion plate

Prism sheet

Light guide plate

a reflector

Knock light

Holding frame

Printed board

Scan line

Gate electrode

Gate insulation film

Source electrode

Drain electrode

Protective film (silicon nitride film)

Photoresist

Contact Honoré

Amorphous silicon channel film (active semiconductor film) Signal line (source-drain wiring)

52, 53, 54 Nolia methanol layer

Non-doped hydrogenated amorphous silicon film (aS to H) n ⁺ type hydrogenated amorphous silicon film (n ⁺ aS to H) Chamber

Dielectric window

antenna 64 high frequency power (antenna side)

 65 matcher (antenna side)

 66 Process gas inlet

 67 substrate (material to be etched)

 68 Susceptor

 69 dielectric chuck

 70 colors

 71 Matching device (board side)

 72 high frequency power (board side)

 BEST MODE FOR CARRYING OUT THE INVENTION

 [0056] The present inventor can directly connect to a transparent pixel electrode made of a conductive oxide film and each electrode such as a source, drain, and gate of a thin film transistor, and has a relatively low force of about 220 ° C. ! /, Low enough even when heat treatment temperature is applied! /, Which has both electrical resistivity and excellent heat resistance, and preferably eagerly to provide a new wiring material with excellent dry etching properties I have been considering it. In particular, the inventor further reduces the electrical resistivity in the A1-based alloy thin film even under conditions of lower temperature and shorter time than the heat treatment conditions described in the above-mentioned JP-A-2006-261636. Based on the viewpoint of further improving the heat resistance, studies have been repeated. As a result, among the alloy components belonging to group α described in JP-A-2006-261636, in particular, Ge is contained in a specific range, and a predetermined amount of Gd and / or La is used as the third component. The inventors have found that the intended purpose can be achieved and completed the present invention.

[0057] According to the present invention, since a predetermined amount of Ge is contained as an alloy component in the A1 alloy film, the heat treatment in the process after the formation of the A1 alloy film is performed at a relatively low temperature for a short time. The contact resistance between the A1 alloy film and the transparent pixel electrode and the source “drain” gate of the thin film transistor and each electrode can be kept low. Further, as will be described later, the A1 alloy film to which Ge is added is compared with the A1 alloy film to which Ni, Ag, Zn, and Cu are added, which is included in the group α described in JP-A-2006-261636. There is little variation in contact resistance. [0058] Further, according to the present invention, since a predetermined amount of Gd and / or La is contained in the A1 alloy film as a heat resistance improving element, hillocks and the like can be obtained even by heat treatment at 220 ° C to 300 ° C. Excellent heat resistance can be ensured without generating heat. In addition, if the Gd and / or La content and the Ni content are appropriately controlled, the dry etching property can be improved.

 Therefore, according to the present invention, the transparent pixel electrode having both sufficiently low! /, Electrical resistivity and sufficiently high // heat resistance, and preferably excellent in dry etching property. It is possible to provide a wiring material that can be directly connected to the wiring.

 [0060] In this specification, "dry etching" means removal of an object to be etched (interlayer insulating film), and the purpose of cleaning the surface of the A1 alloy film even after the contact hole reaches the A1 alloy film. This also means that the surface of the A1 alloy film is exposed to an etching gas.

 In the present specification, “excellent in dry etching property” means (a) a small amount of residue generated after etching and (i) a high etching rate ratio. . Specifically, when the above characteristics (a) and (i) were evaluated by the method described in the examples described later, (a) no residue was generated after etching, and (i) the etching rate ratio was 0. Those that satisfy 3 or more are called “excellent dry etching”. Those satisfying these characteristics are excellent in dry etching properties, so the precise control of the wiring dimensions' shape can be achieved with the force S.

 Here, the “etching rate ratio” is an index of the ease of etching of the A1 alloy thin film by plasma irradiation. In this specification, the etching rate ratio is the ratio of the etching rate of the A1 alloy film based on the etching rate of pure A1 with a good etching rate (that is, the etching rate of the A1 alloy film is Nl, When the etching rate is N2, the ratio is expressed as the ratio of N1 / N2. The higher the etching rate ratio, the shorter the dry etching processing time and the higher the productivity.

[0063] First, the action of Ge used in the A1 alloy film of the present invention will be described.

[0064] Ge is particularly useful for reducing the contact resistance between the A1 alloy film and the transparent pixel electrode. Specifically, Ge is added in the range of 0.05 to 0.5 atomic%. The reason why the Ge content is 0.05 atomic% or more is to exhibit the effect of reducing contact resistance. Preferably it is 0.07 atomic% or more, More preferably, it is 0.1 atomic% or more. On the other hand, the Ge content is 0.5 The reason for not more than atomic% is to prevent the electrical resistivity of the Al alloy film from becoming too high. Preferably it is 0.4 atomic% or less, more preferably 0.3 atomic% or less.

 [0065] Here, the effect of Ge on the electrical resistance of the A1 alloy film will be described in a little more detail.

 When Ge is added to the A1 alloy film, a Ge-containing precipitate (Ge-containing precipitate) or a concentrated layer (Ge-containing concentrated) is formed at the connection interface between the A1 alloy film and the transparent pixel electrode at a relatively low heat treatment temperature. Therefore, as shown in the examples described later, the electrical resistivity when heat-treated at 220 ° C. for 10 minutes can be reduced to approximately 4.5 Ω′cm or less.

 [0066] Further, as shown in the examples described later, if Ge is within the above range, dry etching can be performed well.

 [0067] Here, the "Ge-containing precipitate" means a precipitate in which Ge is precipitated, for example, an Al-Ge-Gd alloy, an A Ge-La alloy, or an Al-Ge-Gd-La alloy. Examples include Ge alone, an intermetallic compound of A1, Ge, and Gd, an intermetallic compound of A1, Ge, and La, or an intermetallic compound of A1, Ge, Gd, and La.

 [0068] In addition, the "Ge-containing concentrated layer" means that the average concentration of Ge in the Ge concentrated layer is Al-Ge-Gd alloy, A Ge-La alloy or Al-Ge-Gd- This means that the average concentration of Ge in the La alloy is 2 times or more, preferably 2.5 times or more.

 [0069] In the A1 alloy film containing Ge, Ge exceeding the solid solubility limit (0.1 atomic%) of Ge in the A1 alloy film is precipitated at the grain boundary of the A1 alloy film by heat treatment or the like. The Ge may be diffused and concentrated on the surface of the A1 alloy film to form a Ge-enriched layer. Such a Ge enriched layer is also included in the “Ge-containing enriched layer”. Also, for example, when etching contact holes, the Ge halogen compound remains on the surface of the A1 alloy film, where the vapor pressure is lower than that of the A1, and it is difficult to volatilize. It is in a higher concentration state than the Ge concentration of A1 alloy bulk material. Such an embodiment is also included in the “Ge-containing concentrated layer”. By appropriately controlling the etching conditions, the Ge concentration of the A1 alloy thin film surface layer and the thickness of the Ge-containing concentrated layer change. At this time, depending on Gd or La used as the third component, part of the force may be concentrated on the surface layer side. Such a mode is also included in the above-mentioned “Ge-containing concentrated layer”. included.

[0070] The thickness of the Ge-containing concentrated layer is preferably 0.5 nm or more and 10 nm or less. More preferably, it is not less than Onm and not more than 5 nm.

 [0071] As shown below, the electrical resistivity of the Al-Ge alloy binary alloy after heat treatment at 220 ° C for 10 minutes is very low. The third component is contained in the Al-Ge alloy. When further added, the electrical resistivity tends to increase. Therefore, when the purpose is only to reduce the electrical resistivity, an Al_Ge alloy binary alloy may be used, but as mentioned above, the heat resistance is reduced to about 150 ° C. Therefore, for the purpose of providing a wiring material having both low electrical resistivity and high heat resistance as in the present invention, a binary alloy of Al-Ge alloy is insufficient, and will be described below. Thus, the ternary alloy of Al-Ge-Gd alloy or Al-Ge-La alloy or the quaternary alloy of Al-Ge-Gd-La alloy was used.

[0072] By using an Al-Ge-Gd alloy, an Al-Ge-La alloy ternary alloy, or an Al-Ge-Gd-La alloy quaternary alloy, the heat resistance of the A1 alloy film is significantly improved. It is possible to effectively prevent hillocks from forming on the surface of the A1 alloy film. In order to effectively obtain the heat resistance effect, the content of Gd and La must be 0.05 atomic% or more. Preferably, it is 0.1 atomic% or more. On the other hand, if the content of Gd and La is excessively increased, the electrical resistivity of the A1 alloy film will increase, so the upper limit of the content is 0.45 atomic%, more preferably 0.4 atomic percent. _^0/0, more preferably from 0.3 atomic%. These elements may be added alone or in combination of two or more. When adding two or more elements, the total content of each element only needs to satisfy the above range.

 [0073] In consideration of improvement in dry etching property, the upper limit of the content of Gd and / or La is preferably set to 0.35 atomic%. This is because, as shown in the examples described later, if it exceeds 0.35 atomic%, the etching rate ratio is lowered, and residues may be generated after dry etching. If only dry etching properties are considered, the upper limit of the content of Gd and / or La is better. If you want to reduce the electrical resistivity, improve the heat resistance, and improve the dry etching properties of the A1 alloy film, the Gd and / or La content should be approximately 0.1 atomic% or more. It is more preferable to make it atomic% or less.

[0074] Furthermore, when Ni is added to the ternary alloy of A Ge-Gd alloy or AH ^ e-La alloy or the quaternary alloy of AH ^ e-Gd-La alloy, the A1 alloy film and transparent pixel Electrode or A1 alloy film And the contact resistance between each electrode of the source 'drain' gate can be reduced. In order to exert such an effect, it is preferable to contain 0.05 atomic% or more of Ni. More preferably, it is 0.07 atomic% or more, and still more preferably 0.1 atomic% or more. On the other hand, if the Ni content increases too much, the electrical resistivity of the A1 alloy film increases, so the upper limit of the Ni content is preferably 0.35 atomic%, more preferably 0.3 atomic%. More preferably, it is 0.25 atomic%, and still more preferably 0.20 atomic%.

[0075] If the amount of Ni is within the above range, residues after etching are not generated, and a high etching rate ratio is obtained, so that excellent dry etching properties are exhibited (see Examples described later). .

 [0076] Further, when each of the ternary alloy of AH ^ e-Gd alloy or AH ^ e-La alloy or the quaternary alloy of Al-Ge-Gd-La alloy contains Ni, Ge and Ni The total content of is preferably in the range of 0.;! To 0.45 atomic%. When the total amount of Ge and Ni is less than 0.1 atomic%, the contact electrical resistance between the A1 alloy film and the transparent pixel electrode cannot be kept low, and the above-described action of Ge and Ni becomes effective. It is not demonstrated. On the other hand, even if the single content of Ge and Ni satisfies the above-mentioned range, the etching rate ratio decreases when the total amount of Ge and Ni exceeds 0.6 atomic% (described later). See Examples). The upper limit of the total amount of Ge and Ni is more preferably 0.35 atomic%, even more preferably 0.30 atomic% or less.

 Hereinafter, preferred embodiments of the TFT substrate according to the present invention will be described with reference to the drawings. In the following, a liquid crystal display device including an amorphous silicon TFT substrate or a polysilicon TFT substrate will be described as a representative example, but the present invention is not limited to this, and is suitable within a range that can meet the purpose described above. It is also possible to carry out with modifications, and both of them are included in the technical scope of the present invention. The A1 alloy film used in the present invention is also applied to, for example, a reflective electrode such as a reflective liquid crystal display device and a TAB (tab) connecting electrode used for signal input / output to the outside. It is confirmed by.

 (Embodiment 1)

An embodiment of an amorphous silicon TFT substrate will be described in detail with reference to FIG. FIG. 3 is a schematic diagram illustrating a preferred embodiment of a bottom-gate TFT substrate according to the present invention. FIG. In Fig. 3, the same reference numerals as those in Fig. 2 are given to indicate a conventional TFT substrate.

 [0079] As is apparent from the comparison between FIG. 2 and FIG. 3, in the conventional TFT substrate, as shown in FIG. 2, the top of the scanning line 25, the top of the gate electrode 26, the top of the source-drain wiring 34, or Below, the metal layers 51, 52, 54, and 53 are formed, respectively, whereas the metal layers 51, 52, and 54 can be omitted in the TFT substrate of the present embodiment. That is, according to the present embodiment, the wiring material used for the TFT source-drain electrode 29 without the barrier metal layer interposed as in the prior art can be directly connected to the transparent pixel electrode 5, thereby However, it can achieve good TFT characteristics equivalent to or better than those of conventional TFT substrates (see the examples below).

 Note that the wiring material used in the present invention is applied to the wiring material of the source-drain electrode and the gate electrode as in this embodiment. For example, if the wiring material of the present invention is applied to a wiring material for a gate electrode, the noor metal layers 51 and 52 can be omitted. Even in these embodiments !, we are confident that we can achieve good TFT characteristics comparable to or better than conventional TFT substrates.

 Next, an example of a method for manufacturing the amorphous silicon TFT substrate according to the present invention shown in FIG. 3 will be described with reference to FIGS. 4 to 11. Here, A1-0. 2 atomic% 06_0.2 atomic% 0 (1 alloy is used as the material used for the source-drain electrode and its wiring. Also, as the material used for the gate electrode and its wiring. A1-0. 2 atomic% 06- 0.35 atomic% 0 (1 alloy is used. The thin film transistor is an amorphous silicon TFT using hydrogenated amorphous silicon as the semiconductor layer. FIG. 11 has the same reference numerals as FIG.

[0082] First, on a glass substrate (transparent substrate) la, a sputtering method is used to form an A1-0.2 atomic% 06_0.35 atomic% 0 (one alloy film having a thickness of about 200 nm. The temperature was set to 150 ° C. By patterning this film, the gate electrode 26 and the scanning line 25 were formed (see FIG. 4), in which case the coverage of the gate insulating film 27 in FIG. It is preferable to etch the peripheral edge of the laminated thin film into a taper of about 30 ° to 40 ° so that the die is improved. Next, as shown in FIG. 5, a gate insulating film 27 is formed with a silicon oxide film (SiOx) having a thickness of about 30 Onm by using a method such as a plasma CVD method. The deposition temperature for the plasma CVD method was about 350 ° C. Subsequently, using a method such as plasma CVD, a hydrogenated amorphous silicon film (aS to H) 55 having a thickness of about 50 nm and a silicon nitride film (SiNx) having a thickness of about 300 nm are formed on the gate insulating film 27. Is deposited.

Subsequently, by backside exposure using the gate electrode 26 as a mask, a silicon nitride film (SiNx) is patterned as shown in FIG. 6 to form a channel protective film. Further, an n ⁺ type hydrogenated amorphous silicon film (n ⁺ aS to H) 56 having a thickness of about 50 nm doped with phosphorus is formed thereon, and then a hydrogenated amorphous silicon film (n aS to H) 55 and n ⁺ type hydrogenated amorphous silicon film (n ⁺ a_S to H) 56 are patterned.

[0085] Next, thereon by sputtering, the Mo film 53 and the thickness of about 300 nm thickness of about 50 nm A O. 2 atoms ⁰ / _o Ge_0. 2 atoms _^0/0 Gd alloy film 28 , 29 and a Mo film (not shown) having a thickness of about 50 nm are sequentially stacked. The deposition temperature for sputtering was 150 ° C. Next, by patterning as shown in FIG. 8, the source electrode 28 integrated with the signal line and the drain electrode 29 directly connected to the pixel electrode 5 are formed. Further, using the source electrode 28 and the drain electrode 29 as a mask, the n ⁺ type hydrogenated silicon silicon film (n ⁺ aS to H) 56 on the channel protective film (SiNx) is removed by dry etching.

 Next, as shown in FIG. 9, a silicon nitride film 30 having a thickness of about 300 nm is formed using a plasma CVD apparatus, for example, to form a protective film. The film formation temperature at this time is, for example, about 220 ° C. Next, after a photoresist layer 31 is formed on the silicon nitride film 30, the silicon nitride film 30 is patterned, and contact holes 32 are formed in the silicon nitride film 30 by, for example, dry etching. At the same time, a contact hole (not shown) is formed in a portion corresponding to the connection with TAB on the gate electrode at the end of the panel.

Next, after an ashing process using, for example, oxygen plasma, as shown in FIG. 10, the photoresist layer 31 is stripped using, for example, an amine-based stripping solution. Finally, for example, within the range of the storage time (about 8 hours), as shown in FIG. 11, an ITO film having a thickness of, for example, about 40 nm is formed and patterned by wet etching to form the transparent pixel electrode 5. Form. At the same time, connect the TAB to the TAB connection part of the gate electrode at the panel edge. The TFT array substrate 1 is completed by patterning the ITO film for indexing.

In the TFT substrate manufactured in this way, the drain electrode 29 and the transparent pixel electrode 5 are in direct contact, and the gate electrode 26 and the ITO film for TAB connection are also in direct contact.

 In the above, as the transparent pixel electrode 5, a composite oxide containing at least one of a force using an ITO (indium tin oxide) film, indium oxide, zinc oxide, tin oxide, and titanium oxide may be used. For example, an IZO film (Ιηθχ-Ζηθχ-based conductive oxide film) can be used. Further, polysilicon may be used as the active semiconductor layer instead of amorphous silicon V (see Embodiment 2 described later).

 Using the TFT substrate thus obtained, for example, the liquid crystal display device shown in FIG. 1 is completed by the method described below.

 First, for example, polyimide is applied to the surface of the TFT substrate 1 manufactured as described above, and after drying, a rubbing treatment is performed to form an alignment film.

 On the other hand, the counter substrate 2 forms the light shielding film 9 on a glass substrate by patterning, for example, chromium (Cr) in a matrix. Next, resin red, green and blue color filters 8 are formed in the gaps between the light shielding films 9. A counter electrode is formed by disposing a transparent conductive film such as an ITO film as the common electrode 7 on the light shielding film 9 and the color filter 8. Then, for example, polyimide is applied to the uppermost layer of the counter electrode, and after drying, a rubbing process is performed to form the alignment film 11.

 [0093] Next, the TFT substrate 1 and the surface of the counter substrate 2 on which the alignment film 11 is formed are arranged so as to face each other, and the TFT is removed by a sealing material 16 made of resin, excluding the liquid crystal sealing port. Bond substrate 1 and 22 counter substrates. At this time, the gap between the two substrates is kept substantially constant by interposing a spacer 15 between the TFT substrate 1 and the counter substrate 2.

 [0094] The empty cell obtained in this way is placed in a vacuum, and gradually returned to atmospheric pressure with the sealing port immersed in liquid crystal, whereby a liquid crystal material containing liquid crystal molecules is injected into the empty cell. A liquid crystal layer is formed and the sealing port is sealed. Finally, a polarizing plate 10 is attached to both sides of the empty cell to complete the liquid crystal display.

Next, as shown in FIG. 1, the driver circuit 13 for driving the liquid crystal display device is connected to the liquid crystal display. Electrically connected to the lay and placed on the side or back of the liquid crystal display. Then, the liquid crystal display is held by the holding frame 23 including the opening serving as the display surface of the liquid crystal display, the backlight 22 that forms the surface light source, the light guide plate 20, and the holding frame 23, thereby completing the liquid crystal display device.

[0096] (Embodiment 2)

 An embodiment of a polysilicon TFT substrate will be described in detail with reference to FIG.

 FIG. 12 is a schematic cross-sectional explanatory view for explaining a preferred embodiment of a top gate type TFT substrate according to the present invention. In FIG. 12, the same reference numerals as those in FIG. 2 described above showing the conventional TFT substrate are attached.

 In this embodiment, polysilicon is used instead of amorphous silicon as an active semiconductor layer, a top gate type TFT substrate is used instead of a bottom gate type, and source-drain electrodes and gate electrodes are used. A1-0. 2 atomic% 06_0.2 atomic% 0 (one alloy is used in the point that the alloy is used as the wiring material of the source-drain electrode instead of the wiring material, which satisfies the requirements of the present invention. Specifically, in the polysilicon TFT substrate of this embodiment shown in FIG. 12, the active semiconductor film is composed of a polysilicon film (poly-Si) that is not doped with phosphorus and phosphorus or arsenic. This is different from the amorphous silicon TFT substrate shown in Fig. 3 described above in that (As) is formed from a polysilicon film (η + poly-Si) into which ions are implanted. Run through (SiOx) It is formed in so that to intersect the line.

 According to the present embodiment, the near metal layer 54 can be omitted. That is, the wiring material used for the TFT source-drain electrode 29 without the barrier metal layer interposed can be directly connected to the transparent pixel electrode 5 as in the prior art. Experiments have confirmed that good TFT characteristics equivalent to or higher than those of the substrate can be achieved.

In the present embodiment, if the above alloy is applied to the wiring material of the gate electrode, the force S for omitting the rare metal layers 51 and 52 can be achieved. In addition, if the above alloy is applied to the wiring material of the source-drain electrode and the gate electrode, the rare metal layers 51, 52, and 54 can be omitted. Even in these cases, good TFT characteristics equivalent to or better than those of conventional TFT substrates were achieved. Be patient with what you are doing!

 [0100] Next, an example of a method for manufacturing the polysilicon TFT substrate according to the present invention shown in FIG. 12 will be described with reference to FIGS. Here, A1-0.2 atom% 06_0.2 atom% 0 (1 alloy is used as the source-drain electrode and its wiring material. The thin film transistor is made of a polysilicon film (poly-Si). This is a polysilicon TFT used as a semiconductor layer, and the same reference numerals as those in FIG.

[0101] First, a silicon nitride film (SiNx) having a thickness of about 50 nm and a silicon oxide film having a thickness of about lOOnm (SiOx) on a glass substrate la by a plasma CVD method or the like, for example, at a substrate temperature of about 300 ° C. ), And a hydrogenated amorphous silicon film (a-Si-H) with a thickness of about 50 nm. Next, heat treatment (about 470 ° C for about 1 hour) and laser annealing are performed to convert the hydrogenated amorphous silicon film (a-Si-H) to polysilicon. After dehydrogenation treatment, for example, using an excimer laser annealing apparatus, the hydrogenated amorphous silicon film (aS to H) is irradiated with a laser having an energy of about 230 mj / cm ² to obtain a thickness of about 0. A polysilicon film (poly-Si) of about 3 mm is obtained (Fig. 13).

 Next, as shown in FIG. 14, the polysilicon film (poly-Si) is patterned by plasma etching or the like. Next, as shown in FIG. 15, a silicon oxide film (SiOx) having a thickness of about lOOnm is formed, and a gate insulating film 27 is formed. On the gate insulating film 27, by sputtering, etc., 8 1-2 atoms / (^ (1 alloy thin film and approximately 50 nm thick Mo thin film 52 approximately 50 nm thick) are stacked and then plasma etching is performed. Thus, the gate electrode 26 integrated with the scanning line is formed.

Subsequently, as shown in FIG. 16, a mask is formed with a photoresist 31, and, for example, phosphorus is doped with, for example, about 1 × 10 ¹⁵ pieces / cm ^{2 at} about 50 keV by using an ion implantation apparatus or the like to form a polysilicon film. An n ⁺ type polysilicon film (η + poly-Si) is formed on a part of (poly-Si). Next, the photoresist 31 is peeled off, and phosphorus is diffused by heat treatment at about 500 ° C., for example.

Next, as shown in FIG. 17, using a plasma CVD apparatus or the like, a silicon oxide film (SiOx) having a thickness of about 500 nm is formed at a substrate temperature of about 250 ° C. to form an interlayer insulating film. In the same way, using a mask patterned with photoresist, the interlayer insulating film (SiOx) and the silicon oxide film of the gate insulating film 27 are dry-etched to form contact holes. By sputtering, the Mo film 53 with a thickness of about 50 nm and the 0.2 atomic% 06_0.2 atomic% 0 with a thickness of about 450 nm are formed into a signal line by patterning after forming an alloy thin film. An integrated source electrode 28 and drain electrode 29 are formed, and as a result, the source electrode 28 and the drain electrode 29 are contacted with the n ⁺ type polysilicon film (n ⁺ poly-Si) through the contact holes, respectively. .

Next, as shown in FIG. 18, a silicon nitride film (SiNx) having a thickness of about 500 nm is formed at a substrate temperature of about 220 ° C. by using a plasma CVD apparatus or the like to form an interlayer insulating film. After a photoresist layer 31 is formed on the interlayer insulating film, a silicon nitride film (SiNx) is patterned, and contact holes 32 are formed in the silicon nitride film (SiNx), for example, by dry etching.

 Next, as shown in FIG. 19, after undergoing an ashing process using, for example, oxygen plasma, the photoresist is stripped using an amin-based stripping solution in the same manner as in the first embodiment, and then An ITO film is formed and patterned by wet etching to form the pixel electrode 5.

In the polysilicon TFT substrate manufactured in this way, the drain electrode 29 is in direct contact with the transparent pixel electrode 5. Constructing the drain electrode 29 Α 0 · 2 atomic% 0 ₆ -0. 2 atomic% 0 (A Ge-concentrated layer is formed at the interface between the alloy thin film and the pixel electrode 5 to reduce the contact resistance. At the same time, since Ge diffuses and precipitates as a single substance, the recrystallization of A1 is promoted, and the electrical resistivity of the A1 alloy film itself is greatly reduced.

 Next, in order to stabilize the characteristics of the transistor, for example, heat treatment is performed at about 220 ° C. for about 1 hour to complete a polysilicon TFT array substrate.

 [0109] According to the TFT substrate according to the second embodiment and the liquid crystal display device including the TFT substrate, the same effects as those of the TFT substrate according to the first embodiment described above can be obtained. The A1 alloy in the second embodiment can also be used as a reflective electrode for reflective liquid crystals.

 [0110] Using the TFT array substrate thus obtained, a liquid crystal display device is completed in the same manner as the TFT substrate of Embodiment 1 described above.

[0111] As described above, the A1 alloy film of the present invention is also excellent in dry etching property. Less than, The dry etching process will be described.

[0112] In the dry etching process, generally, a halo such as C1 is formed on a substrate placed in a vacuum vessel.

 2 The source gas containing the source gas is turned into plasma by high-frequency power, and on the other hand, by applying another high-frequency power to the susceptor on which the substrate (etching material) is placed, ions in the plasma are drawn onto the substrate, Anisotropy by ion-assisted reaction with reactive plasma.

[0113] For example, when a typical C1 gas is used as an etching gas, the C1 gas is converted into plasma.

 2

 Thus, it is dissociated to produce C1 radical. This C1 radical is adsorbed on the A1 alloy thin film, which is a highly reactive material to be etched, and generates chloride on the surface of the A1 alloy thin film. Since a high-frequency bias is applied to the substrate on which the A1 alloy thin film is formed, ions in the plasma are accelerated and incident on the surface of the A1 alloy thin film, and chloride is evaporated by this ion bombardment effect. Is exhausted out of the vacuum container!

 [0114] In order to perform dry etching efficiently, the vapor pressure of the generated chloride is preferably relatively high. If the vapor pressure is high, chloride can be evaporated by the physical assistance of the surface temperature of the A1 alloy thin film and ion bombardment. On the other hand, when the vapor pressure of chloride is low, chloride remains on the surface without evaporation and etching residue (residual etching generated during dry etching) occurs.

 [0115] The present invention is not limited to a dry etching method or an apparatus used for the dry etching process. For example, a general dry etching process can be performed using a general-purpose dry etching apparatus as shown in FIG. In the examples described later, a single (inductively coupled plasma) type dry etching apparatus shown in FIG. 25 was used.

 Hereinafter, the power to explain a typical dry etching process using the dry etching apparatus of FIG. 25 is not intended to be limited to this.

 [0117] In the apparatus of FIG. 25, there is a dielectric window 62 above the chamber 61, and above the dielectric window 62,

 A one-turn antenna 63 is placed. The plasma generator shown in FIG. 25 is a so-called TCP (Transfer Coupled Plasma) in which the dielectric window 62 is a flat plate type. A high frequency power 64 of 13.56 MHz is introduced into the antenna 63 through a matching unit 65.

[0118] There is a process gas inlet 66 in the chamber 61, where a halogen gas such as C1, C1, etc. An etching gas is introduced. A substrate (material to be etched) 67 is placed on a susceptor 68. The susceptor 68 is an electrostatic chuck 69, and can be chucked by an electrostatic force due to the electric charge flowing into the substrate from the plasma. A member called a quartz glass collar 70 is placed around the susceptor 68.

 [0119] The halogen gas introduced into the chamber 61 is turned into plasma in an excited state by a dielectric magnetic field generated by applying high frequency power to the antenna 63 on the dielectric window 62.

 Furthermore, high frequency power 72 of 400 kHz is introduced into the susceptor 68 via the matching unit 71, and a high frequency bias is applied to the substrate (material to be etched) 67 placed on the susceptor 68. By this high frequency bias, ions in the plasma are attracted to the substrate with anisotropy, and anisotropic etching such as vertical etching becomes possible.

 [0121] The etching gas (process gas) used in the dry etching step typically includes a mixed gas of a halogen gas, a boride of a halogen gas, and a rare gas. The composition of the mixed gas is not limited to this, and for example, hydrogen bromide or carbon tetrafluoride may be further added.

 [0122] The flow ratio of the mixed gas is not particularly limited. For example, a mixed gas of Ar, C1, and BC1 is used.

 twenty three

 When using, generally, Ar: Cl: BC1 = 300sccm: 120sccm: around 60sccm

 twenty three

 It is preferable to adjust.

[0123] In the present invention, dry etching can be used in all steps of etching an A1 alloy thin film or Si semiconductor layer and forming contact holes, thereby improving productivity. However, the present invention is not intended to be limited to this. For example, wet etching is performed until the bottom of the contact hole reaches the A1 alloy film, and switching to dry etching is performed at the final stage of the contact hole formation process. By performing wet etching most of the contact hole formation process, it is possible to process multiple TFT substrates at once. However, productivity can be improved if dry etching is performed in all steps of contact hole formation.

 Example

[0124] Hereinafter, the present invention will be described in more detail with reference to examples. However, before the present invention is not limited by the following examples, the present invention is suitably applied within a range that can be adapted to the purpose described below. It is also possible to carry out with modifications, and all of them depend on the technical scope of the present invention.

 [0125] For the A1 alloy films having various alloy compositions shown in Table 1, Table 2, and Table 3, as shown below, the electrical resistivity of the A1 alloy film itself and the A1 alloy film are transparent pixel electrodes or non- The contact resistivity when directly connected to the crystalline Si layer or the polycrystalline Si layer was measured, and the heat resistance when the A1 alloy film was heated was examined.

 [0126] The various properties described above of the A1 alloy film were performed under the following conditions.

 (1) Transparent pixel electrode configuration: Indium tin oxide (ITO) with 10% by weight tin oxide added to indium oxide, or Indium zinc oxide (IZO) with 10% by weight zinc oxide added to indium oxide

 (2) A1 alloy film formation conditions:

 Atmosphere gas = argon, pressure = 3mTorr, thickness = 200nm

 (3) Content of each alloy element in A1 alloy film:

 The content of each alloy element in the various A1 alloys used in the experiments was determined by ICP emission analysis (inductively coupled plasma emission analysis).

[0127] (Experiment 1)

 As A1 alloy films, five types of samples of A1— 0 · 3 atomic% α— 0 · 35Gd atomic% (a = Ni, Ge, Ag, Zn, Cu) were prepared, and each contact resistance with ITO film The rate was measured. The contact resistance is measured by preparing the Kelvin pattern (contact hole size: 10 μm square) shown in Fig. 20 and measuring it at 4 terminals (by applying current to ITO-A1 alloy or IZO-A1 alloy and using another terminal). A method of measuring the voltage drop between ITO-A1 alloys or between IZO-A1 alloys). Specifically, the current I flows between I and I in Fig. 20, and the voltage V between V and V is monitored.

 1 2 1 2

 Thus, the contact resistance R of the connection C was obtained as [R = (V−V) / I].

FIG. 21 shows the results when ITO is used as the transparent pixel electrode. When IZO was used instead of ITO, the same trend as in Fig. 21 was observed. From Fig. 21, it can be seen that the contact resistivity is lowest when a = Ge. In addition, it can be seen that the Ge-added A1 alloy film has the best stability with the smallest variation in contact resistance (in Fig. 21, the contact resistivity is indicated by ♦, and the upper and lower sides of the ♦ are shown below. Each bar-shaped mark on the side One bar).

 [0129] (Experiment 2)

As A1 alloy film, A1- 0. l atomic% G _e - Prepare / 3 atomic% X 10 different samples (X = Nd, Gd, L a, Dy, Y, β see Table 1), A1 The heat resistance of the alloy film was measured. The measurement method is explained. Only the A1 alloy film was formed on the glass substrate under the conditions described in (2) above. Next, a 10-width line and space pattern was formed, and the sample surface was observed with an optical microscope while gradually heating at a rate of 50 ° CZ in an inert gas atmosphere, confirming the occurrence of hillocks. Temperature (hereinafter referred to as “hillock generation temperature”) was recorded. Table 1 shows the average hillock temperature measured five times.

 [0130] [Table 1]

[0131] From Table 1, in the case of any additive element (X), in the composition range of about 0.5 atomic%, about 430 ° C to 460 ° C, which shows almost the same hillock generation temperature, 0. 1 atom ⁰ /. In the low additive composition region, there is a difference in the hillock generation temperature, and it is clear that the effect of improving heat resistance is higher in the order of Gd and La.

 [0132] (Experiment 3)

A1 alloy films with various compositions shown in Table 2 were heat treated at 220 ° C, and the electrical resistance of the A1 alloy film was The drag rate was measured. FIG. 22 shows the correlation between the heat treatment time and the electrical resistivity of the A1 alloy film. As is clear from FIG. 22, the electric resistivity of the A1 alloy film decreases smoothly when the heat treatment time is increased. When the amount of Gd La added is large, the electric resistivity does not decrease much. In order to obtain a low electrical resistivity of about 4. δ μΩ · cm under a heating time of about 8 minutes, the amount of Gd La added alone or in total is 0.45 atomic% or less. It is considered to be 0.4 atomic% or less, more preferably 0.3 atomic% or less.

[Table 2]

[0134] (Experimental example 4)

 The Al—Ge—Gd film and A1—Ge—La film having various compositions shown in Table 3 were heat-treated at 220 ° C., and the hillock density and electrical resistivity of the A1 alloy film were measured. The hillock density was measured by counting the number of hillocks formed on the surface of the A1 alloy film after heating the sample at 220 ° C for 30 minutes instead of examining the hillock generation temperature as in Experimental Example 2. This is what is done. That is, only the A1 alloy film was formed on the glass substrate under the conditions described in (2) above. Next, a line and space pattern with a width of 10 m was formed, vacuum heat treatment was performed at 220 ° C for 30 minutes, the surface of the wiring was observed with SEM, and the number of hillocks with a diameter of 0; m or more was counted. . The results are shown in Table 3.

 [0135] On the other hand, the electrical resistivity was measured by the 4-terminal method using a Kelvin pattern after heating the sample at 220 ° C for 10 minutes. The results are also shown in Table 3.

[0136] [Table 3]

[0137] Table 3 Force, et al., A1—Ge—Gd and A1—Ge—La materials! /, If the content of Gd and La is 0.1 atomic% or more, hillock You can see that the density is kept small! Addition of Ni to the A1 alloy film has the effect of improving the heat resistance S and increases the electrical resistivity, so the amount of Ni added is limited. For comparison, the hillock density and electrical resistivity of the AL-Ge material (binary system) are shown. However, when neither Gd nor La is contained, the heat resistance is remarkably low. In addition, in the A1-Ge-Gd-Zn-based material, no further heat resistance improvement effect due to the addition of Zn was observed.

 [0138] (Experimental example 5)

The contact resistivity and Si direct contact characteristics of various A1-Ge-X films and ITO films shown in Table 4 were measured. The method shown in Experimental Example 1 was used to measure the contact resistivity with the ITO film. For any of the samples shown in Table ^{4, 2. 00 X 10- 4 Ω} - cm 2 or less of a low contact resistivity is obtained. When Ni and Cu of sample numbers 10, 11, 14, and 15 are added in combination with Ge, the effect of reducing the contact resistivity is particularly great.

[0139] [Table 4]

[OHO] On the other hand, the Si direct contact characteristics (ON current and OFF current of evaluation TEG described later) are Each was measured as follows. First, sputtering method and plasma C on Si wafer

Using the VD method, an evaluation TEG having the TFT shown in FIG. 23 was produced. TFT gate length

L is 10 μm and gate width W is 10 μm.

[0141] The prepared TEG for evaluation was subjected to heat treatment at 300 ° C for 30 minutes. In the actual TFT manufacturing process, a heating process is started after the formation of the A1 alloy film, and when the interdiffusion and interfacial reaction between the Si layer and the A1 alloy film proceed, the on-current decreases and / or the off-current increases. It is because it will produce.

[0142] After the heat treatment, the drain current-gate voltage switching characteristics of the TFT were measured, and the on-current and off-current were identified. The results are shown in FIG. The drain voltage during measurement is 10

V. The off current is the current value when the gate voltage is -3V, and the on current is 20

It was defined as the voltage at V.

With respect to [0143] on-current, in any of the A1 alloy film shown in Table 4, 2. and a 0 X 10- ⁶ [A] or higher, the better.

[0144] On the other hand, with regard to the off-state current, in the A1—Ge2 system A1 alloy film of test numbers 1 to 3 and the A1 alloy film containing Cu of sample number 14 and sample number 15, 1.0 X 10 — ^U [A] is exceeded, and it can be seen that the off-state current increases remarkably.

 Note that the same applies to the case where amorphous silicon or polycrystalline silicon is used as the TFT semiconductor layer.

 [0146] (Experiment 6)

 In this Experimental Example and Experimental Example 7 described later, it was investigated that the A1 alloy film of the present invention has excellent dry etching properties.

First, in Experimental Example 6, it was examined that the A1 alloy film of the present invention has a high etching rate ratio comparable to that of pure A1. Here, as an example of the present invention, A1-0. 2 atomic% 0 ₆ _0.10 atomic% 0 (1 was used. For comparison, in addition to pure A1, A1 − 2. 0 atomic% ^ was used.

 [0148] Specifically, a non-alkali glass substrate having a diameter of 6 inches and a thickness of 0.5 mm (manufactured by Cowing Co., Ltd.)

# 1737 glass), a silicon oxide (SiOx) film with a thickness of 200 nm is deposited at a substrate temperature of about 250 ° C, and then the pure A1 film or A1 alloy film is formed under the conditions described in (2) above. Filmed . Next, a positive photoresist (nopolac resin; TSMR8900 manufactured by Tokyo Ohka Kogyo Co., Ltd., thickness 1 · O ^ m) is formed into a stripe with a line width of 2.0 m by g-line photolithography. Formed.

 Next, dry etching was performed under the following etching conditions using the dry etching apparatus shown in FIG.

[0150] (Etching condition)

 Ar / Cl / BC1: 300sccm / 120sccm / 60sccm

 twenty three

 Power applied to antenna (source RF): 500W

 Substrate bias: 60W

 Process pressure (gas pressure): 14mTorr

 Substrate temperature: Susceptor temperature (20 ° C)

[0151] Etching was performed by changing the etching time in the range where the etching depth was 100 to 300 nm, and samples with different etching depths were produced. Next, after removing the resist in the same way as the etching of the silicon nitride (SiNx) film, using a stylus type film thickness meter ("Dektak II" manufactured by Vecco), pure A or A1 alloy film Measured the etching thickness of

Yes

 [0152] These results are shown in FIG.

 As shown in FIG. 26, it was confirmed that the etching rate ratio of the A Ge—Gd film of the present invention was almost the same as that of pure A1, which is higher than that of the conventional A1_Ni film.

 [0154] (Experimental example 7)

 In this experimental example, the effects of various elements (Ge, Gd and / or La, Ni) of the A1 alloy film shown in Table 5 on dry etching properties were examined. The dry etching conditions are the same as in Example 6 described above. The dry etching property was evaluated as follows.

 [0155] (etching rate ratio)

Etching was performed in the same manner as in Example 6, and the thickness (etching thickness) of the pure A1 film and each A1 alloy film after the etching was measured. These results are statistically processed by the least squares method to calculate the etching rate of pure A1 film (N2) and the etching rate of A1 alloy film (N1), respectively. " In this example, an etching rate ratio of 0.3 or higher was determined to be acceptable (◯).

[0156] (Presence or absence of residue after dry etching)

 SEM observation of the surface of the glass substrate after the resist was peeled off for various A1 alloy films etched for 1.2 times the etching time considered to be necessary up to the etching depth equivalent to the film thickness ( Magnification 3000 times), and the presence or absence of a residue with a diameter (equivalent circle diameter) of 0.5 · 5 ^ 111 or more was examined. The measurement field of view was 5 fields of view, and when the above substrate surface was measured at several points, the above residue was not observed at any measurement point (no residue) and passed (O).

 In this example, an etching rate ratio that passed and no residue after dry etching was determined to be “excellent in dry etching”.

[0158] These results are summarized in Table 5. Table 5 provides a column for comprehensive evaluation, where “O” is marked for those satisfying both of the above characteristics, and “X” is marked for those with V or one of the characteristics rejected (X).

 [0159] Fig. 27 shows the relationship between the Ge amount in the A1 alloy film and the etching rate ratio, Fig. 28 shows the relationship between the Gd amount and La amount in the A1 alloy film, and the etching rate ratio, and Fig. 29 shows the A1 alloy film. The relationship between the amount of Ni in the steel and the etching rate ratio is shown below.

[0160] [Table 5]

 [0161] As shown in Table 5, No. satisfying the requirements of the present invention! ~ 4 Al-Ge-Gd film, No.6 ~ 9 A Ge-La film, No.11 Al-Ge-Gd-Ni film, and No.13 8 1-06-1 ^-^ film Both are excellent in dry etching property.

[0162] In contrast, No. 5 A Ge-Gd film with high Gd content, No. 10 Al- Ge- L with high La content In all the films, residues after etching were observed, and the etching rate ratio also decreased. In addition, the No. 12 A Ge-Gd-Ni film and the No. 14 A Ge-La-Ni film are both examples of a large amount of Ni and a large amount of Ge and Ni. Although no residue was observed after etching, the etching rate ratio decreased.

 [0163] Based on the above experimental results, the influence of each element on the etching rate ratio is as follows.

 [0164] First, the influence of Ge on the Al-Ge-Gd film and the Al-Ge-La film will be considered.

 [0165] As shown in FIG. 27, when the Ge amount is within the range defined by the present invention (0.05-0.0.5 atomic%), the etching rate ratio is approximately 0.6, which is substantially constant. In addition, as shown in Table 5, within the above range, no residue after etching is observed. Therefore, it was confirmed that the A1 alloy film of the present invention showed good dry etching properties regardless of the Ge content.

 [0166] Next, the effect of Gd / La on Al-Ge-Gd and Al-Ge-La films will be discussed.

As shown in FIG. 28, it can be seen that the etching rate ratio increases as the content of Gd or La decreases. In order to satisfy the etching rate ratio of 0.3 or more specified in the present invention, the upper limit of the total amount of Gd and / or La needs to be 0.35 atomic%, and the upper limit is 0.4 atomic%. As a result, desired characteristics could not be obtained.

 [0168] Next, the effect of Ni on the Al-Ge-Gd film and the Al-Ge-La film will be considered.

 [0169] Ni also showed the same tendency as Gd / La described above, and as shown in FIG. 29, the etching rate ratio increased as the Ni content decreased. In order to satisfy the etching rate ratio of 0.3 or more specified in the present invention, the upper limit of the Ni amount needs to be 0.3 atomic%, and when the upper limit is 0.4 atomic%, desired characteristics are obtained. Was not obtained.

 [0170] Although the invention has been described in detail with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. This application consists of a Japanese patent application filed on November 30, 2006 (Japanese Patent Application 2006-324494) and a Japanese patent application filed on June 26, 2007 (Japanese Patent Application 2007-168298). Which is incorporated by reference in its entirety.

Also, all references cited herein are incorporated as a whole. Industrial applicability

 According to the present invention, the A1 alloy film can be directly connected to the transparent pixel electrode made of a conductive oxide film without interposing a barrier metal layer, and a relatively low heat treatment temperature of about 220 ° C. A1 alloy film for display devices that can secure a sufficiently low electrical resistivity and excellent heat resistance even when applying the above, and a display device using the same can be provided.

Claims

The scope of the claims  [1] An A1 alloy film for a display device that is directly connected to a conductive oxide film on a substrate, the A1 alloy film containing 0.05 to 0.5 atomic percent of Ge, Gd and / or A1 alloy film for display devices containing 0.05 to 0.45 atomic% of La in total.  [2] An A1 alloy film for a display device that is directly connected to an amorphous Si layer or a polycrystalline Si layer on a substrate, and the A1 alloy film contains Ge of 0.05 to 0.5 atomic%. A1 alloy film for display devices that contains Gd and / or La in a total amount of 0.05 to 0.45 atomic%.  [3] The A1 alloy film for a display device according to claim 1 or 2, wherein the dry etching characteristics are enhanced by containing 0.05 · 35.35% by atom of Gd and / or La in total.  [4] The indication according to claim 1 or claim 2, further comprising 0.05 to 0.35 atomic% of Ni and a total content of Ge and Ni of 0.45 atomic% or less. A1 alloy film for devices.  [5] A display device comprising the A1 alloy film for display device according to any one of claims 1 to 4 and a thin film transistor.  [6] A display device in which the A1 alloy film for a display device according to any one of claims 1 to 4 is used for a gate electrode and a scanning line of a thin film transistor and is directly connected to a conductive oxide film.  [7] The A1 alloy film for a display device according to any one of claims 1 to 4 is used for a source electrode and / or a drain electrode and a signal line of a thin film transistor, and a conductive oxide film and / or amorphous Si Display device connected directly to a layer or polycrystalline Si layer. 8. The source electrode and / or drain electrode and signal line of the thin film transistor are made of the same material as the gate electrode and scanning line of the thin film transistor. The display device according to any one of ~ 7. [9] The conductive oxide film according to any one of claims 5 to 7, wherein the conductive oxide film is formed of a composite oxide containing at least one selected from the group consisting of indium oxide, zinc oxide, tin oxide, and titanium oxide. The indicated display device. [10] The electrical resistivity of the A1 alloy film for display devices is 4. δ μ Q 'cm or less. V, display device as described in somewhere. [11] Sputtering target for forming an Al alloy film for display devices, containing 0.05 to 0.5 atom% of Ge and 0.05 to 0.45 atom in total of Gd and / or La Including%  [12] The sputtering target according to [11], further comprising 0.05 to 0.5 to 35 atomic% of Ni and a total content of Ge and Ni of not more than 0.45 atomic%.