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WO2007125687A1 - Appareil d'affichage et son procede de commande - Google Patents

Appareil d'affichage et son procede de commande Download PDF

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Publication number
WO2007125687A1
WO2007125687A1 PCT/JP2007/054854 JP2007054854W WO2007125687A1 WO 2007125687 A1 WO2007125687 A1 WO 2007125687A1 JP 2007054854 W JP2007054854 W JP 2007054854W WO 2007125687 A1 WO2007125687 A1 WO 2007125687A1
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WO
WIPO (PCT)
Prior art keywords
potential
period
potential difference
pixel electrode
voltage
Prior art date
Application number
PCT/JP2007/054854
Other languages
English (en)
Japanese (ja)
Inventor
Takaji Numao
Original Assignee
Sharp Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Publication of WO2007125687A1 publication Critical patent/WO2007125687A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0847—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the present invention relates to a driving method for improving response speed of a liquid crystal display or the like, and a display device therefor.
  • liquid crystal TVs have become inexpensive and have become popular in ordinary homes.
  • the opportunity to display moving images on PCs is increasing.
  • the start of digital terrestrial broadcasting is expected to increase the opportunity to display moving images on mobile devices such as mobile phones. For this reason, technological development to improve the quality of moving images on liquid crystal displays has been actively conducted, and many results have been achieved.
  • FIG. 14 to FIG. 16 show one of the moving image quality improvement techniques of such a liquid crystal TV disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2004-240410).
  • FIG. 14 shows the overall configuration of the above-described liquid crystal TV system.
  • the enhancement conversion unit 32 writes the data to be written based on the input image signal. And the write data is supplied to the liquid crystal controller 34. Further, the input image signal subjected to the double speed conversion by the frame frequency conversion unit 37 is stored in the frame memory 31 and given to the enhancement conversion unit 32 with a delay of one frame time.
  • Write data is supplied from the liquid crystal controller 34 to the liquid crystal display panel 30 via the source driver 36.
  • the scanning lines of the liquid crystal display panel 30 are driven by the gate driver 35 based on the control by the liquid crystal controller 34.
  • the enhancement conversion unit 32 uses the input image signal directly input from the frame frequency conversion unit 37 and the image signal input via the frame memory 31 based on the gradation transition of V ⁇ and both image signals. Then write data is created. As shown in FIG. 15, the enhancement conversion unit 32 outputs write data twice in one frame period. Of these, the write data output during the first image display period is based on the table shown in FIG. Created. The write data output during the second image display period is the input image signal itself that has been double-speed converted by the frame frequency converter 37.
  • the vertical axis represents the previous image data (signal from the frame memory 31), and the horizontal axis represents the current image data (input image signal).
  • the write data output from the emphasis conversion unit 32 is shown at the position where each previous image data and each current image data correspond.
  • FIG. 16 shows a case where the input image signal changes from 0 to 64 gradations in the first frame and changes from 64 to 128 gradations in the next frame using this overshoot drive. Yes.
  • the pixel display state changes from 0 to 64 gradations
  • the emphasis data 150 in which the previous image data 64 and the current image data 128 intersect is selected in the above table in the first image display period. And written to the pixel. Thereafter, the current image data 128 is written as it is in the second image display period.
  • the luminance of the pixel changes abruptly during the first image display period as shown by the solid and broken lines in FIG. 16, and the target gradation is generally displayed during the second image display period. .
  • FIG. 17 shows a configuration of the display panel disclosed in Patent Document 2.
  • the TFT 113 and the pixel are arranged near the intersection of the gate wiring 111 and the source wiring 112.
  • the electrode 114 and the auxiliary capacitor Cs are arranged.
  • a gate wiring 111 is connected to the gate terminal of each TFT 113
  • a source wiring 112 is connected to the source terminal
  • a pixel electrode 114 is connected to the drain terminal.
  • One electrode of the auxiliary capacitance Cs is connected to the pixel electrode 114
  • the auxiliary capacitance line 115 is connected to the other electrode of the auxiliary capacitance Cs.
  • the liquid crystal capacitance C is formed between the pixel electrode 114 and the counter electrode 121, so that the display element is configured.
  • a source signal potential is applied to the source wiring 112
  • an auxiliary capacitance line potential is applied to the storage capacitor line 115
  • a counter common electrode potential is applied to the counter electrode 121.
  • the auxiliary capacitance line potential is an alternating rectangular wave that changes in phase opposite to the source signal potential, centered on OV.
  • the potential shown in FIG. 18B is applied to each of the gate wirings 111 in the Nth to N + 3th rows.
  • the liquid crystal C constituting each pixel Aij in the Nth row to the N + 3th row has the structure shown in FIG.
  • the voltage shown is applied.
  • the effective voltage applied to the LC changes, which improves the response of the liquid crystal molecules.
  • Patent Document 3 Japanese Patent Laid-Open No. 2002-202762 discloses a display device that achieves low power consumption.
  • a different selector 134 is arranged for each auxiliary capacitance wiring Yci, and these selectors 134 select either the voltage Vst (+) or the voltage Vst (-)! /
  • the voltage of the auxiliary capacitance line Yci changes. Specifically, the voltage of the auxiliary capacitance line Yci is changed between the state in which the TFT 113 of the pixel is turned on by the voltage Vdd of the gate line Ysi and the state in which the TFT 113 is not turned on thereafter.
  • the pixel electrode 114 is transferred.
  • the amplitude of the applied voltage can be increased.
  • 180 DZA conversion circuits when the TFT113 is conducting due to the voltage Vdd of the gate wiring Ysi, 180 DZA conversion circuits also generate voltages ⁇ 3 (+) to ⁇ 31 ⁇ (+).
  • the voltage of the auxiliary capacitance line Yci is changed from Vst (one) to Vst (+).
  • the voltage of the pixel electrode 114 is changed from Vsw (+) + ⁇ Vwt (+) to Vsk (+) + ⁇ Vbk (+)!
  • Patent Document 1 JP 2004-240410 (released August 26, 2004)
  • Patent Document 2 JP 2003-279929 (published October 2, 2003)
  • Patent Document 3 JP 2002-202762 (published July 19, 2002)
  • the liquid crystal response speed is improved by the driving method disclosed in Patent Document 2.
  • a 2H cycle voltage is applied to the auxiliary capacitance wiring 115, the power consumption increases.
  • the present invention has been made to solve the above-described problems, and an object thereof is to increase the response speed of a display element such as a liquid crystal while suppressing an increase in cost and power consumption.
  • a display device includes a plurality of scanning lines, a plurality of data lines, and pixels arranged in the vicinity of the intersections, and each pixel is a pixel electrode. And a display device having a counter electrode opposite to the pixel electrode, the display device being disposed between the pixel electrode and the data line and being electrically connected to the scan line by a voltage applied to the scan line.
  • the first active element that is in a non-conductive state and one scan line to be scanned are selected. In the selected period, the first active element is turned on by applying a selection voltage to the scanning line, and the pixel line and the data line force are applied based on the data line force and a predetermined potential applied to the pixel electrode.
  • Control means for applying a display potential difference to the counter electrode, setting the first active element in a non-conductive state during the potential difference changing period, and applying a change potential difference different from the display potential difference between the pixel electrode and the counter electrode
  • the length of the potential difference changing period is set shorter than the length of the non-selection period during which the non-conducting state is maintained.
  • a display device driving method includes a plurality of scanning lines, a plurality of data lines, and pixels arranged in the vicinity of the intersections. Is disposed between the pixel electrode and the data line, and is turned on or off by a voltage applied to the scan line.
  • Applying the selection voltage to the scanning line causes the first active element to be in a conductive state, and in the subsequent non-selection period, based on a predetermined potential applied from the data line to the pixel electrode, versus A display potential difference is provided between the pixel electrode and the first active element in a non-conducting state during a potential difference changing period, and the potential of the potential wiring is changed to change the display potential between the pixel electrode and the counter electrode.
  • a potential difference change period that provides a change potential difference different from the potential difference is provided, and the length of the potential difference change period is shorter than the length of the non-selection period.
  • the length of the potential difference changing period is preferably less than 50% of the length of the non-selection period or the length of one frame period.
  • a change potential difference larger or smaller than the display potential difference between the pixel electrode and the counter electrode is temporarily changed to a gradation level that easily shifts to the target gradation level in the potential difference changing period that occupies a part of the non-selection period.
  • a liquid is applied by applying a voltage in advance based on the data of the previous frame at the end of the display period of the previous frame, which is before the selection period. Power the crystal molecules.
  • the second method powers the liquid crystal molecule by applying a voltage in advance based on the data of the current frame at the beginning of the display period of the current frame after the selection period. In this way, the liquid crystal molecules are made to move easily in advance before the display period of the current frame.
  • the first active element is turned on by the control means, so that the data voltage is applied to the pixel electrode via the data line.
  • the difference between the potential of the pixel electrode and the potential of the counter electrode is given to the display element as a display potential difference.
  • the potential difference between the pixel electrode and the counter electrode is returned from the changed potential difference to the display potential difference, so that the display element has the above-described shifted gradation level force data. Transitions to the target gradation level according to the voltage.
  • the potential difference between the pixel electrode and the counter electrode is returned from the change potential difference to the display potential difference during the non-selection period.
  • the display element shifts the displaced gradation level force to the target gradation level corresponding to the data voltage. Therefore, the display element can be shifted to the target gradation level faster than the conventional driving method.
  • the potential change of each pixel electrode is provided with the second potential difference change period once or a plurality of times in one frame period. It's a little bit. Therefore, compared to the case where the voltage applied to the liquid crystal capacitor is changed every several H, the number of potential changes that increase the potential difference between the pixel electrode and the counter electrode is reduced, so that the increase in power consumption can be suppressed. it can.
  • control means sets the first active element in a non-conducting state in an intermediate period between the potential difference changing period and the subsequent selection period, and the pixel electrode, the counter electrode, It is preferable to provide an adjustment potential difference different from the display potential difference and the change potential difference during the period.
  • the response speed is slow when changing from the low voltage side to the high voltage side.
  • the selection period, the potential difference changing period, and the intermediate period are referred to as a first period, a second period, and a third period, respectively.
  • the change potential difference and adjustment potential difference are V2 and V3, respectively.
  • V2 and V3 By setting V2 and V3 in this way, first, a high voltage is applied to the display element to make the response quicker, and then a desired voltage is applied to the display element. Faster response speed can be obtained and the display can be stabilized.
  • V2 and V3 satisfy the relationship of
  • the response speed is slow when changing from the high voltage side to the low voltage side.
  • the following two cases are considered. It is done.
  • V2 and V3 satisfy the relationship of I V2 I and I V3 I, and the voltage applied to the display element in the second period is the voltage applied to the display element in the third period. This is the case for lowering.
  • V2 and V3 By setting V2 and V3 in this way, first, a low voltage is applied to the display element to make the response quicker, and then the desired voltage is applied to the display element. Faster response speed can be obtained and the display can be stabilized.
  • V2 and V3 satisfy the relationship of I V2 I> I V3 I, and the voltage applied to the display element in the third period is the voltage applied to the display element in the second period. This is the case when making it smaller.
  • the ratio of the intermediate period (third period) to one frame period is preferably less than 50%.
  • the ratio of the potential difference changing period (second period) force to the S1 frame period is preferably less than 50%.
  • the potential changing period may be arranged again after the intermediate period. This is because if the frame frequency is less than 60 Hz and the potential difference change period is only once per frame period, the flicker force of less than 60 Hz will be conspicuous. It is preferable to arrange a plurality of potential change periods in the non-selection period because such flickering force can be avoided.
  • the first configuration includes potential holding means (for example, a capacitor) that is provided in each pixel and holds the potential applied to the potential wiring, and the control means sets the potential applied to the potential wiring.
  • a potential control means is provided for changing the change potential difference or the adjustment potential difference so as to be different from the display potential difference.
  • a second configuration includes a potential holding unit that is provided in each of the pixels and holds a potential applied to a potential wiring, and is arranged between the pixel electrode and the potential holding unit.
  • Two active elements, and the control means sets the first active element in a non-conducting state and the second active element in a conducting state, whereby the change potential difference or the adjustment potential difference becomes the display potential difference. Change to be different.
  • the capacitance between the pixel electrode and the counter electrode is Clc, and the potential holding means is used.
  • the capacity of the capacitor used is Cs, and the potential of the counter electrode is Vcom.
  • the control unit applies the potential VL to the potential wiring Ei in the first period (selection period), thereby applying the potential Va to the pixel electrode.
  • Vb Va + Cs (VS -VL) / (Clc + Cs)...
  • V2 Vb-Vcom
  • Vc Va + Cs (VT-VL) / (Clc + Cs)
  • V3 Vc-Vcom
  • the potential difference V2 or V3 can be changed to be different from the potential difference VI.
  • the capacitance between the pixel electrode and the counter electrode is Clc
  • the capacitance of the capacitor employed as the potential holding means is Cs
  • the potential of the counter electrode is Vcom.
  • the second active element is turned off in the first period (selection period), and the potential Va is applied to the pixel electrode.
  • the potential difference of the capacitor is defined as Vz-VL (the potential force Vz of the terminal on the pixel electrode side of the capacitor and the potential of the terminal on the opposite side is VL), during the second period or the third period. If the second active element is made conductive, the potential Vb of the pixel electrode is
  • Vb (ClcVa + CsVz) / (Clc + Cs) (5)
  • V2 Vb-Vcom
  • V2 is reduced.
  • V3 can be changed to be different from the potential difference VI.
  • the first active element in the third period, the first active element is turned off, the second active element is turned on, and electric charges are supplied from the drive circuit to the data wiring. Thereafter, in the first period, the second active element is turned off and the first active element is turned on.
  • the potential Vb of the pixel electrode in the first period is given to the data line in the third period, assuming that the floating capacity of the data line is Cd, and that the floating capacity exists between the counter electrode. If the voltage is Va and the pixel electrode potential is Vz.
  • Vb (Cd'Va + (Clc + Cs) Vz) Z (Cd + Clc + Cs "(7)
  • the same result can be obtained even when the second active element is arranged between the data line and the drive circuit.
  • the display device according to the present invention is connected to the display element in the second period or the third period after the first period, which is a selection period without using an element externally attached to a panel such as a frame memory.
  • the response speed can be improved.
  • the cost of the display device can be eliminated.
  • the potential applied to the potential wiring is varied. Therefore, it is preferable to set the potential fluctuation force so that it only takes a few times per frame period, since the increase in power consumption can be suppressed.
  • the conduction state of the second active element is controlled in the second configuration.
  • the conduction state of the second active element (for example, a MOS transistor) is determined by, for example, the voltage between the source and the gate terminal. Therefore, the gate terminal voltage may be changed several times during one frame period. For this reason, an increase in power consumption can be suppressed. Therefore, it is preferable.
  • the present invention it is possible to achieve the object of the present invention and to improve the response speed of the display element while suppressing the increase in cost and power consumption of the display device.
  • FIG. 1 is a block diagram showing a configuration of a display device according to a first embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing a circuit configuration of a pixel in the display device.
  • FIG. 3 is a timing chart showing the operation of the display device.
  • FIG. 4 is a diagram showing a change in response speed in the case where the driving method of the first embodiment of the display element provided in the pixel before and after the gradation transition is applied!
  • FIG. 5 is a diagram showing a change in response speed when the driving method of the first embodiment of the display element provided in the pixel before and after the gradation transition is applied!
  • FIG. 6 is a timing chart showing the operation of the display device according to the second embodiment of the present invention.
  • FIG. 7 is a block diagram showing a configuration of a display device according to a third embodiment of the present invention.
  • FIG. 8 is a timing chart showing the operation of the display device of FIG.
  • FIG. 9 is a block diagram showing a configuration of a display device according to a fourth embodiment of the present invention.
  • FIG. 10 is a circuit diagram showing a circuit configuration of a pixel in the display device of FIG.
  • FIG. 11 is a timing chart showing the operation of the display device of FIG.
  • FIG. 12 is a circuit diagram showing another circuit configuration of the pixel in the display device of FIG.
  • FIG. 13 is a cross-sectional view showing the structure of the pixel in FIG.
  • FIG. 14 is a block diagram showing a configuration of a conventional display device.
  • FIG. 15 is a diagram showing gradation data stored in a table used for overshoot driving in the display device of FIG.
  • 16 is a diagram showing a change in gradation within one frame in the display device of FIG.
  • FIG. 17 is a circuit diagram showing a configuration of a display panel of another conventional display device.
  • FIG. 18 (a) is a waveform diagram showing a change in potential applied to each part of the display device of FIG.
  • FIG. 18 (b) is a waveform diagram showing a change in potential applied to the gate wiring of the display device of FIG.
  • FIG. 18 (c) is a waveform diagram showing a change in voltage applied to the liquid crystal in each pixel of the display device of FIG.
  • FIG. 19 is a circuit diagram showing a configuration of a display panel of still another conventional display device.
  • FIG. 20 (a) is a waveform diagram showing a change in voltage applied to the pixel electrode of the display device of FIG.
  • FIG. 20 (b) is a waveform diagram showing a change in potential of the storage capacitor line of the display device of FIG.
  • FIG. 22 is a timing chart showing still another operation of the display device according to the first embodiment of the present invention.
  • FIG. 23 is a graph showing changes in liquid crystal transmission characteristics according to the timing chart of FIG.
  • FIG. 24 is a diagram comparing response times of drive waveforms of the display device according to the related art and the first embodiment.
  • FIG. 26 is a timing chart showing another operation for setting the potential change of the potential wiring of the display device according to the first embodiment of the present invention larger.
  • FIG. 27 is a timing chart showing still another operation for setting a larger potential change in the potential wiring of the display device according to the first embodiment of the present invention.
  • ⁇ 28] is a timing chart showing another operation of the display device according to the second embodiment of the present invention.
  • FIG. 29 is a timing chart showing still another operation of the display device according to the second embodiment of the present invention.
  • FIG. 30 is a block diagram showing a configuration of a display device according to a fifth embodiment of the present invention.
  • FIG. 31 is a circuit diagram showing a circuit configuration of a pixel and an analog switch in the display device.
  • FIG. 1 shows a display device 1 used in the present embodiment.
  • the display device 1 includes a source driver circuit 2, a gate driver circuit 3, and a temperature.
  • a sensor 8, a display panel 9, and a potential wiring drive circuit 10 are provided.
  • the pixel Aij is arranged in the vicinity of the intersection of the gate wiring Gi and the source wiring 3 ⁇ 4.
  • the thin film transistor TFT (Thin Film Transistor) 16 which is the first active element, and the display element LC And a capacitor Cs as potential holding means.
  • the gate terminal of the TFT 16 is connected to the gate wiring Gi, the source terminal is connected to the source wiring layer, and the drain terminal is connected to the pixel electrode 17.
  • the pixel electrode 17 serves as one terminal of the display element and the capacitor, and the other terminal of the display element LC is connected to a common electrode COM (counter electrode) disposed facing the pixel electrode 17 to be connected to the capacitor.
  • the other terminal of Cs is connected to potential wiring Ei.
  • a liquid crystal display element is assumed as the display element LC.
  • other electro-optical elements for example, an electoric chromic element and an organic EL element
  • an electoric chromic element and an organic EL element also have the means of the present invention. Applicable.
  • the source driver circuit 2 includes an m-bit shift register 4, an m X 6-bit register 5, an m X 6-bit latch 6 and m 6-bit D / A conversion circuits (D / A in the figure). Have 7! /
  • a start pulse SP is input to the head of the m-bit shift register 4.
  • the start pulse SP is transferred in the shift register 4 at the timing of the clock elk and output to the register 5 as the timing pulse SSP.
  • the m X 6-bit register 5 holds the input 6-bit data Dx at the position of the corresponding source wiring Sj by the timing pulse SSP sent from the shift register 4.
  • the latch 6 fetches the held m ⁇ 6-bit data Dx at the timing of the latch pulse LP and outputs it to the DZA conversion circuit 7.
  • the DZA conversion circuit 7 applies a potential (analog data Daij) corresponding to the input 6-bit data Dx to the source wiring Sj. This data Daij is supplied from the source driver circuit 2 to the source wiring example at the timing shown in FIG.
  • the gate driver circuit 3 (control means) includes a shift register 11 and an output circuit 12 (consisting of a logic circuit and a buffer).
  • the gate driver circuit 3 includes a start pulse YI shown in FIG. 3 and a clock y shown in FIG. ck is input.
  • the input start pulse YI is transferred through the shift register 11 at the timing of the clock yck and output from each output stage.
  • the logic circuit of the output circuit 12 performs a logical product operation (AND) on the pulse output from each output stage of the shift register 11 and the control signal SL input from the external force.
  • the logical product pulse is output as a gate signal VGi (only VG1 to VG4 are shown in the figure) to each gate wiring Gi as shown in FIG. 3 through the buffer of the output circuit 12.
  • the H-level selection voltage GH is applied as the gate signal VG1 to the gate line G1 for a period of time 2t0 to 4t0.
  • the TFTs 16 in the pixels Alj (Al 1 to Alm) connected to the gate wiring G1 are turned on.
  • data Dalj is supplied from the source wiring line to the liquid crystal element LC via the TFT 16.
  • the potential wiring drive circuit 10 includes a shift register 13 and an analog switch circuit 14.
  • the selection register Z I and the clock yck shown in FIG. 3 are input to the shift register 13.
  • the input selection pulse ZI is transferred through the shift register 13 at the timing of the clock yck and output from each output stage.
  • the analog switch circuit 14 performs a logical operation with the control signal SE shown in FIG. 3 into which the noise output from each output stage of the shift register 13 and the external force are also input.
  • the potential VEi shown in FIG. 3 obtained from the calculation result (only VE1 to VE4 is shown in the figure) is applied to each potential wiring Ei.
  • analog switch circuit 14 outputs the potentials shown in Table 1 below so that the voltage applied to the display element LC becomes an alternating current.
  • each potential line Ei is applied to the potential VSa until the time 2 tO when the control signal SE is low.
  • the force potential wiring E1 to which the potential VSb is applied to each potential wiring Ei from time 2t0 is the selection period which is the first period (time 2t0 to 4t0), and therefore the potential VLb is applied.
  • VLb V Sb.
  • the second period time 6t0 to 12t0
  • the potential VTb is applied to the potential wiring Ei.
  • the third period (after time 12t0), which is an intermediate period thereafter, the potential VSb is applied to the potential wiring Ei.
  • the potential VAlj of the pixel electrode 17 of the pixel Alj becomes the potential Valj at the time 2t0 to 4tO, becomes the potential Vblj at the time 6t0 to 12t0, and becomes the potential Vclj after the time 12t0. It becomes.
  • the potential VAlj of the pixel electrode 17 is set to the force potential Vclj that should be returned to the potential Valj after the time 12t0 for the following reason.
  • a stray capacitance exists between the gate wiring Gi and the pixel electrode 17 shown in FIG. Therefore, the voltage of the pixel electrode 17 in the selection period in which the gate wiring Gi is at the potential GH and the same voltage in the non-selection period in which the gate wiring Gi is at the potential GL are used for the gate wiring Gi passing through the stray capacitance.
  • the voltage of the pixel electrode 17 slightly changes due to the influence of the voltage change. In order to correct this variation, the potential V A lj of the pixel electrode 17 is set to the potential Vc 1 j instead of the potential Valj.
  • FIG. 4 shows a change in the response speed of the display element LC before and after the gradation transition.
  • the response speed for transitioning to the same gradation becomes slower as the gradation before transition becomes closer to 0 (response time Tl).
  • the gradation level increases as the absolute value of the applied voltage increases.
  • This response time Ta + Tb can be made shorter than the response time T1 when the transition is made directly from the gray level before transition shown in FIG. Therefore, the response speed can be improved by adopting the first configuration described above.
  • the voltage applied to the display element LC of the pixel Alj in this second period is expressed by the following equation (2):
  • the capacitance of the display element LC is Clc
  • the capacitance of the capacitor Cs is Cs
  • the potential of the common electrode COM is the common potential Vcom.
  • the length of the second period is shorter than the length of the third period.
  • a gradation voltage that should originally transition to the third period is applied to the display element LC.
  • the ratio of the second period to one frame period is less than 50%.
  • the ratio of the second period to the non-selection period may be less than 50%.
  • the voltage is applied to the display element LC as follows. (1) Apply the selection voltage GH (ON voltage) to the gate wiring Gi, turn on the pixel TFT16, and apply the desired voltage to the display element LC. (2) The potential applied to the other electrode of the capacitor Cs is changed by the potential wiring Ei, and the voltage applied to the display element LC of the pixel Aij is changed (to a voltage at which the liquid crystal can move easily). Hold for several tens of H. (3) Then change the potential applied to the other electrode of capacitor Cs by potential wiring Ei The voltage applied to the display element LC of the pixel Aij is returned to a desired voltage.
  • FIG. 21 and FIG. 22 show this drive waveform. Specifically, FIG. 21 shows the gate signals VG1 and VG2, the potentials VE1 and VE2, the source signals VS1 and VS2 output to the source wirings SI and S2, respectively, and the counter electrode potential Vcom. Yes.
  • FIG. 22 shows the gate signal VG1, the potential VE1, the source signals VS1 and VS2, the potential VA11 of the pixel electrode 17 of the pixel All, and the potential VA12 of the pixel electrode 17 of the pixel A12! /
  • the voltages (potentials VA11, VA12) applied to the pixels All, A12 are part of one frame period (part of the non-selection period). ) (Absolute value) greater than the voltage output to the source wiring SI, S2 during the period of
  • the above period is referred to as a potential difference change period or an OS period.
  • FIG. 23 shows a comparison of the effect of this potential difference change period with a conventional drive waveform that does not have a potential difference change period.
  • “Cs—Typel 1/2 frame OS” in FIG. 23 shows the drive waveform when the potentials VA11 and VA12 shown in FIG. 22 are applied to the pixel electrode 17, and “REF” is the conventional drive.
  • the drive waveform by the method is shown.
  • 0 gradation voltage V0 is applied until time 0 [s]
  • 64 gradation voltage V64 is applied.
  • the amplitude of the potential VE1 in FIG. 22 is set as the maximum amplitude at which the black level does not float when a voltage having the same value as the counter electrode potential Vcom is applied to the source wiring S1.
  • the 64-gradation voltage V64 is determined by adjusting the voltage applied to the source wiring S1 so as to give the same average luminance as the conventional driving method with the amplitude of the potential VE1.
  • the response waveform (luminance) of the liquid crystal varies within one frame period as “measured data” shown in FIG. Therefore, to simplify the explanation, the average value of the response waveform is obtained and the response time is calculated.
  • FIG. 24 shows the response time force determined in this way, the case of applying the present embodiment, the case of a conventional drive waveform to which OS drive is not applied, and the case of the drive waveform by the drive method of Patent Document 3, respectively. It shows how it changes.
  • FIG. 24 shows the response time for the conventional drive waveform (drive waveform W1), the response time for the drive waveform (drive waveform W2) according to the drive method of Patent Document 3, and the present embodiment.
  • the response times for three types of drive waveforms W3 to W5 (“lZ2 frame OS”, “1Z4 frame OS”, “1 Z8 frame OS") are shown.
  • the potential difference change period occupies the 1Z2 frame period.
  • the potential difference change period occupies the 1Z4 frame period.
  • the potential difference change period occupies the 1Z8 frame period.
  • the response speed of drive waveform W2 is slightly improved compared to drive waveform W1.
  • the response speed of drive waveforms W3 to W4 is improved compared to drive waveform W2. Therefore, it is clear that the effect of improving the response speed is obtained by this embodiment.
  • a gradation (“0” gradation) having the smallest potential difference from the common electrode COM is given to the pixel A12 so that the potential change of the potential wiring Ei can be set larger.
  • the potential VA12 needs to reverse its polarity from 1 V (0) to + V (0) within one frame period. Therefore, the potential VE1 of the potential wiring E1 and the source signal VS2 (and the counter electrode voltage Vcom) of the source wiring S2 are adjusted.
  • the actual measurement data shown in FIG. 23 fluctuates within one frame period. This is because the voltage applied to the liquid crystal changes during the potential difference change period and other periods (selection period and intermediate period). For this reason, when the frame frequency is less than 60 Hz, this luminance variation is recognized by the user as a flickering force. In order to avoid this, as shown in FIG. 27, it is preferable that the potential difference VA12 is provided with a potential difference change period multiple times in one frame period.
  • the response speed can be improved by using the present embodiment. Also time If the first configuration described above is used, it is not necessary to use a frame memory, and the cost increase factor can be suppressed. In addition, if the potential of the potential wiring Ei is changed several times in one frame period, the response speed is improved, so that the power consumption can be reduced and the effect is clear.
  • the temperature sensor 8 shown in FIG. 1 is provided to change the length of the second period and the voltage VTb applied to the potential wiring Ei during that period depending on the temperature.
  • Valj Vblj
  • Vc lj ⁇ Vcom ⁇ Vb lj ⁇ Vcom Va lj ⁇ Vcom
  • FIG. 6 shows the timing of the data Daij supplied from the source driver circuit 3 to the source wiring Sj.
  • the gate driver circuit 3 receives the start pulse YI and the clock yck shown in FIG. As a result, as shown in FIG. 6, the gate signal VGi (only VG1 to VG4 are shown in FIG. 6) is given to each gate wiring Gi. That is, during the time 8t0 to: LOtO, the selection voltage GH is applied as the gate signal VG1 to the gate wiring G1. As a result, the TFT 16 in the pixel Alj (All to Alm) connected to the gate wiring G1 is turned on. During this time, the data Dalj is also supplied to the liquid crystal element LC via the TFT 16 as the source wiring Sj force.
  • the selection wiring ZI, the clock yck, and the control signal SE shown in FIG. 6 are given to the potential wiring drive circuit 10.
  • potential VEi (only VE1 to VE4 are shown) is applied to each potential wiring Ei. It is done.
  • the potential VLb is applied to the potential wiring E1 because the time 8t0 to 10t0 is the first period.
  • the second period after time 10t0 continues until immediately before the potential VLa is applied to the potential wiring E1.
  • the potential VSb is applied to the potential wiring E1.
  • the third period thereafter time 2t0 to 8t0
  • the potential VTb is applied to the potential wiring E1.
  • the first period follows the third period
  • the second period further follows the first period.
  • the potential Vclj ′ is applied to the pixel electrode 17 of the pixel Alj at times 2t0 to 8t0, the time 8t0 to: the potential Valj is applied to LOtO, and the potential Vblj is applied after time 10t0.
  • the response characteristics before and after the transition of the display element LC are as shown in FIG.
  • the capacitance of the display element LC is Clc
  • the capacitance of the capacitor Cs is Cs
  • the potential of the common electrode COM is the common potential Vcom.
  • the length of the third period is shorter than the length of the second period.
  • the ratio of the third period to one frame period is less than 50%.
  • the display element LC is given a gradation voltage that should be transited in the second period.
  • a voltage is applied to the display element LC as follows. (1) Apply the selection voltage GH (ON voltage) to the gate wiring Gi, turn on the pixel TFT16, and apply the desired voltage to the display element LC. At this time, the liquid crystal element LC is actually The applied voltage is a voltage close to a desired voltage, and then becomes a desired voltage after the voltage of the gate wiring Gi is changed. (2) After that, the potential applied to the other electrode of the capacitor Cs is changed by the potential wiring Ei, and the voltage applied to the display element LC of the pixel Aij is changed (to a voltage at which the liquid crystal can move easily). (3) Hold the state for several H to several tens of H and return to the desired voltage.
  • FIG. 28 shows this drive waveform.
  • FIG. 28 shows the gate signal VG1, the potential VE1, the source signals VS1 and VS2, and the potentials VA11 and VA12.
  • Al l, VA12 is the source wiring S during part of one frame period (part of the non-selection period).
  • this period is referred to as a potential difference change period, it may be referred to as an intermediate period.
  • FIG. 7 shows the display device 15 used in the present embodiment.
  • components having the same functions as those in the display device 1 of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
  • Data Daij from the source driver circuit 3 is supplied to the source wiring Sj at the timing shown in FIG. Further, the gate driver circuit 3 is input with the start pulse YI and the clock y ck shown in FIG. As shown in FIG. 8, a gate signal VGi (only VG1 to VG4 are shown in FIG. 8) is output to each gate wiring Gi.
  • the H level selection voltage GH is applied to the gate line G1 as the gate signal VG1.
  • the TFT 16 in the pixel Alj (A11 to Alm) connected to the gate wiring G1 is turned on.
  • data Dalj is supplied from the source wiring Sj to the liquid crystal element LC via the TFT 16.
  • the potential Vclj ′ is applied to the pixel electrode 17 of the pixel Alj from time 4t0 to 8t0, the potential Valj is applied from time 8t0 to: LOtO, and the potential Vblj is applied from time 10t0 to 12t0.
  • the potential Vclj ′ is applied at time 12t0 to 16t0.
  • the response characteristics before and after the transition of the display element LC are as shown in FIG.
  • the total length of the third period is shorter than the total length of the second period.
  • the ratio of the third period to one frame period is less than 50%.
  • a gradation voltage that should originally transition to the second period is applied to the display element LC.
  • the third period a gradation voltage larger than the gradation that should be displayed is given. Therefore, as the voltage application time becomes longer, the gray scale display error may increase, so the ratio of the third period to one frame period is less than 50%.
  • the potential of the potential wiring Ei is changed every 2H in this embodiment, it is preferably changed every several H to several tens of H.
  • Fig. 29 shows a drive waveform in the case of driving in this way in line inversion drive.
  • FIG. 29 shows the gate signals VG1, VG2, the source signal VSj output to the arbitrary source wiring Sj, the counter electrode potential Vcom, and the four types of potentials VExl to VEx4. Is shown.
  • the potential VExl is the potential of the potential wiring E4k (k is 0 and a positive integer)
  • the potential VEx2 is the potential of the potential wiring E4k + 1
  • the potential VEx3 is the potential of the potential wiring E4k + 2
  • the potential V Ex4 is the potential of the potential wiring E4k + 3.
  • FIG. 9 shows the display device 18 used in the present embodiment.
  • components having the same functions as those in the display device 1 of the first embodiment are denoted by the same reference numerals and description thereof is omitted.
  • the display device 18 includes a source driver circuit 2, a display panel 19, and a gate driver circuit 20.
  • the pixel Aij is disposed in the vicinity of the intersection of the gate wiring Gi and the source wiring 3 ⁇ 4.
  • the TFT 16 as the first active element, the display element LC, and the capacitor as the potential holding means It consists of Cs and TF T23, which is the second active element.
  • the gate terminal of the TFT 16 is connected to the gate line Gi, the source terminal is connected to the source line 2, and the drain terminal is connected to the pixel electrode 17.
  • a TFT 23 is disposed between the pixel electrode 17 and one terminal 24 of the capacitor Cs. That is, the control wiring Pi is connected to the gate terminal of the TFT 23, the pixel electrode 17 is connected to the source terminal, and one terminal 24 of the capacitor Cs is connected to the drain terminal.
  • the potential wiring Ei is connected to the other terminal of the capacitor Cs, and the other terminal of the display element LC is connected to the common electrode COM.
  • a liquid crystal display element is assumed as the display element LC.
  • the method of the present invention can be applied to other electro-optical elements (for example, an electochromic element and an organic EL element). Is possible.
  • the gate driver circuit 20 includes a shift register 21 and an output circuit 22 (consisting of a logic circuit and a buffer).
  • start pulse YI and the clock yck shown in the figure are input to the gate driver circuit 20.
  • This input start pulse YI is the shift register at the timing of the clock yck. Is output from each output stage.
  • the logic circuit of the output circuit 22 performs a logical AND operation (AND) on the pulse output from each output stage of the shift register 21 and the control signal SL input from the outside.
  • the pulse of the logical product is output as a gate signal VGi (only VG1 to VG3 are shown in the figure) to each gate wiring Gi as shown in FIG.
  • the logic circuit of the output circuit 22 is different from the generation of the selection voltage VGi by the pulse output from each output stage of the shift register 21 and the control signal SL input from the outside ( AND).
  • the logical product pulse is output as a potential VPi (only VP 1 to VP 3 are shown in the figure) to each control wiring Pi as shown in FIG. 11 through the buffer of the output circuit 22.
  • the potential VP1 changes from the low level GL to the high level GH and from the high level GH to the low level GL in the same phase as the selection voltage VG3.
  • the period between time t0 and time 2t0 is the first period.
  • an H-level selection voltage GH is applied as a gate signal to the gate wiring G1, and the TFT 16 in the pixel Alj is turned on.
  • the data voltage Val is applied from the source wiring Sj to the pixel electrode 17, and the voltage Vd is applied to the common electrode COM and the potential wiring Ei.
  • the data voltage Val is applied to the pixel electrode 17 of the pixel Alj, and the voltage Val ⁇ Vd is applied to the display element LC.
  • the period between time 2tO and 3tO is the second period.
  • the L level non-selection voltage GL is applied to the gate wiring G1 as the gate signal VG1, and the TFT 16 in the pixel Alj is turned off.
  • the period from time 3t0 to tf + t0 is the third period.
  • this third period between the times 3t0 and 4t0, as shown in FIG. 11, when the H-level selection voltage GH is applied to the control wiring P1, the TFT 23 in the pixel Alj is turned on. .
  • the pixel electrode 17 and one terminal 24 of the capacitor Cs are short-circuited, and the potential of the pixel electrode 17 changes to Vxl.
  • the potential of the pixel electrode 17 is maintained until the TFT 16 is turned on next time.
  • Vxl (Clc -Val + Cs- (VO-Ve)) / (Clc + Cs)
  • Clc is the capacitance between the pixel electrode 17 and the common electrode COM.
  • Cs is the capacitance of the capacitor Cs, and
  • VO is the potential of the pixel electrode 17 before time tO (this is also the potential of one terminal 24 of the capacitor Cs).
  • Vxl -Vd (Clc-Val + Cs- (VO-Ve)) / (Clc + Cs) — Vd
  • Table 2 shows changes in the voltage applied to the display element LC when the ratio between Clc and Cs is changed and the voltages Vd and Ve applied to the common electrode COM as the common electrode potential Vcom are both 0. .
  • Va, Vx, Vb, Vc, and Vz represent the potential of the pixel electrode 17 shown in FIG.
  • the selection voltage GH is applied to the gate wiring G1 and the control wiring P1 at the time of the next frame +1; 0 to £ + 2 tO.
  • the TFTs 16 and 23 in the pixel Alj are turned on.
  • the data voltage Vbl (VAlj) is applied to the source wiring Sj force pixel electrode 17 and one terminal 24 of the capacitor Cs.
  • the voltage Vd (Vcom, VEi) is applied to the common electrode COM and the potential wiring Ei.
  • the voltage Vbl ⁇ Vd is applied to the display element LC.
  • the voltage Vbl given by the source wiring Sj force is held in the pixel electrode 17 as it is without using the second configuration described above. Then, the second configuration is used in the next frame.
  • the TFT 23 as the second active element is disposed between the pixel electrode 17 and the terminal 24 of the capacitor Cs.
  • the voltage of the previous frame is held by the capacitor Cs.
  • the display element LC may hold the voltage of the previous frame instead of the capacitor Cs.
  • the display element LC may be divided into two, and the voltage of the previous frame may be held on one side.
  • the pixel Aij shown in FIG. 12 includes a TFT 16 (first active element), a display element LC1, a capacitor Cs, a display element LC2 (potential holding means), and a TFT 25 (second active element). ing.
  • the gate terminal of the TFT 16 is connected to the gate wiring Gi
  • the source terminal is connected to the source wiring S j
  • the drain terminal is connected to the pixel electrode 17 of the display element LC1.
  • a TFT 25 is disposed between the pixel electrode 17 and the pixel electrode 26 of the display element LC2.
  • a control wiring Pi is connected to the gate terminal of the TFT 25, a pixel electrode 17 is connected to the source terminal, and a pixel electrode 26 is connected to the drain terminal.
  • the terminals facing the pixel electrodes 17 and 26 of the display elements LCI and LC2 are connected to the counter electrode COM.
  • the other terminal of the capacitor Cs is connected to the potential wiring Ei.
  • the display elements LCI and LC2 may be configured by dividing the pixel electrode into multiple parts within one pixel Aij as shown in FIG. By dividing the pixel Aij in this way and applying a voltage to each of the divided areas, the visual dependence can be corrected. Further, the holding capacitor Cs can be divided into two, and one can be used as a potential holding means.
  • FIG. 30 shows a display device 51 used in the present embodiment.
  • the display device 51 constituent elements having the same functions as those of the constituent elements in the display device 1 of the first embodiment are denoted by the same reference numerals and description thereof is omitted.
  • the display device 51 includes a source driver circuit 52, a display panel 53, and a gate driver circuit 3.
  • Each pixel Aij is arranged in the vicinity of the intersection of the gate wiring Gi and the source wiring 3 ⁇ 4.
  • the first active element TFT16, the display element LC, and the potential holding means are used. It consists of a capacitor Cs.
  • the gate driver circuit 3 includes a shift register 11 and an output circuit 12 (configured by a logic circuit and a buffer circuit (logic Z buffer circuit 54)). Since this gate driver circuit 3 has the same configuration as the gate driver circuit 3 of FIG. 1 shown in the first embodiment, the description thereof is omitted here.
  • the source driver circuit 52 further includes an analog switch 53 (AZS in the figure) added to the next stage of the DZ A conversion circuit 7 of the source driver circuit 2 of FIG. 1 shown in the first embodiment.
  • the analog switch 53 includes a TFT 55 connected between the DZA conversion circuit 7 and the source wiring Sj.
  • a control signal HP is supplied to the control terminal of the TFT 55 as shown in FIG. That is, as shown in FIG. 32, the control is performed while the gate lines G1 to G3 are in the selection period, that is, while the gate voltages VGi to VGe + 2 (selection voltage GH) are applied to the gate lines G1 to G3. There is a period during which the signal HP is at the selection voltage GH.
  • the voltage V a corresponding to the data Daj is output from the DZA conversion circuit 7 to the source wiring Sj.
  • the potential of the pixel electrode 17 at this time is Vz.
  • the TFT 55 is turned off to apply the non-selection voltage GL of the control signal HP to the gate wiring Gi.
  • Vb (Cd'Va + (Clc + Cs) Vz) Z (Cd + Clc + Cs "(7)
  • Table 3 shows the potential difference between the pixel electrode potential and the common electrode potential, considering that the potential of each pixel electrode 17 is different for each frame with reference to the potential of the common electrode COM.
  • (1), (2), and (3) indicate the first, second, and third frames, respectively.
  • Table 3 shows that the potential difference changes in the third frame. Specifically, the voltage Vb converges to 2V (10th frame), which is a force stable state where the voltage Vb changes from 2.5 to 2.5V.
  • the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and can be obtained by appropriately combining technical means disclosed in different embodiments. Such embodiments are also included in the technical scope of the present invention.
  • Industrial applicability Since the display device of the present invention can suppress an increase in cost and power consumption by increasing the response speed without using a frame memory, it can be suitably applied particularly to a mopile type display device.

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Abstract

La présente invention a pour but d'améliorer la vitesse de réaction d'un élément d'affichage, tel qu'un cristal liquide ou analogue, tout en supprimant l'augmentation du coût et de la consommation d'énergie. Chacun des pixels (Aij) comporte un transistor à couches minces (élément actif) qui est situé entre une électrode de pixel et un fil de source (Si) et qui est rendu conducteur ou non conducteur par une tension appliquée à un fil de grille (Gj). Chaque pixel (Aij) comporte également un condensateur qui maintient le potentiel d'un fil de potentiel (Ei) entre l'électrode de pixel et le fil de potentiel (Ei). Lors d'un intervalle de sélection pendant lequel un fil de grille (Gj) à balayer est sélectionné, une tension de sélection est appliquée à ce fil de grille (Gj), rendant ainsi le transistor à couches minces du pixel correspondant conducteur, fournissant ainsi une différence de potentiel entre l'électrode de pixel et l'électrode opposée sur la base d'un potentiel prédéterminé à appliquer à partir du fil de source (Si) à l'électrode de pixel. Lors de l'intervalle suivant, un circuit d'attaque de grille (3) rend le transistor à couches minces non conducteur et un circuit de commande de fil potentiel (10) change le potentiel du fil de potentiel (Ei), fournissant ainsi, entre l'électrode de pixel et l'électrode opposée, une différence de potentiel qui est supérieure ou inférieure à la différence de potentiel précédente lors de l'intervalle de sélection.
PCT/JP2007/054854 2006-04-27 2007-03-12 Appareil d'affichage et son procede de commande WO2007125687A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002055325A (ja) * 2000-07-27 2002-02-20 Samsung Electronics Co Ltd スイング共通電極を利用した液晶表示装置及びその駆動方法
JP2005208600A (ja) * 2003-12-26 2005-08-04 Nec Corp 液晶表示装置、その駆動方法及び駆動回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002055325A (ja) * 2000-07-27 2002-02-20 Samsung Electronics Co Ltd スイング共通電極を利用した液晶表示装置及びその駆動方法
JP2005208600A (ja) * 2003-12-26 2005-08-04 Nec Corp 液晶表示装置、その駆動方法及び駆動回路

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