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WO2007030527A3 - Masque photographique utilise pour fabriquer une structure de damasquinage double et procede pour le produire - Google Patents

Masque photographique utilise pour fabriquer une structure de damasquinage double et procede pour le produire Download PDF

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Publication number
WO2007030527A3
WO2007030527A3 PCT/US2006/034697 US2006034697W WO2007030527A3 WO 2007030527 A3 WO2007030527 A3 WO 2007030527A3 US 2006034697 W US2006034697 W US 2006034697W WO 2007030527 A3 WO2007030527 A3 WO 2007030527A3
Authority
WO
WIPO (PCT)
Prior art keywords
dual damascene
damascene structure
photomask
fabrication
forming
Prior art date
Application number
PCT/US2006/034697
Other languages
English (en)
Other versions
WO2007030527A2 (fr
Inventor
Susan S Macdonald
Original Assignee
Toppan Photomasks Inc
Susan S Macdonald
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Photomasks Inc, Susan S Macdonald filed Critical Toppan Photomasks Inc
Priority to US12/064,454 priority Critical patent/US20100215909A1/en
Priority to JP2008530164A priority patent/JP2009523312A/ja
Publication of WO2007030527A2 publication Critical patent/WO2007030527A2/fr
Publication of WO2007030527A3 publication Critical patent/WO2007030527A3/fr

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76817—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics using printing or stamping techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

La présente invention concerne un masque photographique utilisé pour fabriquer des structures de damasquinage double, ainsi qu'un procédé pour le produire. Le procédé pour produire un modèle de lithographie imprint step-and-flash (SFIL) multicouche consiste à disposer d'une ébauche qui présente un substrat, une couche de métallisation et une première couche de résine photosensible. Un motif de couche métallique d'une structure de damasquinage double est formé dans le substrat à une première profondeur au moyen d'un système lithographique. La première couche de résine photosensible est retirée de l'ébauche, puis une seconde couche de résine photosensible est appliquée. Le système lithographique est utilisé pour former un motif de couche à trou de raccordement sur la structure de damasquinage double à ladite première profondeur, alors que le premier motif est simultanément gravé à une seconde profondeur. Le premier et le second motif correspondent à des caractéristiques à établir dans de multiples couches d'un dispositif au moyen d'un procédé SFIL.
PCT/US2006/034697 2005-09-07 2006-09-06 Masque photographique utilise pour fabriquer une structure de damasquinage double et procede pour le produire WO2007030527A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/064,454 US20100215909A1 (en) 2005-09-15 2006-09-06 Photomask for the Fabrication of a Dual Damascene Structure and Method for Forming the Same
JP2008530164A JP2009523312A (ja) 2005-09-07 2006-09-06 デュアル・ダマシン構造を製造するためのフォトマスクおよびその形成方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71462705P 2005-09-07 2005-09-07
US60/714,627 2005-09-07

Publications (2)

Publication Number Publication Date
WO2007030527A2 WO2007030527A2 (fr) 2007-03-15
WO2007030527A3 true WO2007030527A3 (fr) 2009-04-30

Family

ID=37836413

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/034697 WO2007030527A2 (fr) 2005-09-07 2006-09-06 Masque photographique utilise pour fabriquer une structure de damasquinage double et procede pour le produire

Country Status (3)

Country Link
JP (1) JP2009523312A (fr)
CN (1) CN101505974A (fr)
WO (1) WO2007030527A2 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4684984B2 (ja) * 2005-12-07 2011-05-18 キヤノン株式会社 半導体装置の製造方法と物品の製造方法
DE102006030267B4 (de) * 2006-06-30 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Nano-Einprägetechnik mit erhöhter Flexibilität in Bezug auf die Justierung und die Formung von Strukturelementen
FR2942739B1 (fr) * 2009-03-03 2011-05-13 Commissariat Energie Atomique Procede de fabrication d'un moule pour la lithographie par nano-impression
FR2942738B1 (fr) 2009-03-03 2016-04-15 Commissariat A L'energie Atomique Procede de fabrication d'un moule pour la lithographie par nano-impression
KR101711646B1 (ko) * 2009-12-11 2017-03-03 엘지디스플레이 주식회사 임프린트용 몰드의 제조방법 및 임프린트용 몰드를 이용한 패턴 형성방법
JP5349404B2 (ja) * 2010-05-28 2013-11-20 株式会社東芝 パターン形成方法
US9034233B2 (en) 2010-11-30 2015-05-19 Infineon Technologies Ag Method of processing a substrate
CN102650822B (zh) * 2011-02-24 2015-03-11 中芯国际集成电路制造(上海)有限公司 双重图形化的纳米压印模具及其形成方法
JP5681552B2 (ja) * 2011-04-15 2015-03-11 株式会社フジクラ インプリントモールドの製造方法及びインプリントモールド
JP6066793B2 (ja) * 2013-03-25 2017-01-25 京セラクリスタルデバイス株式会社 圧電素子ウエハ形成方法
KR102614850B1 (ko) * 2016-10-05 2023-12-18 삼성전자주식회사 반도체 소자 제조방법
KR102710915B1 (ko) * 2016-10-25 2024-09-26 엘지디스플레이 주식회사 임프린트 몰드 및 이의 제조방법
JP7547265B2 (ja) 2021-03-23 2024-09-09 キオクシア株式会社 設計パターン生成方法、テンプレート、テンプレートの製造方法、及び半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030205658A1 (en) * 2002-05-01 2003-11-06 Molecular Imprints, Inc. Methods of inspecting a lithography template
US20030232252A1 (en) * 2002-06-18 2003-12-18 Mancini David P. Multi-tiered lithographic template and method of formation and use
US20040033424A1 (en) * 2002-08-15 2004-02-19 Talin Albert Alec Lithographic template and method of formation and use
US20040224261A1 (en) * 2003-05-08 2004-11-11 Resnick Douglas J. Unitary dual damascene process using imprint lithography

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3415335B2 (ja) * 1995-08-11 2003-06-09 大日本印刷株式会社 多段エッチング型基板の製造方法
JP3821069B2 (ja) * 2002-08-01 2006-09-13 株式会社日立製作所 転写パターンによる構造体の形成方法
TW200507175A (en) * 2003-06-20 2005-02-16 Matsushita Electric Ind Co Ltd Pattern forming method, and manufacturing method for semiconductor device
CN100483672C (zh) * 2003-09-29 2009-04-29 国际商业机器公司 用于在表面上形成多级结构的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030205658A1 (en) * 2002-05-01 2003-11-06 Molecular Imprints, Inc. Methods of inspecting a lithography template
US20030232252A1 (en) * 2002-06-18 2003-12-18 Mancini David P. Multi-tiered lithographic template and method of formation and use
US20040033424A1 (en) * 2002-08-15 2004-02-19 Talin Albert Alec Lithographic template and method of formation and use
US20040224261A1 (en) * 2003-05-08 2004-11-11 Resnick Douglas J. Unitary dual damascene process using imprint lithography

Also Published As

Publication number Publication date
CN101505974A (zh) 2009-08-12
JP2009523312A (ja) 2009-06-18
WO2007030527A2 (fr) 2007-03-15

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