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WO2007030527A2 - Masque photographique utilise pour fabriquer une structure de damasquinage double et procede pour le produire - Google Patents

Masque photographique utilise pour fabriquer une structure de damasquinage double et procede pour le produire Download PDF

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Publication number
WO2007030527A2
WO2007030527A2 PCT/US2006/034697 US2006034697W WO2007030527A2 WO 2007030527 A2 WO2007030527 A2 WO 2007030527A2 US 2006034697 W US2006034697 W US 2006034697W WO 2007030527 A2 WO2007030527 A2 WO 2007030527A2
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WO
WIPO (PCT)
Prior art keywords
layer
substrate
portions
pattern
absorber layer
Prior art date
Application number
PCT/US2006/034697
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English (en)
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WO2007030527A3 (fr
Inventor
Susan S. Macdonald
Original Assignee
Toppan Photomasks, Inc.
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Filing date
Publication date
Application filed by Toppan Photomasks, Inc. filed Critical Toppan Photomasks, Inc.
Priority to US12/064,454 priority Critical patent/US20100215909A1/en
Priority to JP2008530164A priority patent/JP2009523312A/ja
Publication of WO2007030527A2 publication Critical patent/WO2007030527A2/fr
Publication of WO2007030527A3 publication Critical patent/WO2007030527A3/fr

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76817—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics using printing or stamping techniques

Definitions

  • This disclosure relates in general to step-and-flash imprint lithography and, more particularly, to a photomask for the fabrication of a dual damascene structure and method for forming the same .
  • Advanced microprocessors may require eight or more levels of wiring to transmit electrical signals and power among devices and to external circuitry. Each wiring level may connect to the levels above and below it through via layers .
  • a standard dual damascene process only a single metal deposition step may be used to simultaneously form a metal layer and a via layer.
  • the vias and the trenches may be defined using two lithography steps and at least two etch steps. After the via and trench recesses are etched, the via may be filled with a metal material in the same step used to fill the trench defining the metal layer.
  • the excess metal deposited outside of the trench may be removed by a chemical mechanical polishing (CMP) process such that a planar structure with metal inlays is formed. Once the planarized surface is achieved, a CMP does not have to be performed on the dielectric layer. Thus, a CMP step may be eliminated through use of the dual damascene process .
  • CMP chemical mechanical polishing
  • a step-and-flash imprint lithography (SFIL) process uses a template similar to a mold to form a pattern on a substrate.
  • a polymerizable fluid may be deposited on a substrate surface and the fluid may fill the gaps defined by a relief pattern in the template when the template is applied to the fluid on the wafer.
  • the polymerizable fluid may be solidified to form a mask on the device such that a pattern may be formed on the device.
  • An SFIL processes may have advantages over other lithographic techniques, such as offering a high resolution, excellent pattern fidelity, and the ability to be utilized at room temperature and low pressure. However, a standard SFIL template may only be used to form a single device layer.
  • a multi-layer template is formed using a combination of chrome and resist as etch stop layers during a substrate etch.
  • a method for forming a step-and- flash imprint lithography (SFIL) template.
  • a blank is provided including a substrate, a metallization layer, and a first resist layer.
  • a metal layer pattern of a dual damascene structure is formed in the substrate at a first depth using a lithography system.
  • the first resist layer is removed from the blank and a second resist later is applied.
  • a lithography system is used to form a cia layer pattern of the dual damascene structure at the first depth while the metal layer pattern is simultaneously etched to a second depth.
  • a method for fabricating an SFIL template includes providing a blank having a substrate, an absorber layer and a first resist layer including a first pattern formed therein to expose first portions of the absorber layer.
  • the exposed first portions of the absorber layer are etched to expose first portions of the substrate and the exposed first portions of the substrate are etched to form the first pattern in the substrate .
  • the absorber layer functions to provide a first etch stop during etching of the first portions of the substrate.
  • a second resist layer is deposited on the etched first portions of the substrate and exposed first portions of the absorber layer.
  • a second pattern is developed in the second resist layer to expose second portions of the absorber layer.
  • the exposed second portions of the absorber layer are etched to expose second portions of the substrate such that the second portions of the substrate include the etched first portions of the substrate.
  • the exposed second portions of the substrate are etched to form the second pattern in the substrate .
  • the absorber layer functions to provide a second etch stop during etching of the second portions of the substrate.
  • the absorber layer and the second resist layer are removed to form a multi-layer SFIL template.
  • a multi-layer SFIL template includes a substrate, a first trench formed in the substrate at a first depth and a second trench formed in the substrate at a second depth.
  • the first trench corresponds to a metal layer of a dual damascene structure on a semiconductor wafer using an SFIL process and the second trench corresponds to a via layer of the dual damascene structure .
  • the first and second trenches formed in the substrate by etching the substrate and using an absorber layer as an etch stop.
  • FIGURES IA-IJ illustrate cross-sectional side views of a semiconductor wafer at various stages of manufacturing a dual damascene structure in accordance with teachings of the prior art
  • FIGURES 2A-2E illustrate cross-sectional side views of a semiconductor wafer at various stages of manufacturing a dual damascene structure using a step- and-print imprint lithography (SFIL) process according to teachings of the present disclosure
  • FIGURE 3A illustrates a top view of an SFIL template for use with an SFIL process to create a dual damascene structure on a semiconductor wafer according to teachings of the present disclosure
  • FIGURE 3B illustrates a cross-sectional side view of the SFIL template of FIGURE 3A according to teachings of the present disclosure
  • FIGURE 4 illustrates a flow diagram for a method of fabricating a multi-layer SFIL template according to the teachings of the present disclosure
  • FIGURE 5A illustrates a top view of design data included in a mask pattern file used to fabricate a multi-layer SFIL template according to teachings of the present disclosure
  • FIGURE 5B-5E illustrate cross-sectional side views of an SFIL template at various stages of manufacturing the SFIL template according to teachings of the present disclosure .
  • FIGURES 1 through 5 where like numbers are used to indicate like and corresponding parts.
  • FIGURES IA through IJ illustrate cross-sectional side views of a semiconductor wafer at various stages of a conventional manufacturing process for a dual damascene structure.
  • Some conventional manufacturing processes for a dual damascene structure may require greater than twenty steps to fabricate a single metal-via layer.
  • a conventional dual damascene process includes twenty-three processing steps in order fabricate a single metal-via layer. Assuming that an integrated circuit includes eight layers of metal, the total number of steps required to form all eight metal- via layers would be approximately 161.
  • FIGURE IA illustrates the first eight steps in a conventional manufacturing process for a dual damascene structure.
  • a metal layer 16 may be formed in a dielectric material 14 that is formed over a device layer (not shown) on a semiconductor wafer 12.
  • Metal layer 16 may be copper, aluminum or any other suitable metal that may be used to transmit electrical signals and power among devices in an integrated circuit.
  • Dielectric layer 14 may be silicon dioxide (SiCb) , a low-k interlayer dielectric (ILD) or any other suitable material that may provide an insulation layer of the integrated circuit.
  • Semiconductor wafer 12 may be silicon, gallium arsenide or any other suitable material used to form an integrated circuit .
  • a metal etch barrier 18, such as copper, may be deposited on metal layer 16 and the dielectric layer 14.
  • a via ILD layer 20 may be deposited on metal etch barrier 18.
  • a trench etch stop material 22 may be applied over via ILD- layer 20.
  • a metal ILD layer 24 may be deposited over trench etch stop layer 22.
  • a via hard mask 26 may be applied over metal ILD layer 24 followed by deposition of a trench hard mask 28 over via hard mask 26 in the sixth step.
  • the material used to form via and trench hard masks may be a plasma silicon nitride.
  • the trench hard mask may be any suitable material that provides protection for the ILD layer during a photoresist strip process and/or provides an etch stop during a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • a bottom antireflective coat (BARC) layer 30 may be deposited over the trench hard mask 28.
  • the BARC material may be organic or inorganic.
  • photoresist 32 may be deposited over BARC layer 30. Photoresist 32 may be any suitable positive or negative photoresist.
  • FIGURE IB illustrates the ninth and tenth steps in a conventional process for a dual damascene structure.
  • a trench of approximately the same size as metal layer 16 formed in dielectric layer 14 may be formed in photoresist 32 by exposing the photoresist using a photomask (not shown) and a lithography system (not shown) .
  • photoresist 32 may be developed to expose BARC layer 30 and form a trench of approximately the size of metal layer 16 formed in dielectric layer 14. If a positive photoresist is used, the exposed portion of the resist may be developed and, if a negative photo-resist is used, the unexposed portion of the resist may be developed.
  • FIGURE 1C illustrates steps eleven and twelve in the conventional manufacturing process for a dual damascene structure.
  • any suitable etch process may be used to etch through BARC layer 30- and trench hard mask layer 28 in the trench formed by removal of photoresist 32.
  • the etch process may be an anisotropic dry etch or any other suitable etch process that removes the trench hard mask layer.
  • an ash process may be used to remove any remaining photoresist 32. In one embodiment, the ash process may be conducted in a strongly oxidizing gaseous atmosphere.
  • FIGURE 1E> illustrates steps thirteen and fourteen in the conventional manufacturing process for a dual damascene structure.
  • a second BARC layer 31 may be deposited in the trench over via hard- mask layer 26 and aver the remaining portions of the trench hard mask 28.
  • a second photoresist layer 34 may be formed over second BARC layer 31.
  • FIGURE IE illustrates steps fifteen through seventeen in the conventional manufacturing process for a dual damascene structure.
  • a via pattern may be imaged in photoresist 34 using a second photomask (not shown) and the lithography system (not shown) .
  • photoresist 34 may be developed to form a via pattern in the photoresist 34 and expose a portion of via hard mask 26.
  • the exposed portion of via hard mask layer 26 in the via may be etched to expose a surface of the metal ILD layer 24.
  • FIGURE IF illustrates step eighteen in the conventional manufacturing process for a dual damascene structure.
  • any suitable etch process may be used to etch the exposed po-rtion of metal ILD layer 24 in the via and the trench etch stop layer 22 in the via .
  • FIGURE IG illustrates step nineteen in the conventional manufacturing process for a dual damascene structure.
  • an ash process may be used to remove any remaining photoresist 34 and the via ILD 20 in the trench defining the via may be removed by an etch process . .
  • FIGURE IH illustrates step twenty in the. conventional manufacturing process for a dual damascene structure.
  • barrier layer 18 may be etched in the via to expose a surface of metal layer 16.
  • metal layer 16 may be copper.
  • FIGURE II illustrates steps twenty-one and twenty- two in the conventional manufacturing process for a dual damascene structure.
  • a copper seed layer 36 may be deposited over the exposed surfaces and a copper layer 37 may be plated over copper seed layer 36 formed in the via and over the exposed portions of trench etch stop layer 22 in the trench.
  • FIGURE IJ illustrates step twenty-three in the conventional manufacturing process for a dual damascene structure.
  • the metal-via layer may be completed by using a CMP process such that the metal layer 37 formed in the trench is level with the remaining metal ILD 24 in step twenty-three.
  • via 38 and metal layer 39 may be created and may be electrically coupled to metal layer 16.
  • FIGURES 2A through 2E illustrate cross-sectional side views of a semiconductor wafer 52 and a step-and- print imprint lithography (SFIL) template 62 at various stages of an SFIL manufacturing process for a dual damascene structure.
  • a template for example SFIL template 62
  • SFIL template 62 may be used as a mold or stamp to form a pattern on a semiconductor wafer by contacting the temp-late with a film., for example film 60, on the wafer.
  • the film may be a polymerizable fluid that has a low viscosity and is photocurable.
  • the film may fill the spaces between the template and the surface of the semiconductor wafer.
  • the i film may then be solidified by either exposing, it to light or to heat.
  • the template may be released from contact with the film once the film is hardened and the appropriate structure on the wafer may be formed.
  • FIGURE 2A illustrates the first two steps in an SFIL manufacturing process for a dual damascene structure in accordance with the present disclosure.
  • Metal layer 56 may be formed in dielectric material 54 that is formed on semiconductor wafer 52.
  • metal layer 56 may be copper.
  • Metal layer 56 and dielectric layer 54 may be similar to metal layer 16 and dielectric layer 14 described in reference to FIGURES IA-IJ.
  • a metal etch barrier 58 such as copper, may be deposited on metal layer 56 and dielectric layer 54.
  • film 60 may be dispensed on etch barrier 58.
  • film 60 may be a resist material that acts as a dielectric that separates the various layers of an integrated circuit.
  • film 60 may be an imprintable dielectric material such as a polyhedral oligomeric silsesquixane (POSS) type material.
  • film 60 may be a polymerizable fluid, including but not limited to compounds including an organic acrylate, an organic crosslinker, a silicon containing acrylate, and/or a photoinitiator, or any other suitable compound.
  • FIGURE 2B illustrates the third step in an SFIL manufacturing process for a dual damascene structure .
  • SFIL template 62 may be applied to film 60 on semiconductor wafer by, for example, applying pressure to SFIL template 62.
  • SFIL template 62 may be a transparent material such as quartz, synthetic quartz, fused silica, magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ) , or any other suitable material that transmits at least seventy-five percent (75%) of incident light having, a wavelength between approximately 10 nanometers (ran) and approximately 450 nm.
  • SFIL template 62 may be an opaque material that retains its shape when heat is applied to either SFIL template 62 or semiconductor wafer 52.
  • film 60 may be cured by exposing SFIL template 62 to a radiation source such as an ultraviolet (UV) or deep ultraviolet (DUV) light.
  • UV ultraviolet
  • DUV deep ultraviolet
  • film 60 may be cured by applying a heat source to either SFIL template 62 or semiconductor wafer 52. Once film 60 is sufficiently hardened, SFIL template 62 may be released. As illustrated, a thin layer of film 60 may be present in the via formed by the template .
  • FIGURE 2C illustrates the fourth and fifth steps in an SFIL manufacturing process for a dual damascene structure.
  • an etch may be performed to remove the residual portion of film 60 remaining at the bottom of the via to expose barrier layer 58.
  • the etch process may be any suitable process that removes a dielectric material.
  • an etch process may be performed to remove the portion of barrier layer
  • the etch process may be any suitable process that removes a metal barrier layer.
  • FIGURE 2 ⁇ > illustrates the last three steps in an SFIL manufacturing process for a dual damascene structure .
  • copper seed layer 76 may be deposited over the exposed surfaces and copper layer 77 may be plated over copper seed layer 76 formed in the via and over the exposed portions of film 60 in the trench.
  • the metal-via layer may be completed by using a CMP process such that metal layer 77 formed in the trench is level with the remaining, film 60 in step eight.
  • via 78 and metal layer 79 may be created and may be electrically coupled to metal layer 56, as depicted in FIGURE 2E.
  • FIGURE 3A illustrates a top view of multi-layer SFIL template 82 used to fabricate dual damascene structures on a semiconductor wafer and
  • FIGURE 3B illustrates an cross-sectional side view of SFIL template 82 shown in FIGURE 3A.
  • SFIL template 82 may include features 84, metal features 86 and via features 88.
  • SFIL template 82 may be used in an SFIL process, for example with a dielectric material acting as the polymerizable fluid as described above in reference to FIGURES 2A through 2E .
  • SFIL template 82 When applied- to the. film deposited on a semiconductor wafer, SFIL template 82 may be used to simultaneously form a via layer using via features 88 and a metal layer using metal features 86 on an exposed surface of a semiconductor wafer.
  • Using SFIL template 82 with an SFIL process may reduce the number of steps required to form two layers in a device significantly.
  • FIGURE 4 illustrates a flow diagram for a method, 100 of fabricating a dual damascene SFIL template, for example SFIL template 62 or 82.
  • FIGURE 5A illustrates a top view of design data 130 included in a mask pattern file used to fabricate a multi-layer SFIL template, for example SFIL template 62 or 82, in accordance with the teachings of the present disclosure.
  • FIGURES 5B through 5E illustrate cross-sectional side views of an SFIL template, for example SFIL template 62 or 82, at various stages of manufacture in accordance with the present disclosure.
  • photomask blank 142 including absorber layer 144 formed on substrate 142 and photoresist layer 146 formed on absorber layer 144 may be provided.
  • Metal pattern 132 may be imaged int ⁇ photoresist layer 146 using a mask pattern file and a lithography system. Once the exposed portion of resist layer 146 is developed, the exposed portion of absorber layer 144 may be etched. Metal pattern 132 may then be then formed in substrate 142 by etching substrate 142 and using absorber layer 144 as an etch barrier. Another layer of photoresist 148 may be deposited on the surface of absorber layer 144 and additional trenches may be formed in substrate 142 in order to . image via pattern 134 into photoresist 148 using another mask pattern file and a lithography system. Again, the exposed portion of absorber layer 144 may be etched once the exposed portion of resist layer 148 is developed to form via pattern 134 in absorber layer 144. The remaining portion of the
  • 'absorber layer 144 is used as an etch barrier to form via pattern 134 in substrate 142 by etching exposed portions of the substrate 142.
  • metal pattern 132 included in a mask pattern file may be imaged into- photoresist layer 146 of photomask blank 140 by a lithography system.
  • An example pattern 132 for the metal layer of a dual damascene structure included in a mask pattern file is shown in FIGURE 5A.
  • Design data 130 may be included in one mask pattern file or metal pattern 132 and via pattern 134 may be included in separate mask pattern files.
  • the desired pattern may be imaged into a resist layer of the photomask blank using a laser, electron beam or X-ray lithography system.
  • a laser lithography system uses an argon-ion laser that emits light having a wavelength of approximately 364 nanometers (nm) .
  • the laser lithography system uses lasers emitting light at wavelengths from approximately 150 nm to approximately 300 nm.
  • a 25 keV or 50 keV electron beam lithography system uses a lanthanum hexaboride or thermal field emission source.
  • different electron beam lithography systems- may be used.
  • resist layer 146 may be developed to form metal pattern 132-. Portions of absorber layer 144 that correspond to metal pattern 132 may be exposed by developing the exposed portions of resist layer 146 with an alkaline solution that removes either, the exposed (positive photoresist) 1 or the unexposed (negative photoresist) portion.
  • the developer may be a metal-ion-free developer such as tetramethyl ammonium hydroxide (TMAH) . In other embodiments, any suitable developer may be used.
  • FIGURE 5B illustrates photomask blank 140 after completion of step 101.
  • photomask blank 140 may include substrate 142, absorber layer 144, and photoresist layer 146.
  • Substrate 142 may be a transparent material such as quartz, synthetic quartz, fused silica, magnesium fluoride (Mg-F 2 ) , calcium fluoride (CaF 2 ) , or any .other suitable material .
  • Absorber layer 144 may be a metal material such as chrome, chromium nitride, copper, a metallic oxy-carbo-nitride (e.g., MOCN, where M is selected from the group consisting of chromium, cobalt, iron, zinc, molybdenum, niobium, tantalum, titanium, tungsten, aluminum, magnesium, and silicon) , or any other suitable material that provides an etch stop during a substrate etch step.
  • absorber layer 144 may be formed of molybdenum suicide (MoSi) .
  • Resist layer 146 may be a polymethyl methacrylate (PMMA). resist, a polybutane 1-sulfone (PBS) resist, a polychloromethylstyrene (PCMS) resist, or any other suitable positive or negative resist.
  • PMMA polymethyl methacrylate
  • PBS polybutane 1-sulfone
  • PCMS polychloromethylstyrene
  • the exposed portions of absorber layer 144 may be etched to create metal layer pattern 132 in absorber layer 144.
  • absorber layer 144 may be etched using a ferric perchloride (FeCl 3 6H 2 0) etch, any chloride containing (Cl 2 ) gas etch, an aqua regia etch, or any other suitable etch depending on- the material used- for absorber layer 144.
  • the remaining- resist layer 146 provides an etch stop for the etch process used to etch absorber layer 144.
  • the exposed portions of substrate 142 may be etched to create metal pattern 132 in substrate 142.
  • substrate 142 may be etched using a buffered oxygen etch, a potassium hydroxide (KOH) etch, or any other suitable etch.
  • the etch depth into substrate 142 may be approximately 500 nm. In other embodiments, the etch depth may be any suitable depth that provides the appropriate metal layer on a semiconductor wafer.
  • the remaining portion of photoresist layer 146 may be removed- from photomask blank 140. In another embodiment, the resist may be removed before the substrate etch.
  • FIGURE 5C illustrates photomask blank 140 after completion of step 104.
  • a second photoresist layer 148 may be formed on photomask blank 140 to cover the remaining portion of absorber layer 144 and etched trench (or trenches) 145 in substrate 142.
  • second resist layer 148 may be an essentially identical compound as resist layer 146.
  • second resist layer 148 may be a different compound from that used to form first resist layer 146.
  • Via pattern 134 included in a mask pattern file may then be imaged onto second resist layer 148 by a lithography system. An example pattern 134 for the via layer of a dual damascene structure included in a mask pattern file is shown in FIGURE 5A.
  • portions of absorber layer 144 that correspond to via pattern 134 may be exposed by developing the exposed portions of resist layer 148 with a solution that removes either the exposed (positive photoresist) or the unexposed (negative photoresist ⁇ portions.
  • the exposed portions of absorber layer 144 may be etched to expose portions of substrate 142 that correspond to via pattern 134.
  • the absorber etch process used to form via pattern 134 may be similar to the absorber etch process used to form metal pattern 132.
  • the absorber etch process used to form via pattern 13-4 may be .different than the absorber etch process used to form metal pattern 134.
  • FIGURE 5D illustrates photomask blank 140 after completion of step 107.
  • the exposed portions of substrate 142 may be etched to- form via pattern 134 in substrate 142.
  • the etch depth may be approximately 500 nm. In another embodiment, the etch depth may be any suitable depth that provides the appropriate via layer on a semiconductor wafer.
  • the first and second substrate etches may be approximately the same. For example, as illustrated in FIGURE 3B, the trench formed by feature 84 may have a depth two times larger than the trench formed by metal feature 86. In other embodiments, the first and second substrate etches may be different such that the first etch is greater than the second etch or the second etch is greater than the first etch.
  • the remaining portions of second resist 148 may be stripped and the remaining portions of absorber layer 144 may be stripped at step 110 of method 100.
  • the resulting substrate 142 as depicted in FIGURE 5E may comprise an SFIL temp-late 150 including via features 154 and metal features 152.
  • the res-ulting SFIL template 150 may have features and characteristics similar to that of SFIL template 62. The above described process for fabricating an SFIL template provides aligned metal and via layers that are required for a dual damascene structure.
  • SFIL steps- may also be used throughout the manufacturing process.
  • a release layer may be formed on the surface of SFIL templates 62, 82 and/or template 150 to allow reliable separation from a polymerizable fluid.
  • a release layer may comprise a fluoroalkyltrichlorosilane precursor or any other suitable compound.
  • SFIL template for example SFIL templates 62, 82 and/or 150
  • SFIL templates 62, 82 and/or 150 may provide a number of advantages.
  • the number of steps required- to form a device may be reduced significantly, since multiple layers may be formed in the device simultaneously.
  • Another advantage may be the removal of several ⁇ f the most difficult steps of prior art dual damascene approaches.
  • the use of a SFIL process may reduce alignment errors in a device, since a first layer and a connected second layer are formed simultaneously.
  • Other advantages may be apparent to those of ordinary skill in the art.
  • the substrate may be etched after the resist is stripped.
  • the materials, sizes, and shapes may also be varied depending on specific needs. It should be understood that various changes, substitutions and alternations can- be made herein without departing from the spirit and scope of the disclosure as illustrated by the following claims.

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

La présente invention concerne un masque photographique utilisé pour fabriquer des structures de damasquinage double, ainsi qu'un procédé pour le produire. Le procédé pour produire un modèle de lithographie imprint step-and-flash (SFIL) multicouche consiste à disposer d'une ébauche qui présente un substrat, une couche de métallisation et une première couche de résine photosensible. Un motif de couche métallique d'une structure de damasquinage double est formé dans le substrat à une première profondeur au moyen d'un système lithographique. La première couche de résine photosensible est retirée de l'ébauche, puis une seconde couche de résine photosensible est appliquée. Le système lithographique est utilisé pour former un motif de couche à trou de raccordement sur la structure de damasquinage double à ladite première profondeur, alors que le premier motif est simultanément gravé à une seconde profondeur. Le premier et le second motif correspondent à des caractéristiques à établir dans de multiples couches d'un dispositif au moyen d'un procédé SFIL.
PCT/US2006/034697 2005-09-07 2006-09-06 Masque photographique utilise pour fabriquer une structure de damasquinage double et procede pour le produire WO2007030527A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/064,454 US20100215909A1 (en) 2005-09-15 2006-09-06 Photomask for the Fabrication of a Dual Damascene Structure and Method for Forming the Same
JP2008530164A JP2009523312A (ja) 2005-09-07 2006-09-06 デュアル・ダマシン構造を製造するためのフォトマスクおよびその形成方法

Applications Claiming Priority (2)

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US71462705P 2005-09-07 2005-09-07
US60/714,627 2005-09-07

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WO2007030527A2 true WO2007030527A2 (fr) 2007-03-15
WO2007030527A3 WO2007030527A3 (fr) 2009-04-30

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JP (1) JP2009523312A (fr)
CN (1) CN101505974A (fr)
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2226679A1 (fr) * 2009-03-03 2010-09-08 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Procédé de fabrication d'un moule pour la lithographie par nano-impression
CN102096314A (zh) * 2009-12-11 2011-06-15 乐金显示有限公司 制造压印模的方法和使用压印模形成图案的方法
US8778195B2 (en) 2009-03-03 2014-07-15 Commissariat A L' Energie Atomique Method to fabricate a mould for lithography by nano-imprinting
DE102011053390B4 (de) * 2010-11-30 2014-07-24 Infineon Technologies Ag Verfahren zum Prozessieren eines Substrats
CN107976864A (zh) * 2016-10-25 2018-05-01 乐金显示有限公司 压印模具及其制造方法

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* Cited by examiner, † Cited by third party
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JP5349404B2 (ja) * 2010-05-28 2013-11-20 株式会社東芝 パターン形成方法
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JP5681552B2 (ja) * 2011-04-15 2015-03-11 株式会社フジクラ インプリントモールドの製造方法及びインプリントモールド
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Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US7037639B2 (en) * 2002-05-01 2006-05-02 Molecular Imprints, Inc. Methods of manufacturing a lithography template
US6852454B2 (en) * 2002-06-18 2005-02-08 Freescale Semiconductor, Inc. Multi-tiered lithographic template and method of formation and use
JP3821069B2 (ja) * 2002-08-01 2006-09-13 株式会社日立製作所 転写パターンによる構造体の形成方法
US7083880B2 (en) * 2002-08-15 2006-08-01 Freescale Semiconductor, Inc. Lithographic template and method of formation and use
US20040224261A1 (en) * 2003-05-08 2004-11-11 Resnick Douglas J. Unitary dual damascene process using imprint lithography
TW200507175A (en) * 2003-06-20 2005-02-16 Matsushita Electric Ind Co Ltd Pattern forming method, and manufacturing method for semiconductor device
CN100483672C (zh) * 2003-09-29 2009-04-29 国际商业机器公司 用于在表面上形成多级结构的方法

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FR2942739A1 (fr) * 2009-03-03 2010-09-10 Commissariat Energie Atomique Procede de fabrication d'un moule pour la lithographie par nano-impression
US8778195B2 (en) 2009-03-03 2014-07-15 Commissariat A L' Energie Atomique Method to fabricate a mould for lithography by nano-imprinting
EP2226679A1 (fr) * 2009-03-03 2010-09-08 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Procédé de fabrication d'un moule pour la lithographie par nano-impression
CN102096314B (zh) * 2009-12-11 2013-05-01 乐金显示有限公司 制造压印模的方法和使用压印模形成图案的方法
US8728331B2 (en) 2009-12-11 2014-05-20 Lg Display Co., Ltd. Methods of fabricating imprint mold and of forming pattern using the imprint mold
CN102096314A (zh) * 2009-12-11 2011-06-15 乐金显示有限公司 制造压印模的方法和使用压印模形成图案的方法
DE102011053390B4 (de) * 2010-11-30 2014-07-24 Infineon Technologies Ag Verfahren zum Prozessieren eines Substrats
US9034233B2 (en) 2010-11-30 2015-05-19 Infineon Technologies Ag Method of processing a substrate
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EP3316035A3 (fr) * 2016-10-25 2018-07-25 LG Display Co., Ltd. Moule d'empreinte et son procédé de fabrication
US10583586B2 (en) 2016-10-25 2020-03-10 Lg Display Co., Ltd. Imprint mold and manufacturing method of the same
CN107976864B (zh) * 2016-10-25 2021-01-26 乐金显示有限公司 压印模具及其制造方法

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WO2007030527A3 (fr) 2009-04-30
JP2009523312A (ja) 2009-06-18

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