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WO2007010600A1 - Dispositif à semi-conducteurs et son procédé de fabrication - Google Patents

Dispositif à semi-conducteurs et son procédé de fabrication Download PDF

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Publication number
WO2007010600A1
WO2007010600A1 PCT/JP2005/013294 JP2005013294W WO2007010600A1 WO 2007010600 A1 WO2007010600 A1 WO 2007010600A1 JP 2005013294 W JP2005013294 W JP 2005013294W WO 2007010600 A1 WO2007010600 A1 WO 2007010600A1
Authority
WO
WIPO (PCT)
Prior art keywords
active region
semiconductor device
gate electrode
region
type
Prior art date
Application number
PCT/JP2005/013294
Other languages
English (en)
Japanese (ja)
Inventor
Hideharu Shido
Yasuyoshi Mishima
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2005/013294 priority Critical patent/WO2007010600A1/fr
Publication of WO2007010600A1 publication Critical patent/WO2007010600A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS

Definitions

  • the present invention relates to a semiconductor device suitable for a CMOS transistor and a method for manufacturing the same.
  • CMOS transistor In a CMOS transistor provided, it is desirable to obtain high performance in both an nMOS transistor and a pMOS transistor. However, at present, if the size is the same, the on-current of the pMOS transistor is as low as 1Z2 of the nMOS transistor. Therefore, the switching speed of the pMOS transistor is not enough compared to the nMOS transistor.
  • a structure called a strained silicon transistor in which strain is generated in the vicinity of the channel region has been proposed.
  • a structure has also been proposed in which strain is generated in the channel region by embedding a SiGe layer in the source / drain region.
  • a method has been proposed in which stress is applied to the whole after forming an insulating film covering the pMOS transistor.
  • proposals have been made to improve the mobility of charges (holes) by appropriately selecting the crystal orientation of the substrate.
  • Patent Document 1 Japanese Patent Laid-Open No. 10-144921
  • Patent Document 2 JP-A-5-110104
  • Patent Document 3 Japanese Patent Application Laid-Open No. 2004-319704
  • Patent Document 4 Japanese Patent Laid-Open No. 4-369843
  • An object of the present invention is to provide a semiconductor device capable of improving the characteristics of a p-channel MOS transistor and a method for manufacturing the same.
  • a semiconductor device includes a device active region located on a surface of a semiconductor substrate, a gate insulating film and a gate electrode formed on the device active region, and a planar surface of the surface of the device active region.
  • a plurality of grooves extending in a direction connecting the source region and the drain region and having a rectangular cross-sectional shape are formed on the surface of the element active region.
  • a plurality of grooves extending in the same direction and having a substantially rectangular cross section are formed on the surface of the element active region located on the surface of the semiconductor substrate.
  • a gate insulating film and a gate electrode are formed on the element active region.
  • the source region and the drain region are arranged at a position sandwiching the gate electrode in plan view on the surface of the element active region, and the direction in which the source region and the drain region are connected and the direction in which the groove extends. Form to match.
  • FIG. 1A is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 1B is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 1A.
  • FIG. 1C is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 1B.
  • FIG. 1D is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 1C.
  • FIG. 1E is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 1D.
  • FIG. 1F is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 1E.
  • FIG. 2A is a cross-sectional view showing a cross section taken along line II in FIG. 1A.
  • FIG. 2B is a cross-sectional view showing a cross section taken along line II in FIG. 1B.
  • FIG. 2C is a cross-sectional view showing a cross section taken along line II in FIG. 1C.
  • FIG. 2D is a cross-sectional view showing a cross section taken along line II in FIG. 1D.
  • FIG. 2E is a cross-sectional view showing a cross section taken along line II in FIG. IE.
  • FIG. 2F is a cross-sectional view showing a cross section taken along the line II in FIG. 1F.
  • FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 2F.
  • FIG. 4A is a graph showing the results of measurement on an nMOS transistor.
  • FIG. 4B is a graph showing the measurement results for the pMOS transistor.
  • FIG. 5 is a graph showing the results of the second test.
  • FIG. 6A is a photograph showing a TEM (transmission electron microscope) image in the vicinity of groove 4.
  • FIG. 6B is an enlarged view showing the vicinity of measurement points (* 1 to * 5) in FIG. 6A.
  • FIG. 6C is a diagram showing a result of the third test.
  • FIGS. 1A to 1F are cross-sectional views showing a semiconductor device manufacturing method according to an embodiment of the present invention in order.
  • 2A to 2F are cross-sectional views showing cross sections taken along line I I in FIGS. 1A to 1F, respectively.
  • FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 2F.
  • an element isolation insulating film 2 is selectively formed on the surface of a semiconductor substrate 1 such as a silicon substrate.
  • the element active region is partitioned by the element isolation insulating film 2.
  • the surface of the semiconductor substrate 1 is crystallographic (0
  • the conductivity type of the element active region is set to n-type by forming a well or the like.
  • a resist pattern 3 having a line “and space” (LZS) pattern is formed in a portion corresponding to the element active region. That is, a resist pattern 3 is formed in which a portion corresponding to the element active region is processed into a stripe shape. At this time, the direction in which each stripe extends is [1
  • dry etching for example, reactive ion etching, is performed using the resist pattern 3 as a mask to form a plurality of grooves 4 having a substantially rectangular cross-sectional shape on the surface of the semiconductor substrate 1.
  • the side surface perpendicular to the direction in which the groove 4 extends is 1 0) plane.
  • a gate insulating film 5 is formed on the surface of the semiconductor substrate 1 by thermal oxidation or thermal nitridation.
  • a polycrystalline silicon film in which boron is introduced over the entire surface is formed.
  • the gate electrode 6 is formed by patterning the polycrystalline silicon film.
  • the direction in which the gate electrode 6 extends is set to a direction orthogonal to the direction in which each groove 4 extends ([1-1 0] direction). That is, the gate width direction is [1
  • the sidewall insulating film 7 and the source Z drain diffusion layer 8 are formed.
  • ion implantation of p-type impurities is performed.
  • an interlayer insulating film 9 is formed on the entire surface, and the contact hole 10 reaching the gate electrode 6 and the source Z drain diffusion layer are formed on the interlayer insulating film.
  • a contact hole 11 reaching 8 is formed.
  • contact plugs 12 are embedded in the contact holes 10 and 11.
  • a wiring 13 connected to the contact plug 12 is formed on the interlayer insulating film 9.
  • the interlayer insulating film 14, the wiring 15, the interlayer insulating film 16, the conductive plug 17, the wiring 18, the interlayer insulating film 19, the cover film 20, and the like are formed, and the semiconductor device is formed. Finalize.
  • a trench 4 is formed in an element active region, and a gate electrode 6 made of polycrystalline silicon having boron introduced therein is embedded.
  • a lateral compressive stress acts on the convex portion located between the adjacent grooves 4.
  • high mobility of holes can be obtained. That is, a high on-current can be obtained and a fast switching speed can be obtained.
  • the internal stress can be adjusted relatively easily, it is easy to adjust the on-current.
  • the thickness of the gate electrode 6 is 150 nm
  • the width of the groove 4 is 70 nm
  • the width of the convex portion is 80 nm.
  • the depth of the groove 4 was 15 nm, 25 nm, and 35 nm.
  • the current value per unit length (1 m) of the channel region the current value increased in the force pMOS transistor in which the current value did not increase in the nMOS transistor. This means that there is a factor that increases the current value in addition to the increase in the area of the channel region. This is considered to be due to the presence of compressive stress as described above.
  • the characteristic value (C VZl) obtained by normalizing the product of the gate capacitance and the applied voltage by the on-current and the depth of the groove 4 was obtained.
  • the gate width is 20. O ⁇ m and the gate length is 0.3 m.
  • the characteristic value (CVZI) corresponds to the response time. The smaller this value, the higher the response speed (switching speed).
  • Vg is the gate voltage
  • Vth is the threshold voltage
  • I is the on-current.
  • FIG. 6A is a photograph showing a TEM (transmission electron microscope) image in the vicinity of the groove 4
  • FIG. 6B is an enlarged view showing the vicinity of the measurement points (* 1 to * 5) in FIG. 6A. The result is shown in FIG. 6C.
  • the width of the groove 4 is preferably equal to or smaller than the width of the convex portion located between the adjacent grooves 4.
  • the material of the gate electrode is not limited to polycrystalline silicon.
  • any material can be used as long as a lateral compressive stress acts on the channel region.
  • a SiGe film or a SiC film may be used.
  • a pure metal film or an alloy film having a work function substantially equal to that of p + Si may be used.
  • a silicide film formed by siliciding the polycrystalline silicon film as a whole may be used. In this case, for example, a nickel silicide film, a platinum silicide film, or the like can be used.
  • nMOS transistor it is said that high charge (electron) mobility can be obtained when a lateral tensile stress acts on the channel region. This can also be understood from the fact that in the first and second tests, the result was that mobility was not improved. Therefore, when high mobility is to be obtained also for the nMOS transistor, a lateral tensile stress is applied to the convex portion located between the adjacent grooves 4 as the material of the gate electrode. It is only necessary to select one that acts, or to have a structure in which tensile stress acts without forming the groove 4 in the channel region of the nMOS transistor.
  • the groove is formed at the same time and the gate electrode is formed at a different time.
  • the formation of the groove 4 may cause a damage layer on the surface of the element active region.
  • a sacrificial oxide film on the surface of the element active region after the formation of the trench 4 and remove the sacrificial oxide film by wet etching.
  • the electric field tends to concentrate on the corners of the convex portions, the corners of the convex portions are rounded as the sacrificial oxide film is formed and removed. As a result, even better characteristics can be obtained than when the electric field is less concentrated.
  • a silicon substrate having a (100) surface is mainly used.
  • One reason for this is that the hole mobility is smaller than the electron mobility in the (100) plane.
  • a groove is formed in a silicon substrate having a (100) surface, and the wall surface of the groove is defined as a (110) surface.
  • the hole mobility is larger than the electron mobility. This improves the characteristics of the pMOS transistor.
  • the stress acts on the channel as the gate electrode is embedded, the hole mobility is further increased.
  • the characteristics of the pMOS transistor can be improved in the silicon substrate having the (100) surface.
  • a groove is formed in a (110) plane silicon substrate, and the wall surface of the groove is defined as a (100) plane.
  • a groove is formed in a (100) surface silicon substrate, and the wall surface of this groove is (
  • the surface of the channel is parallel to the direction connecting the source and the drain.
  • Patent Document 2 describes a method of forming irregularities with an isosceles triangle section on the surface of a substrate by wet etching for the purpose of miniaturization.
  • the unevenness of the isosceles triangle section cannot apply sufficient stress to the element active region. For this reason, with the technique described in Patent Document 2, if the on-current in the pMOS transistor is increased as in the present invention, the effect cannot be obtained.

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

La présente invention concerne la surface d'une région active d'élément de type n d’un substrat semi-conducteur (1) avec un plan (100), sur lequel sont formées des rainures généralement rectangulaires (4). Le côté perpendiculaire à la direction dans laquelle se prolongent les rainures (4) est plane (110). Un film d'isolation de grille (5) et une électrode de grille (6) sont formés sur la surface du substrat semi-conducteur (1) par oxydation thermique. La direction dans laquelle se prolonge l'électrode de grille (6) est perpendiculaire à la direction ([1-10]) dans laquelle s'étendent les rainures (4). En fait, la direction de la largeur de grille est la direction [110]. Un film d'isolement de la paroi latérale (7) et une couche de diffusion source/drain de type p (8) sont formés.
PCT/JP2005/013294 2005-07-20 2005-07-20 Dispositif à semi-conducteurs et son procédé de fabrication WO2007010600A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/013294 WO2007010600A1 (fr) 2005-07-20 2005-07-20 Dispositif à semi-conducteurs et son procédé de fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/013294 WO2007010600A1 (fr) 2005-07-20 2005-07-20 Dispositif à semi-conducteurs et son procédé de fabrication

Publications (1)

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WO2007010600A1 true WO2007010600A1 (fr) 2007-01-25

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0575121A (ja) * 1991-09-18 1993-03-26 Fujitsu Ltd 半導体装置
JPH09199726A (ja) * 1995-11-15 1997-07-31 Nec Corp 半導体装置
JP2004172389A (ja) * 2002-11-20 2004-06-17 Renesas Technology Corp 半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0575121A (ja) * 1991-09-18 1993-03-26 Fujitsu Ltd 半導体装置
JPH09199726A (ja) * 1995-11-15 1997-07-31 Nec Corp 半導体装置
JP2004172389A (ja) * 2002-11-20 2004-06-17 Renesas Technology Corp 半導体装置およびその製造方法

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