WO2007010600A1 - Semiconductor device and its manufacturing method - Google Patents

Abstract

In the surface of an n-type element active region of a semiconductor substrate (1) having a (100) plane, generally rectangular grooves (4) are formed. The side perpendicular to the direction in which the grooves (4) extend is (110) plane. A gate insulating film (5) and a gate electrode (6) are formed on the surface of the semiconductor substrate (1) by thermal oxidation. The direction in which the gate electrode (6) extends is perpendicular to the direction ([1-10]) in which the grooves (4) extend. That is, the gate width direction is the [110] direction. A side wall insulating film (7) and a p-type source/drain diffusion layer (8) are formed.

Description

 Specification

 Semiconductor device and manufacturing method thereof

 Technical field

 The present invention relates to a semiconductor device suitable for a CMOS transistor and a method for manufacturing the same.

 Background Art In a CMOS transistor provided, it is desirable to obtain high performance in both an nMOS transistor and a pMOS transistor. However, at present, if the size is the same, the on-current of the pMOS transistor is as low as 1Z2 of the nMOS transistor. Therefore, the switching speed of the pMOS transistor is not enough compared to the nMOS transistor.

 [0003] Therefore, various studies have been made to improve the performance of pMOS transistors.

 For example, a structure called a strained silicon transistor in which strain is generated in the vicinity of the channel region has been proposed. A structure has also been proposed in which strain is generated in the channel region by embedding a SiGe layer in the source / drain region. Furthermore, a method has been proposed in which stress is applied to the whole after forming an insulating film covering the pMOS transistor. In addition, proposals have been made to improve the mobility of charges (holes) by appropriately selecting the crystal orientation of the substrate.

 [0004] However, according to any proposal, it is difficult to obtain a sufficient on-current in the pMOS transistor. It is also difficult to adjust the on-current appropriately. In addition, there is a problem that the number of processes, time and cost required for completing these structures are extremely large.

 Patent Document 1: Japanese Patent Laid-Open No. 10-144921

 Patent Document 2: JP-A-5-110104

 Patent Document 3: Japanese Patent Application Laid-Open No. 2004-319704

 Patent Document 4: Japanese Patent Laid-Open No. 4-369843

Disclosure of the invention An object of the present invention is to provide a semiconductor device capable of improving the characteristics of a p-channel MOS transistor and a method for manufacturing the same.

[0007] As a result of intensive studies to solve the above-mentioned problems, the inventors of the present application have come up with the following aspects of the invention.

 [0008] A semiconductor device according to the present invention includes a device active region located on a surface of a semiconductor substrate, a gate insulating film and a gate electrode formed on the device active region, and a planar surface of the surface of the device active region. A source region and a drain region, which are formed at positions sandwiching the gate electrode as viewed, are provided. A plurality of grooves extending in a direction connecting the source region and the drain region and having a rectangular cross-sectional shape are formed on the surface of the element active region.

 In the method for manufacturing a semiconductor device according to the present invention, a plurality of grooves extending in the same direction and having a substantially rectangular cross section are formed on the surface of the element active region located on the surface of the semiconductor substrate. Thereafter, a gate insulating film and a gate electrode are formed on the element active region. Next, the source region and the drain region are arranged at a position sandwiching the gate electrode in plan view on the surface of the element active region, and the direction in which the source region and the drain region are connected and the direction in which the groove extends. Form to match.

 Brief Description of Drawings

 FIG. 1A is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

 FIG. 1B is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 1A.

 FIG. 1C is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 1B.

 FIG. 1D is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 1C.

 FIG. 1E is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 1D.

 FIG. 1F is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 1E.

 FIG. 2A is a cross-sectional view showing a cross section taken along line II in FIG. 1A.

 FIG. 2B is a cross-sectional view showing a cross section taken along line II in FIG. 1B.

 FIG. 2C is a cross-sectional view showing a cross section taken along line II in FIG. 1C.

FIG. 2D is a cross-sectional view showing a cross section taken along line II in FIG. 1D. FIG. 2E is a cross-sectional view showing a cross section taken along line II in FIG. IE.

 FIG. 2F is a cross-sectional view showing a cross section taken along the line II in FIG. 1F.

 FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 2F.

 [FIG. 4A] FIG. 4A is a graph showing the results of measurement on an nMOS transistor.

 FIG. 4B is a graph showing the measurement results for the pMOS transistor.

 FIG. 5 is a graph showing the results of the second test.

 FIG. 6A is a photograph showing a TEM (transmission electron microscope) image in the vicinity of groove 4.

 FIG. 6B is an enlarged view showing the vicinity of measurement points (* 1 to * 5) in FIG. 6A.

 FIG. 6C is a diagram showing a result of the third test.

 BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. However, here, for convenience, the cross-sectional structure of the semiconductor device will be described together with its manufacturing method. 1A to 1F are cross-sectional views showing a semiconductor device manufacturing method according to an embodiment of the present invention in order. 2A to 2F are cross-sectional views showing cross sections taken along line I I in FIGS. 1A to 1F, respectively. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 2F.

 In this embodiment, first, as shown in FIGS. 1A and 2A, an element isolation insulating film 2 is selectively formed on the surface of a semiconductor substrate 1 such as a silicon substrate. The element active region is partitioned by the element isolation insulating film 2. The surface of the semiconductor substrate 1 is crystallographic (0

 0 1) Surface. Note that the conductivity type of the element active region is set to n-type by forming a well or the like.

Next, as shown in FIGS. 1B and 2B, a resist pattern 3 having a line “and space” (LZS) pattern is formed in a portion corresponding to the element active region. That is, a resist pattern 3 is formed in which a portion corresponding to the element active region is processed into a stripe shape. At this time, the direction in which each stripe extends is [1

1 0] direction. Next, dry etching, for example, reactive ion etching, is performed using the resist pattern 3 as a mask to form a plurality of grooves 4 having a substantially rectangular cross-sectional shape on the surface of the semiconductor substrate 1. The side surface perpendicular to the direction in which the groove 4 extends is 1 0) plane.

 Thereafter, as shown in FIGS. 1C and 2C, the resist pattern 3 is removed.

Subsequently, as shown in FIGS. 1D and 2D, a gate insulating film 5 is formed on the surface of the semiconductor substrate 1 by thermal oxidation or thermal nitridation. Next, a polycrystalline silicon film in which boron is introduced over the entire surface is formed. In forming the polycrystalline silicon film, it is preferable to crystallize the amorphous silicon film by heat treatment at 580 ° C. to 620 ° C. after forming the amorphous silicon film. Next, the gate electrode 6 is formed by patterning the polycrystalline silicon film. At this time, the direction in which the gate electrode 6 extends (gate width direction) is set to a direction orthogonal to the direction in which each groove 4 extends ([1-1 0] direction). That is, the gate width direction is [1

 1 0] direction. Next, the sidewall insulating film 7 and the source Z drain diffusion layer 8 are formed. In forming the source Z drain diffusion layer 8, ion implantation of p-type impurities is performed.

 Thereafter, as shown in FIGS. 1E and 2E, an interlayer insulating film 9 is formed on the entire surface, and the contact hole 10 reaching the gate electrode 6 and the source Z drain diffusion layer are formed on the interlayer insulating film.

A contact hole 11 reaching 8 is formed.

Subsequently, as shown in FIGS. 1F and 2F, contact plugs 12 are embedded in the contact holes 10 and 11. Next, a wiring 13 connected to the contact plug 12 is formed on the interlayer insulating film 9.

 Thereafter, as shown in FIG. 3, the interlayer insulating film 14, the wiring 15, the interlayer insulating film 16, the conductive plug 17, the wiring 18, the interlayer insulating film 19, the cover film 20, and the like are formed, and the semiconductor device is formed. Finalize.

In a pMOS transistor formed by such a method, a trench 4 is formed in an element active region, and a gate electrode 6 made of polycrystalline silicon having boron introduced therein is embedded. As a result, a lateral compressive stress acts on the convex portion located between the adjacent grooves 4. For this reason, high mobility of holes can be obtained. That is, a high on-current can be obtained and a fast switching speed can be obtained. Also, since the internal stress can be adjusted relatively easily, it is easy to adjust the on-current. [0020] Further, most of the surface of the groove 4 that contacts the gate electrode 6 is (1

 Since it is a (1 0) plane, higher mobility can be obtained.

 Next, a test conducted by the inventor will be described.

 [0022] (First test)

 In the first test, the relationship between the depth of the groove 4 and the characteristics was verified. Here, the thickness of the gate electrode 6 (thickness with respect to the top of the convex portion) is 150 nm, the width of the groove 4 is 70 nm, and the width of the convex portion is 80 nm. The depth of the groove 4 was 15 nm, 25 nm, and 35 nm. Then, for the nMOS transistor and the pMOS transistor having such a structure, an on-current was measured by applying a voltage IV to the source Z drain diffusion layer 8. The results are shown in FIGS. 4A and 4B. FIG. 4A is a graph showing the measurement results for the nMOS transistor, and FIG. 4B is a graph showing the measurement results for the pMOS transistor.

 [0023] As shown in FIGS. 4A and 4B, even when the nMOS transistor and the pMOS transistor were shifted from each other! /, The current value increased as the groove 4 was deepened. One of the factors is an increase in the area where the gate electrode 6 and the semiconductor substrate 1 face each other. That is, the deeper the groove 4, the larger the area of the channel region.

 On the other hand, regarding the current value per unit length (1 m) of the channel region, the current value increased in the force pMOS transistor in which the current value did not increase in the nMOS transistor. This means that there is a factor that increases the current value in addition to the increase in the area of the channel region. This is considered to be due to the presence of compressive stress as described above.

 [0025] (second test)

 In the second test, the relationship between the characteristic value (C VZl) obtained by normalizing the product of the gate capacitance and the applied voltage by the on-current and the depth of the groove 4 was obtained. Here, the gate width is 20. O ^ m and the gate length is 0.3 m. The result is shown in FIG. The characteristic value (CVZI) corresponds to the response time. The smaller this value, the higher the response speed (switching speed). In Fig. 5, Vg is the gate voltage, Vth is the threshold voltage, and I is the on-current.

 on

[0026] As shown in FIG. 5, in the nMOS transistor, even if the level difference (depth of the groove 4) is large, the force with the characteristic value hardly changed. In the pMOS transistor, the level difference is large. The value of the characteristic value From the results shown in FIG. 5, it is considered that a characteristic value comparable to that of an nMOS transistor can be obtained in a pMOS transistor if the step is about 50 nm or more.

 [0027] (Third test)

 In the third test, the internal stress acting around the groove 4 was investigated. Here, the stress acting in the horizontal and vertical directions (thickness direction) is measured at the five measurement points (* 1 to * 5) shown in Fig. 6A and Fig. 6B by micro electron diffraction. did. 6A is a photograph showing a TEM (transmission electron microscope) image in the vicinity of the groove 4, and FIG. 6B is an enlarged view showing the vicinity of the measurement points (* 1 to * 5) in FIG. 6A. The result is shown in FIG. 6C.

 [0028] As shown in FIG. 6C, all of the lateral stresses at the measurement points (* 1 to * 5) were compressive stresses. Of these, particularly at the measurement points (* 2, * 4) located near the bottom corner and the top corner of the groove 4, higher compressive stress was applied than at the other measurement points. On the other hand, regarding the stress in the vertical direction, the measurement point (* 1, * 2) at a position lower than the bottom of the groove 4 was subjected to compressive stress, whereas the measurement was at a position higher than the bottom. At points (* 3 to * 5), tensile stress was acting.

 [0029] Note that the width of the groove 4 is preferably equal to or smaller than the width of the convex portion located between the adjacent grooves 4.

 This is because stress is effectively applied to the channel region.

 [0030] The material of the gate electrode is not limited to polycrystalline silicon. In the pMOS transistor, any material can be used as long as a lateral compressive stress acts on the channel region. For example, a SiGe film or a SiC film may be used. Further, a pure metal film or an alloy film having a work function substantially equal to that of p + Si may be used. Further, a silicide film formed by siliciding the polycrystalline silicon film as a whole may be used. In this case, for example, a nickel silicide film, a platinum silicide film, or the like can be used.

[0031] In addition, with regard to the nMOS transistor, it is said that high charge (electron) mobility can be obtained when a lateral tensile stress acts on the channel region. This can also be understood from the fact that in the first and second tests, the result was that mobility was not improved. Therefore, when high mobility is to be obtained also for the nMOS transistor, a lateral tensile stress is applied to the convex portion located between the adjacent grooves 4 as the material of the gate electrode. It is only necessary to select one that acts, or to have a structure in which tensile stress acts without forming the groove 4 in the channel region of the nMOS transistor.

 [0032] When the nMOS transistor is formed in parallel with the pMOS transistor, for example, the groove is formed at the same time and the gate electrode is formed at a different time.

 Further, the formation of the groove 4 may cause a damage layer on the surface of the element active region.

 Therefore, it is preferable to form a sacrificial oxide film on the surface of the element active region after the formation of the trench 4 and remove the sacrificial oxide film by wet etching. In other words, it is preferable to incorporate a damage layer into the sacrificial oxide film and remove the damaged layer by removing the sacrificial oxide film. In addition, although the electric field tends to concentrate on the corners of the convex portions, the corners of the convex portions are rounded as the sacrificial oxide film is formed and removed. As a result, even better characteristics can be obtained than when the electric field is less concentrated.

 [0034] Here, an outline of the present invention will be described.

 Conventionally, a silicon substrate having a (100) surface is mainly used. However, it is difficult to improve the performance of pMOS transistors. One reason for this is that the hole mobility is smaller than the electron mobility in the (100) plane.

 On the other hand, in the above-described embodiment, a groove is formed in a silicon substrate having a (100) surface, and the wall surface of the groove is defined as a (110) surface. On the (110) plane, the hole mobility is larger than the electron mobility. This improves the characteristics of the pMOS transistor. In addition, since the stress acts on the channel as the gate electrode is embedded, the hole mobility is further increased.

[0037] Thus, the characteristics of the pMOS transistor can be improved in the silicon substrate having the (100) surface.

[0038] It is possible to improve the characteristics of the nMOS transistor. In this case, for example, a groove is formed in a (110) plane silicon substrate, and the wall surface of the groove is defined as a (100) plane. (Ten

On the 0) plane, the mobility of electrons is larger than the mobility of holes. This improves the characteristics of the nMOS transistor. A groove is formed in a (100) surface silicon substrate, and the wall surface of this groove is (

001) plane.

As described above, in the present invention, the surface of the channel is parallel to the direction connecting the source and the drain. By forming an extending groove (unevenness) and embedding a gate electrode therebetween, stress can be generated in the gate width direction, and the mobility of charges can be improved.

 [0040] Note that Patent Document 2 describes a method of forming irregularities with an isosceles triangle section on the surface of a substrate by wet etching for the purpose of miniaturization. However, the unevenness of the isosceles triangle section cannot apply sufficient stress to the element active region. For this reason, with the technique described in Patent Document 2, if the on-current in the pMOS transistor is increased as in the present invention, the effect cannot be obtained.

 Industrial applicability

[0041] As described above in detail, according to the present invention, since an appropriate stress acts on the channel region, the on-current can be increased and the adjustment thereof is easy. Furthermore, no new materials are required for this adjustment!

Claims

The scope of the claims  [1] an element active region located on a surface of a semiconductor substrate;  A gate insulating film and a gate electrode formed on the device active region;  A source region and a drain region formed on the surface of the device active region at positions sandwiching the gate electrode in plan view;  Have  A semiconductor device characterized in that a plurality of grooves extending in a direction connecting the source region and the drain region and having a substantially rectangular cross-sectional shape are formed on a surface of the element active region.  [2] The conductivity type of the element active region is n-type,  The conductivity type of the source region and the drain region is P type,  2. The semiconductor device according to claim 1, wherein compressive stress acts on the surface region of the element active region in a direction orthogonal to a direction in which the plurality of grooves extend.  3. The semiconductor device according to claim 1, wherein the gate electrode is made of a semiconductor film containing silicon.  4. The semiconductor device according to claim 1, wherein the gate electrode is made of a silicide film.  5. The semiconductor device according to claim 1, wherein the gate electrode is made of a pure metal film or an alloy film. [6] The width of the groove is equal to or less than the width of the convex portion sandwiching the groove of the element active region,  2. The semiconductor device according to claim 1, wherein the gate electrode is embedded in the trench.  7. The semiconductor device according to claim 1, wherein the depth of the groove is determined according to the rectangular pitch or the film thickness of the gate electrode. 8. The semiconductor device according to claim 7, wherein the depth of the groove is 50 nm or more. [9] A P-type element active region formed on the surface of the semiconductor substrate and insulated from the n-type element active region, An n-type source region and a drain region formed on the surface of the p-type device active region,  A plurality of second grooves extending in a direction connecting the n-type source region and the n-type drain region and having a rectangular cross-sectional shape are formed on the surface of the P-type element active region, 3. The surface area of the element active region of the mold is subjected to at least a bow I tension stress in a direction orthogonal to a direction in which the plurality of second grooves extend. Semiconductor device.  10. The semiconductor device according to claim 1, wherein there are two plane orientations of the element active region due to the presence of the plurality of grooves. [11] forming a plurality of grooves extending in the same direction and having a substantially rectangular cross-section on the surface of the element active region located on the surface of the semiconductor substrate;  A step of forming a gate insulating film and a gate electrode on the device active region; and a surface of the device active region at a position sandwiching the gate electrode in plan view, the source region and the drain region, Forming so that the direction connecting the regions and the direction in which the groove extends are aligned;  A method for manufacturing a semiconductor device, comprising: [12] The conductivity type of the element active region is n-type,  The conductivity type of the source region and the drain region is P type,  12. The semiconductor device according to claim 11, wherein, in the step of forming the gate electrode, a compressive stress is applied to a surface region of the element active region in a direction orthogonal to a direction in which the plurality of grooves extend. Manufacturing method. 13. The method for manufacturing a semiconductor device according to claim 11, wherein the gate electrode is composed of a semiconductor film containing silicon. 14. The method for manufacturing a semiconductor device according to claim 11, wherein the gate electrode is made of a silicide film. 15. The method for manufacturing a semiconductor device according to claim 11, wherein the gate electrode is made of a pure metal film or an alloy film. 16. The manufacturing of a semiconductor device according to claim 11, wherein a width of the groove is equal to or less than a width of a convex portion sandwiching the groove of the element active region, and the groove is embedded with the gate electrode. Method.  17. The method for manufacturing a semiconductor device according to claim 11, wherein the depth of the groove is determined according to the rectangular pitch or the film thickness of the gate electrode. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the depth of the groove is 50 nm or more.  [19] Before the step of forming a gate insulating film and a gate electrode on the element active region, a p-type element located on the surface of the semiconductor substrate and isolated from the n-type element active region is isolated. Forming a plurality of second grooves extending in the same direction on the surface of the child active region,  After the step of forming a gate insulating film and a gate electrode on the device active region, an n-type source region and a drain region are formed on the surface of the P-type device active region, and the source region and the drain region are provided. 13. The method of manufacturing a semiconductor device according to claim 12, further comprising a step of forming the connecting direction and a direction in which the second groove extends. [20] Between the step of forming the plurality of grooves and the step of forming the gate insulating film and the gate electrode,  Forming a sacrificial oxide film on the surface of the device active region;  Removing the sacrificial oxide film by wet etching;  The method of manufacturing a semiconductor device according to claim 11, comprising: 21. The method of manufacturing a semiconductor device according to claim 11, wherein the step of forming the plurality of grooves includes a step of performing dry etching on the element active region.